Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.14-rc5' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Couple of the arm people seem to wake up so this has imx and msm
fixes, along with a bunch of i915 stable bounds fixes and an amdgpu
regression fix.
All seems pretty okay for now"
* tag 'drm-fixes-for-v4.14-rc5' of git://people.freedesktop.org/~airlied/linux:
drm/msm: fix _NO_IMPLICIT fencing case
drm/msm: fix error path cleanup
drm/msm/mdp5: Remove extra pm_runtime_put call in mdp5_crtc_cursor_set()
drm/msm/dsi: Use correct pm_runtime_put variant during host_init
drm/msm: fix return value check in _msm_gem_kernel_new()
drm/msm: use proper memory barriers for updating tail/head
drm/msm/mdp5: add missing max size for 8x74 v1
drm/amdgpu: fix placement flags in amdgpu_ttm_bind
drm/i915/bios: parse DDI ports also for CHV for HDMI DDC pin and DP AUX channel
gpu: ipu-v3: pre: implement workaround for ERR009624
gpu: ipu-v3: prg: wait for double buffers to be filled on channel startup
gpu: ipu-v3: Allow channel burst locking on i.MX6 only
drm/i915: Read timings from the correct transcoder in intel_crtc_mode_get()
drm/i915: Order two completing nop_submit_request
drm/i915: Silence compiler warning for hsw_power_well_enable()
drm/i915: Use crtc_state_is_legacy_gamma in intel_color_check
drm/i915/edp: Increase the T12 delay quirk to 1300ms
drm/i915/edp: Get the Panel Power Off timestamp after panel is off
sync_file: Return consistent status in SYNC_IOC_FILE_INFO
drm/atomic: Unref duplicated drm_atomic_state in drm_atomic_helper_resume()
+119
-50
+12
-5
drivers/dma-buf/sync_file.c
+12
-5
drivers/dma-buf/sync_file.c
···
383
383
return err;
384
384
}
385
385
386
-
static void sync_fill_fence_info(struct dma_fence *fence,
386
+
static int sync_fill_fence_info(struct dma_fence *fence,
387
387
struct sync_fence_info *info)
388
388
{
389
389
strlcpy(info->obj_name, fence->ops->get_timeline_name(fence),
···
399
399
test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags) ?
400
400
ktime_to_ns(fence->timestamp) :
401
401
ktime_set(0, 0);
402
+
403
+
return info->status;
402
404
}
403
405
404
406
static long sync_file_ioctl_fence_info(struct sync_file *sync_file,
···
426
424
* sync_fence_info and return the actual number of fences on
427
425
* info->num_fences.
428
426
*/
429
-
if (!info.num_fences)
427
+
if (!info.num_fences) {
428
+
info.status = dma_fence_is_signaled(sync_file->fence);
430
429
goto no_fences;
430
+
} else {
431
+
info.status = 1;
432
+
}
431
433
432
434
if (info.num_fences < num_fences)
433
435
return -EINVAL;
···
441
435
if (!fence_info)
442
436
return -ENOMEM;
443
437
444
-
for (i = 0; i < num_fences; i++)
445
-
sync_fill_fence_info(fences[i], &fence_info[i]);
438
+
for (i = 0; i < num_fences; i++) {
439
+
int status = sync_fill_fence_info(fences[i], &fence_info[i]);
440
+
info.status = info.status <= 0 ? info.status : status;
441
+
}
446
442
447
443
if (copy_to_user(u64_to_user_ptr(info.sync_fence_info), fence_info,
448
444
size)) {
···
454
446
455
447
no_fences:
456
448
sync_file_get_name(sync_file, info.name, sizeof(info.name));
457
-
info.status = dma_fence_is_signaled(sync_file->fence);
458
449
info.num_fences = num_fences;
459
450
460
451
if (copy_to_user((void __user *)arg, &info, sizeof(info)))
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
···
834
834
placement.busy_placement = &placements;
835
835
placements.fpfn = 0;
836
836
placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT;
837
-
placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
837
+
placements.flags = bo->mem.placement | TTM_PL_FLAG_TT;
838
838
839
839
r = ttm_bo_mem_space(bo, &placement, &tmp, true, false);
840
840
if (unlikely(r))
+1
drivers/gpu/drm/drm_atomic_helper.c
+1
drivers/gpu/drm/drm_atomic_helper.c
+6
-1
drivers/gpu/drm/i915/i915_gem.c
+6
-1
drivers/gpu/drm/i915/i915_gem.c
···
3013
3013
3014
3014
static void nop_submit_request(struct drm_i915_gem_request *request)
3015
3015
{
3016
+
unsigned long flags;
3017
+
3016
3018
GEM_BUG_ON(!i915_terminally_wedged(&request->i915->gpu_error));
3017
3019
dma_fence_set_error(&request->fence, -EIO);
3018
-
i915_gem_request_submit(request);
3020
+
3021
+
spin_lock_irqsave(&request->engine->timeline->lock, flags);
3022
+
__i915_gem_request_submit(request);
3019
3023
intel_engine_init_global_seqno(request->engine, request->global_seqno);
3024
+
spin_unlock_irqrestore(&request->engine->timeline->lock, flags);
3020
3025
}
3021
3026
3022
3027
static void engine_set_wedged(struct intel_engine_cs *engine)
+1
-1
drivers/gpu/drm/i915/intel_bios.c
+1
-1
drivers/gpu/drm/i915/intel_bios.c
+7
-9
drivers/gpu/drm/i915/intel_color.c
+7
-9
drivers/gpu/drm/i915/intel_color.c
···
74
74
#define I9XX_CSC_COEFF_1_0 \
75
75
((7 << 12) | I9XX_CSC_COEFF_FP(CTM_COEFF_1_0, 8))
76
76
77
-
static bool crtc_state_is_legacy(struct drm_crtc_state *state)
77
+
static bool crtc_state_is_legacy_gamma(struct drm_crtc_state *state)
78
78
{
79
79
return !state->degamma_lut &&
80
80
!state->ctm &&
···
288
288
}
289
289
290
290
mode = (state->ctm ? CGM_PIPE_MODE_CSC : 0);
291
-
if (!crtc_state_is_legacy(state)) {
291
+
if (!crtc_state_is_legacy_gamma(state)) {
292
292
mode |= (state->degamma_lut ? CGM_PIPE_MODE_DEGAMMA : 0) |
293
293
(state->gamma_lut ? CGM_PIPE_MODE_GAMMA : 0);
294
294
}
···
469
469
struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
470
470
enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
471
471
472
-
if (crtc_state_is_legacy(state)) {
472
+
if (crtc_state_is_legacy_gamma(state)) {
473
473
haswell_load_luts(state);
474
474
return;
475
475
}
···
529
529
530
530
glk_load_degamma_lut(state);
531
531
532
-
if (crtc_state_is_legacy(state)) {
532
+
if (crtc_state_is_legacy_gamma(state)) {
533
533
haswell_load_luts(state);
534
534
return;
535
535
}
···
551
551
uint32_t i, lut_size;
552
552
uint32_t word0, word1;
553
553
554
-
if (crtc_state_is_legacy(state)) {
554
+
if (crtc_state_is_legacy_gamma(state)) {
555
555
/* Turn off degamma/gamma on CGM block. */
556
556
I915_WRITE(CGM_PIPE_MODE(pipe),
557
557
(state->ctm ? CGM_PIPE_MODE_CSC : 0));
···
632
632
return 0;
633
633
634
634
/*
635
-
* We also allow no degamma lut and a gamma lut at the legacy
635
+
* We also allow no degamma lut/ctm and a gamma lut at the legacy
636
636
* size (256 entries).
637
637
*/
638
-
if (!crtc_state->degamma_lut &&
639
-
crtc_state->gamma_lut &&
640
-
crtc_state->gamma_lut->length == LEGACY_LUT_LENGTH)
638
+
if (crtc_state_is_legacy_gamma(crtc_state))
641
639
return 0;
642
640
643
641
return -EINVAL;
+9
-5
drivers/gpu/drm/i915/intel_display.c
+9
-5
drivers/gpu/drm/i915/intel_display.c
···
10245
10245
{
10246
10246
struct drm_i915_private *dev_priv = to_i915(dev);
10247
10247
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10248
-
enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10248
+
enum transcoder cpu_transcoder;
10249
10249
struct drm_display_mode *mode;
10250
10250
struct intel_crtc_state *pipe_config;
10251
-
int htot = I915_READ(HTOTAL(cpu_transcoder));
10252
-
int hsync = I915_READ(HSYNC(cpu_transcoder));
10253
-
int vtot = I915_READ(VTOTAL(cpu_transcoder));
10254
-
int vsync = I915_READ(VSYNC(cpu_transcoder));
10251
+
u32 htot, hsync, vtot, vsync;
10255
10252
enum pipe pipe = intel_crtc->pipe;
10256
10253
10257
10254
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
···
10276
10279
i9xx_crtc_clock_get(intel_crtc, pipe_config);
10277
10280
10278
10281
mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10282
+
10283
+
cpu_transcoder = pipe_config->cpu_transcoder;
10284
+
htot = I915_READ(HTOTAL(cpu_transcoder));
10285
+
hsync = I915_READ(HSYNC(cpu_transcoder));
10286
+
vtot = I915_READ(VTOTAL(cpu_transcoder));
10287
+
vsync = I915_READ(VSYNC(cpu_transcoder));
10288
+
10279
10289
mode->hdisplay = (htot & 0xffff) + 1;
10280
10290
mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10281
10291
mode->hsync_start = (hsync & 0xffff) + 1;
+2
-2
drivers/gpu/drm/i915/intel_dp.c
+2
-2
drivers/gpu/drm/i915/intel_dp.c
···
2307
2307
I915_WRITE(pp_ctrl_reg, pp);
2308
2308
POSTING_READ(pp_ctrl_reg);
2309
2309
2310
-
intel_dp->panel_power_off_time = ktime_get_boottime();
2311
2310
wait_panel_off(intel_dp);
2311
+
intel_dp->panel_power_off_time = ktime_get_boottime();
2312
2312
2313
2313
/* We got a reference when we enabled the VDD. */
2314
2314
intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
···
5273
5273
* seems sufficient to avoid this problem.
5274
5274
*/
5275
5275
if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5276
-
vbt.t11_t12 = max_t(u16, vbt.t11_t12, 900 * 10);
5276
+
vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5277
5277
DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5278
5278
vbt.t11_t12);
5279
5279
}
+1
-1
drivers/gpu/drm/i915/intel_runtime_pm.c
+1
-1
drivers/gpu/drm/i915/intel_runtime_pm.c
+1
-1
drivers/gpu/drm/msm/dsi/dsi_host.c
+1
-1
drivers/gpu/drm/msm/dsi/dsi_host.c
+2
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
+2
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c
-2
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
-2
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+2
-13
drivers/gpu/drm/msm/msm_gem.c
+2
-13
drivers/gpu/drm/msm/msm_gem.c
···
610
610
struct dma_fence *fence;
611
611
int i, ret;
612
612
613
-
if (!exclusive) {
614
-
/* NOTE: _reserve_shared() must happen before _add_shared_fence(),
615
-
* which makes this a slightly strange place to call it. OTOH this
616
-
* is a convenient can-fail point to hook it in. (And similar to
617
-
* how etnaviv and nouveau handle this.)
618
-
*/
619
-
ret = reservation_object_reserve_shared(msm_obj->resv);
620
-
if (ret)
621
-
return ret;
622
-
}
623
-
624
613
fobj = reservation_object_get_list(msm_obj->resv);
625
614
if (!fobj || (fobj->shared_count == 0)) {
626
615
fence = reservation_object_get_excl(msm_obj->resv);
···
1034
1045
}
1035
1046
1036
1047
vaddr = msm_gem_get_vaddr(obj);
1037
-
if (!vaddr) {
1048
+
if (IS_ERR(vaddr)) {
1038
1049
msm_gem_put_iova(obj, aspace);
1039
1050
drm_gem_object_unreference(obj);
1040
-
return ERR_PTR(-ENOMEM);
1051
+
return ERR_CAST(vaddr);
1041
1052
}
1042
1053
1043
1054
if (bo)
+18
-6
drivers/gpu/drm/msm/msm_gem_submit.c
+18
-6
drivers/gpu/drm/msm/msm_gem_submit.c
···
221
221
return ret;
222
222
}
223
223
224
-
static int submit_fence_sync(struct msm_gem_submit *submit)
224
+
static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit)
225
225
{
226
226
int i, ret = 0;
227
227
228
228
for (i = 0; i < submit->nr_bos; i++) {
229
229
struct msm_gem_object *msm_obj = submit->bos[i].obj;
230
230
bool write = submit->bos[i].flags & MSM_SUBMIT_BO_WRITE;
231
+
232
+
if (!write) {
233
+
/* NOTE: _reserve_shared() must happen before
234
+
* _add_shared_fence(), which makes this a slightly
235
+
* strange place to call it. OTOH this is a
236
+
* convenient can-fail point to hook it in.
237
+
*/
238
+
ret = reservation_object_reserve_shared(msm_obj->resv);
239
+
if (ret)
240
+
return ret;
241
+
}
242
+
243
+
if (no_implicit)
244
+
continue;
231
245
232
246
ret = msm_gem_sync_object(&msm_obj->base, submit->gpu->fctx, write);
233
247
if (ret)
···
465
451
if (ret)
466
452
goto out;
467
453
468
-
if (!(args->flags & MSM_SUBMIT_NO_IMPLICIT)) {
469
-
ret = submit_fence_sync(submit);
470
-
if (ret)
471
-
goto out;
472
-
}
454
+
ret = submit_fence_sync(submit, !!(args->flags & MSM_SUBMIT_NO_IMPLICIT));
455
+
if (ret)
456
+
goto out;
473
457
474
458
ret = submit_pin_objects(submit);
475
459
if (ret)
+2
-1
drivers/gpu/drm/msm/msm_gpu.c
+2
-1
drivers/gpu/drm/msm/msm_gpu.c
···
718
718
msm_gem_put_iova(gpu->rb->bo, gpu->aspace);
719
719
msm_ringbuffer_destroy(gpu->rb);
720
720
}
721
-
if (gpu->aspace) {
721
+
722
+
if (!IS_ERR_OR_NULL(gpu->aspace)) {
722
723
gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu,
723
724
NULL, 0);
724
725
msm_gem_address_space_put(gpu->aspace);
+10
-2
drivers/gpu/drm/msm/msm_rd.c
+10
-2
drivers/gpu/drm/msm/msm_rd.c
···
111
111
112
112
wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0);
113
113
114
+
/* Note that smp_load_acquire() is not strictly required
115
+
* as CIRC_SPACE_TO_END() does not access the tail more
116
+
* than once.
117
+
*/
114
118
n = min(sz, circ_space_to_end(&rd->fifo));
115
119
memcpy(fptr, ptr, n);
116
120
117
-
fifo->head = (fifo->head + n) & (BUF_SZ - 1);
121
+
smp_store_release(&fifo->head, (fifo->head + n) & (BUF_SZ - 1));
118
122
sz -= n;
119
123
ptr += n;
120
124
···
149
145
if (ret)
150
146
goto out;
151
147
148
+
/* Note that smp_load_acquire() is not strictly required
149
+
* as CIRC_CNT_TO_END() does not access the head more than
150
+
* once.
151
+
*/
152
152
n = min_t(int, sz, circ_count_to_end(&rd->fifo));
153
153
if (copy_to_user(buf, fptr, n)) {
154
154
ret = -EFAULT;
155
155
goto out;
156
156
}
157
157
158
-
fifo->tail = (fifo->tail + n) & (BUF_SZ - 1);
158
+
smp_store_release(&fifo->tail, (fifo->tail + n) & (BUF_SZ - 1));
159
159
*ppos += n;
160
160
161
161
wake_up_all(&rd->fifo_event);
+8
drivers/gpu/ipu-v3/ipu-common.c
+8
drivers/gpu/ipu-v3/ipu-common.c
···
405
405
return -EINVAL;
406
406
}
407
407
408
+
/*
409
+
* IPUv3EX / i.MX51 has a different register layout, and on IPUv3M /
410
+
* i.MX53 channel arbitration locking doesn't seem to work properly.
411
+
* Allow enabling the lock feature on IPUv3H / i.MX6 only.
412
+
*/
413
+
if (bursts && ipu->ipu_type != IPUV3H)
414
+
return -EINVAL;
415
+
408
416
for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
409
417
if (channel->num == idmac_lock_en_info[i].chnum)
410
418
break;
+29
drivers/gpu/ipu-v3/ipu-pre.c
+29
drivers/gpu/ipu-v3/ipu-pre.c
···
73
73
#define IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v) ((v & 0x7) << 1)
74
74
#define IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v) ((v & 0x3) << 4)
75
75
76
+
#define IPU_PRE_STORE_ENG_STATUS 0x120
77
+
#define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_MASK 0xffff
78
+
#define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_X_SHIFT 0
79
+
#define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK 0x3fff
80
+
#define IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT 16
81
+
#define IPU_PRE_STORE_ENG_STATUS_STORE_FIFO_FULL (1 << 30)
82
+
#define IPU_PRE_STORE_ENG_STATUS_STORE_FIELD (1 << 31)
83
+
76
84
#define IPU_PRE_STORE_ENG_SIZE 0x130
77
85
#define IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v) ((v & 0xffff) << 0)
78
86
#define IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v) ((v & 0xffff) << 16)
···
101
93
dma_addr_t buffer_paddr;
102
94
void *buffer_virt;
103
95
bool in_use;
96
+
unsigned int safe_window_end;
104
97
};
105
98
106
99
static DEFINE_MUTEX(ipu_pre_list_mutex);
···
169
160
u32 active_bpp = info->cpp[0] >> 1;
170
161
u32 val;
171
162
163
+
/* calculate safe window for ctrl register updates */
164
+
pre->safe_window_end = height - 2;
165
+
172
166
writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
173
167
writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
174
168
···
211
199
212
200
void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
213
201
{
202
+
unsigned long timeout = jiffies + msecs_to_jiffies(5);
203
+
unsigned short current_yblock;
204
+
u32 val;
205
+
214
206
writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
207
+
208
+
do {
209
+
if (time_after(jiffies, timeout)) {
210
+
dev_warn(pre->dev, "timeout waiting for PRE safe window\n");
211
+
return;
212
+
}
213
+
214
+
val = readl(pre->regs + IPU_PRE_STORE_ENG_STATUS);
215
+
current_yblock =
216
+
(val >> IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_SHIFT) &
217
+
IPU_PRE_STORE_ENG_STATUS_STORE_BLOCK_Y_MASK;
218
+
} while (current_yblock == 0 || current_yblock >= pre->safe_window_end);
219
+
215
220
writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET);
216
221
}
217
222
+7
drivers/gpu/ipu-v3/ipu-prg.c
+7
drivers/gpu/ipu-v3/ipu-prg.c
···
14
14
#include <drm/drm_fourcc.h>
15
15
#include <linux/clk.h>
16
16
#include <linux/err.h>
17
+
#include <linux/iopoll.h>
17
18
#include <linux/mfd/syscon.h>
18
19
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
19
20
#include <linux/module.h>
···
329
328
330
329
val = IPU_PRG_REG_UPDATE_REG_UPDATE;
331
330
writel(val, prg->regs + IPU_PRG_REG_UPDATE);
331
+
332
+
/* wait for both double buffers to be filled */
333
+
readl_poll_timeout(prg->regs + IPU_PRG_STATUS, val,
334
+
(val & IPU_PRG_STATUS_BUFFER0_READY(prg_chan)) &&
335
+
(val & IPU_PRG_STATUS_BUFFER1_READY(prg_chan)),
336
+
5, 1000);
332
337
333
338
clk_disable_unprepare(prg->clk_ipg);
334
339