Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-3.6-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc fixes from Arnd Bergmann:
"Bug fixes for various ARM platforms. About half of these are for OMAP
and submitted before but did not make it into v3.6-rc2."
* tag 'fixes-3.6-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits)
ARM: ux500: don't select LEDS_GPIO for snowball
ARM: imx: build i.MX6 functions only when needed
ARM: imx: select CPU_FREQ_TABLE when needed
ARM: imx: fix ksz9021rn_phy_fixup
ARM: imx: build pm-imx5 code only when PM is enabled
ARM: omap: allow building omap44xx without SMP
ARM: dts: imx51-babbage: fix esdhc cd/wp properties
ARM: imx6: spin the cpu until hardware takes it down
ARM: ux500: Ensure probing of Audio devices when Device Tree is enabled
ARM: ux500: Fix merge error, no matching driver name for 'snd_soc_u8500'
ARM i.MX6q: Add virtual 1/3.5 dividers in the LDB clock path
ARM: Kirkwood: fix Makefile.boot
ARM: Kirkwood: Fix iconnect leds
ARM: Orion: Set eth packet size csum offload limit
ARM: mv78xx0: fix win_cfg_base prototype
ARM: OMAP: dmtimers: Fix locking issue in omap_dm_timer_request*()
ARM: mmp: fix potential NULL dereference
ARM: OMAP4: Register the OPP table only for 4430 device
cpufreq: OMAP: Handle missing frequency table on SMP systems
ARM: OMAP4: sleep: Save the complete used register stack frame
...
+175
-102
+4
-4
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+4
-4
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
···
10
10
- compatible : Should be "fsl,<chip>-esdhc"
11
11
12
12
Optional properties:
13
-
- fsl,cd-internal : Indicate to use controller internal card detection
14
-
- fsl,wp-internal : Indicate to use controller internal write protection
13
+
- fsl,cd-controller : Indicate to use controller internal card detection
14
+
- fsl,wp-controller : Indicate to use controller internal write protection
15
15
16
16
Examples:
17
17
···
19
19
compatible = "fsl,imx51-esdhc";
20
20
reg = <0x70004000 0x4000>;
21
21
interrupts = <1>;
22
-
fsl,cd-internal;
23
-
fsl,wp-internal;
22
+
fsl,cd-controller;
23
+
fsl,wp-controller;
24
24
};
25
25
26
26
esdhc@70008000 {
+1
arch/arm/Kconfig
+1
arch/arm/Kconfig
+5
arch/arm/boot/dts/am33xx.dtsi
+5
arch/arm/boot/dts/am33xx.dtsi
+2
-2
arch/arm/boot/dts/imx51-babbage.dts
+2
-2
arch/arm/boot/dts/imx51-babbage.dts
+5
-1
arch/arm/boot/dts/kirkwood-iconnect.dts
+5
-1
arch/arm/boot/dts/kirkwood-iconnect.dts
+3
arch/arm/boot/dts/twl6030.dtsi
+3
arch/arm/boot/dts/twl6030.dtsi
···
66
66
67
67
vcxio: regulator@8 {
68
68
compatible = "ti,twl6030-vcxio";
69
+
regulator-always-on;
69
70
};
70
71
71
72
vusb: regulator@9 {
···
75
74
76
75
v1v8: regulator@10 {
77
76
compatible = "ti,twl6030-v1v8";
77
+
regulator-always-on;
78
78
};
79
79
80
80
v2v1: regulator@11 {
81
81
compatible = "ti,twl6030-v2v1";
82
+
regulator-always-on;
82
83
};
83
84
84
85
clk32kg: regulator@12 {
+1
arch/arm/configs/u8500_defconfig
+1
arch/arm/configs/u8500_defconfig
+2
-1
arch/arm/mach-dove/common.c
+2
-1
arch/arm/mach-dove/common.c
···
102
102
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
103
103
{
104
104
orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
105
-
IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR);
105
+
IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
106
+
1600);
106
107
}
107
108
108
109
/*****************************************************************************
+7
arch/arm/mach-exynos/mach-origen.c
+7
arch/arm/mach-exynos/mach-origen.c
···
42
42
#include <plat/backlight.h>
43
43
#include <plat/fb.h>
44
44
#include <plat/mfc.h>
45
+
#include <plat/hdmi.h>
45
46
46
47
#include <mach/ohci.h>
47
48
#include <mach/map.h>
···
735
734
s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
736
735
}
737
736
737
+
/* I2C module and id for HDMIPHY */
738
+
static struct i2c_board_info hdmiphy_info = {
739
+
I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
740
+
};
741
+
738
742
static void s5p_tv_setup(void)
739
743
{
740
744
/* Direct HPD to HDMI chip */
···
787
781
788
782
s5p_tv_setup();
789
783
s5p_i2c_hdmiphy_set_platdata(NULL);
784
+
s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
790
785
791
786
#ifdef CONFIG_DRM_EXYNOS
792
787
s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
+7
arch/arm/mach-exynos/mach-smdkv310.c
+7
arch/arm/mach-exynos/mach-smdkv310.c
···
40
40
#include <plat/mfc.h>
41
41
#include <plat/ehci.h>
42
42
#include <plat/clock.h>
43
+
#include <plat/hdmi.h>
43
44
44
45
#include <mach/map.h>
45
46
#include <mach/ohci.h>
···
355
354
.pwm_period_ns = 1000,
356
355
};
357
356
357
+
/* I2C module and id for HDMIPHY */
358
+
static struct i2c_board_info hdmiphy_info = {
359
+
I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
360
+
};
361
+
358
362
static void s5p_tv_setup(void)
359
363
{
360
364
/* direct HPD to HDMI chip */
···
394
388
395
389
s5p_tv_setup();
396
390
s5p_i2c_hdmiphy_set_platdata(NULL);
391
+
s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
397
392
398
393
samsung_keypad_set_platdata(&smdkv310_keypad_data);
399
394
+5
-5
arch/arm/mach-imx/Makefile
+5
-5
arch/arm/mach-imx/Makefile
···
9
9
obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
10
10
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
11
11
12
-
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
12
+
imx5-pm-$(CONFIG_PM) += pm-imx5.o
13
+
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
13
14
14
15
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
15
16
clk-pfd.o clk-busy.o
···
71
70
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
72
71
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
73
72
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
74
-
obj-$(CONFIG_CPU_V7) += head-v7.o
75
-
AFLAGS_head-v7.o :=-Wa,-march=armv7-a
76
-
obj-$(CONFIG_SMP) += platsmp.o
73
+
AFLAGS_headsmp.o :=-Wa,-march=armv7-a
74
+
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
77
75
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
78
76
obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
79
77
80
78
ifeq ($(CONFIG_PM),y)
81
-
obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
79
+
obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
82
80
endif
83
81
84
82
# i.MX5 based machines
+5
-3
arch/arm/mach-imx/clk-imx6q.c
+5
-3
arch/arm/mach-imx/clk-imx6q.c
···
152
152
ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
153
153
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
154
154
pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
155
-
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2,
155
+
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
156
156
clk_max
157
157
};
158
158
···
288
288
clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
289
289
clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
290
290
clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
291
-
clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_sel", base + 0x20, 10, 1);
292
-
clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_sel", base + 0x20, 11, 1);
291
+
clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
292
+
clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1);
293
+
clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
294
+
clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1);
293
295
clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
294
296
clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
295
297
clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
arch/arm/mach-imx/head-v7.S
arch/arm/mach-imx/headsmp.S
arch/arm/mach-imx/head-v7.S
arch/arm/mach-imx/headsmp.S
+3
-20
arch/arm/mach-imx/hotplug.c
+3
-20
arch/arm/mach-imx/hotplug.c
···
42
42
: "cc");
43
43
}
44
44
45
-
static inline void cpu_leave_lowpower(void)
46
-
{
47
-
unsigned int v;
48
-
49
-
asm volatile(
50
-
"mrc p15, 0, %0, c1, c0, 0\n"
51
-
" orr %0, %0, %1\n"
52
-
" mcr p15, 0, %0, c1, c0, 0\n"
53
-
" mrc p15, 0, %0, c1, c0, 1\n"
54
-
" orr %0, %0, %2\n"
55
-
" mcr p15, 0, %0, c1, c0, 1\n"
56
-
: "=&r" (v)
57
-
: "Ir" (CR_C), "Ir" (0x40)
58
-
: "cc");
59
-
}
60
-
61
45
/*
62
46
* platform-specific code to shutdown a CPU
63
47
*
···
51
67
{
52
68
cpu_enter_lowpower();
53
69
imx_enable_cpu(cpu, false);
54
-
cpu_do_idle();
55
-
cpu_leave_lowpower();
56
70
57
-
/* We should never return from idle */
58
-
panic("cpu %d unexpectedly exit from shutdown\n", cpu);
71
+
/* spin here until hardware takes it down */
72
+
while (1)
73
+
;
59
74
}
60
75
61
76
int platform_cpu_disable(unsigned int cpu)
+2
-2
arch/arm/mach-imx/mach-imx6q.c
+2
-2
arch/arm/mach-imx/mach-imx6q.c
···
71
71
/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
72
72
static int ksz9021rn_phy_fixup(struct phy_device *phydev)
73
73
{
74
-
if (IS_ENABLED(CONFIG_PHYLIB)) {
74
+
if (IS_BUILTIN(CONFIG_PHYLIB)) {
75
75
/* min rx data delay */
76
76
phy_write(phydev, 0x0b, 0x8105);
77
77
phy_write(phydev, 0x0c, 0x0000);
···
112
112
113
113
static void __init imx6q_sabrelite_init(void)
114
114
{
115
-
if (IS_ENABLED(CONFIG_PHYLIB))
115
+
if (IS_BUILTIN(CONFIG_PHYLIB))
116
116
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
117
117
ksz9021rn_phy_fixup);
118
118
imx6q_sabrelite_cko1_setup();
+2
-1
arch/arm/mach-kirkwood/Makefile.boot
+2
-1
arch/arm/mach-kirkwood/Makefile.boot
···
7
7
dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
8
8
dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
9
9
dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
10
-
dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-qnap-ts219.dtb
10
+
dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6281.dtb
11
+
dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6282.dtb
11
12
dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
12
13
dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
13
14
dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
+2
-2
arch/arm/mach-kirkwood/common.c
+2
-2
arch/arm/mach-kirkwood/common.c
···
301
301
{
302
302
orion_ge00_init(eth_data,
303
303
GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
304
-
IRQ_KIRKWOOD_GE00_ERR);
304
+
IRQ_KIRKWOOD_GE00_ERR, 1600);
305
305
/* The interface forgets the MAC address assigned by u-boot if
306
306
the clock is turned off, so claim the clk now. */
307
307
clk_prepare_enable(ge0);
···
315
315
{
316
316
orion_ge01_init(eth_data,
317
317
GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
318
-
IRQ_KIRKWOOD_GE01_ERR);
318
+
IRQ_KIRKWOOD_GE01_ERR, 1600);
319
319
clk_prepare_enable(ge1);
320
320
}
321
321
+1
-1
arch/arm/mach-mmp/sram.c
+1
-1
arch/arm/mach-mmp/sram.c
+1
-1
arch/arm/mach-mv78xx0/addr-map.c
+1
-1
arch/arm/mach-mv78xx0/addr-map.c
···
37
37
#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
38
38
#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
39
39
40
-
static void __init __iomem *win_cfg_base(int win)
40
+
static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
41
41
{
42
42
/*
43
43
* Find the control register base address for this window.
+4
-2
arch/arm/mach-mv78xx0/common.c
+4
-2
arch/arm/mach-mv78xx0/common.c
···
213
213
{
214
214
orion_ge00_init(eth_data,
215
215
GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
216
-
IRQ_MV78XX0_GE_ERR);
216
+
IRQ_MV78XX0_GE_ERR,
217
+
MV643XX_TX_CSUM_DEFAULT_LIMIT);
217
218
}
218
219
219
220
···
225
224
{
226
225
orion_ge01_init(eth_data,
227
226
GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
228
-
NO_IRQ);
227
+
NO_IRQ,
228
+
MV643XX_TX_CSUM_DEFAULT_LIMIT);
229
229
}
230
230
231
231
+2
-1
arch/arm/mach-omap2/Kconfig
+2
-1
arch/arm/mach-omap2/Kconfig
···
62
62
select PM_OPP if PM
63
63
select USB_ARCH_HAS_EHCI if USB_SUPPORT
64
64
select ARM_CPU_SUSPEND if PM
65
-
select ARCH_NEEDS_CPU_IDLE_COUPLED
65
+
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
66
66
67
67
config SOC_OMAP5
68
68
bool "TI OMAP5"
69
69
select CPU_V7
70
70
select ARM_GIC
71
71
select HAVE_SMP
72
+
select ARM_CPU_SUSPEND if PM
72
73
73
74
comment "OMAP Core Type"
74
75
depends on ARCH_OMAP2
+2
arch/arm/mach-omap2/board-igep0020.c
+2
arch/arm/mach-omap2/board-igep0020.c
+1
arch/arm/mach-omap2/board-omap3evm.c
+1
arch/arm/mach-omap2/board-omap3evm.c
-11
arch/arm/mach-omap2/common-board-devices.c
-11
arch/arm/mach-omap2/common-board-devices.c
···
35
35
.turbo_mode = 0,
36
36
};
37
37
38
-
/*
39
-
* ADS7846 driver maybe request a gpio according to the value
40
-
* of pdata->get_pendown_state, but we have done this. So set
41
-
* get_pendown_state to avoid twice gpio requesting.
42
-
*/
43
-
static int omap3_get_pendown_state(void)
44
-
{
45
-
return !gpio_get_value(OMAP3_EVM_TS_GPIO);
46
-
}
47
-
48
38
static struct ads7846_platform_data ads7846_config = {
49
39
.x_max = 0x0fff,
50
40
.y_max = 0x0fff,
···
45
55
.debounce_rep = 1,
46
56
.gpio_pendown = -EINVAL,
47
57
.keep_vref_on = 1,
48
-
.get_pendown_state = &omap3_get_pendown_state,
49
58
};
50
59
51
60
static struct spi_board_info ads7846_spi_board_info __initdata = {
-1
arch/arm/mach-omap2/common-board-devices.h
-1
arch/arm/mach-omap2/common-board-devices.h
+2
-1
arch/arm/mach-omap2/cpuidle44xx.c
+2
-1
arch/arm/mach-omap2/cpuidle44xx.c
···
238
238
for_each_cpu(cpu_id, cpu_online_mask) {
239
239
dev = &per_cpu(omap4_idle_dev, cpu_id);
240
240
dev->cpu = cpu_id;
241
+
#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
241
242
dev->coupled_cpus = *cpu_online_mask;
242
-
243
+
#endif
243
244
cpuidle_register_driver(&omap4_idle_driver);
244
245
245
246
if (cpuidle_register_device(dev)) {
-1
arch/arm/mach-omap2/mux.h
-1
arch/arm/mach-omap2/mux.h
+1
-1
arch/arm/mach-omap2/opp4xxx_data.c
+1
-1
arch/arm/mach-omap2/opp4xxx_data.c
+5
-16
arch/arm/mach-omap2/pm34xx.c
+5
-16
arch/arm/mach-omap2/pm34xx.c
···
272
272
per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
273
273
core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
274
274
275
-
if (mpu_next_state < PWRDM_POWER_ON) {
276
-
pwrdm_pre_transition(mpu_pwrdm);
277
-
pwrdm_pre_transition(neon_pwrdm);
278
-
}
275
+
pwrdm_pre_transition(NULL);
279
276
280
277
/* PER */
281
278
if (per_next_state < PWRDM_POWER_ON) {
282
-
pwrdm_pre_transition(per_pwrdm);
283
279
per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
284
280
omap2_gpio_prepare_for_idle(per_going_off);
285
281
}
286
282
287
283
/* CORE */
288
284
if (core_next_state < PWRDM_POWER_ON) {
289
-
pwrdm_pre_transition(core_pwrdm);
290
285
if (core_next_state == PWRDM_POWER_OFF) {
291
286
omap3_core_save_context();
292
287
omap3_cm_save_context();
···
334
339
omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
335
340
OMAP3430_GR_MOD,
336
341
OMAP3_PRM_VOLTCTRL_OFFSET);
337
-
pwrdm_post_transition(core_pwrdm);
338
342
}
339
343
omap3_intc_resume_idle();
340
344
341
-
/* PER */
342
-
if (per_next_state < PWRDM_POWER_ON) {
343
-
omap2_gpio_resume_after_idle();
344
-
pwrdm_post_transition(per_pwrdm);
345
-
}
345
+
pwrdm_post_transition(NULL);
346
346
347
-
if (mpu_next_state < PWRDM_POWER_ON) {
348
-
pwrdm_post_transition(mpu_pwrdm);
349
-
pwrdm_post_transition(neon_pwrdm);
350
-
}
347
+
/* PER */
348
+
if (per_next_state < PWRDM_POWER_ON)
349
+
omap2_gpio_resume_after_idle();
351
350
}
352
351
353
352
static void omap3_pm_idle(void)
+6
-2
arch/arm/mach-omap2/sleep44xx.S
+6
-2
arch/arm/mach-omap2/sleep44xx.S
···
56
56
* The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
57
57
* It returns to the caller for CPU INACTIVE and ON power states or in case
58
58
* CPU failed to transition to targeted OFF/DORMANT state.
59
+
*
60
+
* omap4_finish_suspend() calls v7_flush_dcache_all() which doesn't save
61
+
* stack frame and it expects the caller to take care of it. Hence the entire
62
+
* stack frame is saved to avoid possible stack corruption.
59
63
*/
60
64
ENTRY(omap4_finish_suspend)
61
-
stmfd sp!, {lr}
65
+
stmfd sp!, {r4-r12, lr}
62
66
cmp r0, #0x0
63
67
beq do_WFI @ No lowpower state, jump to WFI
64
68
···
230
226
skip_scu_gp_clear:
231
227
isb
232
228
dsb
233
-
ldmfd sp!, {pc}
229
+
ldmfd sp!, {r4-r12, pc}
234
230
ENDPROC(omap4_finish_suspend)
235
231
236
232
/*
+1
arch/arm/mach-omap2/twl-common.c
+1
arch/arm/mach-omap2/twl-common.c
···
67
67
const char *pmic_type, int pmic_irq,
68
68
struct twl4030_platform_data *pmic_data)
69
69
{
70
+
omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
70
71
strncpy(pmic_i2c_board_info.type, pmic_type,
71
72
sizeof(pmic_i2c_board_info.type));
72
73
pmic_i2c_board_info.irq = pmic_irq;
+2
-1
arch/arm/mach-orion5x/common.c
+2
-1
arch/arm/mach-orion5x/common.c
+2
-1
arch/arm/mach-s3c24xx/include/mach/dma.h
+2
-1
arch/arm/mach-s3c24xx/include/mach/dma.h
-1
arch/arm/mach-ux500/Kconfig
-1
arch/arm/mach-ux500/Kconfig
+5
-5
arch/arm/mach-ux500/board-mop500-msp.c
+5
-5
arch/arm/mach-ux500/board-mop500-msp.c
···
191
191
return pdev;
192
192
}
193
193
194
-
/* Platform device for ASoC U8500 machine */
195
-
static struct platform_device snd_soc_u8500 = {
196
-
.name = "snd-soc-u8500",
194
+
/* Platform device for ASoC MOP500 machine */
195
+
static struct platform_device snd_soc_mop500 = {
196
+
.name = "snd-soc-mop500",
197
197
.id = 0,
198
198
.dev = {
199
199
.platform_data = NULL,
···
227
227
{
228
228
struct platform_device *msp1;
229
229
230
-
pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
231
-
platform_device_register(&snd_soc_u8500);
230
+
pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
231
+
platform_device_register(&snd_soc_mop500);
232
232
233
233
pr_info("Initialize MSP I2S-devices.\n");
234
234
db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
+4
arch/arm/mach-ux500/board-mop500.c
+4
arch/arm/mach-ux500/board-mop500.c
···
797
797
ARRAY_SIZE(mop500_platform_devs));
798
798
799
799
mop500_sdi_init(parent);
800
+
mop500_msp_init(parent);
800
801
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
801
802
i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
802
803
i2c_register_board_info(2, mop500_i2c2_devices,
···
805
804
806
805
mop500_uib_init();
807
806
807
+
} else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
808
+
mop500_msp_init(parent);
808
809
} else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
809
810
/*
810
811
* The HREFv60 board removed a GPIO expander and routed
···
818
815
ARRAY_SIZE(mop500_platform_devs));
819
816
820
817
hrefv60_sdi_init(parent);
818
+
mop500_msp_init(parent);
821
819
822
820
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
823
821
i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
+3
-3
arch/arm/plat-omap/dmtimer.c
+3
-3
arch/arm/plat-omap/dmtimer.c
···
189
189
timer->reserved = 1;
190
190
break;
191
191
}
192
+
spin_unlock_irqrestore(&dm_timer_lock, flags);
192
193
193
194
if (timer) {
194
195
ret = omap_dm_timer_prepare(timer);
···
198
197
timer = NULL;
199
198
}
200
199
}
201
-
spin_unlock_irqrestore(&dm_timer_lock, flags);
202
200
203
201
if (!timer)
204
202
pr_debug("%s: timer request failed!\n", __func__);
···
220
220
break;
221
221
}
222
222
}
223
+
spin_unlock_irqrestore(&dm_timer_lock, flags);
223
224
224
225
if (timer) {
225
226
ret = omap_dm_timer_prepare(timer);
···
229
228
timer = NULL;
230
229
}
231
230
}
232
-
spin_unlock_irqrestore(&dm_timer_lock, flags);
233
231
234
232
if (!timer)
235
233
pr_debug("%s: timer%d request failed!\n", __func__, id);
···
258
258
259
259
void omap_dm_timer_disable(struct omap_dm_timer *timer)
260
260
{
261
-
pm_runtime_put(&timer->pdev->dev);
261
+
pm_runtime_put_sync(&timer->pdev->dev);
262
262
}
263
263
EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
264
264
+2
-1
arch/arm/plat-omap/include/plat/cpu.h
+2
-1
arch/arm/plat-omap/include/plat/cpu.h
···
372
372
#define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \
373
373
cpu_is_omap16xx())
374
374
#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx() || \
375
-
cpu_is_omap44xx() || soc_is_omap54xx())
375
+
cpu_is_omap44xx() || soc_is_omap54xx() || \
376
+
soc_is_am33xx())
376
377
377
378
/* Various silicon revisions for omap2 */
378
379
#define OMAP242X_CLASS 0x24200024
+9
arch/arm/plat-omap/include/plat/multi.h
+9
arch/arm/plat-omap/include/plat/multi.h
+1
-3
arch/arm/plat-omap/include/plat/uncompress.h
+1
-3
arch/arm/plat-omap/include/plat/uncompress.h
···
110
110
_DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \
111
111
AM33XXUART##p)
112
112
113
-
static inline void __arch_decomp_setup(unsigned long arch_id)
113
+
static inline void arch_decomp_setup(void)
114
114
{
115
115
int port = 0;
116
116
···
197
197
DEBUG_LL_AM33XX(1, am335xevm);
198
198
} while (0);
199
199
}
200
-
201
-
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
202
200
203
201
/*
204
202
* nothing to do
+6
-2
arch/arm/plat-orion/common.c
+6
-2
arch/arm/plat-orion/common.c
···
291
291
void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
292
292
unsigned long mapbase,
293
293
unsigned long irq,
294
-
unsigned long irq_err)
294
+
unsigned long irq_err,
295
+
unsigned int tx_csum_limit)
295
296
{
296
297
fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
297
298
mapbase + 0x2000, SZ_16K - 1, irq_err);
299
+
orion_ge00_shared_data.tx_csum_limit = tx_csum_limit;
298
300
ge_complete(&orion_ge00_shared_data,
299
301
orion_ge00_resources, irq, &orion_ge00_shared,
300
302
eth_data, &orion_ge00);
···
345
343
void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
346
344
unsigned long mapbase,
347
345
unsigned long irq,
348
-
unsigned long irq_err)
346
+
unsigned long irq_err,
347
+
unsigned int tx_csum_limit)
349
348
{
350
349
fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
351
350
mapbase + 0x2000, SZ_16K - 1, irq_err);
351
+
orion_ge01_shared_data.tx_csum_limit = tx_csum_limit;
352
352
ge_complete(&orion_ge01_shared_data,
353
353
orion_ge01_resources, irq, &orion_ge01_shared,
354
354
eth_data, &orion_ge01);
+4
-2
arch/arm/plat-orion/include/plat/common.h
+4
-2
arch/arm/plat-orion/include/plat/common.h
···
39
39
void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
40
40
unsigned long mapbase,
41
41
unsigned long irq,
42
-
unsigned long irq_err);
42
+
unsigned long irq_err,
43
+
unsigned int tx_csum_limit);
43
44
44
45
void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
45
46
unsigned long mapbase,
46
47
unsigned long irq,
47
-
unsigned long irq_err);
48
+
unsigned long irq_err,
49
+
unsigned int tx_csum_limit);
48
50
49
51
void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
50
52
unsigned long mapbase,
+1
-1
arch/arm/plat-s3c24xx/dma.c
+1
-1
arch/arm/plat-s3c24xx/dma.c
+28
-1
arch/arm/plat-samsung/devs.c
+28
-1
arch/arm/plat-samsung/devs.c
···
32
32
#include <linux/platform_data/s3c-hsudc.h>
33
33
#include <linux/platform_data/s3c-hsotg.h>
34
34
35
+
#include <media/s5p_hdmi.h>
36
+
35
37
#include <asm/irq.h>
36
38
#include <asm/pmu.h>
37
39
#include <asm/mach/arch.h>
···
750
748
if (!pd) {
751
749
pd = &default_i2c_data;
752
750
753
-
if (soc_is_exynos4210())
751
+
if (soc_is_exynos4210() ||
752
+
soc_is_exynos4212() || soc_is_exynos4412())
754
753
pd->bus_num = 8;
755
754
else if (soc_is_s5pv210())
756
755
pd->bus_num = 3;
···
762
759
npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
763
760
&s5p_device_i2c_hdmiphy);
764
761
}
762
+
763
+
struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
764
+
765
+
void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
766
+
struct i2c_board_info *mhl_info, int mhl_bus)
767
+
{
768
+
struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
769
+
770
+
if (soc_is_exynos4210() ||
771
+
soc_is_exynos4212() || soc_is_exynos4412())
772
+
pd->hdmiphy_bus = 8;
773
+
else if (soc_is_s5pv210())
774
+
pd->hdmiphy_bus = 3;
775
+
else
776
+
pd->hdmiphy_bus = 0;
777
+
778
+
pd->hdmiphy_info = hdmiphy_info;
779
+
pd->mhl_info = mhl_info;
780
+
pd->mhl_bus = mhl_bus;
781
+
782
+
s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
783
+
&s5p_device_hdmi);
784
+
}
785
+
765
786
#endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
766
787
767
788
/* I2S */
+16
arch/arm/plat-samsung/include/plat/hdmi.h
+16
arch/arm/plat-samsung/include/plat/hdmi.h
···
1
+
/*
2
+
* Copyright (C) 2012 Samsung Electronics Co.Ltd
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify it
5
+
* under the terms of the GNU General Public License as published by the
6
+
* Free Software Foundation; either version 2 of the License, or (at your
7
+
* option) any later version.
8
+
*/
9
+
10
+
#ifndef __PLAT_SAMSUNG_HDMI_H
11
+
#define __PLAT_SAMSUNG_HDMI_H __FILE__
12
+
13
+
extern void s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
14
+
struct i2c_board_info *mhl_info, int mhl_bus);
15
+
16
+
#endif /* __PLAT_SAMSUNG_HDMI_H */
+1
-1
arch/arm/plat-samsung/pm.c
+1
-1
arch/arm/plat-samsung/pm.c
+3
-1
drivers/cpufreq/omap-cpufreq.c
+3
-1
drivers/cpufreq/omap-cpufreq.c
···
218
218
219
219
policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu);
220
220
221
-
if (atomic_inc_return(&freq_table_users) == 1)
221
+
if (!freq_table)
222
222
result = opp_init_cpufreq_table(mpu_dev, &freq_table);
223
223
224
224
if (result) {
···
226
226
__func__, policy->cpu, result);
227
227
goto fail_ck;
228
228
}
229
+
230
+
atomic_inc_return(&freq_table_users);
229
231
230
232
result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
231
233
if (result)
+4
include/linux/cpuidle.h
+4
include/linux/cpuidle.h
···
194
194
195
195
#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
196
196
void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a);
197
+
#else
198
+
static inline void cpuidle_coupled_parallel_barrier(struct cpuidle_device *dev, atomic_t *a)
199
+
{
200
+
}
197
201
#endif
198
202
199
203
/******************************
+2
include/linux/mv643xx_eth.h
+2
include/linux/mv643xx_eth.h