Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
usb: dwc3: Add dwc pointer to dwc3_readl/writel
Use dwc pointer in dwc3_readl() dwc3_writel() instead of passing
the dwc->regs. This would help us access the dwc structure and
log the base address in traces. There's no functional changes in
this patch, just refactoring existing APIs.
Signed-off-by: Prashanth K <prashanth.k@oss.qualcomm.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://patch.msgid.link/20260114100748.2950103-3-prashanth.k@oss.qualcomm.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Prashanth K
and committed by
Greg Kroah-Hartman
9accc68b
abdd1eef
+253
-250
+97
-97
drivers/usb/dwc3/core.c
+97
-97
drivers/usb/dwc3/core.c
···
114
114
int i;
115
115
116
116
for (i = 0; i < dwc->num_usb3_ports; i++) {
117
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i));
117
+
reg = dwc3_readl(dwc, DWC3_GUSB3PIPECTL(i));
118
118
if (enable && !dwc->dis_u3_susphy_quirk)
119
119
reg |= DWC3_GUSB3PIPECTL_SUSPHY;
120
120
else
121
121
reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
122
122
123
-
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg);
123
+
dwc3_writel(dwc, DWC3_GUSB3PIPECTL(i), reg);
124
124
}
125
125
126
126
for (i = 0; i < dwc->num_usb2_ports; i++) {
127
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
127
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i));
128
128
if (enable && !dwc->dis_u2_susphy_quirk)
129
129
reg |= DWC3_GUSB2PHYCFG_SUSPHY;
130
130
else
131
131
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
132
132
133
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
133
+
dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg);
134
134
}
135
135
}
136
136
EXPORT_SYMBOL_GPL(dwc3_enable_susphy);
···
140
140
unsigned int hw_mode;
141
141
u32 reg;
142
142
143
-
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
143
+
reg = dwc3_readl(dwc, DWC3_GCTL);
144
144
145
145
/*
146
146
* For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE and
···
155
155
156
156
reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
157
157
reg |= DWC3_GCTL_PRTCAPDIR(mode);
158
-
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
158
+
dwc3_writel(dwc, DWC3_GCTL, reg);
159
159
160
160
dwc->current_dr_role = mode;
161
161
trace_dwc3_set_prtcap(mode);
···
216
216
if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
217
217
DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
218
218
desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
219
-
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
219
+
reg = dwc3_readl(dwc, DWC3_GCTL);
220
220
reg |= DWC3_GCTL_CORESOFTRESET;
221
-
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
221
+
dwc3_writel(dwc, DWC3_GCTL, reg);
222
222
223
223
/*
224
224
* Wait for internal clocks to synchronized. DWC_usb31 and
···
228
228
*/
229
229
msleep(100);
230
230
231
-
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
231
+
reg = dwc3_readl(dwc, DWC3_GCTL);
232
232
reg &= ~DWC3_GCTL_CORESOFTRESET;
233
-
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
233
+
dwc3_writel(dwc, DWC3_GCTL, reg);
234
234
}
235
235
236
236
spin_lock_irqsave(&dwc->lock, flags);
···
254
254
phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
255
255
256
256
if (dwc->dis_split_quirk) {
257
-
reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
257
+
reg = dwc3_readl(dwc, DWC3_GUCTL3);
258
258
reg |= DWC3_GUCTL3_SPLITDISABLE;
259
-
dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
259
+
dwc3_writel(dwc, DWC3_GUCTL3, reg);
260
260
}
261
261
}
262
262
break;
···
306
306
struct dwc3 *dwc = dep->dwc;
307
307
u32 reg;
308
308
309
-
dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
310
-
DWC3_GDBGFIFOSPACE_NUM(dep->number) |
311
-
DWC3_GDBGFIFOSPACE_TYPE(type));
309
+
dwc3_writel(dwc, DWC3_GDBGFIFOSPACE,
310
+
DWC3_GDBGFIFOSPACE_NUM(dep->number) |
311
+
DWC3_GDBGFIFOSPACE_TYPE(type));
312
312
313
-
reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
313
+
reg = dwc3_readl(dwc, DWC3_GDBGFIFOSPACE);
314
314
315
315
return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
316
316
}
···
332
332
if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
333
333
return 0;
334
334
335
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
335
+
reg = dwc3_readl(dwc, DWC3_DCTL);
336
336
reg |= DWC3_DCTL_CSFTRST;
337
337
reg &= ~DWC3_DCTL_RUN_STOP;
338
338
dwc3_gadget_dctl_write_safe(dwc, reg);
···
347
347
retries = 10;
348
348
349
349
do {
350
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
350
+
reg = dwc3_readl(dwc, DWC3_DCTL);
351
351
if (!(reg & DWC3_DCTL_CSFTRST))
352
352
goto done;
353
353
···
387
387
if (dwc->fladj == 0)
388
388
return;
389
389
390
-
reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
390
+
reg = dwc3_readl(dwc, DWC3_GFLADJ);
391
391
dft = reg & DWC3_GFLADJ_30MHZ_MASK;
392
392
if (dft != dwc->fladj) {
393
393
reg &= ~DWC3_GFLADJ_30MHZ_MASK;
394
394
reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
395
-
dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
395
+
dwc3_writel(dwc, DWC3_GFLADJ, reg);
396
396
}
397
397
}
398
398
···
424
424
return;
425
425
}
426
426
427
-
reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
427
+
reg = dwc3_readl(dwc, DWC3_GUCTL);
428
428
reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
429
429
reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
430
-
dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
430
+
dwc3_writel(dwc, DWC3_GUCTL, reg);
431
431
432
432
if (DWC3_VER_IS_PRIOR(DWC3, 250A))
433
433
return;
···
455
455
*/
456
456
decr = 480000000 / rate;
457
457
458
-
reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
458
+
reg = dwc3_readl(dwc, DWC3_GFLADJ);
459
459
reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
460
460
& ~DWC3_GFLADJ_240MHZDECR
461
461
& ~DWC3_GFLADJ_240MHZDECR_PLS1;
···
466
466
if (dwc->gfladj_refclk_lpm_sel)
467
467
reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
468
468
469
-
dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
469
+
dwc3_writel(dwc, DWC3_GFLADJ, reg);
470
470
}
471
471
472
472
/**
···
569
569
570
570
evt = dwc->ev_buf;
571
571
evt->lpos = 0;
572
-
dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
573
-
lower_32_bits(evt->dma));
574
-
dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
575
-
upper_32_bits(evt->dma));
576
-
dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
577
-
DWC3_GEVNTSIZ_SIZE(evt->length));
572
+
dwc3_writel(dwc, DWC3_GEVNTADRLO(0),
573
+
lower_32_bits(evt->dma));
574
+
dwc3_writel(dwc, DWC3_GEVNTADRHI(0),
575
+
upper_32_bits(evt->dma));
576
+
dwc3_writel(dwc, DWC3_GEVNTSIZ(0),
577
+
DWC3_GEVNTSIZ_SIZE(evt->length));
578
578
579
579
/* Clear any stale event */
580
-
reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
581
-
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg);
580
+
reg = dwc3_readl(dwc, DWC3_GEVNTCOUNT(0));
581
+
dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), reg);
582
582
return 0;
583
583
}
584
584
···
593
593
* Exynos platforms may not be able to access event buffer if the
594
594
* controller failed to halt on dwc3_core_exit().
595
595
*/
596
-
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
596
+
reg = dwc3_readl(dwc, DWC3_DSTS);
597
597
if (!(reg & DWC3_DSTS_DEVCTRLHLT))
598
598
return;
599
599
···
601
601
602
602
evt->lpos = 0;
603
603
604
-
dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
605
-
dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
606
-
dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
604
+
dwc3_writel(dwc, DWC3_GEVNTADRLO(0), 0);
605
+
dwc3_writel(dwc, DWC3_GEVNTADRHI(0), 0);
606
+
dwc3_writel(dwc, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
607
607
| DWC3_GEVNTSIZ_SIZE(0));
608
608
609
609
/* Clear any stale event */
610
-
reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
611
-
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), reg);
610
+
reg = dwc3_readl(dwc, DWC3_GEVNTCOUNT(0));
611
+
dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), reg);
612
612
}
613
613
614
614
static void dwc3_core_num_eps(struct dwc3 *dwc)
···
622
622
{
623
623
struct dwc3_hwparams *parms = &dwc->hwparams;
624
624
625
-
parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
626
-
parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
627
-
parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
628
-
parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
629
-
parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
630
-
parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
631
-
parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
632
-
parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
633
-
parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
625
+
parms->hwparams0 = dwc3_readl(dwc, DWC3_GHWPARAMS0);
626
+
parms->hwparams1 = dwc3_readl(dwc, DWC3_GHWPARAMS1);
627
+
parms->hwparams2 = dwc3_readl(dwc, DWC3_GHWPARAMS2);
628
+
parms->hwparams3 = dwc3_readl(dwc, DWC3_GHWPARAMS3);
629
+
parms->hwparams4 = dwc3_readl(dwc, DWC3_GHWPARAMS4);
630
+
parms->hwparams5 = dwc3_readl(dwc, DWC3_GHWPARAMS5);
631
+
parms->hwparams6 = dwc3_readl(dwc, DWC3_GHWPARAMS6);
632
+
parms->hwparams7 = dwc3_readl(dwc, DWC3_GHWPARAMS7);
633
+
parms->hwparams8 = dwc3_readl(dwc, DWC3_GHWPARAMS8);
634
634
635
635
if (DWC3_IP_IS(DWC32))
636
-
parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
636
+
parms->hwparams9 = dwc3_readl(dwc, DWC3_GHWPARAMS9);
637
637
}
638
638
639
639
static void dwc3_config_soc_bus(struct dwc3 *dwc)
···
641
641
if (dwc->gsbuscfg0_reqinfo != DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) {
642
642
u32 reg;
643
643
644
-
reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
644
+
reg = dwc3_readl(dwc, DWC3_GSBUSCFG0);
645
645
reg &= ~DWC3_GSBUSCFG0_REQINFO(~0);
646
646
reg |= DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo);
647
-
dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, reg);
647
+
dwc3_writel(dwc, DWC3_GSBUSCFG0, reg);
648
648
}
649
649
}
650
650
···
668
668
{
669
669
u32 reg;
670
670
671
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
671
+
reg = dwc3_readl(dwc, DWC3_GUSB3PIPECTL(index));
672
672
673
673
/*
674
674
* Make sure UX_EXIT_PX is cleared as that causes issues with some
···
706
706
if (dwc->dis_del_phy_power_chg_quirk)
707
707
reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
708
708
709
-
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
709
+
dwc3_writel(dwc, DWC3_GUSB3PIPECTL(index), reg);
710
710
711
711
return 0;
712
712
}
···
715
715
{
716
716
u32 reg;
717
717
718
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
718
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(index));
719
719
720
720
/* Select the HS PHY interface */
721
721
switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
···
727
727
} else if (dwc->hsphy_interface &&
728
728
!strncmp(dwc->hsphy_interface, "ulpi", 4)) {
729
729
reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
730
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
730
+
dwc3_writel(dwc, DWC3_GUSB2PHYCFG(index), reg);
731
731
} else {
732
732
/* Relying on default value. */
733
733
if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
···
777
777
if (dwc->ulpi_ext_vbus_drv)
778
778
reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
779
779
780
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
780
+
dwc3_writel(dwc, DWC3_GUSB2PHYCFG(index), reg);
781
781
782
782
return 0;
783
783
}
···
991
991
{
992
992
u32 reg;
993
993
994
-
reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
994
+
reg = dwc3_readl(dwc, DWC3_GSNPSID);
995
995
dwc->ip = DWC3_GSNPS_ID(reg);
996
996
997
997
/* This should read as U3 followed by revision number */
998
998
if (DWC3_IP_IS(DWC3)) {
999
999
dwc->revision = reg;
1000
1000
} else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
1001
-
dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
1002
-
dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
1001
+
dwc->revision = dwc3_readl(dwc, DWC3_VER_NUMBER);
1002
+
dwc->version_type = dwc3_readl(dwc, DWC3_VER_TYPE);
1003
1003
} else {
1004
1004
return false;
1005
1005
}
···
1013
1013
unsigned int hw_mode;
1014
1014
u32 reg;
1015
1015
1016
-
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1016
+
reg = dwc3_readl(dwc, DWC3_GCTL);
1017
1017
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
1018
1018
hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1019
1019
power_opt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
···
1091
1091
if (DWC3_VER_IS_PRIOR(DWC3, 190A))
1092
1092
reg |= DWC3_GCTL_U2RSTECN;
1093
1093
1094
-
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1094
+
dwc3_writel(dwc, DWC3_GCTL, reg);
1095
1095
}
1096
1096
1097
1097
static int dwc3_core_get_phy(struct dwc3 *dwc);
···
1111
1111
int ret;
1112
1112
int i;
1113
1113
1114
-
cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
1114
+
cfg = dwc3_readl(dwc, DWC3_GSBUSCFG0);
1115
1115
1116
1116
/*
1117
1117
* Handle property "snps,incr-burst-type-adjustment".
···
1186
1186
break;
1187
1187
}
1188
1188
1189
-
dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1189
+
dwc3_writel(dwc, DWC3_GSBUSCFG0, cfg);
1190
1190
}
1191
1191
1192
1192
static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
···
1211
1211
* (3x or more) to be within the requirement.
1212
1212
*/
1213
1213
scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1214
-
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1214
+
reg = dwc3_readl(dwc, DWC3_GCTL);
1215
1215
if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1216
1216
(reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1217
1217
reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1218
1218
reg |= DWC3_GCTL_PWRDNSCALE(scale);
1219
-
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1219
+
dwc3_writel(dwc, DWC3_GCTL, reg);
1220
1220
}
1221
1221
}
1222
1222
···
1239
1239
tx_maxburst = dwc->tx_max_burst_prd;
1240
1240
1241
1241
if (rx_thr_num && rx_maxburst) {
1242
-
reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1242
+
reg = dwc3_readl(dwc, DWC3_GRXTHRCFG);
1243
1243
reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1244
1244
1245
1245
reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
···
1248
1248
reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1249
1249
reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1250
1250
1251
-
dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1251
+
dwc3_writel(dwc, DWC3_GRXTHRCFG, reg);
1252
1252
}
1253
1253
1254
1254
if (tx_thr_num && tx_maxburst) {
1255
-
reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1255
+
reg = dwc3_readl(dwc, DWC3_GTXTHRCFG);
1256
1256
reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1257
1257
1258
1258
reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
···
1261
1261
reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1262
1262
reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1263
1263
1264
-
dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1264
+
dwc3_writel(dwc, DWC3_GTXTHRCFG, reg);
1265
1265
}
1266
1266
}
1267
1267
···
1272
1272
1273
1273
if (DWC3_IP_IS(DWC3)) {
1274
1274
if (rx_thr_num && rx_maxburst) {
1275
-
reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1275
+
reg = dwc3_readl(dwc, DWC3_GRXTHRCFG);
1276
1276
reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1277
1277
1278
1278
reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
···
1281
1281
reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1282
1282
reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1283
1283
1284
-
dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1284
+
dwc3_writel(dwc, DWC3_GRXTHRCFG, reg);
1285
1285
}
1286
1286
1287
1287
if (tx_thr_num && tx_maxburst) {
1288
-
reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1288
+
reg = dwc3_readl(dwc, DWC3_GTXTHRCFG);
1289
1289
reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1290
1290
1291
1291
reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
···
1294
1294
reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1295
1295
reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1296
1296
1297
-
dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1297
+
dwc3_writel(dwc, DWC3_GTXTHRCFG, reg);
1298
1298
}
1299
1299
} else {
1300
1300
if (rx_thr_num && rx_maxburst) {
1301
-
reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1301
+
reg = dwc3_readl(dwc, DWC3_GRXTHRCFG);
1302
1302
reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1303
1303
1304
1304
reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
···
1307
1307
reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1308
1308
reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1309
1309
1310
-
dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1310
+
dwc3_writel(dwc, DWC3_GRXTHRCFG, reg);
1311
1311
}
1312
1312
1313
1313
if (tx_thr_num && tx_maxburst) {
1314
-
reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1314
+
reg = dwc3_readl(dwc, DWC3_GTXTHRCFG);
1315
1315
reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1316
1316
1317
1317
reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
···
1320
1320
reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1321
1321
reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1322
1322
1323
-
dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1323
+
dwc3_writel(dwc, DWC3_GTXTHRCFG, reg);
1324
1324
}
1325
1325
}
1326
1326
}
···
1343
1343
* Write Linux Version Code to our GUID register so it's easy to figure
1344
1344
* out which kernel version a bug was found.
1345
1345
*/
1346
-
dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1346
+
dwc3_writel(dwc, DWC3_GUID, LINUX_VERSION_CODE);
1347
1347
1348
1348
ret = dwc3_phy_setup(dwc);
1349
1349
if (ret)
···
1408
1408
* DWC_usb31 controller.
1409
1409
*/
1410
1410
if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1411
-
reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1411
+
reg = dwc3_readl(dwc, DWC3_GUCTL2);
1412
1412
reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1413
-
dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1413
+
dwc3_writel(dwc, DWC3_GUCTL2, reg);
1414
1414
}
1415
1415
1416
1416
/*
···
1423
1423
* setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0.
1424
1424
*/
1425
1425
if (DWC3_VER_IS(DWC3, 320A)) {
1426
-
reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1426
+
reg = dwc3_readl(dwc, DWC3_GUCTL2);
1427
1427
reg &= ~DWC3_GUCTL2_LC_TIMER;
1428
-
dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1428
+
dwc3_writel(dwc, DWC3_GUCTL2, reg);
1429
1429
}
1430
1430
1431
1431
/*
···
1438
1438
* legacy ULPI PHYs.
1439
1439
*/
1440
1440
if (dwc->resume_hs_terminations) {
1441
-
reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1441
+
reg = dwc3_readl(dwc, DWC3_GUCTL1);
1442
1442
reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1443
-
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1443
+
dwc3_writel(dwc, DWC3_GUCTL1, reg);
1444
1444
}
1445
1445
1446
1446
if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1447
-
reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1447
+
reg = dwc3_readl(dwc, DWC3_GUCTL1);
1448
1448
1449
1449
/*
1450
1450
* Enable hardware control of sending remote wakeup
···
1479
1479
reg &= ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1480
1480
}
1481
1481
1482
-
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1482
+
dwc3_writel(dwc, DWC3_GUCTL1, reg);
1483
1483
}
1484
1484
1485
1485
dwc3_config_threshold(dwc);
···
1490
1490
int i;
1491
1491
1492
1492
for (i = 0; i < dwc->num_usb3_ports; i++) {
1493
-
reg = dwc3_readl(dwc->regs, DWC3_LLUCTL(i));
1493
+
reg = dwc3_readl(dwc, DWC3_LLUCTL(i));
1494
1494
reg |= DWC3_LLUCTL_FORCE_GEN1;
1495
-
dwc3_writel(dwc->regs, DWC3_LLUCTL(i), reg);
1495
+
dwc3_writel(dwc, DWC3_LLUCTL(i), reg);
1496
1496
}
1497
1497
}
1498
1498
···
1511
1511
* function is available only from version 1.70a.
1512
1512
*/
1513
1513
if (DWC3_VER_IS_WITHIN(DWC31, 170A, 180A)) {
1514
-
reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1514
+
reg = dwc3_readl(dwc, DWC3_GUCTL3);
1515
1515
reg |= DWC3_GUCTL3_USB20_RETRY_DISABLE;
1516
-
dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1516
+
dwc3_writel(dwc, DWC3_GUCTL3, reg);
1517
1517
}
1518
1518
1519
1519
return 0;
···
2437
2437
int ret;
2438
2438
2439
2439
if (!pm_runtime_suspended(dwc->dev) && !PMSG_IS_AUTO(msg)) {
2440
-
dwc->susphy_state = (dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)) &
2440
+
dwc->susphy_state = (dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0)) &
2441
2441
DWC3_GUSB2PHYCFG_SUSPHY) ||
2442
-
(dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)) &
2442
+
(dwc3_readl(dwc, DWC3_GUSB3PIPECTL(0)) &
2443
2443
DWC3_GUSB3PIPECTL_SUSPHY);
2444
2444
/*
2445
2445
* TI AM62 platform requires SUSPHY to be
···
2469
2469
if (dwc->dis_u2_susphy_quirk ||
2470
2470
dwc->dis_enblslpm_quirk) {
2471
2471
for (i = 0; i < dwc->num_usb2_ports; i++) {
2472
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
2472
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i));
2473
2473
reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
2474
2474
DWC3_GUSB2PHYCFG_SUSPHY;
2475
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
2475
+
dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg);
2476
2476
}
2477
2477
2478
2478
/* Give some time for USB2 PHY to suspend */
···
2532
2532
}
2533
2533
/* Restore GUSB2PHYCFG bits that were modified in suspend */
2534
2534
for (i = 0; i < dwc->num_usb2_ports; i++) {
2535
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
2535
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(i));
2536
2536
if (dwc->dis_u2_susphy_quirk)
2537
2537
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2538
2538
2539
2539
if (dwc->dis_enblslpm_quirk)
2540
2540
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2541
2541
2542
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
2542
+
dwc3_writel(dwc, DWC3_GUSB2PHYCFG(i), reg);
2543
2543
}
2544
2544
2545
2545
for (i = 0; i < dwc->num_usb2_ports; i++)
···
2721
2721
2722
2722
if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2723
2723
dwc->dis_split_quirk) {
2724
-
reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2724
+
reg = dwc3_readl(dwc, DWC3_GUCTL3);
2725
2725
reg |= DWC3_GUCTL3_SPLITDISABLE;
2726
-
dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2726
+
dwc3_writel(dwc, DWC3_GUCTL3, reg);
2727
2727
}
2728
2728
}
2729
2729
EXPORT_SYMBOL_GPL(dwc3_pm_complete);
+16
-16
drivers/usb/dwc3/debugfs.c
+16
-16
drivers/usb/dwc3/debugfs.c
···
296
296
297
297
reg = DWC3_GDBGLSPMUX_HOSTSELECT(sel);
298
298
299
-
dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);
300
-
val = dwc3_readl(dwc->regs, DWC3_GDBGLSP);
299
+
dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg);
300
+
val = dwc3_readl(dwc, DWC3_GDBGLSP);
301
301
seq_printf(s, "GDBGLSP[%d] = 0x%08x\n", sel, val);
302
302
303
303
if (dbc_enabled && sel < 256) {
304
304
reg |= DWC3_GDBGLSPMUX_ENDBC;
305
-
dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);
306
-
val = dwc3_readl(dwc->regs, DWC3_GDBGLSP);
305
+
dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg);
306
+
val = dwc3_readl(dwc, DWC3_GDBGLSP);
307
307
seq_printf(s, "GDBGLSP_DBC[%d] = 0x%08x\n", sel, val);
308
308
}
309
309
}
···
316
316
317
317
for (i = 0; i < 16; i++) {
318
318
reg = DWC3_GDBGLSPMUX_DEVSELECT(i);
319
-
dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);
320
-
reg = dwc3_readl(dwc->regs, DWC3_GDBGLSP);
319
+
dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg);
320
+
reg = dwc3_readl(dwc, DWC3_GDBGLSP);
321
321
seq_printf(s, "GDBGLSP[%d] = 0x%08x\n", i, reg);
322
322
}
323
323
}
···
335
335
return ret;
336
336
337
337
spin_lock_irqsave(&dwc->lock, flags);
338
-
reg = dwc3_readl(dwc->regs, DWC3_GSTS);
338
+
reg = dwc3_readl(dwc, DWC3_GSTS);
339
339
current_mode = DWC3_GSTS_CURMOD(reg);
340
340
341
341
switch (current_mode) {
···
406
406
return ret;
407
407
408
408
spin_lock_irqsave(&dwc->lock, flags);
409
-
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
409
+
reg = dwc3_readl(dwc, DWC3_GCTL);
410
410
spin_unlock_irqrestore(&dwc->lock, flags);
411
411
412
412
mode = DWC3_GCTL_PRTCAP(reg);
···
478
478
return ret;
479
479
480
480
spin_lock_irqsave(&dwc->lock, flags);
481
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
481
+
reg = dwc3_readl(dwc, DWC3_DCTL);
482
482
reg &= DWC3_DCTL_TSTCTRL_MASK;
483
483
reg >>= 1;
484
484
spin_unlock_irqrestore(&dwc->lock, flags);
···
577
577
return ret;
578
578
579
579
spin_lock_irqsave(&dwc->lock, flags);
580
-
reg = dwc3_readl(dwc->regs, DWC3_GSTS);
580
+
reg = dwc3_readl(dwc, DWC3_GSTS);
581
581
if (DWC3_GSTS_CURMOD(reg) != DWC3_GSTS_CURMOD_DEVICE) {
582
582
seq_puts(s, "Not available\n");
583
583
spin_unlock_irqrestore(&dwc->lock, flags);
···
585
585
return 0;
586
586
}
587
587
588
-
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
588
+
reg = dwc3_readl(dwc, DWC3_DSTS);
589
589
state = DWC3_DSTS_USBLNKST(reg);
590
590
speed = reg & DWC3_DSTS_CONNECTSPD;
591
591
···
639
639
return ret;
640
640
641
641
spin_lock_irqsave(&dwc->lock, flags);
642
-
reg = dwc3_readl(dwc->regs, DWC3_GSTS);
642
+
reg = dwc3_readl(dwc, DWC3_GSTS);
643
643
if (DWC3_GSTS_CURMOD(reg) != DWC3_GSTS_CURMOD_DEVICE) {
644
644
spin_unlock_irqrestore(&dwc->lock, flags);
645
645
pm_runtime_put_sync(dwc->dev);
646
646
return -EINVAL;
647
647
}
648
648
649
-
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
649
+
reg = dwc3_readl(dwc, DWC3_DSTS);
650
650
speed = reg & DWC3_DSTS_CONNECTSPD;
651
651
652
652
if (speed < DWC3_DSTS_SUPERSPEED &&
···
942
942
943
943
spin_lock_irqsave(&dwc->lock, flags);
944
944
reg = DWC3_GDBGLSPMUX_EPSELECT(dep->number);
945
-
dwc3_writel(dwc->regs, DWC3_GDBGLSPMUX, reg);
945
+
dwc3_writel(dwc, DWC3_GDBGLSPMUX, reg);
946
946
947
-
lower_32_bits = dwc3_readl(dwc->regs, DWC3_GDBGEPINFO0);
948
-
upper_32_bits = dwc3_readl(dwc->regs, DWC3_GDBGEPINFO1);
947
+
lower_32_bits = dwc3_readl(dwc, DWC3_GDBGEPINFO0);
948
+
upper_32_bits = dwc3_readl(dwc, DWC3_GDBGEPINFO1);
949
949
950
950
ep_info = ((u64)upper_32_bits << 32) | lower_32_bits;
951
951
seq_printf(s, "0x%016llx\n", ep_info);
+38
-38
drivers/usb/dwc3/drd.c
+38
-38
drivers/usb/dwc3/drd.c
···
18
18
19
19
static void dwc3_otg_disable_events(struct dwc3 *dwc, u32 disable_mask)
20
20
{
21
-
u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN);
21
+
u32 reg = dwc3_readl(dwc, DWC3_OEVTEN);
22
22
23
23
reg &= ~(disable_mask);
24
-
dwc3_writel(dwc->regs, DWC3_OEVTEN, reg);
24
+
dwc3_writel(dwc, DWC3_OEVTEN, reg);
25
25
}
26
26
27
27
static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask)
28
28
{
29
-
u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN);
29
+
u32 reg = dwc3_readl(dwc, DWC3_OEVTEN);
30
30
31
31
reg |= (enable_mask);
32
-
dwc3_writel(dwc->regs, DWC3_OEVTEN, reg);
32
+
dwc3_writel(dwc, DWC3_OEVTEN, reg);
33
33
}
34
34
35
35
static void dwc3_otg_clear_events(struct dwc3 *dwc)
36
36
{
37
-
u32 reg = dwc3_readl(dwc->regs, DWC3_OEVT);
37
+
u32 reg = dwc3_readl(dwc, DWC3_OEVT);
38
38
39
-
dwc3_writel(dwc->regs, DWC3_OEVTEN, reg);
39
+
dwc3_writel(dwc, DWC3_OEVTEN, reg);
40
40
}
41
41
42
42
#define DWC3_OTG_ALL_EVENTS (DWC3_OEVTEN_XHCIRUNSTPSETEN | \
···
72
72
struct dwc3 *dwc = _dwc;
73
73
irqreturn_t ret = IRQ_NONE;
74
74
75
-
reg = dwc3_readl(dwc->regs, DWC3_OEVT);
75
+
reg = dwc3_readl(dwc, DWC3_OEVT);
76
76
if (reg) {
77
77
/* ignore non OTG events, we can't disable them in OEVTEN */
78
78
if (!(reg & DWC3_OTG_ALL_EVENTS)) {
79
-
dwc3_writel(dwc->regs, DWC3_OEVT, reg);
79
+
dwc3_writel(dwc, DWC3_OEVT, reg);
80
80
return IRQ_NONE;
81
81
}
82
82
83
83
if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST &&
84
84
!(reg & DWC3_OEVT_DEVICEMODE))
85
85
dwc->otg_restart_host = true;
86
-
dwc3_writel(dwc->regs, DWC3_OEVT, reg);
86
+
dwc3_writel(dwc, DWC3_OEVT, reg);
87
87
ret = IRQ_WAKE_THREAD;
88
88
}
89
89
···
100
100
* the signal outputs sent to the PHY, the OTG FSM logic of the
101
101
* core and also the resets to the VBUS filters inside the core.
102
102
*/
103
-
reg = dwc3_readl(dwc->regs, DWC3_OCFG);
103
+
reg = dwc3_readl(dwc, DWC3_OCFG);
104
104
reg |= DWC3_OCFG_SFTRSTMASK;
105
-
dwc3_writel(dwc->regs, DWC3_OCFG, reg);
105
+
dwc3_writel(dwc, DWC3_OCFG, reg);
106
106
107
107
/* Disable hibernation for simplicity */
108
-
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
108
+
reg = dwc3_readl(dwc, DWC3_GCTL);
109
109
reg &= ~DWC3_GCTL_GBLHIBERNATIONEN;
110
-
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
110
+
dwc3_writel(dwc, DWC3_GCTL, reg);
111
111
112
112
/*
113
113
* Initialize OTG registers as per
114
114
* Figure 11-4 OTG Driver Overall Programming Flow
115
115
*/
116
116
/* OCFG.SRPCap = 0, OCFG.HNPCap = 0 */
117
-
reg = dwc3_readl(dwc->regs, DWC3_OCFG);
117
+
reg = dwc3_readl(dwc, DWC3_OCFG);
118
118
reg &= ~(DWC3_OCFG_SRPCAP | DWC3_OCFG_HNPCAP);
119
-
dwc3_writel(dwc->regs, DWC3_OCFG, reg);
119
+
dwc3_writel(dwc, DWC3_OCFG, reg);
120
120
/* OEVT = FFFF */
121
121
dwc3_otg_clear_events(dwc);
122
122
/* OEVTEN = 0 */
···
127
127
* OCTL.PeriMode = 1, OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0,
128
128
* OCTL.HNPReq = 0
129
129
*/
130
-
reg = dwc3_readl(dwc->regs, DWC3_OCTL);
130
+
reg = dwc3_readl(dwc, DWC3_OCTL);
131
131
reg |= DWC3_OCTL_PERIMODE;
132
132
reg &= ~(DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN |
133
133
DWC3_OCTL_HNPREQ);
134
-
dwc3_writel(dwc->regs, DWC3_OCTL, reg);
134
+
dwc3_writel(dwc, DWC3_OCTL, reg);
135
135
}
136
136
137
137
static int dwc3_otg_get_irq(struct dwc3 *dwc)
···
175
175
/* GCTL.PrtCapDir=2'b11 */
176
176
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_OTG, true);
177
177
/* GUSB2PHYCFG0.SusPHY=0 */
178
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
178
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0));
179
179
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
180
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
180
+
dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg);
181
181
182
182
/* Initialize OTG registers */
183
183
dwc3_otgregs_init(dwc);
···
203
203
* OCTL.PeriMode=0, OCTL.TermSelDLPulse = 0,
204
204
* OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0
205
205
*/
206
-
reg = dwc3_readl(dwc->regs, DWC3_OCTL);
206
+
reg = dwc3_readl(dwc, DWC3_OCTL);
207
207
reg &= ~(DWC3_OCTL_PERIMODE | DWC3_OCTL_TERMSELIDPULSE |
208
208
DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN);
209
-
dwc3_writel(dwc->regs, DWC3_OCTL, reg);
209
+
dwc3_writel(dwc, DWC3_OCTL, reg);
210
210
211
211
/*
212
212
* OCFG.DisPrtPwrCutoff = 0/1
213
213
*/
214
-
reg = dwc3_readl(dwc->regs, DWC3_OCFG);
214
+
reg = dwc3_readl(dwc, DWC3_OCFG);
215
215
reg &= ~DWC3_OCFG_DISPWRCUTTOFF;
216
-
dwc3_writel(dwc->regs, DWC3_OCFG, reg);
216
+
dwc3_writel(dwc, DWC3_OCFG, reg);
217
217
218
218
/*
219
219
* OCFG.SRPCap = 1, OCFG.HNPCap = GHWPARAMS6.HNP_CAP
···
229
229
230
230
/* GUSB2PHYCFG.ULPIAutoRes = 1/0, GUSB2PHYCFG.SusPHY = 1 */
231
231
if (!dwc->dis_u2_susphy_quirk) {
232
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
232
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0));
233
233
reg |= DWC3_GUSB2PHYCFG_SUSPHY;
234
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
234
+
dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg);
235
235
}
236
236
237
237
/* Set Port Power to enable VBUS: OCTL.PrtPwrCtl = 1 */
238
-
reg = dwc3_readl(dwc->regs, DWC3_OCTL);
238
+
reg = dwc3_readl(dwc, DWC3_OCTL);
239
239
reg |= DWC3_OCTL_PRTPWRCTL;
240
-
dwc3_writel(dwc->regs, DWC3_OCTL, reg);
240
+
dwc3_writel(dwc, DWC3_OCTL, reg);
241
241
}
242
242
243
243
/* should be called after Host controller driver is stopped */
···
258
258
*/
259
259
260
260
/* OCTL.HstSetHNPEn = 0, OCTL.PrtPwrCtl=0 */
261
-
reg = dwc3_readl(dwc->regs, DWC3_OCTL);
261
+
reg = dwc3_readl(dwc, DWC3_OCTL);
262
262
reg &= ~(DWC3_OCTL_HSTSETHNPEN | DWC3_OCTL_PRTPWRCTL);
263
-
dwc3_writel(dwc->regs, DWC3_OCTL, reg);
263
+
dwc3_writel(dwc, DWC3_OCTL, reg);
264
264
}
265
265
266
266
/* should be called before the gadget controller driver is started */
···
274
274
* OCFG.HNPCap = GHWPARAMS6.HNP_CAP, OCFG.SRPCap = 1
275
275
* but we keep them 0 for simple dual-role operation.
276
276
*/
277
-
reg = dwc3_readl(dwc->regs, DWC3_OCFG);
277
+
reg = dwc3_readl(dwc, DWC3_OCFG);
278
278
/* OCFG.OTGSftRstMsk = 0/1 */
279
279
reg |= DWC3_OCFG_SFTRSTMASK;
280
-
dwc3_writel(dwc->regs, DWC3_OCFG, reg);
280
+
dwc3_writel(dwc, DWC3_OCFG, reg);
281
281
/*
282
282
* OCTL.PeriMode = 1
283
283
* OCTL.TermSelDLPulse = 0/1, OCTL.HNPReq = 0
284
284
* OCTL.DevSetHNPEn = 0, OCTL.HstSetHNPEn = 0
285
285
*/
286
-
reg = dwc3_readl(dwc->regs, DWC3_OCTL);
286
+
reg = dwc3_readl(dwc, DWC3_OCTL);
287
287
reg |= DWC3_OCTL_PERIMODE;
288
288
reg &= ~(DWC3_OCTL_TERMSELIDPULSE | DWC3_OCTL_HNPREQ |
289
289
DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HSTSETHNPEN);
290
-
dwc3_writel(dwc->regs, DWC3_OCTL, reg);
290
+
dwc3_writel(dwc, DWC3_OCTL, reg);
291
291
/* OEVTEN.OTGBDevSesVldDetEvntEn = 1 */
292
292
dwc3_otg_enable_events(dwc, DWC3_OEVTEN_BDEVSESSVLDDETEN);
293
293
/* GUSB2PHYCFG.ULPIAutoRes = 0, GUSB2PHYCFG0.SusPHY = 1 */
294
294
if (!dwc->dis_u2_susphy_quirk) {
295
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
295
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0));
296
296
reg |= DWC3_GUSB2PHYCFG_SUSPHY;
297
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
297
+
dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg);
298
298
}
299
299
/* GCTL.GblHibernationEn = 0. Already 0. */
300
300
}
···
319
319
DWC3_OEVTEN_BDEVBHOSTENDEN);
320
320
321
321
/* OCTL.DevSetHNPEn = 0, OCTL.HNPReq = 0, OCTL.PeriMode=1 */
322
-
reg = dwc3_readl(dwc->regs, DWC3_OCTL);
322
+
reg = dwc3_readl(dwc, DWC3_OCTL);
323
323
reg &= ~(DWC3_OCTL_DEVSETHNPEN | DWC3_OCTL_HNPREQ);
324
324
reg |= DWC3_OCTL_PERIMODE;
325
-
dwc3_writel(dwc->regs, DWC3_OCTL, reg);
325
+
dwc3_writel(dwc, DWC3_OCTL, reg);
326
326
}
327
327
328
328
void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
···
341
341
return;
342
342
343
343
if (!ignore_idstatus) {
344
-
reg = dwc3_readl(dwc->regs, DWC3_OSTS);
344
+
reg = dwc3_readl(dwc, DWC3_OSTS);
345
345
id = !!(reg & DWC3_OSTS_CONIDSTS);
346
346
347
347
dwc->desired_otg_role = id ? DWC3_OTG_ROLE_DEVICE :
+10
-10
drivers/usb/dwc3/ep0.c
+10
-10
drivers/usb/dwc3/ep0.c
···
361
361
362
362
if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
363
363
(dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
364
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
364
+
reg = dwc3_readl(dwc, DWC3_DCTL);
365
365
if (reg & DWC3_DCTL_INITU1ENA)
366
366
usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
367
367
if (reg & DWC3_DCTL_INITU2ENA)
···
417
417
if (set && dwc->dis_u1_entry_quirk)
418
418
return -EINVAL;
419
419
420
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
420
+
reg = dwc3_readl(dwc, DWC3_DCTL);
421
421
if (set)
422
422
reg |= DWC3_DCTL_INITU1ENA;
423
423
else
424
424
reg &= ~DWC3_DCTL_INITU1ENA;
425
-
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
425
+
dwc3_writel(dwc, DWC3_DCTL, reg);
426
426
427
427
return 0;
428
428
}
···
441
441
if (set && dwc->dis_u2_entry_quirk)
442
442
return -EINVAL;
443
443
444
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
444
+
reg = dwc3_readl(dwc, DWC3_DCTL);
445
445
if (set)
446
446
reg |= DWC3_DCTL_INITU2ENA;
447
447
else
448
448
reg &= ~DWC3_DCTL_INITU2ENA;
449
-
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
449
+
dwc3_writel(dwc, DWC3_DCTL, reg);
450
450
451
451
return 0;
452
452
}
···
612
612
return -EINVAL;
613
613
}
614
614
615
-
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
615
+
reg = dwc3_readl(dwc, DWC3_DCFG);
616
616
reg &= ~(DWC3_DCFG_DEVADDR_MASK);
617
617
reg |= DWC3_DCFG_DEVADDR(addr);
618
-
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
618
+
dwc3_writel(dwc, DWC3_DCFG, reg);
619
619
620
620
if (addr)
621
621
usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
···
672
672
* Enable transition to U1/U2 state when
673
673
* nothing is pending from application.
674
674
*/
675
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
675
+
reg = dwc3_readl(dwc, DWC3_DCTL);
676
676
if (!dwc->dis_u1_entry_quirk)
677
677
reg |= DWC3_DCTL_ACCEPTU1ENA;
678
678
if (!dwc->dis_u2_entry_quirk)
679
679
reg |= DWC3_DCTL_ACCEPTU2ENA;
680
-
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
680
+
dwc3_writel(dwc, DWC3_DCTL, reg);
681
681
}
682
682
break;
683
683
···
717
717
dwc->u2sel = le16_to_cpu(timing.u2sel);
718
718
dwc->u2pel = le16_to_cpu(timing.u2pel);
719
719
720
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
720
+
reg = dwc3_readl(dwc, DWC3_DCTL);
721
721
if (reg & DWC3_DCTL_INITU2ENA)
722
722
param = dwc->u2pel;
723
723
if (reg & DWC3_DCTL_INITU1ENA)
+80
-80
drivers/usb/dwc3/gadget.c
+80
-80
drivers/usb/dwc3/gadget.c
···
42
42
{
43
43
u32 reg;
44
44
45
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
45
+
reg = dwc3_readl(dwc, DWC3_DCTL);
46
46
reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47
47
48
48
switch (mode) {
···
73
73
{
74
74
u32 reg;
75
75
76
-
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
76
+
reg = dwc3_readl(dwc, DWC3_DSTS);
77
77
78
78
return DWC3_DSTS_USBLNKST(reg);
79
79
}
···
97
97
*/
98
98
if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
99
99
while (--retries) {
100
-
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
100
+
reg = dwc3_readl(dwc, DWC3_DSTS);
101
101
if (reg & DWC3_DSTS_DCNRD)
102
102
udelay(5);
103
103
else
···
108
108
return -ETIMEDOUT;
109
109
}
110
110
111
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
111
+
reg = dwc3_readl(dwc, DWC3_DCTL);
112
112
reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113
113
114
114
/* set no action before sending new link state change */
115
-
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
115
+
dwc3_writel(dwc, DWC3_DCTL, reg);
116
116
117
117
/* set requested state */
118
118
reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119
-
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
119
+
dwc3_writel(dwc, DWC3_DCTL, reg);
120
120
121
121
/*
122
122
* The following code is racy when called from dwc3_gadget_wakeup,
···
128
128
/* wait for a change in DSTS */
129
129
retries = 10000;
130
130
while (--retries) {
131
-
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
131
+
reg = dwc3_readl(dwc, DWC3_DSTS);
132
132
133
133
if (DWC3_DSTS_USBLNKST(reg) == state)
134
134
return 0;
···
260
260
int ret = 0;
261
261
u32 reg;
262
262
263
-
dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
264
-
dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
263
+
dwc3_writel(dwc, DWC3_DGCMDPAR, param);
264
+
dwc3_writel(dwc, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
265
265
266
266
do {
267
-
reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
267
+
reg = dwc3_readl(dwc, DWC3_DGCMD);
268
268
if (!(reg & DWC3_DGCMD_CMDACT)) {
269
269
status = DWC3_DGCMD_STATUS(reg);
270
270
if (status)
···
334
334
*/
335
335
if (dwc->gadget->speed <= USB_SPEED_HIGH ||
336
336
DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) {
337
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
337
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0));
338
338
if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
339
339
saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
340
340
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
···
346
346
}
347
347
348
348
if (saved_config)
349
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
349
+
dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg);
350
350
}
351
351
352
352
/*
···
356
356
* improve performance.
357
357
*/
358
358
if (DWC3_DEPCMD_CMD(cmd) != DWC3_DEPCMD_UPDATETRANSFER) {
359
-
dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(epnum), params->param0);
360
-
dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(epnum), params->param1);
361
-
dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(epnum), params->param2);
359
+
dwc3_writel(dwc, DWC3_DEPCMDPAR0(epnum), params->param0);
360
+
dwc3_writel(dwc, DWC3_DEPCMDPAR1(epnum), params->param1);
361
+
dwc3_writel(dwc, DWC3_DEPCMDPAR2(epnum), params->param2);
362
362
}
363
363
364
364
/*
···
382
382
else
383
383
cmd |= DWC3_DEPCMD_CMDACT;
384
384
385
-
dwc3_writel(dwc->regs, DWC3_DEPCMD(epnum), cmd);
385
+
dwc3_writel(dwc, DWC3_DEPCMD(epnum), cmd);
386
386
387
387
if (!(cmd & DWC3_DEPCMD_CMDACT) ||
388
388
(DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER &&
···
392
392
}
393
393
394
394
do {
395
-
reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(epnum));
395
+
reg = dwc3_readl(dwc, DWC3_DEPCMD(epnum));
396
396
if (!(reg & DWC3_DEPCMD_CMDACT)) {
397
397
cmd_status = DWC3_DEPCMD_STATUS(reg);
398
398
···
448
448
mdelay(1);
449
449
450
450
if (saved_config) {
451
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
451
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0));
452
452
reg |= saved_config;
453
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
453
+
dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg);
454
454
}
455
455
456
456
return ret;
···
727
727
u32 reg;
728
728
729
729
/* Check if TXFIFOs start at non-zero addr */
730
-
reg = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
730
+
reg = dwc3_readl(dwc, DWC3_GTXFIFOSIZ(0));
731
731
fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(reg);
732
732
733
733
ram_depth -= (fifo_0_start >> 16);
···
755
755
756
756
/* Read ep0IN related TXFIFO size */
757
757
dep = dwc->eps[1];
758
-
size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
758
+
size = dwc3_readl(dwc, DWC3_GTXFIFOSIZ(0));
759
759
if (DWC3_IP_IS(DWC3))
760
760
fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
761
761
else
···
770
770
771
771
/* Don't change TXFRAMNUM on usb31 version */
772
772
size = DWC3_IP_IS(DWC3) ? 0 :
773
-
dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
773
+
dwc3_readl(dwc, DWC3_GTXFIFOSIZ(num >> 1)) &
774
774
DWC31_GTXFIFOSIZ_TXFRAMNUM;
775
775
776
-
dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
776
+
dwc3_writel(dwc, DWC3_GTXFIFOSIZ(num >> 1), size);
777
777
dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
778
778
}
779
779
dwc->num_ep_resized = 0;
···
876
876
fifo_size++;
877
877
878
878
/* Check if TXFIFOs start at non-zero addr */
879
-
tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
879
+
tmp = dwc3_readl(dwc, DWC3_GTXFIFOSIZ(0));
880
880
fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
881
881
882
882
fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
···
899
899
return -ENOMEM;
900
900
}
901
901
902
-
dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
902
+
dwc3_writel(dwc, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
903
903
dep->flags |= DWC3_EP_TXFIFO_RESIZED;
904
904
dwc->num_ep_resized++;
905
905
···
943
943
dep->type = usb_endpoint_type(desc);
944
944
dep->flags |= DWC3_EP_ENABLED;
945
945
946
-
reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
946
+
reg = dwc3_readl(dwc, DWC3_DALEPENA);
947
947
reg |= DWC3_DALEPENA_EP(dep->number);
948
-
dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
948
+
dwc3_writel(dwc, DWC3_DALEPENA, reg);
949
949
950
950
dep->trb_dequeue = 0;
951
951
dep->trb_enqueue = 0;
···
1080
1080
if (dep->flags & DWC3_EP_STALL)
1081
1081
__dwc3_gadget_ep_set_halt(dep, 0, false);
1082
1082
1083
-
reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
1083
+
reg = dwc3_readl(dwc, DWC3_DALEPENA);
1084
1084
reg &= ~DWC3_DALEPENA_EP(dep->number);
1085
-
dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
1085
+
dwc3_writel(dwc, DWC3_DALEPENA, reg);
1086
1086
1087
1087
dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
1088
1088
···
1743
1743
{
1744
1744
u32 reg;
1745
1745
1746
-
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1746
+
reg = dwc3_readl(dwc, DWC3_DSTS);
1747
1747
return DWC3_DSTS_SOFFN(reg);
1748
1748
}
1749
1749
···
2351
2351
if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2352
2352
return;
2353
2353
2354
-
reg = dwc3_readl(dwc->regs, DWC3_DEVTEN);
2354
+
reg = dwc3_readl(dwc, DWC3_DEVTEN);
2355
2355
if (set)
2356
2356
reg |= DWC3_DEVTEN_ULSTCNGEN;
2357
2357
else
2358
2358
reg &= ~DWC3_DEVTEN_ULSTCNGEN;
2359
2359
2360
-
dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2360
+
dwc3_writel(dwc, DWC3_DEVTEN, reg);
2361
2361
}
2362
2362
2363
2363
static int dwc3_gadget_get_frame(struct usb_gadget *g)
···
2380
2380
*
2381
2381
* We can check that via USB Link State bits in DSTS register.
2382
2382
*/
2383
-
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2383
+
reg = dwc3_readl(dwc, DWC3_DSTS);
2384
2384
2385
2385
link_state = DWC3_DSTS_USBLNKST(reg);
2386
2386
···
2408
2408
/* Recent versions do this automatically */
2409
2409
if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2410
2410
/* write zeroes to Link Change Request */
2411
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2411
+
reg = dwc3_readl(dwc, DWC3_DCTL);
2412
2412
reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2413
-
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2413
+
dwc3_writel(dwc, DWC3_DCTL, reg);
2414
2414
}
2415
2415
2416
2416
/*
···
2530
2530
if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2531
2531
ssp_rate = dwc->max_ssp_rate;
2532
2532
2533
-
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2533
+
reg = dwc3_readl(dwc, DWC3_DCFG);
2534
2534
reg &= ~DWC3_DCFG_SPEED_MASK;
2535
2535
reg &= ~DWC3_DCFG_NUMLANES(~0);
2536
2536
···
2543
2543
dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2544
2544
reg |= DWC3_DCFG_NUMLANES(1);
2545
2545
2546
-
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2546
+
dwc3_writel(dwc, DWC3_DCFG, reg);
2547
2547
}
2548
2548
2549
2549
static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
···
2561
2561
return;
2562
2562
}
2563
2563
2564
-
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2564
+
reg = dwc3_readl(dwc, DWC3_DCFG);
2565
2565
reg &= ~(DWC3_DCFG_SPEED_MASK);
2566
2566
2567
2567
/*
···
2612
2612
speed < USB_SPEED_SUPER_PLUS)
2613
2613
reg &= ~DWC3_DCFG_NUMLANES(~0);
2614
2614
2615
-
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2615
+
dwc3_writel(dwc, DWC3_DCFG, reg);
2616
2616
}
2617
2617
2618
2618
static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
···
2637
2637
* mentioned in the dwc3 programming guide. It has been tested on an
2638
2638
* Exynos platforms.
2639
2639
*/
2640
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2640
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0));
2641
2641
if (reg & DWC3_GUSB2PHYCFG_SUSPHY) {
2642
2642
saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
2643
2643
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
···
2649
2649
}
2650
2650
2651
2651
if (saved_config)
2652
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2652
+
dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg);
2653
2653
2654
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2654
+
reg = dwc3_readl(dwc, DWC3_DCTL);
2655
2655
if (is_on) {
2656
2656
if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2657
2657
reg &= ~DWC3_DCTL_TRGTULST_MASK;
···
2675
2675
2676
2676
do {
2677
2677
usleep_range(1000, 2000);
2678
-
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2678
+
reg = dwc3_readl(dwc, DWC3_DSTS);
2679
2679
reg &= DWC3_DSTS_DEVCTRLHLT;
2680
2680
} while (--timeout && !(!is_on ^ !reg));
2681
2681
2682
2682
if (saved_config) {
2683
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2683
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0));
2684
2684
reg |= saved_config;
2685
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2685
+
dwc3_writel(dwc, DWC3_GUSB2PHYCFG(0), reg);
2686
2686
}
2687
2687
2688
2688
if (!timeout)
···
2858
2858
if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2859
2859
reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2860
2860
2861
-
dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2861
+
dwc3_writel(dwc, DWC3_DEVTEN, reg);
2862
2862
}
2863
2863
2864
2864
static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2865
2865
{
2866
2866
/* mask all interrupts */
2867
-
dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2867
+
dwc3_writel(dwc, DWC3_DEVTEN, 0x00);
2868
2868
}
2869
2869
2870
2870
static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
···
2905
2905
nump = min_t(u32, nump, 16);
2906
2906
2907
2907
/* update NumP */
2908
-
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2908
+
reg = dwc3_readl(dwc, DWC3_DCFG);
2909
2909
reg &= ~DWC3_DCFG_NUMP_MASK;
2910
2910
reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2911
-
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2911
+
dwc3_writel(dwc, DWC3_DCFG, reg);
2912
2912
}
2913
2913
2914
2914
static int __dwc3_gadget_start(struct dwc3 *dwc)
···
2922
2922
* the core supports IMOD, disable it.
2923
2923
*/
2924
2924
if (dwc->imod_interval) {
2925
-
dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2926
-
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2925
+
dwc3_writel(dwc, DWC3_DEV_IMOD(0), dwc->imod_interval);
2926
+
dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2927
2927
} else if (dwc3_has_imod(dwc)) {
2928
-
dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2928
+
dwc3_writel(dwc, DWC3_DEV_IMOD(0), 0);
2929
2929
}
2930
2930
2931
2931
/*
···
2935
2935
* This way, we maximize the chances that we'll be able to get several
2936
2936
* bursts of data without going through any sort of endpoint throttling.
2937
2937
*/
2938
-
reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2938
+
reg = dwc3_readl(dwc, DWC3_GRXTHRCFG);
2939
2939
if (DWC3_IP_IS(DWC3))
2940
2940
reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2941
2941
else
2942
2942
reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2943
2943
2944
-
dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2944
+
dwc3_writel(dwc, DWC3_GRXTHRCFG, reg);
2945
2945
2946
2946
dwc3_gadget_setup_nump(dwc);
2947
2947
···
2952
2952
* ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2953
2953
* the stream performance.
2954
2954
*/
2955
-
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2955
+
reg = dwc3_readl(dwc, DWC3_DCFG);
2956
2956
reg |= DWC3_DCFG_IGNSTRMPP;
2957
-
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2957
+
dwc3_writel(dwc, DWC3_DCFG, reg);
2958
2958
2959
2959
/* Enable MST by default if the device is capable of MST */
2960
2960
if (DWC3_MST_CAPABLE(&dwc->hwparams)) {
2961
-
reg = dwc3_readl(dwc->regs, DWC3_DCFG1);
2961
+
reg = dwc3_readl(dwc, DWC3_DCFG1);
2962
2962
reg &= ~DWC3_DCFG1_DIS_MST_ENH;
2963
-
dwc3_writel(dwc->regs, DWC3_DCFG1, reg);
2963
+
dwc3_writel(dwc, DWC3_DCFG1, reg);
2964
2964
}
2965
2965
2966
2966
/* Start with SuperSpeed Default */
···
3240
3240
/* MDWIDTH is represented in bits, we need it in bytes */
3241
3241
mdwidth /= 8;
3242
3242
3243
-
size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
3243
+
size = dwc3_readl(dwc, DWC3_GTXFIFOSIZ(dep->number >> 1));
3244
3244
if (DWC3_IP_IS(DWC3))
3245
3245
size = DWC3_GTXFIFOSIZ_TXFDEP(size);
3246
3246
else
···
3289
3289
mdwidth /= 8;
3290
3290
3291
3291
/* All OUT endpoints share a single RxFIFO space */
3292
-
size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
3292
+
size = dwc3_readl(dwc, DWC3_GRXFIFOSIZ(0));
3293
3293
if (DWC3_IP_IS(DWC3))
3294
3294
size = DWC3_GRXFIFOSIZ_RXFDEP(size);
3295
3295
else
···
3742
3742
return no_started_trb;
3743
3743
}
3744
3744
3745
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3745
+
reg = dwc3_readl(dwc, DWC3_DCTL);
3746
3746
reg |= dwc->u1u2;
3747
-
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3747
+
dwc3_writel(dwc, DWC3_DCTL, reg);
3748
3748
3749
3749
dwc->u1u2 = 0;
3750
3750
}
···
4074
4074
4075
4075
dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
4076
4076
4077
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4077
+
reg = dwc3_readl(dwc, DWC3_DCTL);
4078
4078
reg &= ~DWC3_DCTL_INITU1ENA;
4079
4079
reg &= ~DWC3_DCTL_INITU2ENA;
4080
4080
dwc3_gadget_dctl_write_safe(dwc, reg);
···
4163
4163
dwc3_stop_active_transfers(dwc);
4164
4164
dwc->connected = true;
4165
4165
4166
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4166
+
reg = dwc3_readl(dwc, DWC3_DCTL);
4167
4167
reg &= ~DWC3_DCTL_TSTCTRL_MASK;
4168
4168
dwc3_gadget_dctl_write_safe(dwc, reg);
4169
4169
dwc->test_mode = false;
···
4172
4172
dwc3_clear_stall_all_ep(dwc);
4173
4173
4174
4174
/* Reset device address to zero */
4175
-
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4175
+
reg = dwc3_readl(dwc, DWC3_DCFG);
4176
4176
reg &= ~(DWC3_DCFG_DEVADDR_MASK);
4177
-
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4177
+
dwc3_writel(dwc, DWC3_DCFG, reg);
4178
4178
}
4179
4179
4180
4180
static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
···
4188
4188
if (!dwc->softconnect)
4189
4189
return;
4190
4190
4191
-
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
4191
+
reg = dwc3_readl(dwc, DWC3_DSTS);
4192
4192
speed = reg & DWC3_DSTS_CONNECTSPD;
4193
4193
dwc->speed = speed;
4194
4194
···
4263
4263
!dwc->usb2_gadget_lpm_disable &&
4264
4264
(speed != DWC3_DSTS_SUPERSPEED) &&
4265
4265
(speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
4266
-
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4266
+
reg = dwc3_readl(dwc, DWC3_DCFG);
4267
4267
reg |= DWC3_DCFG_LPM_CAP;
4268
-
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4268
+
dwc3_writel(dwc, DWC3_DCFG, reg);
4269
4269
4270
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4270
+
reg = dwc3_readl(dwc, DWC3_DCTL);
4271
4271
reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
4272
4272
4273
4273
reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
···
4290
4290
dwc3_gadget_dctl_write_safe(dwc, reg);
4291
4291
} else {
4292
4292
if (dwc->usb2_gadget_lpm_disable) {
4293
-
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4293
+
reg = dwc3_readl(dwc, DWC3_DCFG);
4294
4294
reg &= ~DWC3_DCFG_LPM_CAP;
4295
-
dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4295
+
dwc3_writel(dwc, DWC3_DCFG, reg);
4296
4296
}
4297
4297
4298
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4298
+
reg = dwc3_readl(dwc, DWC3_DCTL);
4299
4299
reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
4300
4300
dwc3_gadget_dctl_write_safe(dwc, reg);
4301
4301
}
···
4401
4401
switch (dwc->link_state) {
4402
4402
case DWC3_LINK_STATE_U1:
4403
4403
case DWC3_LINK_STATE_U2:
4404
-
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4404
+
reg = dwc3_readl(dwc, DWC3_DCTL);
4405
4405
u1u2 = reg & (DWC3_DCTL_INITU2ENA
4406
4406
| DWC3_DCTL_ACCEPTU2ENA
4407
4407
| DWC3_DCTL_INITU1ENA
···
4558
4558
ret = IRQ_HANDLED;
4559
4559
4560
4560
/* Unmask interrupt */
4561
-
dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4561
+
dwc3_writel(dwc, DWC3_GEVNTSIZ(0),
4562
4562
DWC3_GEVNTSIZ_SIZE(evt->length));
4563
4563
4564
4564
evt->flags &= ~DWC3_EVENT_PENDING;
···
4569
4569
wmb();
4570
4570
4571
4571
if (dwc->imod_interval) {
4572
-
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4573
-
dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4572
+
dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4573
+
dwc3_writel(dwc, DWC3_DEV_IMOD(0), dwc->imod_interval);
4574
4574
}
4575
4575
4576
4576
return ret;
···
4619
4619
if (evt->flags & DWC3_EVENT_PENDING)
4620
4620
return IRQ_HANDLED;
4621
4621
4622
-
count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4622
+
count = dwc3_readl(dwc, DWC3_GEVNTCOUNT(0));
4623
4623
count &= DWC3_GEVNTCOUNT_MASK;
4624
4624
if (!count)
4625
4625
return IRQ_NONE;
···
4634
4634
evt->flags |= DWC3_EVENT_PENDING;
4635
4635
4636
4636
/* Mask interrupt */
4637
-
dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4637
+
dwc3_writel(dwc, DWC3_GEVNTSIZ(0),
4638
4638
DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(evt->length));
4639
4639
4640
4640
amount = min(count, evt->length - evt->lpos);
···
4643
4643
if (amount < count)
4644
4644
memcpy(evt->cache, evt->buf, count - amount);
4645
4645
4646
-
dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4646
+
dwc3_writel(dwc, DWC3_GEVNTCOUNT(0), count);
4647
4647
4648
4648
return IRQ_WAKE_THREAD;
4649
4649
}
+2
-2
drivers/usb/dwc3/gadget.h
+2
-2
drivers/usb/dwc3/gadget.h
···
132
132
{
133
133
u32 res_id;
134
134
135
-
res_id = dwc3_readl(dep->dwc->regs, DWC3_DEPCMD(dep->number));
135
+
res_id = dwc3_readl(dep->dwc, DWC3_DEPCMD(dep->number));
136
136
dep->resource_index = DWC3_DEPCMD_GET_RSC_IDX(res_id);
137
137
}
138
138
···
147
147
static inline void dwc3_gadget_dctl_write_safe(struct dwc3 *dwc, u32 value)
148
148
{
149
149
value &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
150
-
dwc3_writel(dwc->regs, DWC3_DCTL, value);
150
+
dwc3_writel(dwc, DWC3_DCTL, value);
151
151
}
152
152
153
153
#endif /* __DRIVERS_USB_DWC3_GADGET_H */
+5
-2
drivers/usb/dwc3/io.h
+5
-2
drivers/usb/dwc3/io.h
···
16
16
#include "debug.h"
17
17
#include "core.h"
18
18
19
-
static inline u32 dwc3_readl(void __iomem *base, u32 offset)
19
+
static inline u32 dwc3_readl(struct dwc3 *dwc, u32 offset)
20
20
{
21
21
u32 value;
22
+
void __iomem *base = dwc->regs;
22
23
23
24
/*
24
25
* We requested the mem region starting from the Globals address
···
38
37
return value;
39
38
}
40
39
41
-
static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
40
+
static inline void dwc3_writel(struct dwc3 *dwc, u32 offset, u32 value)
42
41
{
42
+
void __iomem *base = dwc->regs;
43
+
43
44
/*
44
45
* We requested the mem region starting from the Globals address
45
46
* space, see dwc3_probe in core.c.
+5
-5
drivers/usb/dwc3/ulpi.c
+5
-5
drivers/usb/dwc3/ulpi.c
···
33
33
if (read)
34
34
ns += DWC3_ULPI_BASE_DELAY;
35
35
36
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
36
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYCFG(0));
37
37
if (reg & DWC3_GUSB2PHYCFG_SUSPHY)
38
38
usleep_range(1000, 1200);
39
39
40
40
while (count--) {
41
41
ndelay(ns);
42
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
42
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYACC(0));
43
43
if (reg & DWC3_GUSB2PHYACC_DONE)
44
44
return 0;
45
45
cpu_relax();
···
55
55
int ret;
56
56
57
57
reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
58
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
58
+
dwc3_writel(dwc, DWC3_GUSB2PHYACC(0), reg);
59
59
60
60
ret = dwc3_ulpi_busyloop(dwc, addr, true);
61
61
if (ret)
62
62
return ret;
63
63
64
-
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
64
+
reg = dwc3_readl(dwc, DWC3_GUSB2PHYACC(0));
65
65
66
66
return DWC3_GUSB2PHYACC_DATA(reg);
67
67
}
···
73
73
74
74
reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
75
75
reg |= DWC3_GUSB2PHYACC_WRITE | val;
76
-
dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
76
+
dwc3_writel(dwc, DWC3_GUSB2PHYACC(0), reg);
77
77
78
78
return dwc3_ulpi_busyloop(dwc, addr, false);
79
79
}