Merge branch 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6

+3 -5

drivers/char/drm/ati_pcigart.c

··· 76 76 for (i = 0; i < pages; i++) { 77 77 if (!entry->busaddr[i]) 78 78 break; 79 - pci_unmap_single(dev->pdev, entry->busaddr[i], 79 + pci_unmap_page(dev->pdev, entry->busaddr[i], 80 80 PAGE_SIZE, PCI_DMA_TODEVICE); 81 81 } 82 82 ··· 137 137 138 138 for (i = 0; i < pages; i++) { 139 139 /* we need to support large memory configurations */ 140 - entry->busaddr[i] = pci_map_single(dev->pdev, 141 - page_address(entry-> 142 - pagelist[i]), 143 - PAGE_SIZE, PCI_DMA_TODEVICE); 140 + entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i], 141 + 0, PAGE_SIZE, PCI_DMA_TODEVICE); 144 142 if (entry->busaddr[i] == 0) { 145 143 DRM_ERROR("unable to map PCIGART pages!\n"); 146 144 drm_ati_pcigart_cleanup(dev, gart_info);

+1 -1

drivers/char/drm/drm.h

··· 628 628 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 629 629 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 630 630 631 - #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather) 631 + #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) 632 632 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 633 633 634 634 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)

+4 -3

drivers/char/drm/drm_drv.c

··· 470 470 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) && 471 471 (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) 472 472 ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE]; 473 - else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) 473 + else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) { 474 474 ioctl = &drm_ioctls[nr]; 475 - else 475 + cmd = ioctl->cmd; 476 + } else 476 477 goto err_i1; 477 478 479 + /* Do not trust userspace, use our own definition */ 478 480 func = ioctl->func; 479 481 /* is there a local override? */ 480 482 if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl) 481 483 func = dev->driver->dma_ioctl; 482 - 483 484 484 485 if (!func) { 485 486 DRM_DEBUG("no function\n");

+9 -8

drivers/char/drm/drm_pciids.h

··· 103 103 {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 104 104 {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ 105 105 {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ 106 - {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 107 - {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 108 - {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 109 - {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 106 + {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 107 + {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 108 + {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 109 + {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 110 110 {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 111 111 {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 112 112 {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 113 113 {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 114 114 {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ 115 115 {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ 116 - {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 117 - {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 118 - {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 119 - {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 116 + {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 117 + {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ 120 118 {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 121 119 {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ 122 120 {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ ··· 409 411 {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 410 412 {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 411 413 {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 414 + {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 415 + {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 416 + {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ 412 417 {0, 0, 0}

+9 -2

drivers/char/drm/i915_drv.h

··· 1112 1112 (dev)->pci_device == 0x29A2 || \ 1113 1113 (dev)->pci_device == 0x2A02 || \ 1114 1114 (dev)->pci_device == 0x2A12 || \ 1115 - (dev)->pci_device == 0x2A42) 1115 + (dev)->pci_device == 0x2A42 || \ 1116 + (dev)->pci_device == 0x2E02 || \ 1117 + (dev)->pci_device == 0x2E12 || \ 1118 + (dev)->pci_device == 0x2E22) 1116 1119 1117 1120 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1118 1121 1119 1122 #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42) 1123 + 1124 + #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ 1125 + (dev)->pci_device == 0x2E12 || \ 1126 + (dev)->pci_device == 0x2E22) 1120 1127 1121 1128 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ 1122 1129 (dev)->pci_device == 0x29B2 || \ ··· 1135 1128 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 1136 1129 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev)) 1137 1130 1138 - #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev)) 1131 + #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev)) 1139 1132 1140 1133 #define PRIMARY_RINGBUFFER_SIZE (128*1024) 1141 1134

+95 -22

drivers/char/drm/r300_cmdbuf.c

··· 189 189 ADD_RANGE(R300_RE_CULL_CNTL, 1); 190 190 ADD_RANGE(0x42C0, 2); 191 191 ADD_RANGE(R300_RS_CNTL_0, 2); 192 - ADD_RANGE(R300_RS_INTERP_0, 8); 193 - ADD_RANGE(R300_RS_ROUTE_0, 8); 194 - ADD_RANGE(0x43A4, 2); 192 + 193 + ADD_RANGE(R300_SC_HYPERZ, 2); 195 194 ADD_RANGE(0x43E8, 1); 196 - ADD_RANGE(R300_PFS_CNTL_0, 3); 197 - ADD_RANGE(R300_PFS_NODE_0, 4); 198 - ADD_RANGE(R300_PFS_TEXI_0, 64); 195 + 199 196 ADD_RANGE(0x46A4, 5); 200 - ADD_RANGE(R300_PFS_INSTR0_0, 64); 201 - ADD_RANGE(R300_PFS_INSTR1_0, 64); 202 - ADD_RANGE(R300_PFS_INSTR2_0, 64); 203 - ADD_RANGE(R300_PFS_INSTR3_0, 64); 197 + 204 198 ADD_RANGE(R300_RE_FOG_STATE, 1); 205 199 ADD_RANGE(R300_FOG_COLOR_R, 3); 206 200 ADD_RANGE(R300_PP_ALPHA_TEST, 2); ··· 209 215 ADD_RANGE(0x4E50, 9); 210 216 ADD_RANGE(0x4E88, 1); 211 217 ADD_RANGE(0x4EA0, 2); 212 - ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3); 213 - ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4); 214 - ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ 215 - ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); 216 - ADD_RANGE(0x4F28, 1); 217 - ADD_RANGE(0x4F30, 2); 218 - ADD_RANGE(0x4F44, 1); 219 - ADD_RANGE(0x4F54, 1); 218 + ADD_RANGE(R300_ZB_CNTL, 3); 219 + ADD_RANGE(R300_ZB_FORMAT, 4); 220 + ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ 221 + ADD_RANGE(R300_ZB_DEPTHPITCH, 1); 222 + ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1); 223 + ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13); 220 224 221 225 ADD_RANGE(R300_TX_FILTER_0, 16); 222 226 ADD_RANGE(R300_TX_FILTER1_0, 16); ··· 227 235 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); 228 236 229 237 /* Sporadic registers used as primitives are emitted */ 230 - ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1); 238 + ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1); 231 239 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); 232 240 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); 233 241 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); 234 242 235 243 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { 236 - ADD_RANGE(0x4074, 16); 244 + ADD_RANGE(R500_VAP_INDEX_OFFSET, 1); 245 + ADD_RANGE(R500_US_CONFIG, 2); 246 + ADD_RANGE(R500_US_CODE_ADDR, 3); 247 + ADD_RANGE(R500_US_FC_CTRL, 1); 248 + ADD_RANGE(R500_RS_IP_0, 16); 249 + ADD_RANGE(R500_RS_INST_0, 16); 250 + ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2); 251 + ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2); 252 + ADD_RANGE(R500_ZB_FIFO_SIZE, 2); 253 + } else { 254 + ADD_RANGE(R300_PFS_CNTL_0, 3); 255 + ADD_RANGE(R300_PFS_NODE_0, 4); 256 + ADD_RANGE(R300_PFS_TEXI_0, 64); 257 + ADD_RANGE(R300_PFS_INSTR0_0, 64); 258 + ADD_RANGE(R300_PFS_INSTR1_0, 64); 259 + ADD_RANGE(R300_PFS_INSTR2_0, 64); 260 + ADD_RANGE(R300_PFS_INSTR3_0, 64); 261 + ADD_RANGE(R300_RS_INTERP_0, 8); 262 + ADD_RANGE(R300_RS_ROUTE_0, 8); 263 + 237 264 } 238 265 } 239 266 ··· 718 707 BEGIN_RING(6); 719 708 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 720 709 OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A); 721 - OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 722 - OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03); 710 + OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); 711 + OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE| 712 + R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); 723 713 OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0)); 724 714 OUT_RING(0x0); 725 715 ADVANCE_RING(); ··· 839 827 840 828 return 0; 841 829 } 830 + 831 + /** 832 + * Uploads user-supplied vertex program instructions or parameters onto 833 + * the graphics card. 834 + * Called by r300_do_cp_cmdbuf. 835 + */ 836 + static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv, 837 + drm_radeon_kcmd_buffer_t *cmdbuf, 838 + drm_r300_cmd_header_t header) 839 + { 840 + int sz; 841 + int addr; 842 + int type; 843 + int clamp; 844 + int stride; 845 + RING_LOCALS; 846 + 847 + sz = header.r500fp.count; 848 + /* address is 9 bits 0 - 8, bit 1 of flags is part of address */ 849 + addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo; 850 + 851 + type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE); 852 + clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP); 853 + 854 + addr |= (type << 16); 855 + addr |= (clamp << 17); 856 + 857 + stride = type ? 4 : 6; 858 + 859 + DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type); 860 + if (!sz) 861 + return 0; 862 + if (sz * stride * 4 > cmdbuf->bufsz) 863 + return -EINVAL; 864 + 865 + BEGIN_RING(3 + sz * stride); 866 + OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr); 867 + OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1)); 868 + OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride); 869 + 870 + ADVANCE_RING(); 871 + 872 + cmdbuf->buf += sz * stride * 4; 873 + cmdbuf->bufsz -= sz * stride * 4; 874 + 875 + return 0; 876 + } 877 + 842 878 843 879 /** 844 880 * Parses and validates a user-supplied command buffer and emits appropriate ··· 1023 963 } 1024 964 break; 1025 965 966 + case R300_CMD_R500FP: 967 + if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { 968 + DRM_ERROR("Calling r500 command on r300 card\n"); 969 + ret = -EINVAL; 970 + goto cleanup; 971 + } 972 + DRM_DEBUG("R300_CMD_R500FP\n"); 973 + ret = r300_emit_r500fp(dev_priv, cmdbuf, header); 974 + if (ret) { 975 + DRM_ERROR("r300_emit_r500fp failed\n"); 976 + goto cleanup; 977 + } 978 + break; 1026 979 default: 1027 980 DRM_ERROR("bad cmd_type %i at %p\n", 1028 981 header.header.cmd_type,

+196 -50

drivers/char/drm/r300_reg.h

··· 702 702 # define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) 703 703 /* END: Rasterization / Interpolators - many guesses */ 704 704 705 + /* Hierarchical Z Enable */ 706 + #define R300_SC_HYPERZ 0x43a4 707 + # define R300_SC_HYPERZ_DISABLE (0 << 0) 708 + # define R300_SC_HYPERZ_ENABLE (1 << 0) 709 + # define R300_SC_HYPERZ_MIN (0 << 1) 710 + # define R300_SC_HYPERZ_MAX (1 << 1) 711 + # define R300_SC_HYPERZ_ADJ_256 (0 << 2) 712 + # define R300_SC_HYPERZ_ADJ_128 (1 << 2) 713 + # define R300_SC_HYPERZ_ADJ_64 (2 << 2) 714 + # define R300_SC_HYPERZ_ADJ_32 (3 << 2) 715 + # define R300_SC_HYPERZ_ADJ_16 (4 << 2) 716 + # define R300_SC_HYPERZ_ADJ_8 (5 << 2) 717 + # define R300_SC_HYPERZ_ADJ_4 (6 << 2) 718 + # define R300_SC_HYPERZ_ADJ_2 (7 << 2) 719 + # define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5) 720 + # define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5) 721 + # define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6) 722 + # define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6) 723 + 724 + #define R300_SC_EDGERULE 0x43a8 725 + 705 726 /* BEGIN: Scissors and cliprects */ 706 727 707 728 /* There are four clipping rectangles. Their corner coordinates are inclusive. ··· 1367 1346 /* Guess by Vladimir. 1368 1347 * Set to 0A before 3D operations, set to 02 afterwards. 1369 1348 */ 1370 - #define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C 1349 + /*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/ 1371 1350 # define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002 1372 1351 # define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A 1373 1352 ··· 1376 1355 * for this. 1377 1356 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd 1378 1357 */ 1379 - #define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 1380 - # define R300_RB3D_Z_DISABLED_1 0x00000010 1381 - # define R300_RB3D_Z_DISABLED_2 0x00000014 1382 - # define R300_RB3D_Z_TEST 0x00000012 1383 - # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 1384 - # define R300_RB3D_Z_WRITE_ONLY 0x00000006 1358 + #define R300_ZB_CNTL 0x4F00 1359 + # define R300_STENCIL_ENABLE (1 << 0) 1360 + # define R300_Z_ENABLE (1 << 1) 1361 + # define R300_Z_WRITE_ENABLE (1 << 2) 1362 + # define R300_Z_SIGNED_COMPARE (1 << 3) 1363 + # define R300_STENCIL_FRONT_BACK (1 << 4) 1385 1364 1386 - # define R300_RB3D_Z_TEST 0x00000012 1387 - # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 1388 - # define R300_RB3D_Z_WRITE_ONLY 0x00000006 1389 - # define R300_RB3D_STENCIL_ENABLE 0x00000001 1390 - 1391 - #define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04 1365 + #define R300_ZB_ZSTENCILCNTL 0x4f04 1392 1366 /* functions */ 1393 1367 # define R300_ZS_NEVER 0 1394 1368 # define R300_ZS_LESS 1 ··· 1403 1387 # define R300_ZS_INVERT 5 1404 1388 # define R300_ZS_INCR_WRAP 6 1405 1389 # define R300_ZS_DECR_WRAP 7 1390 + # define R300_Z_FUNC_SHIFT 0 1406 1391 /* front and back refer to operations done for front 1407 1392 and back faces, i.e. separate stencil function support */ 1408 - # define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0 1409 - # define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3 1410 - # define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6 1411 - # define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9 1412 - # define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12 1413 - # define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15 1414 - # define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18 1415 - # define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21 1416 - # define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24 1393 + # define R300_S_FRONT_FUNC_SHIFT 3 1394 + # define R300_S_FRONT_SFAIL_OP_SHIFT 6 1395 + # define R300_S_FRONT_ZPASS_OP_SHIFT 9 1396 + # define R300_S_FRONT_ZFAIL_OP_SHIFT 12 1397 + # define R300_S_BACK_FUNC_SHIFT 15 1398 + # define R300_S_BACK_SFAIL_OP_SHIFT 18 1399 + # define R300_S_BACK_ZPASS_OP_SHIFT 21 1400 + # define R300_S_BACK_ZFAIL_OP_SHIFT 24 1417 1401 1418 - #define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08 1419 - # define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0 1420 - # define R300_RB3D_ZS2_STENCIL_MASK 0xFF 1421 - # define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8 1422 - # define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16 1423 - 1424 - /* gap */ 1425 - 1426 - #define R300_RB3D_ZSTENCIL_FORMAT 0x4F10 1427 - # define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1428 - # define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1429 - /* 16 bit format or some aditional bit ? */ 1430 - # define R300_DEPTH_FORMAT_UNK32 (32 << 0) 1431 - 1432 - #define R300_RB3D_EARLY_Z 0x4F14 1433 - # define R300_EARLY_Z_DISABLE (0 << 0) 1434 - # define R300_EARLY_Z_ENABLE (1 << 0) 1402 + #define R300_ZB_STENCILREFMASK 0x4f08 1403 + # define R300_STENCILREF_SHIFT 0 1404 + # define R300_STENCILREF_MASK 0x000000ff 1405 + # define R300_STENCILMASK_SHIFT 8 1406 + # define R300_STENCILMASK_MASK 0x0000ff00 1407 + # define R300_STENCILWRITEMASK_SHIFT 16 1408 + # define R300_STENCILWRITEMASK_MASK 0x00ff0000 1435 1409 1436 1410 /* gap */ 1437 1411 1438 - #define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */ 1439 - # define R300_RB3D_ZCACHE_UNKNOWN_01 0x1 1440 - # define R300_RB3D_ZCACHE_UNKNOWN_03 0x3 1412 + #define R300_ZB_FORMAT 0x4f10 1413 + # define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0) 1414 + # define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0) 1415 + # define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0) 1416 + /* reserved up to (15 << 0) */ 1417 + # define R300_INVERT_13E3_LEADING_ONES (0 << 4) 1418 + # define R300_INVERT_13E3_LEADING_ZEROS (1 << 4) 1419 + 1420 + #define R300_ZB_ZTOP 0x4F14 1421 + # define R300_ZTOP_DISABLE (0 << 0) 1422 + # define R300_ZTOP_ENABLE (1 << 0) 1441 1423 1442 1424 /* gap */ 1443 1425 1444 - #define R300_RB3D_DEPTHOFFSET 0x4F20 1445 - #define R300_RB3D_DEPTHPITCH 0x4F24 1446 - # define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ 1447 - # define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ 1448 - # define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ 1449 - # define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 1450 - # define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 1451 - # define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 1426 + #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 1427 + # define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0) 1428 + # define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0) 1429 + # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1) 1430 + # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1) 1431 + # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31) 1432 + # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) 1433 + 1434 + #define R300_ZB_BW_CNTL 0x4f1c 1435 + # define R300_HIZ_DISABLE (0 << 0) 1436 + # define R300_HIZ_ENABLE (1 << 0) 1437 + # define R300_HIZ_MIN (0 << 1) 1438 + # define R300_HIZ_MAX (1 << 1) 1439 + # define R300_FAST_FILL_DISABLE (0 << 2) 1440 + # define R300_FAST_FILL_ENABLE (1 << 2) 1441 + # define R300_RD_COMP_DISABLE (0 << 3) 1442 + # define R300_RD_COMP_ENABLE (1 << 3) 1443 + # define R300_WR_COMP_DISABLE (0 << 4) 1444 + # define R300_WR_COMP_ENABLE (1 << 4) 1445 + # define R300_ZB_CB_CLEAR_RMW (0 << 5) 1446 + # define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5) 1447 + # define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6) 1448 + # define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6) 1449 + 1450 + # define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7) 1451 + # define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7) 1452 + # define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8) 1453 + # define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8) 1454 + 1455 + # define R500_BMASK_ENABLE (0 << 10) 1456 + # define R500_BMASK_DISABLE (1 << 10) 1457 + # define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11) 1458 + # define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11) 1459 + # define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12) 1460 + # define R500_HIZ_FP_EXP_BITS_1 (1 << 12) 1461 + # define R500_HIZ_FP_EXP_BITS_2 (2 << 12) 1462 + # define R500_HIZ_FP_EXP_BITS_3 (3 << 12) 1463 + # define R500_HIZ_FP_EXP_BITS_4 (4 << 12) 1464 + # define R500_HIZ_FP_EXP_BITS_5 (5 << 12) 1465 + # define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15) 1466 + # define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15) 1467 + # define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16) 1468 + # define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16) 1469 + # define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17) 1470 + # define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17) 1471 + # define R500_PEQ_PACKING_DISABLE (0 << 18) 1472 + # define R500_PEQ_PACKING_ENABLE (1 << 18) 1473 + # define R500_COVERED_PTR_MASKING_DISABLE (0 << 18) 1474 + # define R500_COVERED_PTR_MASKING_ENABLE (1 << 18) 1475 + 1476 + 1477 + /* gap */ 1478 + 1479 + /* Z Buffer Address Offset. 1480 + * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles. 1481 + */ 1482 + #define R300_ZB_DEPTHOFFSET 0x4f20 1483 + 1484 + /* Z Buffer Pitch and Endian Control */ 1485 + #define R300_ZB_DEPTHPITCH 0x4f24 1486 + # define R300_DEPTHPITCH_MASK 0x00003FFC 1487 + # define R300_DEPTHMACROTILE_DISABLE (0 << 16) 1488 + # define R300_DEPTHMACROTILE_ENABLE (1 << 16) 1489 + # define R300_DEPTHMICROTILE_LINEAR (0 << 17) 1490 + # define R300_DEPTHMICROTILE_TILED (1 << 17) 1491 + # define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17) 1492 + # define R300_DEPTHENDIAN_NO_SWAP (0 << 18) 1493 + # define R300_DEPTHENDIAN_WORD_SWAP (1 << 18) 1494 + # define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18) 1495 + # define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18) 1496 + 1497 + /* Z Buffer Clear Value */ 1498 + #define R300_ZB_DEPTHCLEARVALUE 0x4f28 1499 + 1500 + #define R300_ZB_ZMASK_OFFSET 0x4f30 1501 + #define R300_ZB_ZMASK_PITCH 0x4f34 1502 + #define R300_ZB_ZMASK_WRINDEX 0x4f38 1503 + #define R300_ZB_ZMASK_DWORD 0x4f3c 1504 + #define R300_ZB_ZMASK_RDINDEX 0x4f40 1505 + 1506 + /* Hierarchical Z Memory Offset */ 1507 + #define R300_ZB_HIZ_OFFSET 0x4f44 1508 + 1509 + /* Hierarchical Z Write Index */ 1510 + #define R300_ZB_HIZ_WRINDEX 0x4f48 1511 + 1512 + /* Hierarchical Z Data */ 1513 + #define R300_ZB_HIZ_DWORD 0x4f4c 1514 + 1515 + /* Hierarchical Z Read Index */ 1516 + #define R300_ZB_HIZ_RDINDEX 0x4f50 1517 + 1518 + /* Hierarchical Z Pitch */ 1519 + #define R300_ZB_HIZ_PITCH 0x4f54 1520 + 1521 + /* Z Buffer Z Pass Counter Data */ 1522 + #define R300_ZB_ZPASS_DATA 0x4f58 1523 + 1524 + /* Z Buffer Z Pass Counter Address */ 1525 + #define R300_ZB_ZPASS_ADDR 0x4f5c 1526 + 1527 + /* Depth buffer X and Y coordinate offset */ 1528 + #define R300_ZB_DEPTHXY_OFFSET 0x4f60 1529 + # define R300_DEPTHX_OFFSET_SHIFT 1 1530 + # define R300_DEPTHX_OFFSET_MASK 0x000007FE 1531 + # define R300_DEPTHY_OFFSET_SHIFT 17 1532 + # define R300_DEPTHY_OFFSET_MASK 0x07FE0000 1533 + 1534 + /* Sets the fifo sizes */ 1535 + #define R500_ZB_FIFO_SIZE 0x4fd0 1536 + # define R500_OP_FIFO_SIZE_FULL (0 << 0) 1537 + # define R500_OP_FIFO_SIZE_HALF (1 << 0) 1538 + # define R500_OP_FIFO_SIZE_QUATER (2 << 0) 1539 + # define R500_OP_FIFO_SIZE_EIGTHS (4 << 0) 1540 + 1541 + /* Stencil Reference Value and Mask for backfacing quads */ 1542 + /* R300_ZB_STENCILREFMASK handles front face */ 1543 + #define R500_ZB_STENCILREFMASK_BF 0x4fd4 1544 + # define R500_STENCILREF_SHIFT 0 1545 + # define R500_STENCILREF_MASK 0x000000ff 1546 + # define R500_STENCILMASK_SHIFT 8 1547 + # define R500_STENCILMASK_MASK 0x0000ff00 1548 + # define R500_STENCILWRITEMASK_SHIFT 16 1549 + # define R500_STENCILWRITEMASK_MASK 0x00ff0000 1452 1550 1453 1551 /* BEGIN: Vertex program instruction set */ 1454 1552 ··· 1752 1622 * CP type-3 packets 1753 1623 */ 1754 1624 #define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 1625 + 1626 + #define R500_VAP_INDEX_OFFSET 0x208c 1627 + 1628 + #define R500_GA_US_VECTOR_INDEX 0x4250 1629 + #define R500_GA_US_VECTOR_DATA 0x4254 1630 + 1631 + #define R500_RS_IP_0 0x4074 1632 + #define R500_RS_INST_0 0x4320 1633 + 1634 + #define R500_US_CONFIG 0x4600 1635 + 1636 + #define R500_US_FC_CTRL 0x4624 1637 + #define R500_US_CODE_ADDR 0x4630 1638 + 1639 + #define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0 1640 + #define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 1755 1641 1756 1642 #endif /* _R300_REG_H */

+241 -903

drivers/char/drm/radeon_cp.c

··· 2 2 /* 3 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 + * Copyright 2007 Advanced Micro Devices, Inc. 5 6 * All Rights Reserved. 6 7 * 7 8 * Permission is hereby granted, free of charge, to any person obtaining a ··· 35 34 #include "radeon_drv.h" 36 35 #include "r300_reg.h" 37 36 37 + #include "radeon_microcode.h" 38 + 38 39 #define RADEON_FIFO_DEBUG 0 39 40 40 41 static int radeon_do_cleanup_cp(struct drm_device * dev); 41 42 42 - /* CP microcode (from ATI) */ 43 - static const u32 R200_cp_microcode[][2] = { 44 - {0x21007000, 0000000000}, 45 - {0x20007000, 0000000000}, 46 - {0x000000ab, 0x00000004}, 47 - {0x000000af, 0x00000004}, 48 - {0x66544a49, 0000000000}, 49 - {0x49494174, 0000000000}, 50 - {0x54517d83, 0000000000}, 51 - {0x498d8b64, 0000000000}, 52 - {0x49494949, 0000000000}, 53 - {0x49da493c, 0000000000}, 54 - {0x49989898, 0000000000}, 55 - {0xd34949d5, 0000000000}, 56 - {0x9dc90e11, 0000000000}, 57 - {0xce9b9b9b, 0000000000}, 58 - {0x000f0000, 0x00000016}, 59 - {0x352e232c, 0000000000}, 60 - {0x00000013, 0x00000004}, 61 - {0x000f0000, 0x00000016}, 62 - {0x352e272c, 0000000000}, 63 - {0x000f0001, 0x00000016}, 64 - {0x3239362f, 0000000000}, 65 - {0x000077ef, 0x00000002}, 66 - {0x00061000, 0x00000002}, 67 - {0x00000020, 0x0000001a}, 68 - {0x00004000, 0x0000001e}, 69 - {0x00061000, 0x00000002}, 70 - {0x00000020, 0x0000001a}, 71 - {0x00004000, 0x0000001e}, 72 - {0x00061000, 0x00000002}, 73 - {0x00000020, 0x0000001a}, 74 - {0x00004000, 0x0000001e}, 75 - {0x00000016, 0x00000004}, 76 - {0x0003802a, 0x00000002}, 77 - {0x040067e0, 0x00000002}, 78 - {0x00000016, 0x00000004}, 79 - {0x000077e0, 0x00000002}, 80 - {0x00065000, 0x00000002}, 81 - {0x000037e1, 0x00000002}, 82 - {0x040067e1, 0x00000006}, 83 - {0x000077e0, 0x00000002}, 84 - {0x000077e1, 0x00000002}, 85 - {0x000077e1, 0x00000006}, 86 - {0xffffffff, 0000000000}, 87 - {0x10000000, 0000000000}, 88 - {0x0003802a, 0x00000002}, 89 - {0x040067e0, 0x00000006}, 90 - {0x00007675, 0x00000002}, 91 - {0x00007676, 0x00000002}, 92 - {0x00007677, 0x00000002}, 93 - {0x00007678, 0x00000006}, 94 - {0x0003802b, 0x00000002}, 95 - {0x04002676, 0x00000002}, 96 - {0x00007677, 0x00000002}, 97 - {0x00007678, 0x00000006}, 98 - {0x0000002e, 0x00000018}, 99 - {0x0000002e, 0x00000018}, 100 - {0000000000, 0x00000006}, 101 - {0x0000002f, 0x00000018}, 102 - {0x0000002f, 0x00000018}, 103 - {0000000000, 0x00000006}, 104 - {0x01605000, 0x00000002}, 105 - {0x00065000, 0x00000002}, 106 - {0x00098000, 0x00000002}, 107 - {0x00061000, 0x00000002}, 108 - {0x64c0603d, 0x00000004}, 109 - {0x00080000, 0x00000016}, 110 - {0000000000, 0000000000}, 111 - {0x0400251d, 0x00000002}, 112 - {0x00007580, 0x00000002}, 113 - {0x00067581, 0x00000002}, 114 - {0x04002580, 0x00000002}, 115 - {0x00067581, 0x00000002}, 116 - {0x00000046, 0x00000004}, 117 - {0x00005000, 0000000000}, 118 - {0x00061000, 0x00000002}, 119 - {0x0000750e, 0x00000002}, 120 - {0x00019000, 0x00000002}, 121 - {0x00011055, 0x00000014}, 122 - {0x00000055, 0x00000012}, 123 - {0x0400250f, 0x00000002}, 124 - {0x0000504a, 0x00000004}, 125 - {0x00007565, 0x00000002}, 126 - {0x00007566, 0x00000002}, 127 - {0x00000051, 0x00000004}, 128 - {0x01e655b4, 0x00000002}, 129 - {0x4401b0dc, 0x00000002}, 130 - {0x01c110dc, 0x00000002}, 131 - {0x2666705d, 0x00000018}, 132 - {0x040c2565, 0x00000002}, 133 - {0x0000005d, 0x00000018}, 134 - {0x04002564, 0x00000002}, 135 - {0x00007566, 0x00000002}, 136 - {0x00000054, 0x00000004}, 137 - {0x00401060, 0x00000008}, 138 - {0x00101000, 0x00000002}, 139 - {0x000d80ff, 0x00000002}, 140 - {0x00800063, 0x00000008}, 141 - {0x000f9000, 0x00000002}, 142 - {0x000e00ff, 0x00000002}, 143 - {0000000000, 0x00000006}, 144 - {0x00000080, 0x00000018}, 145 - {0x00000054, 0x00000004}, 146 - {0x00007576, 0x00000002}, 147 - {0x00065000, 0x00000002}, 148 - {0x00009000, 0x00000002}, 149 - {0x00041000, 0x00000002}, 150 - {0x0c00350e, 0x00000002}, 151 - {0x00049000, 0x00000002}, 152 - {0x00051000, 0x00000002}, 153 - {0x01e785f8, 0x00000002}, 154 - {0x00200000, 0x00000002}, 155 - {0x00600073, 0x0000000c}, 156 - {0x00007563, 0x00000002}, 157 - {0x006075f0, 0x00000021}, 158 - {0x20007068, 0x00000004}, 159 - {0x00005068, 0x00000004}, 160 - {0x00007576, 0x00000002}, 161 - {0x00007577, 0x00000002}, 162 - {0x0000750e, 0x00000002}, 163 - {0x0000750f, 0x00000002}, 164 - {0x00a05000, 0x00000002}, 165 - {0x00600076, 0x0000000c}, 166 - {0x006075f0, 0x00000021}, 167 - {0x000075f8, 0x00000002}, 168 - {0x00000076, 0x00000004}, 169 - {0x000a750e, 0x00000002}, 170 - {0x0020750f, 0x00000002}, 171 - {0x00600079, 0x00000004}, 172 - {0x00007570, 0x00000002}, 173 - {0x00007571, 0x00000002}, 174 - {0x00007572, 0x00000006}, 175 - {0x00005000, 0x00000002}, 176 - {0x00a05000, 0x00000002}, 177 - {0x00007568, 0x00000002}, 178 - {0x00061000, 0x00000002}, 179 - {0x00000084, 0x0000000c}, 180 - {0x00058000, 0x00000002}, 181 - {0x0c607562, 0x00000002}, 182 - {0x00000086, 0x00000004}, 183 - {0x00600085, 0x00000004}, 184 - {0x400070dd, 0000000000}, 185 - {0x000380dd, 0x00000002}, 186 - {0x00000093, 0x0000001c}, 187 - {0x00065095, 0x00000018}, 188 - {0x040025bb, 0x00000002}, 189 - {0x00061096, 0x00000018}, 190 - {0x040075bc, 0000000000}, 191 - {0x000075bb, 0x00000002}, 192 - {0x000075bc, 0000000000}, 193 - {0x00090000, 0x00000006}, 194 - {0x00090000, 0x00000002}, 195 - {0x000d8002, 0x00000006}, 196 - {0x00005000, 0x00000002}, 197 - {0x00007821, 0x00000002}, 198 - {0x00007800, 0000000000}, 199 - {0x00007821, 0x00000002}, 200 - {0x00007800, 0000000000}, 201 - {0x01665000, 0x00000002}, 202 - {0x000a0000, 0x00000002}, 203 - {0x000671cc, 0x00000002}, 204 - {0x0286f1cd, 0x00000002}, 205 - {0x000000a3, 0x00000010}, 206 - {0x21007000, 0000000000}, 207 - {0x000000aa, 0x0000001c}, 208 - {0x00065000, 0x00000002}, 209 - {0x000a0000, 0x00000002}, 210 - {0x00061000, 0x00000002}, 211 - {0x000b0000, 0x00000002}, 212 - {0x38067000, 0x00000002}, 213 - {0x000a00a6, 0x00000004}, 214 - {0x20007000, 0000000000}, 215 - {0x01200000, 0x00000002}, 216 - {0x20077000, 0x00000002}, 217 - {0x01200000, 0x00000002}, 218 - {0x20007000, 0000000000}, 219 - {0x00061000, 0x00000002}, 220 - {0x0120751b, 0x00000002}, 221 - {0x8040750a, 0x00000002}, 222 - {0x8040750b, 0x00000002}, 223 - {0x00110000, 0x00000002}, 224 - {0x000380dd, 0x00000002}, 225 - {0x000000bd, 0x0000001c}, 226 - {0x00061096, 0x00000018}, 227 - {0x844075bd, 0x00000002}, 228 - {0x00061095, 0x00000018}, 229 - {0x840075bb, 0x00000002}, 230 - {0x00061096, 0x00000018}, 231 - {0x844075bc, 0x00000002}, 232 - {0x000000c0, 0x00000004}, 233 - {0x804075bd, 0x00000002}, 234 - {0x800075bb, 0x00000002}, 235 - {0x804075bc, 0x00000002}, 236 - {0x00108000, 0x00000002}, 237 - {0x01400000, 0x00000002}, 238 - {0x006000c4, 0x0000000c}, 239 - {0x20c07000, 0x00000020}, 240 - {0x000000c6, 0x00000012}, 241 - {0x00800000, 0x00000006}, 242 - {0x0080751d, 0x00000006}, 243 - {0x000025bb, 0x00000002}, 244 - {0x000040c0, 0x00000004}, 245 - {0x0000775c, 0x00000002}, 246 - {0x00a05000, 0x00000002}, 247 - {0x00661000, 0x00000002}, 248 - {0x0460275d, 0x00000020}, 249 - {0x00004000, 0000000000}, 250 - {0x00007999, 0x00000002}, 251 - {0x00a05000, 0x00000002}, 252 - {0x00661000, 0x00000002}, 253 - {0x0460299b, 0x00000020}, 254 - {0x00004000, 0000000000}, 255 - {0x01e00830, 0x00000002}, 256 - {0x21007000, 0000000000}, 257 - {0x00005000, 0x00000002}, 258 - {0x00038042, 0x00000002}, 259 - {0x040025e0, 0x00000002}, 260 - {0x000075e1, 0000000000}, 261 - {0x00000001, 0000000000}, 262 - {0x000380d9, 0x00000002}, 263 - {0x04007394, 0000000000}, 264 - {0000000000, 0000000000}, 265 - {0000000000, 0000000000}, 266 - {0000000000, 0000000000}, 267 - {0000000000, 0000000000}, 268 - {0000000000, 0000000000}, 269 - {0000000000, 0000000000}, 270 - {0000000000, 0000000000}, 271 - {0000000000, 0000000000}, 272 - {0000000000, 0000000000}, 273 - {0000000000, 0000000000}, 274 - {0000000000, 0000000000}, 275 - {0000000000, 0000000000}, 276 - {0000000000, 0000000000}, 277 - {0000000000, 0000000000}, 278 - {0000000000, 0000000000}, 279 - {0000000000, 0000000000}, 280 - {0000000000, 0000000000}, 281 - {0000000000, 0000000000}, 282 - {0000000000, 0000000000}, 283 - {0000000000, 0000000000}, 284 - {0000000000, 0000000000}, 285 - {0000000000, 0000000000}, 286 - {0000000000, 0000000000}, 287 - {0000000000, 0000000000}, 288 - {0000000000, 0000000000}, 289 - {0000000000, 0000000000}, 290 - {0000000000, 0000000000}, 291 - {0000000000, 0000000000}, 292 - {0000000000, 0000000000}, 293 - {0000000000, 0000000000}, 294 - {0000000000, 0000000000}, 295 - {0000000000, 0000000000}, 296 - {0000000000, 0000000000}, 297 - {0000000000, 0000000000}, 298 - {0000000000, 0000000000}, 299 - {0000000000, 0000000000}, 300 - }; 301 - 302 - static const u32 radeon_cp_microcode[][2] = { 303 - {0x21007000, 0000000000}, 304 - {0x20007000, 0000000000}, 305 - {0x000000b4, 0x00000004}, 306 - {0x000000b8, 0x00000004}, 307 - {0x6f5b4d4c, 0000000000}, 308 - {0x4c4c427f, 0000000000}, 309 - {0x5b568a92, 0000000000}, 310 - {0x4ca09c6d, 0000000000}, 311 - {0xad4c4c4c, 0000000000}, 312 - {0x4ce1af3d, 0000000000}, 313 - {0xd8afafaf, 0000000000}, 314 - {0xd64c4cdc, 0000000000}, 315 - {0x4cd10d10, 0000000000}, 316 - {0x000f0000, 0x00000016}, 317 - {0x362f242d, 0000000000}, 318 - {0x00000012, 0x00000004}, 319 - {0x000f0000, 0x00000016}, 320 - {0x362f282d, 0000000000}, 321 - {0x000380e7, 0x00000002}, 322 - {0x04002c97, 0x00000002}, 323 - {0x000f0001, 0x00000016}, 324 - {0x333a3730, 0000000000}, 325 - {0x000077ef, 0x00000002}, 326 - {0x00061000, 0x00000002}, 327 - {0x00000021, 0x0000001a}, 328 - {0x00004000, 0x0000001e}, 329 - {0x00061000, 0x00000002}, 330 - {0x00000021, 0x0000001a}, 331 - {0x00004000, 0x0000001e}, 332 - {0x00061000, 0x00000002}, 333 - {0x00000021, 0x0000001a}, 334 - {0x00004000, 0x0000001e}, 335 - {0x00000017, 0x00000004}, 336 - {0x0003802b, 0x00000002}, 337 - {0x040067e0, 0x00000002}, 338 - {0x00000017, 0x00000004}, 339 - {0x000077e0, 0x00000002}, 340 - {0x00065000, 0x00000002}, 341 - {0x000037e1, 0x00000002}, 342 - {0x040067e1, 0x00000006}, 343 - {0x000077e0, 0x00000002}, 344 - {0x000077e1, 0x00000002}, 345 - {0x000077e1, 0x00000006}, 346 - {0xffffffff, 0000000000}, 347 - {0x10000000, 0000000000}, 348 - {0x0003802b, 0x00000002}, 349 - {0x040067e0, 0x00000006}, 350 - {0x00007675, 0x00000002}, 351 - {0x00007676, 0x00000002}, 352 - {0x00007677, 0x00000002}, 353 - {0x00007678, 0x00000006}, 354 - {0x0003802c, 0x00000002}, 355 - {0x04002676, 0x00000002}, 356 - {0x00007677, 0x00000002}, 357 - {0x00007678, 0x00000006}, 358 - {0x0000002f, 0x00000018}, 359 - {0x0000002f, 0x00000018}, 360 - {0000000000, 0x00000006}, 361 - {0x00000030, 0x00000018}, 362 - {0x00000030, 0x00000018}, 363 - {0000000000, 0x00000006}, 364 - {0x01605000, 0x00000002}, 365 - {0x00065000, 0x00000002}, 366 - {0x00098000, 0x00000002}, 367 - {0x00061000, 0x00000002}, 368 - {0x64c0603e, 0x00000004}, 369 - {0x000380e6, 0x00000002}, 370 - {0x040025c5, 0x00000002}, 371 - {0x00080000, 0x00000016}, 372 - {0000000000, 0000000000}, 373 - {0x0400251d, 0x00000002}, 374 - {0x00007580, 0x00000002}, 375 - {0x00067581, 0x00000002}, 376 - {0x04002580, 0x00000002}, 377 - {0x00067581, 0x00000002}, 378 - {0x00000049, 0x00000004}, 379 - {0x00005000, 0000000000}, 380 - {0x000380e6, 0x00000002}, 381 - {0x040025c5, 0x00000002}, 382 - {0x00061000, 0x00000002}, 383 - {0x0000750e, 0x00000002}, 384 - {0x00019000, 0x00000002}, 385 - {0x00011055, 0x00000014}, 386 - {0x00000055, 0x00000012}, 387 - {0x0400250f, 0x00000002}, 388 - {0x0000504f, 0x00000004}, 389 - {0x000380e6, 0x00000002}, 390 - {0x040025c5, 0x00000002}, 391 - {0x00007565, 0x00000002}, 392 - {0x00007566, 0x00000002}, 393 - {0x00000058, 0x00000004}, 394 - {0x000380e6, 0x00000002}, 395 - {0x040025c5, 0x00000002}, 396 - {0x01e655b4, 0x00000002}, 397 - {0x4401b0e4, 0x00000002}, 398 - {0x01c110e4, 0x00000002}, 399 - {0x26667066, 0x00000018}, 400 - {0x040c2565, 0x00000002}, 401 - {0x00000066, 0x00000018}, 402 - {0x04002564, 0x00000002}, 403 - {0x00007566, 0x00000002}, 404 - {0x0000005d, 0x00000004}, 405 - {0x00401069, 0x00000008}, 406 - {0x00101000, 0x00000002}, 407 - {0x000d80ff, 0x00000002}, 408 - {0x0080006c, 0x00000008}, 409 - {0x000f9000, 0x00000002}, 410 - {0x000e00ff, 0x00000002}, 411 - {0000000000, 0x00000006}, 412 - {0x0000008f, 0x00000018}, 413 - {0x0000005b, 0x00000004}, 414 - {0x000380e6, 0x00000002}, 415 - {0x040025c5, 0x00000002}, 416 - {0x00007576, 0x00000002}, 417 - {0x00065000, 0x00000002}, 418 - {0x00009000, 0x00000002}, 419 - {0x00041000, 0x00000002}, 420 - {0x0c00350e, 0x00000002}, 421 - {0x00049000, 0x00000002}, 422 - {0x00051000, 0x00000002}, 423 - {0x01e785f8, 0x00000002}, 424 - {0x00200000, 0x00000002}, 425 - {0x0060007e, 0x0000000c}, 426 - {0x00007563, 0x00000002}, 427 - {0x006075f0, 0x00000021}, 428 - {0x20007073, 0x00000004}, 429 - {0x00005073, 0x00000004}, 430 - {0x000380e6, 0x00000002}, 431 - {0x040025c5, 0x00000002}, 432 - {0x00007576, 0x00000002}, 433 - {0x00007577, 0x00000002}, 434 - {0x0000750e, 0x00000002}, 435 - {0x0000750f, 0x00000002}, 436 - {0x00a05000, 0x00000002}, 437 - {0x00600083, 0x0000000c}, 438 - {0x006075f0, 0x00000021}, 439 - {0x000075f8, 0x00000002}, 440 - {0x00000083, 0x00000004}, 441 - {0x000a750e, 0x00000002}, 442 - {0x000380e6, 0x00000002}, 443 - {0x040025c5, 0x00000002}, 444 - {0x0020750f, 0x00000002}, 445 - {0x00600086, 0x00000004}, 446 - {0x00007570, 0x00000002}, 447 - {0x00007571, 0x00000002}, 448 - {0x00007572, 0x00000006}, 449 - {0x000380e6, 0x00000002}, 450 - {0x040025c5, 0x00000002}, 451 - {0x00005000, 0x00000002}, 452 - {0x00a05000, 0x00000002}, 453 - {0x00007568, 0x00000002}, 454 - {0x00061000, 0x00000002}, 455 - {0x00000095, 0x0000000c}, 456 - {0x00058000, 0x00000002}, 457 - {0x0c607562, 0x00000002}, 458 - {0x00000097, 0x00000004}, 459 - {0x000380e6, 0x00000002}, 460 - {0x040025c5, 0x00000002}, 461 - {0x00600096, 0x00000004}, 462 - {0x400070e5, 0000000000}, 463 - {0x000380e6, 0x00000002}, 464 - {0x040025c5, 0x00000002}, 465 - {0x000380e5, 0x00000002}, 466 - {0x000000a8, 0x0000001c}, 467 - {0x000650aa, 0x00000018}, 468 - {0x040025bb, 0x00000002}, 469 - {0x000610ab, 0x00000018}, 470 - {0x040075bc, 0000000000}, 471 - {0x000075bb, 0x00000002}, 472 - {0x000075bc, 0000000000}, 473 - {0x00090000, 0x00000006}, 474 - {0x00090000, 0x00000002}, 475 - {0x000d8002, 0x00000006}, 476 - {0x00007832, 0x00000002}, 477 - {0x00005000, 0x00000002}, 478 - {0x000380e7, 0x00000002}, 479 - {0x04002c97, 0x00000002}, 480 - {0x00007820, 0x00000002}, 481 - {0x00007821, 0x00000002}, 482 - {0x00007800, 0000000000}, 483 - {0x01200000, 0x00000002}, 484 - {0x20077000, 0x00000002}, 485 - {0x01200000, 0x00000002}, 486 - {0x20007000, 0x00000002}, 487 - {0x00061000, 0x00000002}, 488 - {0x0120751b, 0x00000002}, 489 - {0x8040750a, 0x00000002}, 490 - {0x8040750b, 0x00000002}, 491 - {0x00110000, 0x00000002}, 492 - {0x000380e5, 0x00000002}, 493 - {0x000000c6, 0x0000001c}, 494 - {0x000610ab, 0x00000018}, 495 - {0x844075bd, 0x00000002}, 496 - {0x000610aa, 0x00000018}, 497 - {0x840075bb, 0x00000002}, 498 - {0x000610ab, 0x00000018}, 499 - {0x844075bc, 0x00000002}, 500 - {0x000000c9, 0x00000004}, 501 - {0x804075bd, 0x00000002}, 502 - {0x800075bb, 0x00000002}, 503 - {0x804075bc, 0x00000002}, 504 - {0x00108000, 0x00000002}, 505 - {0x01400000, 0x00000002}, 506 - {0x006000cd, 0x0000000c}, 507 - {0x20c07000, 0x00000020}, 508 - {0x000000cf, 0x00000012}, 509 - {0x00800000, 0x00000006}, 510 - {0x0080751d, 0x00000006}, 511 - {0000000000, 0000000000}, 512 - {0x0000775c, 0x00000002}, 513 - {0x00a05000, 0x00000002}, 514 - {0x00661000, 0x00000002}, 515 - {0x0460275d, 0x00000020}, 516 - {0x00004000, 0000000000}, 517 - {0x01e00830, 0x00000002}, 518 - {0x21007000, 0000000000}, 519 - {0x6464614d, 0000000000}, 520 - {0x69687420, 0000000000}, 521 - {0x00000073, 0000000000}, 522 - {0000000000, 0000000000}, 523 - {0x00005000, 0x00000002}, 524 - {0x000380d0, 0x00000002}, 525 - {0x040025e0, 0x00000002}, 526 - {0x000075e1, 0000000000}, 527 - {0x00000001, 0000000000}, 528 - {0x000380e0, 0x00000002}, 529 - {0x04002394, 0x00000002}, 530 - {0x00005000, 0000000000}, 531 - {0000000000, 0000000000}, 532 - {0000000000, 0000000000}, 533 - {0x00000008, 0000000000}, 534 - {0x00000004, 0000000000}, 535 - {0000000000, 0000000000}, 536 - {0000000000, 0000000000}, 537 - {0000000000, 0000000000}, 538 - {0000000000, 0000000000}, 539 - {0000000000, 0000000000}, 540 - {0000000000, 0000000000}, 541 - {0000000000, 0000000000}, 542 - {0000000000, 0000000000}, 543 - {0000000000, 0000000000}, 544 - {0000000000, 0000000000}, 545 - {0000000000, 0000000000}, 546 - {0000000000, 0000000000}, 547 - {0000000000, 0000000000}, 548 - {0000000000, 0000000000}, 549 - {0000000000, 0000000000}, 550 - {0000000000, 0000000000}, 551 - {0000000000, 0000000000}, 552 - {0000000000, 0000000000}, 553 - {0000000000, 0000000000}, 554 - {0000000000, 0000000000}, 555 - {0000000000, 0000000000}, 556 - {0000000000, 0000000000}, 557 - {0000000000, 0000000000}, 558 - {0000000000, 0000000000}, 559 - }; 560 - 561 - static const u32 R300_cp_microcode[][2] = { 562 - {0x4200e000, 0000000000}, 563 - {0x4000e000, 0000000000}, 564 - {0x000000af, 0x00000008}, 565 - {0x000000b3, 0x00000008}, 566 - {0x6c5a504f, 0000000000}, 567 - {0x4f4f497a, 0000000000}, 568 - {0x5a578288, 0000000000}, 569 - {0x4f91906a, 0000000000}, 570 - {0x4f4f4f4f, 0000000000}, 571 - {0x4fe24f44, 0000000000}, 572 - {0x4f9c9c9c, 0000000000}, 573 - {0xdc4f4fde, 0000000000}, 574 - {0xa1cd4f4f, 0000000000}, 575 - {0xd29d9d9d, 0000000000}, 576 - {0x4f0f9fd7, 0000000000}, 577 - {0x000ca000, 0x00000004}, 578 - {0x000d0012, 0x00000038}, 579 - {0x0000e8b4, 0x00000004}, 580 - {0x000d0014, 0x00000038}, 581 - {0x0000e8b6, 0x00000004}, 582 - {0x000d0016, 0x00000038}, 583 - {0x0000e854, 0x00000004}, 584 - {0x000d0018, 0x00000038}, 585 - {0x0000e855, 0x00000004}, 586 - {0x000d001a, 0x00000038}, 587 - {0x0000e856, 0x00000004}, 588 - {0x000d001c, 0x00000038}, 589 - {0x0000e857, 0x00000004}, 590 - {0x000d001e, 0x00000038}, 591 - {0x0000e824, 0x00000004}, 592 - {0x000d0020, 0x00000038}, 593 - {0x0000e825, 0x00000004}, 594 - {0x000d0022, 0x00000038}, 595 - {0x0000e830, 0x00000004}, 596 - {0x000d0024, 0x00000038}, 597 - {0x0000f0c0, 0x00000004}, 598 - {0x000d0026, 0x00000038}, 599 - {0x0000f0c1, 0x00000004}, 600 - {0x000d0028, 0x00000038}, 601 - {0x0000f041, 0x00000004}, 602 - {0x000d002a, 0x00000038}, 603 - {0x0000f184, 0x00000004}, 604 - {0x000d002c, 0x00000038}, 605 - {0x0000f185, 0x00000004}, 606 - {0x000d002e, 0x00000038}, 607 - {0x0000f186, 0x00000004}, 608 - {0x000d0030, 0x00000038}, 609 - {0x0000f187, 0x00000004}, 610 - {0x000d0032, 0x00000038}, 611 - {0x0000f180, 0x00000004}, 612 - {0x000d0034, 0x00000038}, 613 - {0x0000f393, 0x00000004}, 614 - {0x000d0036, 0x00000038}, 615 - {0x0000f38a, 0x00000004}, 616 - {0x000d0038, 0x00000038}, 617 - {0x0000f38e, 0x00000004}, 618 - {0x0000e821, 0x00000004}, 619 - {0x0140a000, 0x00000004}, 620 - {0x00000043, 0x00000018}, 621 - {0x00cce800, 0x00000004}, 622 - {0x001b0001, 0x00000004}, 623 - {0x08004800, 0x00000004}, 624 - {0x001b0001, 0x00000004}, 625 - {0x08004800, 0x00000004}, 626 - {0x001b0001, 0x00000004}, 627 - {0x08004800, 0x00000004}, 628 - {0x0000003a, 0x00000008}, 629 - {0x0000a000, 0000000000}, 630 - {0x02c0a000, 0x00000004}, 631 - {0x000ca000, 0x00000004}, 632 - {0x00130000, 0x00000004}, 633 - {0x000c2000, 0x00000004}, 634 - {0xc980c045, 0x00000008}, 635 - {0x2000451d, 0x00000004}, 636 - {0x0000e580, 0x00000004}, 637 - {0x000ce581, 0x00000004}, 638 - {0x08004580, 0x00000004}, 639 - {0x000ce581, 0x00000004}, 640 - {0x0000004c, 0x00000008}, 641 - {0x0000a000, 0000000000}, 642 - {0x000c2000, 0x00000004}, 643 - {0x0000e50e, 0x00000004}, 644 - {0x00032000, 0x00000004}, 645 - {0x00022056, 0x00000028}, 646 - {0x00000056, 0x00000024}, 647 - {0x0800450f, 0x00000004}, 648 - {0x0000a050, 0x00000008}, 649 - {0x0000e565, 0x00000004}, 650 - {0x0000e566, 0x00000004}, 651 - {0x00000057, 0x00000008}, 652 - {0x03cca5b4, 0x00000004}, 653 - {0x05432000, 0x00000004}, 654 - {0x00022000, 0x00000004}, 655 - {0x4ccce063, 0x00000030}, 656 - {0x08274565, 0x00000004}, 657 - {0x00000063, 0x00000030}, 658 - {0x08004564, 0x00000004}, 659 - {0x0000e566, 0x00000004}, 660 - {0x0000005a, 0x00000008}, 661 - {0x00802066, 0x00000010}, 662 - {0x00202000, 0x00000004}, 663 - {0x001b00ff, 0x00000004}, 664 - {0x01000069, 0x00000010}, 665 - {0x001f2000, 0x00000004}, 666 - {0x001c00ff, 0x00000004}, 667 - {0000000000, 0x0000000c}, 668 - {0x00000085, 0x00000030}, 669 - {0x0000005a, 0x00000008}, 670 - {0x0000e576, 0x00000004}, 671 - {0x000ca000, 0x00000004}, 672 - {0x00012000, 0x00000004}, 673 - {0x00082000, 0x00000004}, 674 - {0x1800650e, 0x00000004}, 675 - {0x00092000, 0x00000004}, 676 - {0x000a2000, 0x00000004}, 677 - {0x000f0000, 0x00000004}, 678 - {0x00400000, 0x00000004}, 679 - {0x00000079, 0x00000018}, 680 - {0x0000e563, 0x00000004}, 681 - {0x00c0e5f9, 0x000000c2}, 682 - {0x0000006e, 0x00000008}, 683 - {0x0000a06e, 0x00000008}, 684 - {0x0000e576, 0x00000004}, 685 - {0x0000e577, 0x00000004}, 686 - {0x0000e50e, 0x00000004}, 687 - {0x0000e50f, 0x00000004}, 688 - {0x0140a000, 0x00000004}, 689 - {0x0000007c, 0x00000018}, 690 - {0x00c0e5f9, 0x000000c2}, 691 - {0x0000007c, 0x00000008}, 692 - {0x0014e50e, 0x00000004}, 693 - {0x0040e50f, 0x00000004}, 694 - {0x00c0007f, 0x00000008}, 695 - {0x0000e570, 0x00000004}, 696 - {0x0000e571, 0x00000004}, 697 - {0x0000e572, 0x0000000c}, 698 - {0x0000a000, 0x00000004}, 699 - {0x0140a000, 0x00000004}, 700 - {0x0000e568, 0x00000004}, 701 - {0x000c2000, 0x00000004}, 702 - {0x00000089, 0x00000018}, 703 - {0x000b0000, 0x00000004}, 704 - {0x18c0e562, 0x00000004}, 705 - {0x0000008b, 0x00000008}, 706 - {0x00c0008a, 0x00000008}, 707 - {0x000700e4, 0x00000004}, 708 - {0x00000097, 0x00000038}, 709 - {0x000ca099, 0x00000030}, 710 - {0x080045bb, 0x00000004}, 711 - {0x000c209a, 0x00000030}, 712 - {0x0800e5bc, 0000000000}, 713 - {0x0000e5bb, 0x00000004}, 714 - {0x0000e5bc, 0000000000}, 715 - {0x00120000, 0x0000000c}, 716 - {0x00120000, 0x00000004}, 717 - {0x001b0002, 0x0000000c}, 718 - {0x0000a000, 0x00000004}, 719 - {0x0000e821, 0x00000004}, 720 - {0x0000e800, 0000000000}, 721 - {0x0000e821, 0x00000004}, 722 - {0x0000e82e, 0000000000}, 723 - {0x02cca000, 0x00000004}, 724 - {0x00140000, 0x00000004}, 725 - {0x000ce1cc, 0x00000004}, 726 - {0x050de1cd, 0x00000004}, 727 - {0x000000a7, 0x00000020}, 728 - {0x4200e000, 0000000000}, 729 - {0x000000ae, 0x00000038}, 730 - {0x000ca000, 0x00000004}, 731 - {0x00140000, 0x00000004}, 732 - {0x000c2000, 0x00000004}, 733 - {0x00160000, 0x00000004}, 734 - {0x700ce000, 0x00000004}, 735 - {0x001400aa, 0x00000008}, 736 - {0x4000e000, 0000000000}, 737 - {0x02400000, 0x00000004}, 738 - {0x400ee000, 0x00000004}, 739 - {0x02400000, 0x00000004}, 740 - {0x4000e000, 0000000000}, 741 - {0x000c2000, 0x00000004}, 742 - {0x0240e51b, 0x00000004}, 743 - {0x0080e50a, 0x00000005}, 744 - {0x0080e50b, 0x00000005}, 745 - {0x00220000, 0x00000004}, 746 - {0x000700e4, 0x00000004}, 747 - {0x000000c1, 0x00000038}, 748 - {0x000c209a, 0x00000030}, 749 - {0x0880e5bd, 0x00000005}, 750 - {0x000c2099, 0x00000030}, 751 - {0x0800e5bb, 0x00000005}, 752 - {0x000c209a, 0x00000030}, 753 - {0x0880e5bc, 0x00000005}, 754 - {0x000000c4, 0x00000008}, 755 - {0x0080e5bd, 0x00000005}, 756 - {0x0000e5bb, 0x00000005}, 757 - {0x0080e5bc, 0x00000005}, 758 - {0x00210000, 0x00000004}, 759 - {0x02800000, 0x00000004}, 760 - {0x00c000c8, 0x00000018}, 761 - {0x4180e000, 0x00000040}, 762 - {0x000000ca, 0x00000024}, 763 - {0x01000000, 0x0000000c}, 764 - {0x0100e51d, 0x0000000c}, 765 - {0x000045bb, 0x00000004}, 766 - {0x000080c4, 0x00000008}, 767 - {0x0000f3ce, 0x00000004}, 768 - {0x0140a000, 0x00000004}, 769 - {0x00cc2000, 0x00000004}, 770 - {0x08c053cf, 0x00000040}, 771 - {0x00008000, 0000000000}, 772 - {0x0000f3d2, 0x00000004}, 773 - {0x0140a000, 0x00000004}, 774 - {0x00cc2000, 0x00000004}, 775 - {0x08c053d3, 0x00000040}, 776 - {0x00008000, 0000000000}, 777 - {0x0000f39d, 0x00000004}, 778 - {0x0140a000, 0x00000004}, 779 - {0x00cc2000, 0x00000004}, 780 - {0x08c0539e, 0x00000040}, 781 - {0x00008000, 0000000000}, 782 - {0x03c00830, 0x00000004}, 783 - {0x4200e000, 0000000000}, 784 - {0x0000a000, 0x00000004}, 785 - {0x200045e0, 0x00000004}, 786 - {0x0000e5e1, 0000000000}, 787 - {0x00000001, 0000000000}, 788 - {0x000700e1, 0x00000004}, 789 - {0x0800e394, 0000000000}, 790 - {0000000000, 0000000000}, 791 - {0000000000, 0000000000}, 792 - {0000000000, 0000000000}, 793 - {0000000000, 0000000000}, 794 - {0000000000, 0000000000}, 795 - {0000000000, 0000000000}, 796 - {0000000000, 0000000000}, 797 - {0000000000, 0000000000}, 798 - {0000000000, 0000000000}, 799 - {0000000000, 0000000000}, 800 - {0000000000, 0000000000}, 801 - {0000000000, 0000000000}, 802 - {0000000000, 0000000000}, 803 - {0000000000, 0000000000}, 804 - {0000000000, 0000000000}, 805 - {0000000000, 0000000000}, 806 - {0000000000, 0000000000}, 807 - {0000000000, 0000000000}, 808 - {0000000000, 0000000000}, 809 - {0000000000, 0000000000}, 810 - {0000000000, 0000000000}, 811 - {0000000000, 0000000000}, 812 - {0000000000, 0000000000}, 813 - {0000000000, 0000000000}, 814 - {0000000000, 0000000000}, 815 - {0000000000, 0000000000}, 816 - {0000000000, 0000000000}, 817 - {0000000000, 0000000000}, 818 - }; 819 - 820 - static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 43 + static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 821 44 { 822 45 u32 ret; 823 46 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); ··· 50 825 return ret; 51 826 } 52 827 828 + static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 829 + { 830 + u32 ret; 831 + RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); 832 + ret = RADEON_READ(RS480_NB_MC_DATA); 833 + RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); 834 + return ret; 835 + } 836 + 53 837 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 54 838 { 839 + u32 ret; 55 840 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 56 - return RADEON_READ(RS690_MC_DATA); 841 + ret = RADEON_READ(RS690_MC_DATA); 842 + RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); 843 + return ret; 844 + } 845 + 846 + static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 847 + { 848 + if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 849 + return RS690_READ_MCIND(dev_priv, addr); 850 + else 851 + return RS480_READ_MCIND(dev_priv, addr); 57 852 } 58 853 59 854 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) 60 855 { 61 856 62 857 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 63 - return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); 858 + return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); 64 859 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 65 860 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); 66 861 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 67 - return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 862 + return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 68 863 else 69 864 return RADEON_READ(RADEON_MC_FB_LOCATION); 70 865 } ··· 92 847 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) 93 848 { 94 849 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 95 - RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); 850 + R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); 96 851 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 97 852 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); 98 853 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 99 - RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 854 + R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 100 855 else 101 856 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); 102 857 } ··· 104 859 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) 105 860 { 106 861 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 107 - RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); 862 + R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); 108 863 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 109 864 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); 110 865 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 111 - RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 866 + R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 112 867 else 113 868 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); 869 + } 870 + 871 + static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) 872 + { 873 + u32 agp_base_hi = upper_32_bits(agp_base); 874 + u32 agp_base_lo = agp_base & 0xffffffff; 875 + 876 + if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { 877 + R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo); 878 + R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi); 879 + } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { 880 + RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); 881 + RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); 882 + } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { 883 + R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); 884 + R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); 885 + } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) { 886 + RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 887 + RADEON_WRITE(RS480_AGP_BASE_2, 0); 888 + } else { 889 + RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 890 + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) 891 + RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi); 892 + } 114 893 } 115 894 116 895 static int RADEON_READ_PLL(struct drm_device * dev, int addr) ··· 149 880 { 150 881 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); 151 882 return RADEON_READ(RADEON_PCIE_DATA); 152 - } 153 - 154 - static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr) 155 - { 156 - u32 ret; 157 - RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f); 158 - ret = RADEON_READ(RADEON_IGPGART_DATA); 159 - RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f); 160 - return ret; 161 883 } 162 884 163 885 #if RADEON_FIFO_DEBUG ··· 185 925 186 926 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 187 927 188 - tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); 189 - tmp |= RADEON_RB3D_DC_FLUSH_ALL; 190 - RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); 928 + if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { 929 + tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); 930 + tmp |= RADEON_RB3D_DC_FLUSH_ALL; 931 + RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); 191 932 192 - for (i = 0; i < dev_priv->usec_timeout; i++) { 193 - if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) 194 - & RADEON_RB3D_DC_BUSY)) { 195 - return 0; 933 + for (i = 0; i < dev_priv->usec_timeout; i++) { 934 + if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) 935 + & RADEON_RB3D_DC_BUSY)) { 936 + return 0; 937 + } 938 + DRM_UDELAY(1); 196 939 } 197 - DRM_UDELAY(1); 940 + } else { 941 + /* 3D */ 942 + tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT); 943 + tmp |= RADEON_RB3D_DC_FLUSH_ALL; 944 + RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp); 945 + 946 + /* 2D */ 947 + tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT); 948 + tmp |= RADEON_RB3D_DC_FLUSH_ALL; 949 + RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp); 950 + 951 + for (i = 0; i < dev_priv->usec_timeout; i++) { 952 + if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT) 953 + & RADEON_RB3D_DC_BUSY)) { 954 + return 0; 955 + } 956 + DRM_UDELAY(1); 957 + } 198 958 } 199 959 200 960 #if RADEON_FIFO_DEBUG ··· 271 991 return -EBUSY; 272 992 } 273 993 994 + static void radeon_init_pipes(drm_radeon_private_t *dev_priv) 995 + { 996 + uint32_t gb_tile_config, gb_pipe_sel = 0; 997 + 998 + /* RS4xx/RS6xx/R4xx/R5xx */ 999 + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { 1000 + gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); 1001 + dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; 1002 + } else { 1003 + /* R3xx */ 1004 + if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || 1005 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { 1006 + dev_priv->num_gb_pipes = 2; 1007 + } else { 1008 + /* R3Vxx */ 1009 + dev_priv->num_gb_pipes = 1; 1010 + } 1011 + } 1012 + DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); 1013 + 1014 + gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); 1015 + 1016 + switch (dev_priv->num_gb_pipes) { 1017 + case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; 1018 + case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; 1019 + case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; 1020 + default: 1021 + case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; 1022 + } 1023 + 1024 + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { 1025 + RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); 1026 + RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); 1027 + } 1028 + RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); 1029 + radeon_do_wait_for_idle(dev_priv); 1030 + RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); 1031 + RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) | 1032 + R300_DC_AUTOFLUSH_ENABLE | 1033 + R300_DC_DC_DISABLE_IGNORE_PE)); 1034 + 1035 + 1036 + } 1037 + 274 1038 /* ================================================================ 275 1039 * CP control, initialization 276 1040 */ ··· 328 1004 radeon_do_wait_for_idle(dev_priv); 329 1005 330 1006 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); 331 - 332 - if (dev_priv->microcode_version == UCODE_R200) { 1007 + if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || 1008 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || 1009 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || 1010 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || 1011 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { 1012 + DRM_INFO("Loading R100 Microcode\n"); 1013 + for (i = 0; i < 256; i++) { 1014 + RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 1015 + R100_cp_microcode[i][1]); 1016 + RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 1017 + R100_cp_microcode[i][0]); 1018 + } 1019 + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || 1020 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || 1021 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || 1022 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { 333 1023 DRM_INFO("Loading R200 Microcode\n"); 334 1024 for (i = 0; i < 256; i++) { 335 1025 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, ··· 351 1013 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 352 1014 R200_cp_microcode[i][0]); 353 1015 } 354 - } else if (dev_priv->microcode_version == UCODE_R300) { 1016 + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || 1017 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || 1018 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || 1019 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || 1020 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 355 1021 DRM_INFO("Loading R300 Microcode\n"); 356 1022 for (i = 0; i < 256; i++) { 357 1023 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, ··· 363 1021 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 364 1022 R300_cp_microcode[i][0]); 365 1023 } 366 - } else { 1024 + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || 1025 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { 1026 + DRM_INFO("Loading R400 Microcode\n"); 367 1027 for (i = 0; i < 256; i++) { 368 1028 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 369 - radeon_cp_microcode[i][1]); 1029 + R420_cp_microcode[i][1]); 370 1030 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 371 - radeon_cp_microcode[i][0]); 1031 + R420_cp_microcode[i][0]); 1032 + } 1033 + } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { 1034 + DRM_INFO("Loading RS690 Microcode\n"); 1035 + for (i = 0; i < 256; i++) { 1036 + RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 1037 + RS690_cp_microcode[i][1]); 1038 + RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 1039 + RS690_cp_microcode[i][0]); 1040 + } 1041 + } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || 1042 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || 1043 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || 1044 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) || 1045 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || 1046 + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { 1047 + DRM_INFO("Loading R500 Microcode\n"); 1048 + for (i = 0; i < 256; i++) { 1049 + RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, 1050 + R520_cp_microcode[i][1]); 1051 + RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, 1052 + R520_cp_microcode[i][0]); 372 1053 } 373 1054 } 374 1055 } ··· 486 1121 static int radeon_do_engine_reset(struct drm_device * dev) 487 1122 { 488 1123 drm_radeon_private_t *dev_priv = dev->dev_private; 489 - u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; 1124 + u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset; 490 1125 DRM_DEBUG("\n"); 491 1126 492 1127 radeon_do_pixcache_flush(dev_priv); 493 1128 494 - if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { 1129 + if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { 1130 + /* may need something similar for newer chips */ 495 1131 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); 496 1132 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); 497 1133 ··· 503 1137 RADEON_FORCEON_YCLKB | 504 1138 RADEON_FORCEON_MC | 505 1139 RADEON_FORCEON_AIC)); 1140 + } 506 1141 507 - rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); 1142 + rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); 508 1143 509 - RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 510 - RADEON_SOFT_RESET_CP | 511 - RADEON_SOFT_RESET_HI | 512 - RADEON_SOFT_RESET_SE | 513 - RADEON_SOFT_RESET_RE | 514 - RADEON_SOFT_RESET_PP | 515 - RADEON_SOFT_RESET_E2 | 516 - RADEON_SOFT_RESET_RB)); 517 - RADEON_READ(RADEON_RBBM_SOFT_RESET); 518 - RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 519 - ~(RADEON_SOFT_RESET_CP | 520 - RADEON_SOFT_RESET_HI | 521 - RADEON_SOFT_RESET_SE | 522 - RADEON_SOFT_RESET_RE | 523 - RADEON_SOFT_RESET_PP | 524 - RADEON_SOFT_RESET_E2 | 525 - RADEON_SOFT_RESET_RB))); 526 - RADEON_READ(RADEON_RBBM_SOFT_RESET); 1144 + RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 1145 + RADEON_SOFT_RESET_CP | 1146 + RADEON_SOFT_RESET_HI | 1147 + RADEON_SOFT_RESET_SE | 1148 + RADEON_SOFT_RESET_RE | 1149 + RADEON_SOFT_RESET_PP | 1150 + RADEON_SOFT_RESET_E2 | 1151 + RADEON_SOFT_RESET_RB)); 1152 + RADEON_READ(RADEON_RBBM_SOFT_RESET); 1153 + RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 1154 + ~(RADEON_SOFT_RESET_CP | 1155 + RADEON_SOFT_RESET_HI | 1156 + RADEON_SOFT_RESET_SE | 1157 + RADEON_SOFT_RESET_RE | 1158 + RADEON_SOFT_RESET_PP | 1159 + RADEON_SOFT_RESET_E2 | 1160 + RADEON_SOFT_RESET_RB))); 1161 + RADEON_READ(RADEON_RBBM_SOFT_RESET); 527 1162 1163 + if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { 528 1164 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); 529 1165 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); 530 1166 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 531 1167 } 1168 + 1169 + /* setup the raster pipes */ 1170 + if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) 1171 + radeon_init_pipes(dev_priv); 532 1172 533 1173 /* Reset the CP ring */ 534 1174 radeon_do_cp_reset(dev_priv); ··· 566 1194 567 1195 #if __OS_HAS_AGP 568 1196 if (dev_priv->flags & RADEON_IS_AGP) { 569 - RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); 1197 + radeon_write_agp_base(dev_priv, dev->agp->base); 1198 + 570 1199 radeon_write_agp_location(dev_priv, 571 1200 (((dev_priv->gart_vm_start - 1 + 572 1201 dev_priv->gart_size) & 0xffff0000) | ··· 712 1339 /* Enable or disable IGP GART on the chip */ 713 1340 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) 714 1341 { 715 - u32 temp, tmp; 716 - 717 - tmp = RADEON_READ(RADEON_AIC_CNTL); 718 - if (on) { 719 - DRM_DEBUG("programming igpgart %08X %08lX %08X\n", 720 - dev_priv->gart_vm_start, 721 - (long)dev_priv->gart_info.bus_addr, 722 - dev_priv->gart_size); 723 - 724 - RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000); 725 - RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1); 726 - RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800); 727 - RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR, 728 - dev_priv->gart_info.bus_addr); 729 - 730 - temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39); 731 - RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp); 732 - 733 - RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start); 734 - dev_priv->gart_size = 32*1024*1024; 735 - radeon_write_agp_location(dev_priv, 736 - (((dev_priv->gart_vm_start - 1 + 737 - dev_priv->gart_size) & 0xffff0000) | 738 - (dev_priv->gart_vm_start >> 16))); 739 - 740 - temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE); 741 - RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp); 742 - 743 - RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH); 744 - RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1); 745 - RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH); 746 - RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0); 747 - } 748 - } 749 - 750 - /* Enable or disable RS690 GART on the chip */ 751 - static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on) 752 - { 753 1342 u32 temp; 754 1343 755 1344 if (on) { 756 - DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n", 1345 + DRM_DEBUG("programming igp gart %08X %08lX %08X\n", 757 1346 dev_priv->gart_vm_start, 758 1347 (long)dev_priv->gart_info.bus_addr, 759 1348 dev_priv->gart_size); 760 1349 761 - temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL); 762 - RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000); 1350 + temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); 1351 + if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) 1352 + IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | 1353 + RS690_BLOCK_GFX_D3_EN)); 1354 + else 1355 + IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); 763 1356 764 - RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, 765 - RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); 1357 + IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | 1358 + RS480_VA_SIZE_32MB)); 766 1359 767 - temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID); 768 - RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800); 1360 + temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); 1361 + IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | 1362 + RS480_TLB_ENABLE | 1363 + RS480_GTW_LAC_EN | 1364 + RS480_1LEVEL_GART)); 769 1365 770 - RS690_WRITE_MCIND(RS690_MC_GART_BASE, 771 - dev_priv->gart_info.bus_addr); 1366 + temp = dev_priv->gart_info.bus_addr & 0xfffff000; 1367 + temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; 1368 + IGP_WRITE_MCIND(RS480_GART_BASE, temp); 772 1369 773 - temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL); 774 - RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000); 1370 + temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); 1371 + IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | 1372 + RS480_REQ_TYPE_SNOOP_DIS)); 775 1373 776 - RS690_WRITE_MCIND(RS690_MC_AGP_BASE, 777 - (unsigned int)dev_priv->gart_vm_start); 1374 + radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); 778 1375 779 1376 dev_priv->gart_size = 32*1024*1024; 780 1377 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & 781 1378 0xffff0000) | (dev_priv->gart_vm_start >> 16)); 782 1379 783 - RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp); 1380 + radeon_write_agp_location(dev_priv, temp); 784 1381 785 - temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE); 786 - RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, 787 - RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); 1382 + temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); 1383 + IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | 1384 + RS480_VA_SIZE_32MB)); 788 1385 789 1386 do { 790 - temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); 791 - if ((temp & RS690_MC_GART_CLEAR_STATUS) == 792 - RS690_MC_GART_CLEAR_DONE) 1387 + temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 1388 + if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) 793 1389 break; 794 1390 DRM_UDELAY(1); 795 1391 } while (1); 796 1392 797 - RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, 798 - RS690_MC_GART_CC_CLEAR); 1393 + IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 1394 + RS480_GART_CACHE_INVALIDATE); 1395 + 799 1396 do { 800 - temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); 801 - if ((temp & RS690_MC_GART_CLEAR_STATUS) == 802 - RS690_MC_GART_CLEAR_DONE) 1397 + temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 1398 + if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) 803 1399 break; 804 1400 DRM_UDELAY(1); 805 1401 } while (1); 806 1402 807 - RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, 808 - RS690_MC_GART_CC_NO_CHANGE); 1403 + IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); 809 1404 } else { 810 - RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS); 1405 + IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 811 1406 } 812 1407 } 813 1408 ··· 813 1472 { 814 1473 u32 tmp; 815 1474 816 - if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { 817 - radeon_set_rs690gart(dev_priv, on); 818 - return; 819 - } 820 - 821 - if (dev_priv->flags & RADEON_IS_IGPGART) { 1475 + if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 1476 + (dev_priv->flags & RADEON_IS_IGPGART)) { 822 1477 radeon_set_igpgart(dev_priv, on); 823 1478 return; 824 1479 } ··· 1288 1951 radeon_cp_init_ring_buffer(dev, dev_priv); 1289 1952 1290 1953 radeon_do_engine_reset(dev); 1954 + radeon_enable_interrupt(dev); 1291 1955 1292 1956 DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1293 1957

+8

drivers/char/drm/radeon_drm.h

··· 240 240 # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 241 241 242 242 #define R300_CMD_SCRATCH 8 243 + #define R300_CMD_R500FP 9 243 244 244 245 typedef union { 245 246 unsigned int u; ··· 269 268 struct { 270 269 unsigned char cmd_type, reg, n_bufs, flags; 271 270 } scratch; 271 + struct { 272 + unsigned char cmd_type, count, adrlo, adrhi_flags; 273 + } r500fp; 272 274 } drm_r300_cmd_header_t; 273 275 274 276 #define RADEON_FRONT 0x1 ··· 281 277 #define RADEON_CLEAR_FASTZ 0x80000000 282 278 #define RADEON_USE_HIERZ 0x40000000 283 279 #define RADEON_USE_COMP_ZBUF 0x20000000 280 + 281 + #define R500FP_CONSTANT_TYPE (1 << 1) 282 + #define R500FP_CONSTANT_CLAMP (1 << 2) 284 283 285 284 /* Primitive types 286 285 */ ··· 676 669 #define RADEON_PARAM_CARD_TYPE 12 677 670 #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ 678 671 #define RADEON_PARAM_FB_LOCATION 14 /* FB location */ 672 + #define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ 679 673 680 674 typedef struct drm_radeon_getparam { 681 675 int param;

+180 -73

drivers/char/drm/radeon_drv.h

··· 38 38 39 39 #define DRIVER_NAME "radeon" 40 40 #define DRIVER_DESC "ATI Radeon" 41 - #define DRIVER_DATE "20060524" 41 + #define DRIVER_DATE "20080528" 42 42 43 43 /* Interface history: 44 44 * ··· 98 98 * 1.26- Add support for variable size PCI(E) gart aperture 99 99 * 1.27- Add support for IGP GART 100 100 * 1.28- Add support for VBL on CRTC2 101 + * 1.29- R500 3D cmd buffer support 101 102 */ 102 103 #define DRIVER_MAJOR 1 103 - #define DRIVER_MINOR 28 104 + #define DRIVER_MINOR 29 104 105 #define DRIVER_PATCHLEVEL 0 105 106 106 107 /* ··· 123 122 CHIP_RV380, 124 123 CHIP_R420, 125 124 CHIP_RV410, 126 - CHIP_RS400, 125 + CHIP_RS480, 127 126 CHIP_RS690, 128 127 CHIP_RV515, 129 128 CHIP_R520, ··· 295 294 int vblank_crtc; 296 295 uint32_t irq_enable_reg; 297 296 int irq_enabled; 297 + uint32_t r500_disp_irq_reg; 298 298 299 299 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 300 300 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; ··· 309 307 /* starting from here on, data is preserved accross an open */ 310 308 uint32_t flags; /* see radeon_chip_flags */ 311 309 unsigned long fb_aper_offset; 310 + 311 + int num_gb_pipes; 312 312 } drm_radeon_private_t; 313 313 314 314 typedef struct drm_radeon_buf_priv { ··· 386 382 extern void radeon_driver_irq_preinstall(struct drm_device * dev); 387 383 extern void radeon_driver_irq_postinstall(struct drm_device * dev); 388 384 extern void radeon_driver_irq_uninstall(struct drm_device * dev); 385 + extern void radeon_enable_interrupt(struct drm_device *dev); 389 386 extern int radeon_vblank_crtc_get(struct drm_device *dev); 390 387 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 391 388 ··· 449 444 #define RADEON_PCIE_DATA 0x0034 450 445 #define RADEON_PCIE_TX_GART_CNTL 0x10 451 446 # define RADEON_PCIE_TX_GART_EN (1 << 0) 452 - # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) 453 - # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) 454 - # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) 455 - # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) 456 - # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) 457 - # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) 458 - # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) 447 + # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 448 + # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 449 + # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 450 + # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 451 + # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 452 + # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 453 + # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 459 454 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 460 455 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 461 456 #define RADEON_PCIE_TX_GART_BASE 0x13 ··· 464 459 #define RADEON_PCIE_TX_GART_END_LO 0x16 465 460 #define RADEON_PCIE_TX_GART_END_HI 0x17 466 461 467 - #define RADEON_IGPGART_INDEX 0x168 468 - #define RADEON_IGPGART_DATA 0x16c 469 - #define RADEON_IGPGART_UNK_18 0x18 470 - #define RADEON_IGPGART_CTRL 0x2b 471 - #define RADEON_IGPGART_BASE_ADDR 0x2c 472 - #define RADEON_IGPGART_FLUSH 0x2e 473 - #define RADEON_IGPGART_ENABLE 0x38 474 - #define RADEON_IGPGART_UNK_39 0x39 462 + #define RS480_NB_MC_INDEX 0x168 463 + # define RS480_NB_MC_IND_WR_EN (1 << 8) 464 + #define RS480_NB_MC_DATA 0x16c 475 465 476 466 #define RS690_MC_INDEX 0x78 477 467 # define RS690_MC_INDEX_MASK 0x1ff ··· 474 474 # define RS690_MC_INDEX_WR_ACK 0x7f 475 475 #define RS690_MC_DATA 0x7c 476 476 477 - #define RS690_MC_MISC_CNTL 0x18 478 - #define RS690_MC_GART_FEATURE_ID 0x2b 479 - #define RS690_MC_GART_BASE 0x2c 480 - #define RS690_MC_GART_CACHE_CNTL 0x2e 481 - # define RS690_MC_GART_CC_NO_CHANGE 0x0 482 - # define RS690_MC_GART_CC_CLEAR 0x1 483 - # define RS690_MC_GART_CLEAR_STATUS (1 << 1) 484 - # define RS690_MC_GART_CLEAR_DONE (0 << 1) 485 - # define RS690_MC_GART_CLEAR_PENDING (1 << 1) 486 - #define RS690_MC_AGP_SIZE 0x38 487 - # define RS690_MC_GART_DIS 0x0 488 - # define RS690_MC_GART_EN 0x1 489 - # define RS690_MC_AGP_SIZE_32MB (0 << 1) 490 - # define RS690_MC_AGP_SIZE_64MB (1 << 1) 491 - # define RS690_MC_AGP_SIZE_128MB (2 << 1) 492 - # define RS690_MC_AGP_SIZE_256MB (3 << 1) 493 - # define RS690_MC_AGP_SIZE_512MB (4 << 1) 494 - # define RS690_MC_AGP_SIZE_1GB (5 << 1) 495 - # define RS690_MC_AGP_SIZE_2GB (6 << 1) 496 - #define RS690_MC_AGP_MODE_CONTROL 0x39 477 + /* MC indirect registers */ 478 + #define RS480_MC_MISC_CNTL 0x18 479 + # define RS480_DISABLE_GTW (1 << 1) 480 + /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 481 + # define RS480_GART_INDEX_REG_EN (1 << 12) 482 + # define RS690_BLOCK_GFX_D3_EN (1 << 14) 483 + #define RS480_K8_FB_LOCATION 0x1e 484 + #define RS480_GART_FEATURE_ID 0x2b 485 + # define RS480_HANG_EN (1 << 11) 486 + # define RS480_TLB_ENABLE (1 << 18) 487 + # define RS480_P2P_ENABLE (1 << 19) 488 + # define RS480_GTW_LAC_EN (1 << 25) 489 + # define RS480_2LEVEL_GART (0 << 30) 490 + # define RS480_1LEVEL_GART (1 << 30) 491 + # define RS480_PDC_EN (1 << 31) 492 + #define RS480_GART_BASE 0x2c 493 + #define RS480_GART_CACHE_CNTRL 0x2e 494 + # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 495 + #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 496 + # define RS480_GART_EN (1 << 0) 497 + # define RS480_VA_SIZE_32MB (0 << 1) 498 + # define RS480_VA_SIZE_64MB (1 << 1) 499 + # define RS480_VA_SIZE_128MB (2 << 1) 500 + # define RS480_VA_SIZE_256MB (3 << 1) 501 + # define RS480_VA_SIZE_512MB (4 << 1) 502 + # define RS480_VA_SIZE_1GB (5 << 1) 503 + # define RS480_VA_SIZE_2GB (6 << 1) 504 + #define RS480_AGP_MODE_CNTL 0x39 505 + # define RS480_POST_GART_Q_SIZE (1 << 18) 506 + # define RS480_NONGART_SNOOP (1 << 19) 507 + # define RS480_AGP_RD_BUF_SIZE (1 << 20) 508 + # define RS480_REQ_TYPE_SNOOP_SHIFT 22 509 + # define RS480_REQ_TYPE_SNOOP_MASK 0x3 510 + # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 511 + #define RS480_MC_MISC_UMA_CNTL 0x5f 512 + #define RS480_MC_MCLK_CNTL 0x7a 513 + #define RS480_MC_UMA_DUALCH_CNTL 0x86 514 + 497 515 #define RS690_MC_FB_LOCATION 0x100 498 516 #define RS690_MC_AGP_LOCATION 0x101 499 517 #define RS690_MC_AGP_BASE 0x102 518 + #define RS690_MC_AGP_BASE_2 0x103 500 519 501 520 #define R520_MC_IND_INDEX 0x70 502 - #define R520_MC_IND_WR_EN (1<<24) 521 + #define R520_MC_IND_WR_EN (1 << 24) 503 522 #define R520_MC_IND_DATA 0x74 504 523 505 524 #define RV515_MC_FB_LOCATION 0x01 506 525 #define RV515_MC_AGP_LOCATION 0x02 526 + #define RV515_MC_AGP_BASE 0x03 527 + #define RV515_MC_AGP_BASE_2 0x04 507 528 508 529 #define R520_MC_FB_LOCATION 0x04 509 530 #define R520_MC_AGP_LOCATION 0x05 531 + #define R520_MC_AGP_BASE 0x06 532 + #define R520_MC_AGP_BASE_2 0x07 510 533 511 534 #define RADEON_MPP_TB_CONFIG 0x01c0 512 535 #define RADEON_MEM_CNTL 0x0140 513 536 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 537 + #define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 538 + #define RS480_AGP_BASE_2 0x0164 514 539 #define RADEON_AGP_BASE 0x0170 540 + 541 + /* pipe config regs */ 542 + #define R400_GB_PIPE_SELECT 0x402c 543 + #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 544 + #define R500_SU_REG_DEST 0x42c8 545 + #define R300_GB_TILE_CONFIG 0x4018 546 + # define R300_ENABLE_TILING (1 << 0) 547 + # define R300_PIPE_COUNT_RV350 (0 << 1) 548 + # define R300_PIPE_COUNT_R300 (3 << 1) 549 + # define R300_PIPE_COUNT_R420_3P (6 << 1) 550 + # define R300_PIPE_COUNT_R420 (7 << 1) 551 + # define R300_TILE_SIZE_8 (0 << 4) 552 + # define R300_TILE_SIZE_16 (1 << 4) 553 + # define R300_TILE_SIZE_32 (2 << 4) 554 + # define R300_SUBPIXEL_1_12 (0 << 16) 555 + # define R300_SUBPIXEL_1_16 (1 << 16) 556 + #define R300_DST_PIPE_CONFIG 0x170c 557 + # define R300_PIPE_AUTO_CONFIG (1 << 31) 558 + #define R300_RB2D_DSTCACHE_MODE 0x3428 559 + # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 560 + # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 515 561 516 562 #define RADEON_RB3D_COLOROFFSET 0x1c40 517 563 #define RADEON_RB3D_COLORPITCH 0x1c48 ··· 662 616 #define RADEON_PP_TXFILTER_1 0x1c6c 663 617 #define RADEON_PP_TXFILTER_2 0x1c84 664 618 665 - #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 666 - # define RADEON_RB2D_DC_FLUSH (3 << 0) 667 - # define RADEON_RB2D_DC_FREE (3 << 2) 668 - # define RADEON_RB2D_DC_FLUSH_ALL 0xf 669 - # define RADEON_RB2D_DC_BUSY (1 << 31) 619 + #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 620 + #define R300_DSTCACHE_CTLSTAT 0x1714 621 + # define R300_RB2D_DC_FLUSH (3 << 0) 622 + # define R300_RB2D_DC_FREE (3 << 2) 623 + # define R300_RB2D_DC_FLUSH_ALL 0xf 624 + # define R300_RB2D_DC_BUSY (1 << 31) 670 625 #define RADEON_RB3D_CNTL 0x1c3c 671 626 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 672 627 # define RADEON_PLANE_MASK_ENABLE (1 << 1) ··· 690 643 # define RADEON_RB3D_ZC_FREE (1 << 2) 691 644 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 692 645 # define RADEON_RB3D_ZC_BUSY (1 << 31) 646 + #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 647 + # define R300_ZC_FLUSH (1 << 0) 648 + # define R300_ZC_FREE (1 << 1) 649 + # define R300_ZC_FLUSH_ALL 0x3 650 + # define R300_ZC_BUSY (1 << 31) 693 651 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 694 652 # define RADEON_RB3D_DC_FLUSH (3 << 0) 695 653 # define RADEON_RB3D_DC_FREE (3 << 2) 696 654 # define RADEON_RB3D_DC_FLUSH_ALL 0xf 697 655 # define RADEON_RB3D_DC_BUSY (1 << 31) 656 + #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 657 + # define R300_RB3D_DC_FINISH (1 << 4) 698 658 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 699 659 # define RADEON_Z_TEST_MASK (7 << 4) 700 660 # define RADEON_Z_TEST_ALWAYS (7 << 4) ··· 1111 1057 1112 1058 #define R200_VAP_PVS_CNTL_1 0x22D0 1113 1059 1060 + #define R500_D1CRTC_STATUS 0x609c 1061 + #define R500_D2CRTC_STATUS 0x689c 1062 + #define R500_CRTC_V_BLANK (1<<0) 1063 + 1064 + #define R500_D1CRTC_FRAME_COUNT 0x60a4 1065 + #define R500_D2CRTC_FRAME_COUNT 0x68a4 1066 + 1067 + #define R500_D1MODE_V_COUNTER 0x6530 1068 + #define R500_D2MODE_V_COUNTER 0x6d30 1069 + 1070 + #define R500_D1MODE_VBLANK_STATUS 0x6534 1071 + #define R500_D2MODE_VBLANK_STATUS 0x6d34 1072 + #define R500_VBLANK_OCCURED (1<<0) 1073 + #define R500_VBLANK_ACK (1<<4) 1074 + #define R500_VBLANK_STAT (1<<12) 1075 + #define R500_VBLANK_INT (1<<16) 1076 + 1077 + #define R500_DxMODE_INT_MASK 0x6540 1078 + #define R500_D1MODE_INT_MASK (1<<0) 1079 + #define R500_D2MODE_INT_MASK (1<<8) 1080 + 1081 + #define R500_DISP_INTERRUPT_STATUS 0x7edc 1082 + #define R500_D1_VBLANK_INTERRUPT (1 << 4) 1083 + #define R500_D2_VBLANK_INTERRUPT (1 << 5) 1084 + 1114 1085 /* Constants */ 1115 1086 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1116 1087 ··· 1157 1078 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1158 1079 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1159 1080 1160 - #define RADEON_WRITE_PLL( addr, val ) \ 1081 + #define RADEON_WRITE_PLL(addr, val) \ 1161 1082 do { \ 1162 - RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 1083 + RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ 1163 1084 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1164 - RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 1085 + RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ 1165 1086 } while (0) 1166 1087 1167 - #define RADEON_WRITE_IGPGART( addr, val ) \ 1088 + #define RADEON_WRITE_PCIE(addr, val) \ 1168 1089 do { \ 1169 - RADEON_WRITE( RADEON_IGPGART_INDEX, \ 1170 - ((addr) & 0x7f) | (1 << 8)); \ 1171 - RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \ 1172 - RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \ 1173 - } while (0) 1174 - 1175 - #define RADEON_WRITE_PCIE( addr, val ) \ 1176 - do { \ 1177 - RADEON_WRITE8( RADEON_PCIE_INDEX, \ 1090 + RADEON_WRITE8(RADEON_PCIE_INDEX, \ 1178 1091 ((addr) & 0xff)); \ 1179 - RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 1092 + RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ 1180 1093 } while (0) 1181 1094 1182 - #define RADEON_WRITE_MCIND( addr, val ) \ 1183 - do { \ 1184 - RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1185 - RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1186 - RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1187 - } while (0) 1095 + #define R500_WRITE_MCIND(addr, val) \ 1096 + do { \ 1097 + RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1098 + RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1099 + RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1100 + } while (0) 1188 1101 1189 - #define RS690_WRITE_MCIND( addr, val ) \ 1102 + #define RS480_WRITE_MCIND(addr, val) \ 1103 + do { \ 1104 + RADEON_WRITE(RS480_NB_MC_INDEX, \ 1105 + ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1106 + RADEON_WRITE(RS480_NB_MC_DATA, (val)); \ 1107 + RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \ 1108 + } while (0) 1109 + 1110 + #define RS690_WRITE_MCIND(addr, val) \ 1190 1111 do { \ 1191 1112 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1192 1113 RADEON_WRITE(RS690_MC_DATA, val); \ 1193 1114 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1115 + } while (0) 1116 + 1117 + #define IGP_WRITE_MCIND(addr, val) \ 1118 + do { \ 1119 + if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \ 1120 + RS690_WRITE_MCIND(addr, val); \ 1121 + else \ 1122 + RS480_WRITE_MCIND(addr, val); \ 1194 1123 } while (0) 1195 1124 1196 1125 #define CP_PACKET0( reg, n ) \ ··· 1241 1154 } while (0) 1242 1155 1243 1156 #define RADEON_FLUSH_CACHE() do { \ 1244 - OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ 1245 - OUT_RING( RADEON_RB3D_DC_FLUSH ); \ 1157 + if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1158 + OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1159 + OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1160 + } else { \ 1161 + OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1162 + OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1163 + } \ 1246 1164 } while (0) 1247 1165 1248 1166 #define RADEON_PURGE_CACHE() do { \ 1249 - OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ 1250 - OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \ 1167 + if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1168 + OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1169 + OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ 1170 + } else { \ 1171 + OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1172 + OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ 1173 + } \ 1251 1174 } while (0) 1252 1175 1253 1176 #define RADEON_FLUSH_ZCACHE() do { \ 1254 - OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1255 - OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 1177 + if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1178 + OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1179 + OUT_RING(RADEON_RB3D_ZC_FLUSH); \ 1180 + } else { \ 1181 + OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1182 + OUT_RING(R300_ZC_FLUSH); \ 1183 + } \ 1256 1184 } while (0) 1257 1185 1258 1186 #define RADEON_PURGE_ZCACHE() do { \ 1259 - OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1260 - OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 1187 + if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1188 + OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1189 + OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \ 1190 + } else { \ 1191 + OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1192 + OUT_RING(R300_ZC_FLUSH_ALL); \ 1193 + } \ 1261 1194 } while (0) 1262 1195 1263 1196 /* ================================================================

+1 -1

drivers/char/drm/radeon_irq.c

··· 234 234 return radeon_wait_irq(dev, irqwait->irq_seq); 235 235 } 236 236 237 - static void radeon_enable_interrupt(struct drm_device *dev) 237 + void radeon_enable_interrupt(struct drm_device *dev) 238 238 { 239 239 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; 240 240

+1844

drivers/char/drm/radeon_microcode.h

··· 1 + /* 2 + * Copyright 2007 Advanced Micro Devices, Inc. 3 + * All Rights Reserved. 4 + * 5 + * Permission is hereby granted, free of charge, to any person obtaining a 6 + * copy of this software and associated documentation files (the "Software"), 7 + * to deal in the Software without restriction, including without limitation 8 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 + * and/or sell copies of the Software, and to permit persons to whom the 10 + * Software is furnished to do so, subject to the following conditions: 11 + * 12 + * The above copyright notice and this permission notice (including the next 13 + * paragraph) shall be included in all copies or substantial portions of the 14 + * Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 20 + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 21 + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 22 + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 + * 24 + */ 25 + 26 + #ifndef RADEON_MICROCODE_H 27 + #define RADEON_MICROCODE_H 28 + 29 + /* production radeon ucode r1xx-r6xx */ 30 + static const u32 R100_cp_microcode[][2] = { 31 + { 0x21007000, 0000000000 }, 32 + { 0x20007000, 0000000000 }, 33 + { 0x000000b4, 0x00000004 }, 34 + { 0x000000b8, 0x00000004 }, 35 + { 0x6f5b4d4c, 0000000000 }, 36 + { 0x4c4c427f, 0000000000 }, 37 + { 0x5b568a92, 0000000000 }, 38 + { 0x4ca09c6d, 0000000000 }, 39 + { 0xad4c4c4c, 0000000000 }, 40 + { 0x4ce1af3d, 0000000000 }, 41 + { 0xd8afafaf, 0000000000 }, 42 + { 0xd64c4cdc, 0000000000 }, 43 + { 0x4cd10d10, 0000000000 }, 44 + { 0x000f0000, 0x00000016 }, 45 + { 0x362f242d, 0000000000 }, 46 + { 0x00000012, 0x00000004 }, 47 + { 0x000f0000, 0x00000016 }, 48 + { 0x362f282d, 0000000000 }, 49 + { 0x000380e7, 0x00000002 }, 50 + { 0x04002c97, 0x00000002 }, 51 + { 0x000f0001, 0x00000016 }, 52 + { 0x333a3730, 0000000000 }, 53 + { 0x000077ef, 0x00000002 }, 54 + { 0x00061000, 0x00000002 }, 55 + { 0x00000021, 0x0000001a }, 56 + { 0x00004000, 0x0000001e }, 57 + { 0x00061000, 0x00000002 }, 58 + { 0x00000021, 0x0000001a }, 59 + { 0x00004000, 0x0000001e }, 60 + { 0x00061000, 0x00000002 }, 61 + { 0x00000021, 0x0000001a }, 62 + { 0x00004000, 0x0000001e }, 63 + { 0x00000017, 0x00000004 }, 64 + { 0x0003802b, 0x00000002 }, 65 + { 0x040067e0, 0x00000002 }, 66 + { 0x00000017, 0x00000004 }, 67 + { 0x000077e0, 0x00000002 }, 68 + { 0x00065000, 0x00000002 }, 69 + { 0x000037e1, 0x00000002 }, 70 + { 0x040067e1, 0x00000006 }, 71 + { 0x000077e0, 0x00000002 }, 72 + { 0x000077e1, 0x00000002 }, 73 + { 0x000077e1, 0x00000006 }, 74 + { 0xffffffff, 0000000000 }, 75 + { 0x10000000, 0000000000 }, 76 + { 0x0003802b, 0x00000002 }, 77 + { 0x040067e0, 0x00000006 }, 78 + { 0x00007675, 0x00000002 }, 79 + { 0x00007676, 0x00000002 }, 80 + { 0x00007677, 0x00000002 }, 81 + { 0x00007678, 0x00000006 }, 82 + { 0x0003802c, 0x00000002 }, 83 + { 0x04002676, 0x00000002 }, 84 + { 0x00007677, 0x00000002 }, 85 + { 0x00007678, 0x00000006 }, 86 + { 0x0000002f, 0x00000018 }, 87 + { 0x0000002f, 0x00000018 }, 88 + { 0000000000, 0x00000006 }, 89 + { 0x00000030, 0x00000018 }, 90 + { 0x00000030, 0x00000018 }, 91 + { 0000000000, 0x00000006 }, 92 + { 0x01605000, 0x00000002 }, 93 + { 0x00065000, 0x00000002 }, 94 + { 0x00098000, 0x00000002 }, 95 + { 0x00061000, 0x00000002 }, 96 + { 0x64c0603e, 0x00000004 }, 97 + { 0x000380e6, 0x00000002 }, 98 + { 0x040025c5, 0x00000002 }, 99 + { 0x00080000, 0x00000016 }, 100 + { 0000000000, 0000000000 }, 101 + { 0x0400251d, 0x00000002 }, 102 + { 0x00007580, 0x00000002 }, 103 + { 0x00067581, 0x00000002 }, 104 + { 0x04002580, 0x00000002 }, 105 + { 0x00067581, 0x00000002 }, 106 + { 0x00000049, 0x00000004 }, 107 + { 0x00005000, 0000000000 }, 108 + { 0x000380e6, 0x00000002 }, 109 + { 0x040025c5, 0x00000002 }, 110 + { 0x00061000, 0x00000002 }, 111 + { 0x0000750e, 0x00000002 }, 112 + { 0x00019000, 0x00000002 }, 113 + { 0x00011055, 0x00000014 }, 114 + { 0x00000055, 0x00000012 }, 115 + { 0x0400250f, 0x00000002 }, 116 + { 0x0000504f, 0x00000004 }, 117 + { 0x000380e6, 0x00000002 }, 118 + { 0x040025c5, 0x00000002 }, 119 + { 0x00007565, 0x00000002 }, 120 + { 0x00007566, 0x00000002 }, 121 + { 0x00000058, 0x00000004 }, 122 + { 0x000380e6, 0x00000002 }, 123 + { 0x040025c5, 0x00000002 }, 124 + { 0x01e655b4, 0x00000002 }, 125 + { 0x4401b0e4, 0x00000002 }, 126 + { 0x01c110e4, 0x00000002 }, 127 + { 0x26667066, 0x00000018 }, 128 + { 0x040c2565, 0x00000002 }, 129 + { 0x00000066, 0x00000018 }, 130 + { 0x04002564, 0x00000002 }, 131 + { 0x00007566, 0x00000002 }, 132 + { 0x0000005d, 0x00000004 }, 133 + { 0x00401069, 0x00000008 }, 134 + { 0x00101000, 0x00000002 }, 135 + { 0x000d80ff, 0x00000002 }, 136 + { 0x0080006c, 0x00000008 }, 137 + { 0x000f9000, 0x00000002 }, 138 + { 0x000e00ff, 0x00000002 }, 139 + { 0000000000, 0x00000006 }, 140 + { 0x0000008f, 0x00000018 }, 141 + { 0x0000005b, 0x00000004 }, 142 + { 0x000380e6, 0x00000002 }, 143 + { 0x040025c5, 0x00000002 }, 144 + { 0x00007576, 0x00000002 }, 145 + { 0x00065000, 0x00000002 }, 146 + { 0x00009000, 0x00000002 }, 147 + { 0x00041000, 0x00000002 }, 148 + { 0x0c00350e, 0x00000002 }, 149 + { 0x00049000, 0x00000002 }, 150 + { 0x00051000, 0x00000002 }, 151 + { 0x01e785f8, 0x00000002 }, 152 + { 0x00200000, 0x00000002 }, 153 + { 0x0060007e, 0x0000000c }, 154 + { 0x00007563, 0x00000002 }, 155 + { 0x006075f0, 0x00000021 }, 156 + { 0x20007073, 0x00000004 }, 157 + { 0x00005073, 0x00000004 }, 158 + { 0x000380e6, 0x00000002 }, 159 + { 0x040025c5, 0x00000002 }, 160 + { 0x00007576, 0x00000002 }, 161 + { 0x00007577, 0x00000002 }, 162 + { 0x0000750e, 0x00000002 }, 163 + { 0x0000750f, 0x00000002 }, 164 + { 0x00a05000, 0x00000002 }, 165 + { 0x00600083, 0x0000000c }, 166 + { 0x006075f0, 0x00000021 }, 167 + { 0x000075f8, 0x00000002 }, 168 + { 0x00000083, 0x00000004 }, 169 + { 0x000a750e, 0x00000002 }, 170 + { 0x000380e6, 0x00000002 }, 171 + { 0x040025c5, 0x00000002 }, 172 + { 0x0020750f, 0x00000002 }, 173 + { 0x00600086, 0x00000004 }, 174 + { 0x00007570, 0x00000002 }, 175 + { 0x00007571, 0x00000002 }, 176 + { 0x00007572, 0x00000006 }, 177 + { 0x000380e6, 0x00000002 }, 178 + { 0x040025c5, 0x00000002 }, 179 + { 0x00005000, 0x00000002 }, 180 + { 0x00a05000, 0x00000002 }, 181 + { 0x00007568, 0x00000002 }, 182 + { 0x00061000, 0x00000002 }, 183 + { 0x00000095, 0x0000000c }, 184 + { 0x00058000, 0x00000002 }, 185 + { 0x0c607562, 0x00000002 }, 186 + { 0x00000097, 0x00000004 }, 187 + { 0x000380e6, 0x00000002 }, 188 + { 0x040025c5, 0x00000002 }, 189 + { 0x00600096, 0x00000004 }, 190 + { 0x400070e5, 0000000000 }, 191 + { 0x000380e6, 0x00000002 }, 192 + { 0x040025c5, 0x00000002 }, 193 + { 0x000380e5, 0x00000002 }, 194 + { 0x000000a8, 0x0000001c }, 195 + { 0x000650aa, 0x00000018 }, 196 + { 0x040025bb, 0x00000002 }, 197 + { 0x000610ab, 0x00000018 }, 198 + { 0x040075bc, 0000000000 }, 199 + { 0x000075bb, 0x00000002 }, 200 + { 0x000075bc, 0000000000 }, 201 + { 0x00090000, 0x00000006 }, 202 + { 0x00090000, 0x00000002 }, 203 + { 0x000d8002, 0x00000006 }, 204 + { 0x00007832, 0x00000002 }, 205 + { 0x00005000, 0x00000002 }, 206 + { 0x000380e7, 0x00000002 }, 207 + { 0x04002c97, 0x00000002 }, 208 + { 0x00007820, 0x00000002 }, 209 + { 0x00007821, 0x00000002 }, 210 + { 0x00007800, 0000000000 }, 211 + { 0x01200000, 0x00000002 }, 212 + { 0x20077000, 0x00000002 }, 213 + { 0x01200000, 0x00000002 }, 214 + { 0x20007000, 0x00000002 }, 215 + { 0x00061000, 0x00000002 }, 216 + { 0x0120751b, 0x00000002 }, 217 + { 0x8040750a, 0x00000002 }, 218 + { 0x8040750b, 0x00000002 }, 219 + { 0x00110000, 0x00000002 }, 220 + { 0x000380e5, 0x00000002 }, 221 + { 0x000000c6, 0x0000001c }, 222 + { 0x000610ab, 0x00000018 }, 223 + { 0x844075bd, 0x00000002 }, 224 + { 0x000610aa, 0x00000018 }, 225 + { 0x840075bb, 0x00000002 }, 226 + { 0x000610ab, 0x00000018 }, 227 + { 0x844075bc, 0x00000002 }, 228 + { 0x000000c9, 0x00000004 }, 229 + { 0x804075bd, 0x00000002 }, 230 + { 0x800075bb, 0x00000002 }, 231 + { 0x804075bc, 0x00000002 }, 232 + { 0x00108000, 0x00000002 }, 233 + { 0x01400000, 0x00000002 }, 234 + { 0x006000cd, 0x0000000c }, 235 + { 0x20c07000, 0x00000020 }, 236 + { 0x000000cf, 0x00000012 }, 237 + { 0x00800000, 0x00000006 }, 238 + { 0x0080751d, 0x00000006 }, 239 + { 0000000000, 0000000000 }, 240 + { 0x0000775c, 0x00000002 }, 241 + { 0x00a05000, 0x00000002 }, 242 + { 0x00661000, 0x00000002 }, 243 + { 0x0460275d, 0x00000020 }, 244 + { 0x00004000, 0000000000 }, 245 + { 0x01e00830, 0x00000002 }, 246 + { 0x21007000, 0000000000 }, 247 + { 0x6464614d, 0000000000 }, 248 + { 0x69687420, 0000000000 }, 249 + { 0x00000073, 0000000000 }, 250 + { 0000000000, 0000000000 }, 251 + { 0x00005000, 0x00000002 }, 252 + { 0x000380d0, 0x00000002 }, 253 + { 0x040025e0, 0x00000002 }, 254 + { 0x000075e1, 0000000000 }, 255 + { 0x00000001, 0000000000 }, 256 + { 0x000380e0, 0x00000002 }, 257 + { 0x04002394, 0x00000002 }, 258 + { 0x00005000, 0000000000 }, 259 + { 0000000000, 0000000000 }, 260 + { 0000000000, 0000000000 }, 261 + { 0x00000008, 0000000000 }, 262 + { 0x00000004, 0000000000 }, 263 + { 0000000000, 0000000000 }, 264 + { 0000000000, 0000000000 }, 265 + { 0000000000, 0000000000 }, 266 + { 0000000000, 0000000000 }, 267 + { 0000000000, 0000000000 }, 268 + { 0000000000, 0000000000 }, 269 + { 0000000000, 0000000000 }, 270 + { 0000000000, 0000000000 }, 271 + { 0000000000, 0000000000 }, 272 + { 0000000000, 0000000000 }, 273 + { 0000000000, 0000000000 }, 274 + { 0000000000, 0000000000 }, 275 + { 0000000000, 0000000000 }, 276 + { 0000000000, 0000000000 }, 277 + { 0000000000, 0000000000 }, 278 + { 0000000000, 0000000000 }, 279 + { 0000000000, 0000000000 }, 280 + { 0000000000, 0000000000 }, 281 + { 0000000000, 0000000000 }, 282 + { 0000000000, 0000000000 }, 283 + { 0000000000, 0000000000 }, 284 + { 0000000000, 0000000000 }, 285 + { 0000000000, 0000000000 }, 286 + { 0000000000, 0000000000 }, 287 + }; 288 + 289 + static const u32 R200_cp_microcode[][2] = { 290 + { 0x21007000, 0000000000 }, 291 + { 0x20007000, 0000000000 }, 292 + { 0x000000bf, 0x00000004 }, 293 + { 0x000000c3, 0x00000004 }, 294 + { 0x7a685e5d, 0000000000 }, 295 + { 0x5d5d5588, 0000000000 }, 296 + { 0x68659197, 0000000000 }, 297 + { 0x5da19f78, 0000000000 }, 298 + { 0x5d5d5d5d, 0000000000 }, 299 + { 0x5dee5d50, 0000000000 }, 300 + { 0xf2acacac, 0000000000 }, 301 + { 0xe75df9e9, 0000000000 }, 302 + { 0xb1dd0e11, 0000000000 }, 303 + { 0xe2afafaf, 0000000000 }, 304 + { 0x000f0000, 0x00000016 }, 305 + { 0x452f232d, 0000000000 }, 306 + { 0x00000013, 0x00000004 }, 307 + { 0x000f0000, 0x00000016 }, 308 + { 0x452f272d, 0000000000 }, 309 + { 0x000f0001, 0x00000016 }, 310 + { 0x3e4d4a37, 0000000000 }, 311 + { 0x000077ef, 0x00000002 }, 312 + { 0x00061000, 0x00000002 }, 313 + { 0x00000020, 0x0000001a }, 314 + { 0x00004000, 0x0000001e }, 315 + { 0x00061000, 0x00000002 }, 316 + { 0x00000020, 0x0000001a }, 317 + { 0x00004000, 0x0000001e }, 318 + { 0x00061000, 0x00000002 }, 319 + { 0x00000020, 0x0000001a }, 320 + { 0x00004000, 0x0000001e }, 321 + { 0x00000016, 0x00000004 }, 322 + { 0x0003802a, 0x00000002 }, 323 + { 0x040067e0, 0x00000002 }, 324 + { 0x00000016, 0x00000004 }, 325 + { 0x000077e0, 0x00000002 }, 326 + { 0x00065000, 0x00000002 }, 327 + { 0x000037e1, 0x00000002 }, 328 + { 0x040067e1, 0x00000006 }, 329 + { 0x000077e0, 0x00000002 }, 330 + { 0x000077e1, 0x00000002 }, 331 + { 0x000077e1, 0x00000006 }, 332 + { 0xffffffff, 0000000000 }, 333 + { 0x10000000, 0000000000 }, 334 + { 0x07f007f0, 0000000000 }, 335 + { 0x0003802a, 0x00000002 }, 336 + { 0x040067e0, 0x00000006 }, 337 + { 0x0003802c, 0x00000002 }, 338 + { 0x04002741, 0x00000002 }, 339 + { 0x04002741, 0x00000002 }, 340 + { 0x04002743, 0x00000002 }, 341 + { 0x00007675, 0x00000002 }, 342 + { 0x00007676, 0x00000002 }, 343 + { 0x00007677, 0x00000002 }, 344 + { 0x00007678, 0x00000006 }, 345 + { 0x0003802c, 0x00000002 }, 346 + { 0x04002741, 0x00000002 }, 347 + { 0x04002741, 0x00000002 }, 348 + { 0x04002743, 0x00000002 }, 349 + { 0x00007676, 0x00000002 }, 350 + { 0x00007677, 0x00000002 }, 351 + { 0x00007678, 0x00000006 }, 352 + { 0x0003802b, 0x00000002 }, 353 + { 0x04002676, 0x00000002 }, 354 + { 0x00007677, 0x00000002 }, 355 + { 0x0003802c, 0x00000002 }, 356 + { 0x04002741, 0x00000002 }, 357 + { 0x04002743, 0x00000002 }, 358 + { 0x00007678, 0x00000006 }, 359 + { 0x0003802c, 0x00000002 }, 360 + { 0x04002741, 0x00000002 }, 361 + { 0x04002741, 0x00000002 }, 362 + { 0x04002743, 0x00000002 }, 363 + { 0x00007678, 0x00000006 }, 364 + { 0x0000002f, 0x00000018 }, 365 + { 0x0000002f, 0x00000018 }, 366 + { 0000000000, 0x00000006 }, 367 + { 0x00000037, 0x00000018 }, 368 + { 0x00000037, 0x00000018 }, 369 + { 0000000000, 0x00000006 }, 370 + { 0x01605000, 0x00000002 }, 371 + { 0x00065000, 0x00000002 }, 372 + { 0x00098000, 0x00000002 }, 373 + { 0x00061000, 0x00000002 }, 374 + { 0x64c06051, 0x00000004 }, 375 + { 0x00080000, 0x00000016 }, 376 + { 0000000000, 0000000000 }, 377 + { 0x0400251d, 0x00000002 }, 378 + { 0x00007580, 0x00000002 }, 379 + { 0x00067581, 0x00000002 }, 380 + { 0x04002580, 0x00000002 }, 381 + { 0x00067581, 0x00000002 }, 382 + { 0x0000005a, 0x00000004 }, 383 + { 0x00005000, 0000000000 }, 384 + { 0x00061000, 0x00000002 }, 385 + { 0x0000750e, 0x00000002 }, 386 + { 0x00019000, 0x00000002 }, 387 + { 0x00011064, 0x00000014 }, 388 + { 0x00000064, 0x00000012 }, 389 + { 0x0400250f, 0x00000002 }, 390 + { 0x0000505e, 0x00000004 }, 391 + { 0x00007565, 0x00000002 }, 392 + { 0x00007566, 0x00000002 }, 393 + { 0x00000065, 0x00000004 }, 394 + { 0x01e655b4, 0x00000002 }, 395 + { 0x4401b0f0, 0x00000002 }, 396 + { 0x01c110f0, 0x00000002 }, 397 + { 0x26667071, 0x00000018 }, 398 + { 0x040c2565, 0x00000002 }, 399 + { 0x00000071, 0x00000018 }, 400 + { 0x04002564, 0x00000002 }, 401 + { 0x00007566, 0x00000002 }, 402 + { 0x00000068, 0x00000004 }, 403 + { 0x00401074, 0x00000008 }, 404 + { 0x00101000, 0x00000002 }, 405 + { 0x000d80ff, 0x00000002 }, 406 + { 0x00800077, 0x00000008 }, 407 + { 0x000f9000, 0x00000002 }, 408 + { 0x000e00ff, 0x00000002 }, 409 + { 0000000000, 0x00000006 }, 410 + { 0x00000094, 0x00000018 }, 411 + { 0x00000068, 0x00000004 }, 412 + { 0x00007576, 0x00000002 }, 413 + { 0x00065000, 0x00000002 }, 414 + { 0x00009000, 0x00000002 }, 415 + { 0x00041000, 0x00000002 }, 416 + { 0x0c00350e, 0x00000002 }, 417 + { 0x00049000, 0x00000002 }, 418 + { 0x00051000, 0x00000002 }, 419 + { 0x01e785f8, 0x00000002 }, 420 + { 0x00200000, 0x00000002 }, 421 + { 0x00600087, 0x0000000c }, 422 + { 0x00007563, 0x00000002 }, 423 + { 0x006075f0, 0x00000021 }, 424 + { 0x2000707c, 0x00000004 }, 425 + { 0x0000507c, 0x00000004 }, 426 + { 0x00007576, 0x00000002 }, 427 + { 0x00007577, 0x00000002 }, 428 + { 0x0000750e, 0x00000002 }, 429 + { 0x0000750f, 0x00000002 }, 430 + { 0x00a05000, 0x00000002 }, 431 + { 0x0060008a, 0x0000000c }, 432 + { 0x006075f0, 0x00000021 }, 433 + { 0x000075f8, 0x00000002 }, 434 + { 0x0000008a, 0x00000004 }, 435 + { 0x000a750e, 0x00000002 }, 436 + { 0x0020750f, 0x00000002 }, 437 + { 0x0060008d, 0x00000004 }, 438 + { 0x00007570, 0x00000002 }, 439 + { 0x00007571, 0x00000002 }, 440 + { 0x00007572, 0x00000006 }, 441 + { 0x00005000, 0x00000002 }, 442 + { 0x00a05000, 0x00000002 }, 443 + { 0x00007568, 0x00000002 }, 444 + { 0x00061000, 0x00000002 }, 445 + { 0x00000098, 0x0000000c }, 446 + { 0x00058000, 0x00000002 }, 447 + { 0x0c607562, 0x00000002 }, 448 + { 0x0000009a, 0x00000004 }, 449 + { 0x00600099, 0x00000004 }, 450 + { 0x400070f1, 0000000000 }, 451 + { 0x000380f1, 0x00000002 }, 452 + { 0x000000a7, 0x0000001c }, 453 + { 0x000650a9, 0x00000018 }, 454 + { 0x040025bb, 0x00000002 }, 455 + { 0x000610aa, 0x00000018 }, 456 + { 0x040075bc, 0000000000 }, 457 + { 0x000075bb, 0x00000002 }, 458 + { 0x000075bc, 0000000000 }, 459 + { 0x00090000, 0x00000006 }, 460 + { 0x00090000, 0x00000002 }, 461 + { 0x000d8002, 0x00000006 }, 462 + { 0x00005000, 0x00000002 }, 463 + { 0x00007821, 0x00000002 }, 464 + { 0x00007800, 0000000000 }, 465 + { 0x00007821, 0x00000002 }, 466 + { 0x00007800, 0000000000 }, 467 + { 0x01665000, 0x00000002 }, 468 + { 0x000a0000, 0x00000002 }, 469 + { 0x000671cc, 0x00000002 }, 470 + { 0x0286f1cd, 0x00000002 }, 471 + { 0x000000b7, 0x00000010 }, 472 + { 0x21007000, 0000000000 }, 473 + { 0x000000be, 0x0000001c }, 474 + { 0x00065000, 0x00000002 }, 475 + { 0x000a0000, 0x00000002 }, 476 + { 0x00061000, 0x00000002 }, 477 + { 0x000b0000, 0x00000002 }, 478 + { 0x38067000, 0x00000002 }, 479 + { 0x000a00ba, 0x00000004 }, 480 + { 0x20007000, 0000000000 }, 481 + { 0x01200000, 0x00000002 }, 482 + { 0x20077000, 0x00000002 }, 483 + { 0x01200000, 0x00000002 }, 484 + { 0x20007000, 0000000000 }, 485 + { 0x00061000, 0x00000002 }, 486 + { 0x0120751b, 0x00000002 }, 487 + { 0x8040750a, 0x00000002 }, 488 + { 0x8040750b, 0x00000002 }, 489 + { 0x00110000, 0x00000002 }, 490 + { 0x000380f1, 0x00000002 }, 491 + { 0x000000d1, 0x0000001c }, 492 + { 0x000610aa, 0x00000018 }, 493 + { 0x844075bd, 0x00000002 }, 494 + { 0x000610a9, 0x00000018 }, 495 + { 0x840075bb, 0x00000002 }, 496 + { 0x000610aa, 0x00000018 }, 497 + { 0x844075bc, 0x00000002 }, 498 + { 0x000000d4, 0x00000004 }, 499 + { 0x804075bd, 0x00000002 }, 500 + { 0x800075bb, 0x00000002 }, 501 + { 0x804075bc, 0x00000002 }, 502 + { 0x00108000, 0x00000002 }, 503 + { 0x01400000, 0x00000002 }, 504 + { 0x006000d8, 0x0000000c }, 505 + { 0x20c07000, 0x00000020 }, 506 + { 0x000000da, 0x00000012 }, 507 + { 0x00800000, 0x00000006 }, 508 + { 0x0080751d, 0x00000006 }, 509 + { 0x000025bb, 0x00000002 }, 510 + { 0x000040d4, 0x00000004 }, 511 + { 0x0000775c, 0x00000002 }, 512 + { 0x00a05000, 0x00000002 }, 513 + { 0x00661000, 0x00000002 }, 514 + { 0x0460275d, 0x00000020 }, 515 + { 0x00004000, 0000000000 }, 516 + { 0x00007999, 0x00000002 }, 517 + { 0x00a05000, 0x00000002 }, 518 + { 0x00661000, 0x00000002 }, 519 + { 0x0460299b, 0x00000020 }, 520 + { 0x00004000, 0000000000 }, 521 + { 0x01e00830, 0x00000002 }, 522 + { 0x21007000, 0000000000 }, 523 + { 0x00005000, 0x00000002 }, 524 + { 0x00038056, 0x00000002 }, 525 + { 0x040025e0, 0x00000002 }, 526 + { 0x000075e1, 0000000000 }, 527 + { 0x00000001, 0000000000 }, 528 + { 0x000380ed, 0x00000002 }, 529 + { 0x04007394, 0000000000 }, 530 + { 0000000000, 0000000000 }, 531 + { 0000000000, 0000000000 }, 532 + { 0x000078c4, 0x00000002 }, 533 + { 0x000078c5, 0x00000002 }, 534 + { 0x000078c6, 0x00000002 }, 535 + { 0x00007924, 0x00000002 }, 536 + { 0x00007925, 0x00000002 }, 537 + { 0x00007926, 0x00000002 }, 538 + { 0x000000f2, 0x00000004 }, 539 + { 0x00007924, 0x00000002 }, 540 + { 0x00007925, 0x00000002 }, 541 + { 0x00007926, 0x00000002 }, 542 + { 0x000000f9, 0x00000004 }, 543 + { 0000000000, 0000000000 }, 544 + { 0000000000, 0000000000 }, 545 + { 0000000000, 0000000000 }, 546 + }; 547 + 548 + static const u32 R300_cp_microcode[][2] = { 549 + { 0x4200e000, 0000000000 }, 550 + { 0x4000e000, 0000000000 }, 551 + { 0x000000ae, 0x00000008 }, 552 + { 0x000000b2, 0x00000008 }, 553 + { 0x67554b4a, 0000000000 }, 554 + { 0x4a4a4475, 0000000000 }, 555 + { 0x55527d83, 0000000000 }, 556 + { 0x4a8c8b65, 0000000000 }, 557 + { 0x4aef4af6, 0000000000 }, 558 + { 0x4ae14a4a, 0000000000 }, 559 + { 0xe4979797, 0000000000 }, 560 + { 0xdb4aebdd, 0000000000 }, 561 + { 0x9ccc4a4a, 0000000000 }, 562 + { 0xd1989898, 0000000000 }, 563 + { 0x4a0f9ad6, 0000000000 }, 564 + { 0x000ca000, 0x00000004 }, 565 + { 0x000d0012, 0x00000038 }, 566 + { 0x0000e8b4, 0x00000004 }, 567 + { 0x000d0014, 0x00000038 }, 568 + { 0x0000e8b6, 0x00000004 }, 569 + { 0x000d0016, 0x00000038 }, 570 + { 0x0000e854, 0x00000004 }, 571 + { 0x000d0018, 0x00000038 }, 572 + { 0x0000e855, 0x00000004 }, 573 + { 0x000d001a, 0x00000038 }, 574 + { 0x0000e856, 0x00000004 }, 575 + { 0x000d001c, 0x00000038 }, 576 + { 0x0000e857, 0x00000004 }, 577 + { 0x000d001e, 0x00000038 }, 578 + { 0x0000e824, 0x00000004 }, 579 + { 0x000d0020, 0x00000038 }, 580 + { 0x0000e825, 0x00000004 }, 581 + { 0x000d0022, 0x00000038 }, 582 + { 0x0000e830, 0x00000004 }, 583 + { 0x000d0024, 0x00000038 }, 584 + { 0x0000f0c0, 0x00000004 }, 585 + { 0x000d0026, 0x00000038 }, 586 + { 0x0000f0c1, 0x00000004 }, 587 + { 0x000d0028, 0x00000038 }, 588 + { 0x0000f041, 0x00000004 }, 589 + { 0x000d002a, 0x00000038 }, 590 + { 0x0000f184, 0x00000004 }, 591 + { 0x000d002c, 0x00000038 }, 592 + { 0x0000f185, 0x00000004 }, 593 + { 0x000d002e, 0x00000038 }, 594 + { 0x0000f186, 0x00000004 }, 595 + { 0x000d0030, 0x00000038 }, 596 + { 0x0000f187, 0x00000004 }, 597 + { 0x000d0032, 0x00000038 }, 598 + { 0x0000f180, 0x00000004 }, 599 + { 0x000d0034, 0x00000038 }, 600 + { 0x0000f393, 0x00000004 }, 601 + { 0x000d0036, 0x00000038 }, 602 + { 0x0000f38a, 0x00000004 }, 603 + { 0x000d0038, 0x00000038 }, 604 + { 0x0000f38e, 0x00000004 }, 605 + { 0x0000e821, 0x00000004 }, 606 + { 0x0140a000, 0x00000004 }, 607 + { 0x00000043, 0x00000018 }, 608 + { 0x00cce800, 0x00000004 }, 609 + { 0x001b0001, 0x00000004 }, 610 + { 0x08004800, 0x00000004 }, 611 + { 0x001b0001, 0x00000004 }, 612 + { 0x08004800, 0x00000004 }, 613 + { 0x001b0001, 0x00000004 }, 614 + { 0x08004800, 0x00000004 }, 615 + { 0x0000003a, 0x00000008 }, 616 + { 0x0000a000, 0000000000 }, 617 + { 0x2000451d, 0x00000004 }, 618 + { 0x0000e580, 0x00000004 }, 619 + { 0x000ce581, 0x00000004 }, 620 + { 0x08004580, 0x00000004 }, 621 + { 0x000ce581, 0x00000004 }, 622 + { 0x00000047, 0x00000008 }, 623 + { 0x0000a000, 0000000000 }, 624 + { 0x000c2000, 0x00000004 }, 625 + { 0x0000e50e, 0x00000004 }, 626 + { 0x00032000, 0x00000004 }, 627 + { 0x00022051, 0x00000028 }, 628 + { 0x00000051, 0x00000024 }, 629 + { 0x0800450f, 0x00000004 }, 630 + { 0x0000a04b, 0x00000008 }, 631 + { 0x0000e565, 0x00000004 }, 632 + { 0x0000e566, 0x00000004 }, 633 + { 0x00000052, 0x00000008 }, 634 + { 0x03cca5b4, 0x00000004 }, 635 + { 0x05432000, 0x00000004 }, 636 + { 0x00022000, 0x00000004 }, 637 + { 0x4ccce05e, 0x00000030 }, 638 + { 0x08274565, 0x00000004 }, 639 + { 0x0000005e, 0x00000030 }, 640 + { 0x08004564, 0x00000004 }, 641 + { 0x0000e566, 0x00000004 }, 642 + { 0x00000055, 0x00000008 }, 643 + { 0x00802061, 0x00000010 }, 644 + { 0x00202000, 0x00000004 }, 645 + { 0x001b00ff, 0x00000004 }, 646 + { 0x01000064, 0x00000010 }, 647 + { 0x001f2000, 0x00000004 }, 648 + { 0x001c00ff, 0x00000004 }, 649 + { 0000000000, 0x0000000c }, 650 + { 0x00000080, 0x00000030 }, 651 + { 0x00000055, 0x00000008 }, 652 + { 0x0000e576, 0x00000004 }, 653 + { 0x000ca000, 0x00000004 }, 654 + { 0x00012000, 0x00000004 }, 655 + { 0x00082000, 0x00000004 }, 656 + { 0x1800650e, 0x00000004 }, 657 + { 0x00092000, 0x00000004 }, 658 + { 0x000a2000, 0x00000004 }, 659 + { 0x000f0000, 0x00000004 }, 660 + { 0x00400000, 0x00000004 }, 661 + { 0x00000074, 0x00000018 }, 662 + { 0x0000e563, 0x00000004 }, 663 + { 0x00c0e5f9, 0x000000c2 }, 664 + { 0x00000069, 0x00000008 }, 665 + { 0x0000a069, 0x00000008 }, 666 + { 0x0000e576, 0x00000004 }, 667 + { 0x0000e577, 0x00000004 }, 668 + { 0x0000e50e, 0x00000004 }, 669 + { 0x0000e50f, 0x00000004 }, 670 + { 0x0140a000, 0x00000004 }, 671 + { 0x00000077, 0x00000018 }, 672 + { 0x00c0e5f9, 0x000000c2 }, 673 + { 0x00000077, 0x00000008 }, 674 + { 0x0014e50e, 0x00000004 }, 675 + { 0x0040e50f, 0x00000004 }, 676 + { 0x00c0007a, 0x00000008 }, 677 + { 0x0000e570, 0x00000004 }, 678 + { 0x0000e571, 0x00000004 }, 679 + { 0x0000e572, 0x0000000c }, 680 + { 0x0000a000, 0x00000004 }, 681 + { 0x0140a000, 0x00000004 }, 682 + { 0x0000e568, 0x00000004 }, 683 + { 0x000c2000, 0x00000004 }, 684 + { 0x00000084, 0x00000018 }, 685 + { 0x000b0000, 0x00000004 }, 686 + { 0x18c0e562, 0x00000004 }, 687 + { 0x00000086, 0x00000008 }, 688 + { 0x00c00085, 0x00000008 }, 689 + { 0x000700e3, 0x00000004 }, 690 + { 0x00000092, 0x00000038 }, 691 + { 0x000ca094, 0x00000030 }, 692 + { 0x080045bb, 0x00000004 }, 693 + { 0x000c2095, 0x00000030 }, 694 + { 0x0800e5bc, 0000000000 }, 695 + { 0x0000e5bb, 0x00000004 }, 696 + { 0x0000e5bc, 0000000000 }, 697 + { 0x00120000, 0x0000000c }, 698 + { 0x00120000, 0x00000004 }, 699 + { 0x001b0002, 0x0000000c }, 700 + { 0x0000a000, 0x00000004 }, 701 + { 0x0000e821, 0x00000004 }, 702 + { 0x0000e800, 0000000000 }, 703 + { 0x0000e821, 0x00000004 }, 704 + { 0x0000e82e, 0000000000 }, 705 + { 0x02cca000, 0x00000004 }, 706 + { 0x00140000, 0x00000004 }, 707 + { 0x000ce1cc, 0x00000004 }, 708 + { 0x050de1cd, 0x00000004 }, 709 + { 0x00400000, 0x00000004 }, 710 + { 0x000000a4, 0x00000018 }, 711 + { 0x00c0a000, 0x00000004 }, 712 + { 0x000000a1, 0x00000008 }, 713 + { 0x000000a6, 0x00000020 }, 714 + { 0x4200e000, 0000000000 }, 715 + { 0x000000ad, 0x00000038 }, 716 + { 0x000ca000, 0x00000004 }, 717 + { 0x00140000, 0x00000004 }, 718 + { 0x000c2000, 0x00000004 }, 719 + { 0x00160000, 0x00000004 }, 720 + { 0x700ce000, 0x00000004 }, 721 + { 0x001400a9, 0x00000008 }, 722 + { 0x4000e000, 0000000000 }, 723 + { 0x02400000, 0x00000004 }, 724 + { 0x400ee000, 0x00000004 }, 725 + { 0x02400000, 0x00000004 }, 726 + { 0x4000e000, 0000000000 }, 727 + { 0x000c2000, 0x00000004 }, 728 + { 0x0240e51b, 0x00000004 }, 729 + { 0x0080e50a, 0x00000005 }, 730 + { 0x0080e50b, 0x00000005 }, 731 + { 0x00220000, 0x00000004 }, 732 + { 0x000700e3, 0x00000004 }, 733 + { 0x000000c0, 0x00000038 }, 734 + { 0x000c2095, 0x00000030 }, 735 + { 0x0880e5bd, 0x00000005 }, 736 + { 0x000c2094, 0x00000030 }, 737 + { 0x0800e5bb, 0x00000005 }, 738 + { 0x000c2095, 0x00000030 }, 739 + { 0x0880e5bc, 0x00000005 }, 740 + { 0x000000c3, 0x00000008 }, 741 + { 0x0080e5bd, 0x00000005 }, 742 + { 0x0000e5bb, 0x00000005 }, 743 + { 0x0080e5bc, 0x00000005 }, 744 + { 0x00210000, 0x00000004 }, 745 + { 0x02800000, 0x00000004 }, 746 + { 0x00c000c7, 0x00000018 }, 747 + { 0x4180e000, 0x00000040 }, 748 + { 0x000000c9, 0x00000024 }, 749 + { 0x01000000, 0x0000000c }, 750 + { 0x0100e51d, 0x0000000c }, 751 + { 0x000045bb, 0x00000004 }, 752 + { 0x000080c3, 0x00000008 }, 753 + { 0x0000f3ce, 0x00000004 }, 754 + { 0x0140a000, 0x00000004 }, 755 + { 0x00cc2000, 0x00000004 }, 756 + { 0x08c053cf, 0x00000040 }, 757 + { 0x00008000, 0000000000 }, 758 + { 0x0000f3d2, 0x00000004 }, 759 + { 0x0140a000, 0x00000004 }, 760 + { 0x00cc2000, 0x00000004 }, 761 + { 0x08c053d3, 0x00000040 }, 762 + { 0x00008000, 0000000000 }, 763 + { 0x0000f39d, 0x00000004 }, 764 + { 0x0140a000, 0x00000004 }, 765 + { 0x00cc2000, 0x00000004 }, 766 + { 0x08c0539e, 0x00000040 }, 767 + { 0x00008000, 0000000000 }, 768 + { 0x03c00830, 0x00000004 }, 769 + { 0x4200e000, 0000000000 }, 770 + { 0x0000a000, 0x00000004 }, 771 + { 0x200045e0, 0x00000004 }, 772 + { 0x0000e5e1, 0000000000 }, 773 + { 0x00000001, 0000000000 }, 774 + { 0x000700e0, 0x00000004 }, 775 + { 0x0800e394, 0000000000 }, 776 + { 0000000000, 0000000000 }, 777 + { 0x0000e8c4, 0x00000004 }, 778 + { 0x0000e8c5, 0x00000004 }, 779 + { 0x0000e8c6, 0x00000004 }, 780 + { 0x0000e928, 0x00000004 }, 781 + { 0x0000e929, 0x00000004 }, 782 + { 0x0000e92a, 0x00000004 }, 783 + { 0x000000e4, 0x00000008 }, 784 + { 0x0000e928, 0x00000004 }, 785 + { 0x0000e929, 0x00000004 }, 786 + { 0x0000e92a, 0x00000004 }, 787 + { 0x000000eb, 0x00000008 }, 788 + { 0x02c02000, 0x00000004 }, 789 + { 0x00060000, 0x00000004 }, 790 + { 0x000000f3, 0x00000034 }, 791 + { 0x000000f0, 0x00000008 }, 792 + { 0x00008000, 0x00000004 }, 793 + { 0xc000e000, 0000000000 }, 794 + { 0000000000, 0000000000 }, 795 + { 0x000c2000, 0x00000004 }, 796 + { 0x001d0018, 0x00000004 }, 797 + { 0x001a0001, 0x00000004 }, 798 + { 0x000000fb, 0x00000034 }, 799 + { 0x0000004a, 0x00000008 }, 800 + { 0x0500a04a, 0x00000008 }, 801 + { 0000000000, 0000000000 }, 802 + { 0000000000, 0000000000 }, 803 + { 0000000000, 0000000000 }, 804 + { 0000000000, 0000000000 }, 805 + }; 806 + 807 + static const u32 R420_cp_microcode[][2] = { 808 + { 0x4200e000, 0000000000 }, 809 + { 0x4000e000, 0000000000 }, 810 + { 0x00000099, 0x00000008 }, 811 + { 0x0000009d, 0x00000008 }, 812 + { 0x4a554b4a, 0000000000 }, 813 + { 0x4a4a4467, 0000000000 }, 814 + { 0x55526f75, 0000000000 }, 815 + { 0x4a7e7d65, 0000000000 }, 816 + { 0xd9d3dff6, 0000000000 }, 817 + { 0x4ac54a4a, 0000000000 }, 818 + { 0xc8828282, 0000000000 }, 819 + { 0xbf4acfc1, 0000000000 }, 820 + { 0x87b04a4a, 0000000000 }, 821 + { 0xb5838383, 0000000000 }, 822 + { 0x4a0f85ba, 0000000000 }, 823 + { 0x000ca000, 0x00000004 }, 824 + { 0x000d0012, 0x00000038 }, 825 + { 0x0000e8b4, 0x00000004 }, 826 + { 0x000d0014, 0x00000038 }, 827 + { 0x0000e8b6, 0x00000004 }, 828 + { 0x000d0016, 0x00000038 }, 829 + { 0x0000e854, 0x00000004 }, 830 + { 0x000d0018, 0x00000038 }, 831 + { 0x0000e855, 0x00000004 }, 832 + { 0x000d001a, 0x00000038 }, 833 + { 0x0000e856, 0x00000004 }, 834 + { 0x000d001c, 0x00000038 }, 835 + { 0x0000e857, 0x00000004 }, 836 + { 0x000d001e, 0x00000038 }, 837 + { 0x0000e824, 0x00000004 }, 838 + { 0x000d0020, 0x00000038 }, 839 + { 0x0000e825, 0x00000004 }, 840 + { 0x000d0022, 0x00000038 }, 841 + { 0x0000e830, 0x00000004 }, 842 + { 0x000d0024, 0x00000038 }, 843 + { 0x0000f0c0, 0x00000004 }, 844 + { 0x000d0026, 0x00000038 }, 845 + { 0x0000f0c1, 0x00000004 }, 846 + { 0x000d0028, 0x00000038 }, 847 + { 0x0000f041, 0x00000004 }, 848 + { 0x000d002a, 0x00000038 }, 849 + { 0x0000f184, 0x00000004 }, 850 + { 0x000d002c, 0x00000038 }, 851 + { 0x0000f185, 0x00000004 }, 852 + { 0x000d002e, 0x00000038 }, 853 + { 0x0000f186, 0x00000004 }, 854 + { 0x000d0030, 0x00000038 }, 855 + { 0x0000f187, 0x00000004 }, 856 + { 0x000d0032, 0x00000038 }, 857 + { 0x0000f180, 0x00000004 }, 858 + { 0x000d0034, 0x00000038 }, 859 + { 0x0000f393, 0x00000004 }, 860 + { 0x000d0036, 0x00000038 }, 861 + { 0x0000f38a, 0x00000004 }, 862 + { 0x000d0038, 0x00000038 }, 863 + { 0x0000f38e, 0x00000004 }, 864 + { 0x0000e821, 0x00000004 }, 865 + { 0x0140a000, 0x00000004 }, 866 + { 0x00000043, 0x00000018 }, 867 + { 0x00cce800, 0x00000004 }, 868 + { 0x001b0001, 0x00000004 }, 869 + { 0x08004800, 0x00000004 }, 870 + { 0x001b0001, 0x00000004 }, 871 + { 0x08004800, 0x00000004 }, 872 + { 0x001b0001, 0x00000004 }, 873 + { 0x08004800, 0x00000004 }, 874 + { 0x0000003a, 0x00000008 }, 875 + { 0x0000a000, 0000000000 }, 876 + { 0x2000451d, 0x00000004 }, 877 + { 0x0000e580, 0x00000004 }, 878 + { 0x000ce581, 0x00000004 }, 879 + { 0x08004580, 0x00000004 }, 880 + { 0x000ce581, 0x00000004 }, 881 + { 0x00000047, 0x00000008 }, 882 + { 0x0000a000, 0000000000 }, 883 + { 0x000c2000, 0x00000004 }, 884 + { 0x0000e50e, 0x00000004 }, 885 + { 0x00032000, 0x00000004 }, 886 + { 0x00022051, 0x00000028 }, 887 + { 0x00000051, 0x00000024 }, 888 + { 0x0800450f, 0x00000004 }, 889 + { 0x0000a04b, 0x00000008 }, 890 + { 0x0000e565, 0x00000004 }, 891 + { 0x0000e566, 0x00000004 }, 892 + { 0x00000052, 0x00000008 }, 893 + { 0x03cca5b4, 0x00000004 }, 894 + { 0x05432000, 0x00000004 }, 895 + { 0x00022000, 0x00000004 }, 896 + { 0x4ccce05e, 0x00000030 }, 897 + { 0x08274565, 0x00000004 }, 898 + { 0x0000005e, 0x00000030 }, 899 + { 0x08004564, 0x00000004 }, 900 + { 0x0000e566, 0x00000004 }, 901 + { 0x00000055, 0x00000008 }, 902 + { 0x00802061, 0x00000010 }, 903 + { 0x00202000, 0x00000004 }, 904 + { 0x001b00ff, 0x00000004 }, 905 + { 0x01000064, 0x00000010 }, 906 + { 0x001f2000, 0x00000004 }, 907 + { 0x001c00ff, 0x00000004 }, 908 + { 0000000000, 0x0000000c }, 909 + { 0x00000072, 0x00000030 }, 910 + { 0x00000055, 0x00000008 }, 911 + { 0x0000e576, 0x00000004 }, 912 + { 0x0000e577, 0x00000004 }, 913 + { 0x0000e50e, 0x00000004 }, 914 + { 0x0000e50f, 0x00000004 }, 915 + { 0x0140a000, 0x00000004 }, 916 + { 0x00000069, 0x00000018 }, 917 + { 0x00c0e5f9, 0x000000c2 }, 918 + { 0x00000069, 0x00000008 }, 919 + { 0x0014e50e, 0x00000004 }, 920 + { 0x0040e50f, 0x00000004 }, 921 + { 0x00c0006c, 0x00000008 }, 922 + { 0x0000e570, 0x00000004 }, 923 + { 0x0000e571, 0x00000004 }, 924 + { 0x0000e572, 0x0000000c }, 925 + { 0x0000a000, 0x00000004 }, 926 + { 0x0140a000, 0x00000004 }, 927 + { 0x0000e568, 0x00000004 }, 928 + { 0x000c2000, 0x00000004 }, 929 + { 0x00000076, 0x00000018 }, 930 + { 0x000b0000, 0x00000004 }, 931 + { 0x18c0e562, 0x00000004 }, 932 + { 0x00000078, 0x00000008 }, 933 + { 0x00c00077, 0x00000008 }, 934 + { 0x000700c7, 0x00000004 }, 935 + { 0x00000080, 0x00000038 }, 936 + { 0x0000e5bb, 0x00000004 }, 937 + { 0x0000e5bc, 0000000000 }, 938 + { 0x0000a000, 0x00000004 }, 939 + { 0x0000e821, 0x00000004 }, 940 + { 0x0000e800, 0000000000 }, 941 + { 0x0000e821, 0x00000004 }, 942 + { 0x0000e82e, 0000000000 }, 943 + { 0x02cca000, 0x00000004 }, 944 + { 0x00140000, 0x00000004 }, 945 + { 0x000ce1cc, 0x00000004 }, 946 + { 0x050de1cd, 0x00000004 }, 947 + { 0x00400000, 0x00000004 }, 948 + { 0x0000008f, 0x00000018 }, 949 + { 0x00c0a000, 0x00000004 }, 950 + { 0x0000008c, 0x00000008 }, 951 + { 0x00000091, 0x00000020 }, 952 + { 0x4200e000, 0000000000 }, 953 + { 0x00000098, 0x00000038 }, 954 + { 0x000ca000, 0x00000004 }, 955 + { 0x00140000, 0x00000004 }, 956 + { 0x000c2000, 0x00000004 }, 957 + { 0x00160000, 0x00000004 }, 958 + { 0x700ce000, 0x00000004 }, 959 + { 0x00140094, 0x00000008 }, 960 + { 0x4000e000, 0000000000 }, 961 + { 0x02400000, 0x00000004 }, 962 + { 0x400ee000, 0x00000004 }, 963 + { 0x02400000, 0x00000004 }, 964 + { 0x4000e000, 0000000000 }, 965 + { 0x000c2000, 0x00000004 }, 966 + { 0x0240e51b, 0x00000004 }, 967 + { 0x0080e50a, 0x00000005 }, 968 + { 0x0080e50b, 0x00000005 }, 969 + { 0x00220000, 0x00000004 }, 970 + { 0x000700c7, 0x00000004 }, 971 + { 0x000000a4, 0x00000038 }, 972 + { 0x0080e5bd, 0x00000005 }, 973 + { 0x0000e5bb, 0x00000005 }, 974 + { 0x0080e5bc, 0x00000005 }, 975 + { 0x00210000, 0x00000004 }, 976 + { 0x02800000, 0x00000004 }, 977 + { 0x00c000ab, 0x00000018 }, 978 + { 0x4180e000, 0x00000040 }, 979 + { 0x000000ad, 0x00000024 }, 980 + { 0x01000000, 0x0000000c }, 981 + { 0x0100e51d, 0x0000000c }, 982 + { 0x000045bb, 0x00000004 }, 983 + { 0x000080a7, 0x00000008 }, 984 + { 0x0000f3ce, 0x00000004 }, 985 + { 0x0140a000, 0x00000004 }, 986 + { 0x00cc2000, 0x00000004 }, 987 + { 0x08c053cf, 0x00000040 }, 988 + { 0x00008000, 0000000000 }, 989 + { 0x0000f3d2, 0x00000004 }, 990 + { 0x0140a000, 0x00000004 }, 991 + { 0x00cc2000, 0x00000004 }, 992 + { 0x08c053d3, 0x00000040 }, 993 + { 0x00008000, 0000000000 }, 994 + { 0x0000f39d, 0x00000004 }, 995 + { 0x0140a000, 0x00000004 }, 996 + { 0x00cc2000, 0x00000004 }, 997 + { 0x08c0539e, 0x00000040 }, 998 + { 0x00008000, 0000000000 }, 999 + { 0x03c00830, 0x00000004 }, 1000 + { 0x4200e000, 0000000000 }, 1001 + { 0x0000a000, 0x00000004 }, 1002 + { 0x200045e0, 0x00000004 }, 1003 + { 0x0000e5e1, 0000000000 }, 1004 + { 0x00000001, 0000000000 }, 1005 + { 0x000700c4, 0x00000004 }, 1006 + { 0x0800e394, 0000000000 }, 1007 + { 0000000000, 0000000000 }, 1008 + { 0x0000e8c4, 0x00000004 }, 1009 + { 0x0000e8c5, 0x00000004 }, 1010 + { 0x0000e8c6, 0x00000004 }, 1011 + { 0x0000e928, 0x00000004 }, 1012 + { 0x0000e929, 0x00000004 }, 1013 + { 0x0000e92a, 0x00000004 }, 1014 + { 0x000000c8, 0x00000008 }, 1015 + { 0x0000e928, 0x00000004 }, 1016 + { 0x0000e929, 0x00000004 }, 1017 + { 0x0000e92a, 0x00000004 }, 1018 + { 0x000000cf, 0x00000008 }, 1019 + { 0x02c02000, 0x00000004 }, 1020 + { 0x00060000, 0x00000004 }, 1021 + { 0x000000d7, 0x00000034 }, 1022 + { 0x000000d4, 0x00000008 }, 1023 + { 0x00008000, 0x00000004 }, 1024 + { 0xc000e000, 0000000000 }, 1025 + { 0x0000e1cc, 0x00000004 }, 1026 + { 0x0500e1cd, 0x00000004 }, 1027 + { 0x000ca000, 0x00000004 }, 1028 + { 0x000000de, 0x00000034 }, 1029 + { 0x000000da, 0x00000008 }, 1030 + { 0x0000a000, 0000000000 }, 1031 + { 0x0019e1cc, 0x00000004 }, 1032 + { 0x001b0001, 0x00000004 }, 1033 + { 0x0500a000, 0x00000004 }, 1034 + { 0x080041cd, 0x00000004 }, 1035 + { 0x000ca000, 0x00000004 }, 1036 + { 0x000000fb, 0x00000034 }, 1037 + { 0x0000004a, 0x00000008 }, 1038 + { 0000000000, 0000000000 }, 1039 + { 0000000000, 0000000000 }, 1040 + { 0000000000, 0000000000 }, 1041 + { 0000000000, 0000000000 }, 1042 + { 0000000000, 0000000000 }, 1043 + { 0000000000, 0000000000 }, 1044 + { 0000000000, 0000000000 }, 1045 + { 0000000000, 0000000000 }, 1046 + { 0000000000, 0000000000 }, 1047 + { 0000000000, 0000000000 }, 1048 + { 0000000000, 0000000000 }, 1049 + { 0000000000, 0000000000 }, 1050 + { 0000000000, 0000000000 }, 1051 + { 0000000000, 0000000000 }, 1052 + { 0000000000, 0000000000 }, 1053 + { 0000000000, 0000000000 }, 1054 + { 0x000c2000, 0x00000004 }, 1055 + { 0x001d0018, 0x00000004 }, 1056 + { 0x001a0001, 0x00000004 }, 1057 + { 0x000000fb, 0x00000034 }, 1058 + { 0x0000004a, 0x00000008 }, 1059 + { 0x0500a04a, 0x00000008 }, 1060 + { 0000000000, 0000000000 }, 1061 + { 0000000000, 0000000000 }, 1062 + { 0000000000, 0000000000 }, 1063 + { 0000000000, 0000000000 }, 1064 + }; 1065 + 1066 + static const u32 RS600_cp_microcode[][2] = { 1067 + { 0x4200e000, 0000000000 }, 1068 + { 0x4000e000, 0000000000 }, 1069 + { 0x000000a0, 0x00000008 }, 1070 + { 0x000000a4, 0x00000008 }, 1071 + { 0x4a554b4a, 0000000000 }, 1072 + { 0x4a4a4467, 0000000000 }, 1073 + { 0x55526f75, 0000000000 }, 1074 + { 0x4a7e7d65, 0000000000 }, 1075 + { 0x4ae74af6, 0000000000 }, 1076 + { 0x4ad34a4a, 0000000000 }, 1077 + { 0xd6898989, 0000000000 }, 1078 + { 0xcd4addcf, 0000000000 }, 1079 + { 0x8ebe4ae2, 0000000000 }, 1080 + { 0xc38a8a8a, 0000000000 }, 1081 + { 0x4a0f8cc8, 0000000000 }, 1082 + { 0x000ca000, 0x00000004 }, 1083 + { 0x000d0012, 0x00000038 }, 1084 + { 0x0000e8b4, 0x00000004 }, 1085 + { 0x000d0014, 0x00000038 }, 1086 + { 0x0000e8b6, 0x00000004 }, 1087 + { 0x000d0016, 0x00000038 }, 1088 + { 0x0000e854, 0x00000004 }, 1089 + { 0x000d0018, 0x00000038 }, 1090 + { 0x0000e855, 0x00000004 }, 1091 + { 0x000d001a, 0x00000038 }, 1092 + { 0x0000e856, 0x00000004 }, 1093 + { 0x000d001c, 0x00000038 }, 1094 + { 0x0000e857, 0x00000004 }, 1095 + { 0x000d001e, 0x00000038 }, 1096 + { 0x0000e824, 0x00000004 }, 1097 + { 0x000d0020, 0x00000038 }, 1098 + { 0x0000e825, 0x00000004 }, 1099 + { 0x000d0022, 0x00000038 }, 1100 + { 0x0000e830, 0x00000004 }, 1101 + { 0x000d0024, 0x00000038 }, 1102 + { 0x0000f0c0, 0x00000004 }, 1103 + { 0x000d0026, 0x00000038 }, 1104 + { 0x0000f0c1, 0x00000004 }, 1105 + { 0x000d0028, 0x00000038 }, 1106 + { 0x0000f041, 0x00000004 }, 1107 + { 0x000d002a, 0x00000038 }, 1108 + { 0x0000f184, 0x00000004 }, 1109 + { 0x000d002c, 0x00000038 }, 1110 + { 0x0000f185, 0x00000004 }, 1111 + { 0x000d002e, 0x00000038 }, 1112 + { 0x0000f186, 0x00000004 }, 1113 + { 0x000d0030, 0x00000038 }, 1114 + { 0x0000f187, 0x00000004 }, 1115 + { 0x000d0032, 0x00000038 }, 1116 + { 0x0000f180, 0x00000004 }, 1117 + { 0x000d0034, 0x00000038 }, 1118 + { 0x0000f393, 0x00000004 }, 1119 + { 0x000d0036, 0x00000038 }, 1120 + { 0x0000f38a, 0x00000004 }, 1121 + { 0x000d0038, 0x00000038 }, 1122 + { 0x0000f38e, 0x00000004 }, 1123 + { 0x0000e821, 0x00000004 }, 1124 + { 0x0140a000, 0x00000004 }, 1125 + { 0x00000043, 0x00000018 }, 1126 + { 0x00cce800, 0x00000004 }, 1127 + { 0x001b0001, 0x00000004 }, 1128 + { 0x08004800, 0x00000004 }, 1129 + { 0x001b0001, 0x00000004 }, 1130 + { 0x08004800, 0x00000004 }, 1131 + { 0x001b0001, 0x00000004 }, 1132 + { 0x08004800, 0x00000004 }, 1133 + { 0x0000003a, 0x00000008 }, 1134 + { 0x0000a000, 0000000000 }, 1135 + { 0x2000451d, 0x00000004 }, 1136 + { 0x0000e580, 0x00000004 }, 1137 + { 0x000ce581, 0x00000004 }, 1138 + { 0x08004580, 0x00000004 }, 1139 + { 0x000ce581, 0x00000004 }, 1140 + { 0x00000047, 0x00000008 }, 1141 + { 0x0000a000, 0000000000 }, 1142 + { 0x000c2000, 0x00000004 }, 1143 + { 0x0000e50e, 0x00000004 }, 1144 + { 0x00032000, 0x00000004 }, 1145 + { 0x00022051, 0x00000028 }, 1146 + { 0x00000051, 0x00000024 }, 1147 + { 0x0800450f, 0x00000004 }, 1148 + { 0x0000a04b, 0x00000008 }, 1149 + { 0x0000e565, 0x00000004 }, 1150 + { 0x0000e566, 0x00000004 }, 1151 + { 0x00000052, 0x00000008 }, 1152 + { 0x03cca5b4, 0x00000004 }, 1153 + { 0x05432000, 0x00000004 }, 1154 + { 0x00022000, 0x00000004 }, 1155 + { 0x4ccce05e, 0x00000030 }, 1156 + { 0x08274565, 0x00000004 }, 1157 + { 0x0000005e, 0x00000030 }, 1158 + { 0x08004564, 0x00000004 }, 1159 + { 0x0000e566, 0x00000004 }, 1160 + { 0x00000055, 0x00000008 }, 1161 + { 0x00802061, 0x00000010 }, 1162 + { 0x00202000, 0x00000004 }, 1163 + { 0x001b00ff, 0x00000004 }, 1164 + { 0x01000064, 0x00000010 }, 1165 + { 0x001f2000, 0x00000004 }, 1166 + { 0x001c00ff, 0x00000004 }, 1167 + { 0000000000, 0x0000000c }, 1168 + { 0x00000072, 0x00000030 }, 1169 + { 0x00000055, 0x00000008 }, 1170 + { 0x0000e576, 0x00000004 }, 1171 + { 0x0000e577, 0x00000004 }, 1172 + { 0x0000e50e, 0x00000004 }, 1173 + { 0x0000e50f, 0x00000004 }, 1174 + { 0x0140a000, 0x00000004 }, 1175 + { 0x00000069, 0x00000018 }, 1176 + { 0x00c0e5f9, 0x000000c2 }, 1177 + { 0x00000069, 0x00000008 }, 1178 + { 0x0014e50e, 0x00000004 }, 1179 + { 0x0040e50f, 0x00000004 }, 1180 + { 0x00c0006c, 0x00000008 }, 1181 + { 0x0000e570, 0x00000004 }, 1182 + { 0x0000e571, 0x00000004 }, 1183 + { 0x0000e572, 0x0000000c }, 1184 + { 0x0000a000, 0x00000004 }, 1185 + { 0x0140a000, 0x00000004 }, 1186 + { 0x0000e568, 0x00000004 }, 1187 + { 0x000c2000, 0x00000004 }, 1188 + { 0x00000076, 0x00000018 }, 1189 + { 0x000b0000, 0x00000004 }, 1190 + { 0x18c0e562, 0x00000004 }, 1191 + { 0x00000078, 0x00000008 }, 1192 + { 0x00c00077, 0x00000008 }, 1193 + { 0x000700d5, 0x00000004 }, 1194 + { 0x00000084, 0x00000038 }, 1195 + { 0x000ca086, 0x00000030 }, 1196 + { 0x080045bb, 0x00000004 }, 1197 + { 0x000c2087, 0x00000030 }, 1198 + { 0x0800e5bc, 0000000000 }, 1199 + { 0x0000e5bb, 0x00000004 }, 1200 + { 0x0000e5bc, 0000000000 }, 1201 + { 0x00120000, 0x0000000c }, 1202 + { 0x00120000, 0x00000004 }, 1203 + { 0x001b0002, 0x0000000c }, 1204 + { 0x0000a000, 0x00000004 }, 1205 + { 0x0000e821, 0x00000004 }, 1206 + { 0x0000e800, 0000000000 }, 1207 + { 0x0000e821, 0x00000004 }, 1208 + { 0x0000e82e, 0000000000 }, 1209 + { 0x02cca000, 0x00000004 }, 1210 + { 0x00140000, 0x00000004 }, 1211 + { 0x000ce1cc, 0x00000004 }, 1212 + { 0x050de1cd, 0x00000004 }, 1213 + { 0x00400000, 0x00000004 }, 1214 + { 0x00000096, 0x00000018 }, 1215 + { 0x00c0a000, 0x00000004 }, 1216 + { 0x00000093, 0x00000008 }, 1217 + { 0x00000098, 0x00000020 }, 1218 + { 0x4200e000, 0000000000 }, 1219 + { 0x0000009f, 0x00000038 }, 1220 + { 0x000ca000, 0x00000004 }, 1221 + { 0x00140000, 0x00000004 }, 1222 + { 0x000c2000, 0x00000004 }, 1223 + { 0x00160000, 0x00000004 }, 1224 + { 0x700ce000, 0x00000004 }, 1225 + { 0x0014009b, 0x00000008 }, 1226 + { 0x4000e000, 0000000000 }, 1227 + { 0x02400000, 0x00000004 }, 1228 + { 0x400ee000, 0x00000004 }, 1229 + { 0x02400000, 0x00000004 }, 1230 + { 0x4000e000, 0000000000 }, 1231 + { 0x000c2000, 0x00000004 }, 1232 + { 0x0240e51b, 0x00000004 }, 1233 + { 0x0080e50a, 0x00000005 }, 1234 + { 0x0080e50b, 0x00000005 }, 1235 + { 0x00220000, 0x00000004 }, 1236 + { 0x000700d5, 0x00000004 }, 1237 + { 0x000000b2, 0x00000038 }, 1238 + { 0x000c2087, 0x00000030 }, 1239 + { 0x0880e5bd, 0x00000005 }, 1240 + { 0x000c2086, 0x00000030 }, 1241 + { 0x0800e5bb, 0x00000005 }, 1242 + { 0x000c2087, 0x00000030 }, 1243 + { 0x0880e5bc, 0x00000005 }, 1244 + { 0x000000b5, 0x00000008 }, 1245 + { 0x0080e5bd, 0x00000005 }, 1246 + { 0x0000e5bb, 0x00000005 }, 1247 + { 0x0080e5bc, 0x00000005 }, 1248 + { 0x00210000, 0x00000004 }, 1249 + { 0x02800000, 0x00000004 }, 1250 + { 0x00c000b9, 0x00000018 }, 1251 + { 0x4180e000, 0x00000040 }, 1252 + { 0x000000bb, 0x00000024 }, 1253 + { 0x01000000, 0x0000000c }, 1254 + { 0x0100e51d, 0x0000000c }, 1255 + { 0x000045bb, 0x00000004 }, 1256 + { 0x000080b5, 0x00000008 }, 1257 + { 0x0000f3ce, 0x00000004 }, 1258 + { 0x0140a000, 0x00000004 }, 1259 + { 0x00cc2000, 0x00000004 }, 1260 + { 0x08c053cf, 0x00000040 }, 1261 + { 0x00008000, 0000000000 }, 1262 + { 0x0000f3d2, 0x00000004 }, 1263 + { 0x0140a000, 0x00000004 }, 1264 + { 0x00cc2000, 0x00000004 }, 1265 + { 0x08c053d3, 0x00000040 }, 1266 + { 0x00008000, 0000000000 }, 1267 + { 0x0000f39d, 0x00000004 }, 1268 + { 0x0140a000, 0x00000004 }, 1269 + { 0x00cc2000, 0x00000004 }, 1270 + { 0x08c0539e, 0x00000040 }, 1271 + { 0x00008000, 0000000000 }, 1272 + { 0x03c00830, 0x00000004 }, 1273 + { 0x4200e000, 0000000000 }, 1274 + { 0x0000a000, 0x00000004 }, 1275 + { 0x200045e0, 0x00000004 }, 1276 + { 0x0000e5e1, 0000000000 }, 1277 + { 0x00000001, 0000000000 }, 1278 + { 0x000700d2, 0x00000004 }, 1279 + { 0x0800e394, 0000000000 }, 1280 + { 0000000000, 0000000000 }, 1281 + { 0x0000e8c4, 0x00000004 }, 1282 + { 0x0000e8c5, 0x00000004 }, 1283 + { 0x0000e8c6, 0x00000004 }, 1284 + { 0x0000e928, 0x00000004 }, 1285 + { 0x0000e929, 0x00000004 }, 1286 + { 0x0000e92a, 0x00000004 }, 1287 + { 0x000000d6, 0x00000008 }, 1288 + { 0x0000e928, 0x00000004 }, 1289 + { 0x0000e929, 0x00000004 }, 1290 + { 0x0000e92a, 0x00000004 }, 1291 + { 0x000000dd, 0x00000008 }, 1292 + { 0x00e00116, 0000000000 }, 1293 + { 0x000700e1, 0x00000004 }, 1294 + { 0x0800401c, 0x00000004 }, 1295 + { 0x200050e7, 0x00000004 }, 1296 + { 0x0000e01d, 0x00000004 }, 1297 + { 0x000000e4, 0x00000008 }, 1298 + { 0x02c02000, 0x00000004 }, 1299 + { 0x00060000, 0x00000004 }, 1300 + { 0x000000eb, 0x00000034 }, 1301 + { 0x000000e8, 0x00000008 }, 1302 + { 0x00008000, 0x00000004 }, 1303 + { 0xc000e000, 0000000000 }, 1304 + { 0000000000, 0000000000 }, 1305 + { 0000000000, 0000000000 }, 1306 + { 0000000000, 0000000000 }, 1307 + { 0000000000, 0000000000 }, 1308 + { 0000000000, 0000000000 }, 1309 + { 0000000000, 0000000000 }, 1310 + { 0000000000, 0000000000 }, 1311 + { 0000000000, 0000000000 }, 1312 + { 0000000000, 0000000000 }, 1313 + { 0x000c2000, 0x00000004 }, 1314 + { 0x001d0018, 0x00000004 }, 1315 + { 0x001a0001, 0x00000004 }, 1316 + { 0x000000fb, 0x00000034 }, 1317 + { 0x0000004a, 0x00000008 }, 1318 + { 0x0500a04a, 0x00000008 }, 1319 + { 0000000000, 0000000000 }, 1320 + { 0000000000, 0000000000 }, 1321 + { 0000000000, 0000000000 }, 1322 + { 0000000000, 0000000000 }, 1323 + }; 1324 + 1325 + static const u32 RS690_cp_microcode[][2] = { 1326 + { 0x000000dd, 0x00000008 }, 1327 + { 0x000000df, 0x00000008 }, 1328 + { 0x000000a0, 0x00000008 }, 1329 + { 0x000000a4, 0x00000008 }, 1330 + { 0x4a554b4a, 0000000000 }, 1331 + { 0x4a4a4467, 0000000000 }, 1332 + { 0x55526f75, 0000000000 }, 1333 + { 0x4a7e7d65, 0000000000 }, 1334 + { 0x4ad74af6, 0000000000 }, 1335 + { 0x4ac94a4a, 0000000000 }, 1336 + { 0xcc898989, 0000000000 }, 1337 + { 0xc34ad3c5, 0000000000 }, 1338 + { 0x8e4a4a4a, 0000000000 }, 1339 + { 0x4a8a8a8a, 0000000000 }, 1340 + { 0x4a0f8c4a, 0000000000 }, 1341 + { 0x000ca000, 0x00000004 }, 1342 + { 0x000d0012, 0x00000038 }, 1343 + { 0x0000e8b4, 0x00000004 }, 1344 + { 0x000d0014, 0x00000038 }, 1345 + { 0x0000e8b6, 0x00000004 }, 1346 + { 0x000d0016, 0x00000038 }, 1347 + { 0x0000e854, 0x00000004 }, 1348 + { 0x000d0018, 0x00000038 }, 1349 + { 0x0000e855, 0x00000004 }, 1350 + { 0x000d001a, 0x00000038 }, 1351 + { 0x0000e856, 0x00000004 }, 1352 + { 0x000d001c, 0x00000038 }, 1353 + { 0x0000e857, 0x00000004 }, 1354 + { 0x000d001e, 0x00000038 }, 1355 + { 0x0000e824, 0x00000004 }, 1356 + { 0x000d0020, 0x00000038 }, 1357 + { 0x0000e825, 0x00000004 }, 1358 + { 0x000d0022, 0x00000038 }, 1359 + { 0x0000e830, 0x00000004 }, 1360 + { 0x000d0024, 0x00000038 }, 1361 + { 0x0000f0c0, 0x00000004 }, 1362 + { 0x000d0026, 0x00000038 }, 1363 + { 0x0000f0c1, 0x00000004 }, 1364 + { 0x000d0028, 0x00000038 }, 1365 + { 0x0000f041, 0x00000004 }, 1366 + { 0x000d002a, 0x00000038 }, 1367 + { 0x0000f184, 0x00000004 }, 1368 + { 0x000d002c, 0x00000038 }, 1369 + { 0x0000f185, 0x00000004 }, 1370 + { 0x000d002e, 0x00000038 }, 1371 + { 0x0000f186, 0x00000004 }, 1372 + { 0x000d0030, 0x00000038 }, 1373 + { 0x0000f187, 0x00000004 }, 1374 + { 0x000d0032, 0x00000038 }, 1375 + { 0x0000f180, 0x00000004 }, 1376 + { 0x000d0034, 0x00000038 }, 1377 + { 0x0000f393, 0x00000004 }, 1378 + { 0x000d0036, 0x00000038 }, 1379 + { 0x0000f38a, 0x00000004 }, 1380 + { 0x000d0038, 0x00000038 }, 1381 + { 0x0000f38e, 0x00000004 }, 1382 + { 0x0000e821, 0x00000004 }, 1383 + { 0x0140a000, 0x00000004 }, 1384 + { 0x00000043, 0x00000018 }, 1385 + { 0x00cce800, 0x00000004 }, 1386 + { 0x001b0001, 0x00000004 }, 1387 + { 0x08004800, 0x00000004 }, 1388 + { 0x001b0001, 0x00000004 }, 1389 + { 0x08004800, 0x00000004 }, 1390 + { 0x001b0001, 0x00000004 }, 1391 + { 0x08004800, 0x00000004 }, 1392 + { 0x0000003a, 0x00000008 }, 1393 + { 0x0000a000, 0000000000 }, 1394 + { 0x2000451d, 0x00000004 }, 1395 + { 0x0000e580, 0x00000004 }, 1396 + { 0x000ce581, 0x00000004 }, 1397 + { 0x08004580, 0x00000004 }, 1398 + { 0x000ce581, 0x00000004 }, 1399 + { 0x00000047, 0x00000008 }, 1400 + { 0x0000a000, 0000000000 }, 1401 + { 0x000c2000, 0x00000004 }, 1402 + { 0x0000e50e, 0x00000004 }, 1403 + { 0x00032000, 0x00000004 }, 1404 + { 0x00022051, 0x00000028 }, 1405 + { 0x00000051, 0x00000024 }, 1406 + { 0x0800450f, 0x00000004 }, 1407 + { 0x0000a04b, 0x00000008 }, 1408 + { 0x0000e565, 0x00000004 }, 1409 + { 0x0000e566, 0x00000004 }, 1410 + { 0x00000052, 0x00000008 }, 1411 + { 0x03cca5b4, 0x00000004 }, 1412 + { 0x05432000, 0x00000004 }, 1413 + { 0x00022000, 0x00000004 }, 1414 + { 0x4ccce05e, 0x00000030 }, 1415 + { 0x08274565, 0x00000004 }, 1416 + { 0x0000005e, 0x00000030 }, 1417 + { 0x08004564, 0x00000004 }, 1418 + { 0x0000e566, 0x00000004 }, 1419 + { 0x00000055, 0x00000008 }, 1420 + { 0x00802061, 0x00000010 }, 1421 + { 0x00202000, 0x00000004 }, 1422 + { 0x001b00ff, 0x00000004 }, 1423 + { 0x01000064, 0x00000010 }, 1424 + { 0x001f2000, 0x00000004 }, 1425 + { 0x001c00ff, 0x00000004 }, 1426 + { 0000000000, 0x0000000c }, 1427 + { 0x00000072, 0x00000030 }, 1428 + { 0x00000055, 0x00000008 }, 1429 + { 0x0000e576, 0x00000004 }, 1430 + { 0x0000e577, 0x00000004 }, 1431 + { 0x0000e50e, 0x00000004 }, 1432 + { 0x0000e50f, 0x00000004 }, 1433 + { 0x0140a000, 0x00000004 }, 1434 + { 0x00000069, 0x00000018 }, 1435 + { 0x00c0e5f9, 0x000000c2 }, 1436 + { 0x00000069, 0x00000008 }, 1437 + { 0x0014e50e, 0x00000004 }, 1438 + { 0x0040e50f, 0x00000004 }, 1439 + { 0x00c0006c, 0x00000008 }, 1440 + { 0x0000e570, 0x00000004 }, 1441 + { 0x0000e571, 0x00000004 }, 1442 + { 0x0000e572, 0x0000000c }, 1443 + { 0x0000a000, 0x00000004 }, 1444 + { 0x0140a000, 0x00000004 }, 1445 + { 0x0000e568, 0x00000004 }, 1446 + { 0x000c2000, 0x00000004 }, 1447 + { 0x00000076, 0x00000018 }, 1448 + { 0x000b0000, 0x00000004 }, 1449 + { 0x18c0e562, 0x00000004 }, 1450 + { 0x00000078, 0x00000008 }, 1451 + { 0x00c00077, 0x00000008 }, 1452 + { 0x000700cb, 0x00000004 }, 1453 + { 0x00000084, 0x00000038 }, 1454 + { 0x000ca086, 0x00000030 }, 1455 + { 0x080045bb, 0x00000004 }, 1456 + { 0x000c2087, 0x00000030 }, 1457 + { 0x0800e5bc, 0000000000 }, 1458 + { 0x0000e5bb, 0x00000004 }, 1459 + { 0x0000e5bc, 0000000000 }, 1460 + { 0x00120000, 0x0000000c }, 1461 + { 0x00120000, 0x00000004 }, 1462 + { 0x001b0002, 0x0000000c }, 1463 + { 0x0000a000, 0x00000004 }, 1464 + { 0x0000e821, 0x00000004 }, 1465 + { 0x0000e800, 0000000000 }, 1466 + { 0x0000e821, 0x00000004 }, 1467 + { 0x0000e82e, 0000000000 }, 1468 + { 0x02cca000, 0x00000004 }, 1469 + { 0x00140000, 0x00000004 }, 1470 + { 0x000ce1cc, 0x00000004 }, 1471 + { 0x050de1cd, 0x00000004 }, 1472 + { 0x00400000, 0x00000004 }, 1473 + { 0x00000096, 0x00000018 }, 1474 + { 0x00c0a000, 0x00000004 }, 1475 + { 0x00000093, 0x00000008 }, 1476 + { 0x00000098, 0x00000020 }, 1477 + { 0x4200e000, 0000000000 }, 1478 + { 0x0000009f, 0x00000038 }, 1479 + { 0x000ca000, 0x00000004 }, 1480 + { 0x00140000, 0x00000004 }, 1481 + { 0x000c2000, 0x00000004 }, 1482 + { 0x00160000, 0x00000004 }, 1483 + { 0x700ce000, 0x00000004 }, 1484 + { 0x0014009b, 0x00000008 }, 1485 + { 0x4000e000, 0000000000 }, 1486 + { 0x02400000, 0x00000004 }, 1487 + { 0x400ee000, 0x00000004 }, 1488 + { 0x02400000, 0x00000004 }, 1489 + { 0x4000e000, 0000000000 }, 1490 + { 0x00100000, 0x0000002c }, 1491 + { 0x00004000, 0000000000 }, 1492 + { 0x080045c8, 0x00000004 }, 1493 + { 0x00240005, 0x00000004 }, 1494 + { 0x08004d0b, 0x00000004 }, 1495 + { 0x000c2000, 0x00000004 }, 1496 + { 0x0240e51b, 0x00000004 }, 1497 + { 0x0080e50a, 0x00000005 }, 1498 + { 0x0080e50b, 0x00000005 }, 1499 + { 0x00220000, 0x00000004 }, 1500 + { 0x000700cb, 0x00000004 }, 1501 + { 0x000000b7, 0x00000038 }, 1502 + { 0x000c2087, 0x00000030 }, 1503 + { 0x0880e5bd, 0x00000005 }, 1504 + { 0x000c2086, 0x00000030 }, 1505 + { 0x0800e5bb, 0x00000005 }, 1506 + { 0x000c2087, 0x00000030 }, 1507 + { 0x0880e5bc, 0x00000005 }, 1508 + { 0x000000ba, 0x00000008 }, 1509 + { 0x0080e5bd, 0x00000005 }, 1510 + { 0x0000e5bb, 0x00000005 }, 1511 + { 0x0080e5bc, 0x00000005 }, 1512 + { 0x00210000, 0x00000004 }, 1513 + { 0x02800000, 0x00000004 }, 1514 + { 0x00c000be, 0x00000018 }, 1515 + { 0x4180e000, 0x00000040 }, 1516 + { 0x000000c0, 0x00000024 }, 1517 + { 0x01000000, 0x0000000c }, 1518 + { 0x0100e51d, 0x0000000c }, 1519 + { 0x000045bb, 0x00000004 }, 1520 + { 0x000080ba, 0x00000008 }, 1521 + { 0x03c00830, 0x00000004 }, 1522 + { 0x4200e000, 0000000000 }, 1523 + { 0x0000a000, 0x00000004 }, 1524 + { 0x200045e0, 0x00000004 }, 1525 + { 0x0000e5e1, 0000000000 }, 1526 + { 0x00000001, 0000000000 }, 1527 + { 0x000700c8, 0x00000004 }, 1528 + { 0x0800e394, 0000000000 }, 1529 + { 0000000000, 0000000000 }, 1530 + { 0x0000e8c4, 0x00000004 }, 1531 + { 0x0000e8c5, 0x00000004 }, 1532 + { 0x0000e8c6, 0x00000004 }, 1533 + { 0x0000e928, 0x00000004 }, 1534 + { 0x0000e929, 0x00000004 }, 1535 + { 0x0000e92a, 0x00000004 }, 1536 + { 0x000000cc, 0x00000008 }, 1537 + { 0x0000e928, 0x00000004 }, 1538 + { 0x0000e929, 0x00000004 }, 1539 + { 0x0000e92a, 0x00000004 }, 1540 + { 0x000000d3, 0x00000008 }, 1541 + { 0x02c02000, 0x00000004 }, 1542 + { 0x00060000, 0x00000004 }, 1543 + { 0x000000db, 0x00000034 }, 1544 + { 0x000000d8, 0x00000008 }, 1545 + { 0x00008000, 0x00000004 }, 1546 + { 0xc000e000, 0000000000 }, 1547 + { 0x000000e1, 0x00000030 }, 1548 + { 0x4200e000, 0000000000 }, 1549 + { 0x000000e1, 0x00000030 }, 1550 + { 0x4000e000, 0000000000 }, 1551 + { 0x0025001b, 0x00000004 }, 1552 + { 0x00230000, 0x00000004 }, 1553 + { 0x00250005, 0x00000004 }, 1554 + { 0x000000e6, 0x00000034 }, 1555 + { 0000000000, 0x0000000c }, 1556 + { 0x00244000, 0x00000004 }, 1557 + { 0x080045c8, 0x00000004 }, 1558 + { 0x00240005, 0x00000004 }, 1559 + { 0x08004d0b, 0x0000000c }, 1560 + { 0000000000, 0000000000 }, 1561 + { 0000000000, 0000000000 }, 1562 + { 0000000000, 0000000000 }, 1563 + { 0000000000, 0000000000 }, 1564 + { 0000000000, 0000000000 }, 1565 + { 0000000000, 0000000000 }, 1566 + { 0000000000, 0000000000 }, 1567 + { 0000000000, 0000000000 }, 1568 + { 0000000000, 0000000000 }, 1569 + { 0000000000, 0000000000 }, 1570 + { 0000000000, 0000000000 }, 1571 + { 0000000000, 0000000000 }, 1572 + { 0x000c2000, 0x00000004 }, 1573 + { 0x001d0018, 0x00000004 }, 1574 + { 0x001a0001, 0x00000004 }, 1575 + { 0x000000fb, 0x00000034 }, 1576 + { 0x0000004a, 0x00000008 }, 1577 + { 0x0500a04a, 0x00000008 }, 1578 + { 0000000000, 0000000000 }, 1579 + { 0000000000, 0000000000 }, 1580 + { 0000000000, 0000000000 }, 1581 + { 0000000000, 0000000000 }, 1582 + }; 1583 + 1584 + static const u32 R520_cp_microcode[][2] = { 1585 + { 0x4200e000, 0000000000 }, 1586 + { 0x4000e000, 0000000000 }, 1587 + { 0x00000099, 0x00000008 }, 1588 + { 0x0000009d, 0x00000008 }, 1589 + { 0x4a554b4a, 0000000000 }, 1590 + { 0x4a4a4467, 0000000000 }, 1591 + { 0x55526f75, 0000000000 }, 1592 + { 0x4a7e7d65, 0000000000 }, 1593 + { 0xe0dae6f6, 0000000000 }, 1594 + { 0x4ac54a4a, 0000000000 }, 1595 + { 0xc8828282, 0000000000 }, 1596 + { 0xbf4acfc1, 0000000000 }, 1597 + { 0x87b04ad5, 0000000000 }, 1598 + { 0xb5838383, 0000000000 }, 1599 + { 0x4a0f85ba, 0000000000 }, 1600 + { 0x000ca000, 0x00000004 }, 1601 + { 0x000d0012, 0x00000038 }, 1602 + { 0x0000e8b4, 0x00000004 }, 1603 + { 0x000d0014, 0x00000038 }, 1604 + { 0x0000e8b6, 0x00000004 }, 1605 + { 0x000d0016, 0x00000038 }, 1606 + { 0x0000e854, 0x00000004 }, 1607 + { 0x000d0018, 0x00000038 }, 1608 + { 0x0000e855, 0x00000004 }, 1609 + { 0x000d001a, 0x00000038 }, 1610 + { 0x0000e856, 0x00000004 }, 1611 + { 0x000d001c, 0x00000038 }, 1612 + { 0x0000e857, 0x00000004 }, 1613 + { 0x000d001e, 0x00000038 }, 1614 + { 0x0000e824, 0x00000004 }, 1615 + { 0x000d0020, 0x00000038 }, 1616 + { 0x0000e825, 0x00000004 }, 1617 + { 0x000d0022, 0x00000038 }, 1618 + { 0x0000e830, 0x00000004 }, 1619 + { 0x000d0024, 0x00000038 }, 1620 + { 0x0000f0c0, 0x00000004 }, 1621 + { 0x000d0026, 0x00000038 }, 1622 + { 0x0000f0c1, 0x00000004 }, 1623 + { 0x000d0028, 0x00000038 }, 1624 + { 0x0000e000, 0x00000004 }, 1625 + { 0x000d002a, 0x00000038 }, 1626 + { 0x0000e000, 0x00000004 }, 1627 + { 0x000d002c, 0x00000038 }, 1628 + { 0x0000e000, 0x00000004 }, 1629 + { 0x000d002e, 0x00000038 }, 1630 + { 0x0000e000, 0x00000004 }, 1631 + { 0x000d0030, 0x00000038 }, 1632 + { 0x0000e000, 0x00000004 }, 1633 + { 0x000d0032, 0x00000038 }, 1634 + { 0x0000f180, 0x00000004 }, 1635 + { 0x000d0034, 0x00000038 }, 1636 + { 0x0000f393, 0x00000004 }, 1637 + { 0x000d0036, 0x00000038 }, 1638 + { 0x0000f38a, 0x00000004 }, 1639 + { 0x000d0038, 0x00000038 }, 1640 + { 0x0000f38e, 0x00000004 }, 1641 + { 0x0000e821, 0x00000004 }, 1642 + { 0x0140a000, 0x00000004 }, 1643 + { 0x00000043, 0x00000018 }, 1644 + { 0x00cce800, 0x00000004 }, 1645 + { 0x001b0001, 0x00000004 }, 1646 + { 0x08004800, 0x00000004 }, 1647 + { 0x001b0001, 0x00000004 }, 1648 + { 0x08004800, 0x00000004 }, 1649 + { 0x001b0001, 0x00000004 }, 1650 + { 0x08004800, 0x00000004 }, 1651 + { 0x0000003a, 0x00000008 }, 1652 + { 0x0000a000, 0000000000 }, 1653 + { 0x2000451d, 0x00000004 }, 1654 + { 0x0000e580, 0x00000004 }, 1655 + { 0x000ce581, 0x00000004 }, 1656 + { 0x08004580, 0x00000004 }, 1657 + { 0x000ce581, 0x00000004 }, 1658 + { 0x00000047, 0x00000008 }, 1659 + { 0x0000a000, 0000000000 }, 1660 + { 0x000c2000, 0x00000004 }, 1661 + { 0x0000e50e, 0x00000004 }, 1662 + { 0x00032000, 0x00000004 }, 1663 + { 0x00022051, 0x00000028 }, 1664 + { 0x00000051, 0x00000024 }, 1665 + { 0x0800450f, 0x00000004 }, 1666 + { 0x0000a04b, 0x00000008 }, 1667 + { 0x0000e565, 0x00000004 }, 1668 + { 0x0000e566, 0x00000004 }, 1669 + { 0x00000052, 0x00000008 }, 1670 + { 0x03cca5b4, 0x00000004 }, 1671 + { 0x05432000, 0x00000004 }, 1672 + { 0x00022000, 0x00000004 }, 1673 + { 0x4ccce05e, 0x00000030 }, 1674 + { 0x08274565, 0x00000004 }, 1675 + { 0x0000005e, 0x00000030 }, 1676 + { 0x08004564, 0x00000004 }, 1677 + { 0x0000e566, 0x00000004 }, 1678 + { 0x00000055, 0x00000008 }, 1679 + { 0x00802061, 0x00000010 }, 1680 + { 0x00202000, 0x00000004 }, 1681 + { 0x001b00ff, 0x00000004 }, 1682 + { 0x01000064, 0x00000010 }, 1683 + { 0x001f2000, 0x00000004 }, 1684 + { 0x001c00ff, 0x00000004 }, 1685 + { 0000000000, 0x0000000c }, 1686 + { 0x00000072, 0x00000030 }, 1687 + { 0x00000055, 0x00000008 }, 1688 + { 0x0000e576, 0x00000004 }, 1689 + { 0x0000e577, 0x00000004 }, 1690 + { 0x0000e50e, 0x00000004 }, 1691 + { 0x0000e50f, 0x00000004 }, 1692 + { 0x0140a000, 0x00000004 }, 1693 + { 0x00000069, 0x00000018 }, 1694 + { 0x00c0e5f9, 0x000000c2 }, 1695 + { 0x00000069, 0x00000008 }, 1696 + { 0x0014e50e, 0x00000004 }, 1697 + { 0x0040e50f, 0x00000004 }, 1698 + { 0x00c0006c, 0x00000008 }, 1699 + { 0x0000e570, 0x00000004 }, 1700 + { 0x0000e571, 0x00000004 }, 1701 + { 0x0000e572, 0x0000000c }, 1702 + { 0x0000a000, 0x00000004 }, 1703 + { 0x0140a000, 0x00000004 }, 1704 + { 0x0000e568, 0x00000004 }, 1705 + { 0x000c2000, 0x00000004 }, 1706 + { 0x00000076, 0x00000018 }, 1707 + { 0x000b0000, 0x00000004 }, 1708 + { 0x18c0e562, 0x00000004 }, 1709 + { 0x00000078, 0x00000008 }, 1710 + { 0x00c00077, 0x00000008 }, 1711 + { 0x000700c7, 0x00000004 }, 1712 + { 0x00000080, 0x00000038 }, 1713 + { 0x0000e5bb, 0x00000004 }, 1714 + { 0x0000e5bc, 0000000000 }, 1715 + { 0x0000a000, 0x00000004 }, 1716 + { 0x0000e821, 0x00000004 }, 1717 + { 0x0000e800, 0000000000 }, 1718 + { 0x0000e821, 0x00000004 }, 1719 + { 0x0000e82e, 0000000000 }, 1720 + { 0x02cca000, 0x00000004 }, 1721 + { 0x00140000, 0x00000004 }, 1722 + { 0x000ce1cc, 0x00000004 }, 1723 + { 0x050de1cd, 0x00000004 }, 1724 + { 0x00400000, 0x00000004 }, 1725 + { 0x0000008f, 0x00000018 }, 1726 + { 0x00c0a000, 0x00000004 }, 1727 + { 0x0000008c, 0x00000008 }, 1728 + { 0x00000091, 0x00000020 }, 1729 + { 0x4200e000, 0000000000 }, 1730 + { 0x00000098, 0x00000038 }, 1731 + { 0x000ca000, 0x00000004 }, 1732 + { 0x00140000, 0x00000004 }, 1733 + { 0x000c2000, 0x00000004 }, 1734 + { 0x00160000, 0x00000004 }, 1735 + { 0x700ce000, 0x00000004 }, 1736 + { 0x00140094, 0x00000008 }, 1737 + { 0x4000e000, 0000000000 }, 1738 + { 0x02400000, 0x00000004 }, 1739 + { 0x400ee000, 0x00000004 }, 1740 + { 0x02400000, 0x00000004 }, 1741 + { 0x4000e000, 0000000000 }, 1742 + { 0x000c2000, 0x00000004 }, 1743 + { 0x0240e51b, 0x00000004 }, 1744 + { 0x0080e50a, 0x00000005 }, 1745 + { 0x0080e50b, 0x00000005 }, 1746 + { 0x00220000, 0x00000004 }, 1747 + { 0x000700c7, 0x00000004 }, 1748 + { 0x000000a4, 0x00000038 }, 1749 + { 0x0080e5bd, 0x00000005 }, 1750 + { 0x0000e5bb, 0x00000005 }, 1751 + { 0x0080e5bc, 0x00000005 }, 1752 + { 0x00210000, 0x00000004 }, 1753 + { 0x02800000, 0x00000004 }, 1754 + { 0x00c000ab, 0x00000018 }, 1755 + { 0x4180e000, 0x00000040 }, 1756 + { 0x000000ad, 0x00000024 }, 1757 + { 0x01000000, 0x0000000c }, 1758 + { 0x0100e51d, 0x0000000c }, 1759 + { 0x000045bb, 0x00000004 }, 1760 + { 0x000080a7, 0x00000008 }, 1761 + { 0x0000f3ce, 0x00000004 }, 1762 + { 0x0140a000, 0x00000004 }, 1763 + { 0x00cc2000, 0x00000004 }, 1764 + { 0x08c053cf, 0x00000040 }, 1765 + { 0x00008000, 0000000000 }, 1766 + { 0x0000f3d2, 0x00000004 }, 1767 + { 0x0140a000, 0x00000004 }, 1768 + { 0x00cc2000, 0x00000004 }, 1769 + { 0x08c053d3, 0x00000040 }, 1770 + { 0x00008000, 0000000000 }, 1771 + { 0x0000f39d, 0x00000004 }, 1772 + { 0x0140a000, 0x00000004 }, 1773 + { 0x00cc2000, 0x00000004 }, 1774 + { 0x08c0539e, 0x00000040 }, 1775 + { 0x00008000, 0000000000 }, 1776 + { 0x03c00830, 0x00000004 }, 1777 + { 0x4200e000, 0000000000 }, 1778 + { 0x0000a000, 0x00000004 }, 1779 + { 0x200045e0, 0x00000004 }, 1780 + { 0x0000e5e1, 0000000000 }, 1781 + { 0x00000001, 0000000000 }, 1782 + { 0x000700c4, 0x00000004 }, 1783 + { 0x0800e394, 0000000000 }, 1784 + { 0000000000, 0000000000 }, 1785 + { 0x0000e8c4, 0x00000004 }, 1786 + { 0x0000e8c5, 0x00000004 }, 1787 + { 0x0000e8c6, 0x00000004 }, 1788 + { 0x0000e928, 0x00000004 }, 1789 + { 0x0000e929, 0x00000004 }, 1790 + { 0x0000e92a, 0x00000004 }, 1791 + { 0x000000c8, 0x00000008 }, 1792 + { 0x0000e928, 0x00000004 }, 1793 + { 0x0000e929, 0x00000004 }, 1794 + { 0x0000e92a, 0x00000004 }, 1795 + { 0x000000cf, 0x00000008 }, 1796 + { 0xdeadbeef, 0000000000 }, 1797 + { 0x00000116, 0000000000 }, 1798 + { 0x000700d3, 0x00000004 }, 1799 + { 0x080050e7, 0x00000004 }, 1800 + { 0x000700d4, 0x00000004 }, 1801 + { 0x0800401c, 0x00000004 }, 1802 + { 0x0000e01d, 0000000000 }, 1803 + { 0x02c02000, 0x00000004 }, 1804 + { 0x00060000, 0x00000004 }, 1805 + { 0x000000de, 0x00000034 }, 1806 + { 0x000000db, 0x00000008 }, 1807 + { 0x00008000, 0x00000004 }, 1808 + { 0xc000e000, 0000000000 }, 1809 + { 0x0000e1cc, 0x00000004 }, 1810 + { 0x0500e1cd, 0x00000004 }, 1811 + { 0x000ca000, 0x00000004 }, 1812 + { 0x000000e5, 0x00000034 }, 1813 + { 0x000000e1, 0x00000008 }, 1814 + { 0x0000a000, 0000000000 }, 1815 + { 0x0019e1cc, 0x00000004 }, 1816 + { 0x001b0001, 0x00000004 }, 1817 + { 0x0500a000, 0x00000004 }, 1818 + { 0x080041cd, 0x00000004 }, 1819 + { 0x000ca000, 0x00000004 }, 1820 + { 0x000000fb, 0x00000034 }, 1821 + { 0x0000004a, 0x00000008 }, 1822 + { 0000000000, 0000000000 }, 1823 + { 0000000000, 0000000000 }, 1824 + { 0000000000, 0000000000 }, 1825 + { 0000000000, 0000000000 }, 1826 + { 0000000000, 0000000000 }, 1827 + { 0000000000, 0000000000 }, 1828 + { 0000000000, 0000000000 }, 1829 + { 0000000000, 0000000000 }, 1830 + { 0000000000, 0000000000 }, 1831 + { 0x000c2000, 0x00000004 }, 1832 + { 0x001d0018, 0x00000004 }, 1833 + { 0x001a0001, 0x00000004 }, 1834 + { 0x000000fb, 0x00000034 }, 1835 + { 0x0000004a, 0x00000008 }, 1836 + { 0x0500a04a, 0x00000008 }, 1837 + { 0000000000, 0000000000 }, 1838 + { 0000000000, 0000000000 }, 1839 + { 0000000000, 0000000000 }, 1840 + { 0000000000, 0000000000 }, 1841 + }; 1842 + 1843 + 1844 + #endif

+14 -3

drivers/char/drm/radeon_state.c

··· 1662 1662 u32 height; 1663 1663 int i; 1664 1664 u32 texpitch, microtile; 1665 - u32 offset; 1665 + u32 offset, byte_offset; 1666 1666 RING_LOCALS; 1667 1667 1668 1668 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { ··· 1726 1726 } 1727 1727 } else 1728 1728 microtile = 0; 1729 + 1730 + /* this might fail for zero-sized uploads - are those illegal? */ 1731 + if (!radeon_check_offset(dev_priv, tex->offset + image->height * 1732 + blit_width - 1)) { 1733 + DRM_ERROR("Invalid final destination offset\n"); 1734 + return -EINVAL; 1735 + } 1729 1736 1730 1737 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); 1731 1738 ··· 1847 1840 } 1848 1841 1849 1842 #undef RADEON_COPY_MT 1843 + byte_offset = (image->y & ~2047) * blit_width; 1850 1844 buf->file_priv = file_priv; 1851 1845 buf->used = size; 1852 1846 offset = dev_priv->gart_buffers_offset + buf->offset; ··· 1862 1854 RADEON_DP_SRC_SOURCE_MEMORY | 1863 1855 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); 1864 1856 OUT_RING((spitch << 22) | (offset >> 10)); 1865 - OUT_RING((texpitch << 22) | (tex->offset >> 10)); 1857 + OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10))); 1866 1858 OUT_RING(0); 1867 - OUT_RING((image->x << 16) | image->y); 1859 + OUT_RING((image->x << 16) | (image->y % 2048)); 1868 1860 OUT_RING((image->width << 16) | height); 1869 1861 RADEON_WAIT_UNTIL_2D_IDLE(); 1870 1862 ADVANCE_RING(); ··· 3044 3036 break; 3045 3037 case RADEON_PARAM_FB_LOCATION: 3046 3038 value = radeon_read_fb_location(dev_priv); 3039 + break; 3040 + case RADEON_PARAM_NUM_GB_PIPES: 3041 + value = dev_priv->num_gb_pipes; 3047 3042 break; 3048 3043 default: 3049 3044 DRM_DEBUG("Invalid parameter %d\n", param->param);

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