Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Fixes all over the place:
- amdkfd: two static checker fixes
- mst: a bunch of static checker and spec/hw interaction fixes
- amdgpu: fix Iceland hw properly, and some fiji bugs, along with
some write-combining fixes.
- exynos: some regression fixes
- adv7511: fix some EDID reading issues"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (38 commits)
drm/dp/mst: deallocate payload on port destruction
drm/dp/mst: Reverse order of MST enable and clearing VC payload table.
drm/dp/mst: move GUID storage from mgr, port to only mst branch
drm/dp/mst: change MST detection scheme
drm/dp/mst: Calculate MST PBN with 31.32 fixed point
drm: Add drm_fixp_from_fraction and drm_fixp2int_ceil
drm/mst: Add range check for max_payloads during init
drm/mst: Don't ignore the MST PBN self-test result
drm: fix missing reference counting decrease
drm/amdgpu: disable uvd and vce clockgating on Fiji
drm/amdgpu: remove exp hardware support from iceland
drm/amdgpu: load MEC ucode manually on iceland
drm/amdgpu: don't load MEC2 on topaz
drm/amdgpu: drop topaz support from gmc8 module
drm/amdgpu: pull topaz gmc bits into gmc_v7
drm/amdgpu: The VI specific EXE bit should only apply to GMC v8.0 above
drm/amdgpu: iceland use CI based MC IP
drm/amdgpu: move gmc7 support out of CIK dependency
drm/amdgpu/gfx7: enable cp inst/reg error interrupts
drm/amdgpu/gfx8: enable cp inst/reg error interrupts
...
+457
-248
+2
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+2
-1
drivers/gpu/drm/amd/amdgpu/Makefile
···
25
25
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o
26
26
27
27
# add asic specific block
28
-
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o gmc_v7_0.o cik_ih.o kv_smc.o kv_dpm.o \
28
+
amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
29
29
ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \
30
30
amdgpu_amdkfd_gfx_v7.o
31
31
···
34
34
35
35
# add GMC block
36
36
amdgpu-y += \
37
+
gmc_v7_0.o \
37
38
gmc_v8_0.o
38
39
39
40
# add IH block
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+5
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+5
-5
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
···
256
256
{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
257
257
#endif
258
258
/* topaz */
259
-
{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
260
-
{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
261
-
{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
262
-
{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
263
-
{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT},
259
+
{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
260
+
{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
261
+
{0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
262
+
{0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
263
+
{0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
264
264
/* tonga */
265
265
{0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
266
266
{0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
+8
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+8
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
···
33
33
#include <linux/slab.h>
34
34
#include <drm/drmP.h>
35
35
#include <drm/amdgpu_drm.h>
36
+
#include <drm/drm_cache.h>
36
37
#include "amdgpu.h"
37
38
#include "amdgpu_trace.h"
38
39
···
262
261
AMDGPU_GEM_DOMAIN_OA);
263
262
264
263
bo->flags = flags;
264
+
265
+
/* For architectures that don't support WC memory,
266
+
* mask out the WC flag from the BO
267
+
*/
268
+
if (!drm_arch_can_wc_memory())
269
+
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
270
+
265
271
amdgpu_fill_placement_to_bo(bo, placement);
266
272
/* Kernel allocation are uninterruptible */
267
273
r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+19
-1
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+19
-1
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
···
4738
4738
return 0;
4739
4739
}
4740
4740
4741
+
static int gfx_v7_0_late_init(void *handle)
4742
+
{
4743
+
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4744
+
int r;
4745
+
4746
+
r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4747
+
if (r)
4748
+
return r;
4749
+
4750
+
r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4751
+
if (r)
4752
+
return r;
4753
+
4754
+
return 0;
4755
+
}
4756
+
4741
4757
static int gfx_v7_0_sw_init(void *handle)
4742
4758
{
4743
4759
struct amdgpu_ring *ring;
···
4906
4890
{
4907
4891
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4908
4892
4893
+
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4894
+
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4909
4895
gfx_v7_0_cp_enable(adev, false);
4910
4896
gfx_v7_0_rlc_stop(adev);
4911
4897
gfx_v7_0_fini_pg(adev);
···
5545
5527
5546
5528
const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5547
5529
.early_init = gfx_v7_0_early_init,
5548
-
.late_init = NULL,
5530
+
.late_init = gfx_v7_0_late_init,
5549
5531
.sw_init = gfx_v7_0_sw_init,
5550
5532
.sw_fini = gfx_v7_0_sw_fini,
5551
5533
.hw_init = gfx_v7_0_hw_init,
+22
-6
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+22
-6
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
···
111
111
MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
112
112
MODULE_FIRMWARE("amdgpu/topaz_me.bin");
113
113
MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
114
-
MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
115
114
MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
116
115
117
116
MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
···
827
828
adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
828
829
adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
829
830
830
-
if (adev->asic_type != CHIP_STONEY) {
831
+
if ((adev->asic_type != CHIP_STONEY) &&
832
+
(adev->asic_type != CHIP_TOPAZ)) {
831
833
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
832
834
err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
833
835
if (!err) {
···
3851
3851
if (r)
3852
3852
return -EINVAL;
3853
3853
3854
-
r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3855
-
AMDGPU_UCODE_ID_CP_MEC1);
3856
-
if (r)
3857
-
return -EINVAL;
3854
+
if (adev->asic_type == CHIP_TOPAZ) {
3855
+
r = gfx_v8_0_cp_compute_load_microcode(adev);
3856
+
if (r)
3857
+
return r;
3858
+
} else {
3859
+
r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3860
+
AMDGPU_UCODE_ID_CP_MEC1);
3861
+
if (r)
3862
+
return -EINVAL;
3863
+
}
3858
3864
}
3859
3865
}
3860
3866
···
3907
3901
{
3908
3902
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3909
3903
3904
+
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3905
+
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3910
3906
gfx_v8_0_cp_enable(adev, false);
3911
3907
gfx_v8_0_rlc_stop(adev);
3912
3908
gfx_v8_0_cp_compute_fini(adev);
···
4336
4328
{
4337
4329
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4338
4330
int r;
4331
+
4332
+
r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4333
+
if (r)
4334
+
return r;
4335
+
4336
+
r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4337
+
if (r)
4338
+
return r;
4339
4339
4340
4340
/* requires IBs so do in late init after IB pool is initialized */
4341
4341
r = gfx_v8_0_do_edc_gpr_workarounds(adev);
+41
-2
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+41
-2
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
···
42
42
43
43
MODULE_FIRMWARE("radeon/bonaire_mc.bin");
44
44
MODULE_FIRMWARE("radeon/hawaii_mc.bin");
45
+
MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
46
+
47
+
static const u32 golden_settings_iceland_a11[] =
48
+
{
49
+
mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
50
+
mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
51
+
mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
52
+
mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
53
+
};
54
+
55
+
static const u32 iceland_mgcg_cgcg_init[] =
56
+
{
57
+
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
58
+
};
59
+
60
+
static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
61
+
{
62
+
switch (adev->asic_type) {
63
+
case CHIP_TOPAZ:
64
+
amdgpu_program_register_sequence(adev,
65
+
iceland_mgcg_cgcg_init,
66
+
(const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
67
+
amdgpu_program_register_sequence(adev,
68
+
golden_settings_iceland_a11,
69
+
(const u32)ARRAY_SIZE(golden_settings_iceland_a11));
70
+
break;
71
+
default:
72
+
break;
73
+
}
74
+
}
45
75
46
76
/**
47
-
* gmc8_mc_wait_for_idle - wait for MC idle callback.
77
+
* gmc7_mc_wait_for_idle - wait for MC idle callback.
48
78
*
49
79
* @adev: amdgpu_device pointer
50
80
*
···
162
132
case CHIP_HAWAII:
163
133
chip_name = "hawaii";
164
134
break;
135
+
case CHIP_TOPAZ:
136
+
chip_name = "topaz";
137
+
break;
165
138
case CHIP_KAVERI:
166
139
case CHIP_KABINI:
167
140
return 0;
168
141
default: BUG();
169
142
}
170
143
171
-
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
144
+
if (adev->asic_type == CHIP_TOPAZ)
145
+
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
146
+
else
147
+
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
148
+
172
149
err = request_firmware(&adev->mc.fw, fw_name, adev->dev);
173
150
if (err)
174
151
goto out;
···
1020
983
{
1021
984
int r;
1022
985
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
986
+
987
+
gmc_v7_0_init_golden_registers(adev);
1023
988
1024
989
gmc_v7_0_mc_program(adev);
1025
990
+1
-29
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+1
-29
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
···
42
42
static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev);
43
43
static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
44
44
45
-
MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
46
45
MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
47
-
MODULE_FIRMWARE("amdgpu/fiji_mc.bin");
48
46
49
47
static const u32 golden_settings_tonga_a11[] =
50
48
{
···
73
75
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
74
76
};
75
77
76
-
static const u32 golden_settings_iceland_a11[] =
77
-
{
78
-
mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
79
-
mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
80
-
mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
81
-
mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
82
-
};
83
-
84
-
static const u32 iceland_mgcg_cgcg_init[] =
85
-
{
86
-
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
87
-
};
88
-
89
78
static const u32 cz_mgcg_cgcg_init[] =
90
79
{
91
80
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
···
87
102
static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
88
103
{
89
104
switch (adev->asic_type) {
90
-
case CHIP_TOPAZ:
91
-
amdgpu_program_register_sequence(adev,
92
-
iceland_mgcg_cgcg_init,
93
-
(const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
94
-
amdgpu_program_register_sequence(adev,
95
-
golden_settings_iceland_a11,
96
-
(const u32)ARRAY_SIZE(golden_settings_iceland_a11));
97
-
break;
98
105
case CHIP_FIJI:
99
106
amdgpu_program_register_sequence(adev,
100
107
fiji_mgcg_cgcg_init,
···
206
229
DRM_DEBUG("\n");
207
230
208
231
switch (adev->asic_type) {
209
-
case CHIP_TOPAZ:
210
-
chip_name = "topaz";
211
-
break;
212
232
case CHIP_TONGA:
213
233
chip_name = "tonga";
214
234
break;
215
235
case CHIP_FIJI:
216
-
chip_name = "fiji";
217
-
break;
218
236
case CHIP_CARRIZO:
219
237
case CHIP_STONEY:
220
238
return 0;
···
979
1007
980
1008
gmc_v8_0_mc_program(adev);
981
1009
982
-
if (!(adev->flags & AMD_IS_APU)) {
1010
+
if (adev->asic_type == CHIP_TONGA) {
983
1011
r = gmc_v8_0_mc_load_microcode(adev);
984
1012
if (r) {
985
1013
DRM_ERROR("Failed to load MC firmware!\n");
+3
-9
drivers/gpu/drm/amd/amdgpu/iceland_smc.c
+3
-9
drivers/gpu/drm/amd/amdgpu/iceland_smc.c
···
432
432
case AMDGPU_UCODE_ID_CP_ME:
433
433
return UCODE_ID_CP_ME_MASK;
434
434
case AMDGPU_UCODE_ID_CP_MEC1:
435
-
return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT2_MASK;
435
+
return UCODE_ID_CP_MEC_MASK | UCODE_ID_CP_MEC_JT1_MASK;
436
436
case AMDGPU_UCODE_ID_CP_MEC2:
437
437
return UCODE_ID_CP_MEC_MASK;
438
438
case AMDGPU_UCODE_ID_RLC_G:
···
522
522
return -EINVAL;
523
523
}
524
524
525
-
if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_CP_MEC_JT2,
526
-
&toc->entry[toc->num_entries++])) {
527
-
DRM_ERROR("Failed to get firmware entry for MEC_JT2\n");
528
-
return -EINVAL;
529
-
}
530
-
531
525
if (iceland_smu_populate_single_firmware_entry(adev, UCODE_ID_SDMA0,
532
526
&toc->entry[toc->num_entries++])) {
533
527
DRM_ERROR("Failed to get firmware entry for SDMA0\n");
···
544
550
UCODE_ID_CP_ME_MASK |
545
551
UCODE_ID_CP_PFP_MASK |
546
552
UCODE_ID_CP_MEC_MASK |
547
-
UCODE_ID_CP_MEC_JT1_MASK |
548
-
UCODE_ID_CP_MEC_JT2_MASK;
553
+
UCODE_ID_CP_MEC_JT1_MASK;
554
+
549
555
550
556
if (iceland_send_msg_to_smc_with_parameter_without_waiting(adev, PPSMC_MSG_LoadUcodes, fw_to_load)) {
551
557
DRM_ERROR("Fail to request SMU load ucode\n");
+5
-5
drivers/gpu/drm/amd/amdgpu/vi.c
+5
-5
drivers/gpu/drm/amd/amdgpu/vi.c
···
61
61
#include "vi.h"
62
62
#include "vi_dpm.h"
63
63
#include "gmc_v8_0.h"
64
+
#include "gmc_v7_0.h"
64
65
#include "gfx_v8_0.h"
65
66
#include "sdma_v2_4.h"
66
67
#include "sdma_v3_0.h"
···
1110
1109
},
1111
1110
{
1112
1111
.type = AMD_IP_BLOCK_TYPE_GMC,
1113
-
.major = 8,
1114
-
.minor = 0,
1112
+
.major = 7,
1113
+
.minor = 4,
1115
1114
.rev = 0,
1116
-
.funcs = &gmc_v8_0_ip_funcs,
1115
+
.funcs = &gmc_v7_0_ip_funcs,
1117
1116
},
1118
1117
{
1119
1118
.type = AMD_IP_BLOCK_TYPE_IH,
···
1443
1442
break;
1444
1443
case CHIP_FIJI:
1445
1444
adev->has_uvd = true;
1446
-
adev->cg_flags = AMDGPU_CG_SUPPORT_UVD_MGCG |
1447
-
AMDGPU_CG_SUPPORT_VCE_MGCG;
1445
+
adev->cg_flags = 0;
1448
1446
adev->pg_flags = 0;
1449
1447
adev->external_rev_id = adev->rev_id + 0x3c;
1450
1448
break;
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_process.c
+1
-1
drivers/gpu/drm/amd/amdkfd/kfd_process.c
+178
-93
drivers/gpu/drm/drm_dp_mst_topology.c
+178
-93
drivers/gpu/drm/drm_dp_mst_topology.c
···
803
803
return mstb;
804
804
}
805
805
806
+
static void drm_dp_free_mst_port(struct kref *kref);
807
+
808
+
static void drm_dp_free_mst_branch_device(struct kref *kref)
809
+
{
810
+
struct drm_dp_mst_branch *mstb = container_of(kref, struct drm_dp_mst_branch, kref);
811
+
if (mstb->port_parent) {
812
+
if (list_empty(&mstb->port_parent->next))
813
+
kref_put(&mstb->port_parent->kref, drm_dp_free_mst_port);
814
+
}
815
+
kfree(mstb);
816
+
}
817
+
806
818
static void drm_dp_destroy_mst_branch_device(struct kref *kref)
807
819
{
808
820
struct drm_dp_mst_branch *mstb = container_of(kref, struct drm_dp_mst_branch, kref);
809
821
struct drm_dp_mst_port *port, *tmp;
810
822
bool wake_tx = false;
823
+
824
+
/*
825
+
* init kref again to be used by ports to remove mst branch when it is
826
+
* not needed anymore
827
+
*/
828
+
kref_init(kref);
829
+
830
+
if (mstb->port_parent && list_empty(&mstb->port_parent->next))
831
+
kref_get(&mstb->port_parent->kref);
811
832
812
833
/*
813
834
* destroy all ports - don't need lock
···
856
835
857
836
if (wake_tx)
858
837
wake_up(&mstb->mgr->tx_waitq);
859
-
kfree(mstb);
838
+
839
+
kref_put(kref, drm_dp_free_mst_branch_device);
860
840
}
861
841
862
842
static void drm_dp_put_mst_branch_device(struct drm_dp_mst_branch *mstb)
···
905
883
* from an EDID retrieval */
906
884
907
885
mutex_lock(&mgr->destroy_connector_lock);
886
+
kref_get(&port->parent->kref);
908
887
list_add(&port->next, &mgr->destroy_connector_list);
909
888
mutex_unlock(&mgr->destroy_connector_lock);
910
889
schedule_work(&mgr->destroy_connector_work);
···
1041
1018
return send_link;
1042
1019
}
1043
1020
1044
-
static void drm_dp_check_port_guid(struct drm_dp_mst_branch *mstb,
1045
-
struct drm_dp_mst_port *port)
1021
+
static void drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, u8 *guid)
1046
1022
{
1047
1023
int ret;
1048
-
if (port->dpcd_rev >= 0x12) {
1049
-
port->guid_valid = drm_dp_validate_guid(mstb->mgr, port->guid);
1050
-
if (!port->guid_valid) {
1051
-
ret = drm_dp_send_dpcd_write(mstb->mgr,
1052
-
port,
1053
-
DP_GUID,
1054
-
16, port->guid);
1055
-
port->guid_valid = true;
1024
+
1025
+
memcpy(mstb->guid, guid, 16);
1026
+
1027
+
if (!drm_dp_validate_guid(mstb->mgr, mstb->guid)) {
1028
+
if (mstb->port_parent) {
1029
+
ret = drm_dp_send_dpcd_write(
1030
+
mstb->mgr,
1031
+
mstb->port_parent,
1032
+
DP_GUID,
1033
+
16,
1034
+
mstb->guid);
1035
+
} else {
1036
+
1037
+
ret = drm_dp_dpcd_write(
1038
+
mstb->mgr->aux,
1039
+
DP_GUID,
1040
+
mstb->guid,
1041
+
16);
1056
1042
}
1057
1043
}
1058
1044
}
···
1118
1086
port->dpcd_rev = port_msg->dpcd_revision;
1119
1087
port->num_sdp_streams = port_msg->num_sdp_streams;
1120
1088
port->num_sdp_stream_sinks = port_msg->num_sdp_stream_sinks;
1121
-
memcpy(port->guid, port_msg->peer_guid, 16);
1122
1089
1123
1090
/* manage mstb port lists with mgr lock - take a reference
1124
1091
for this list */
···
1130
1099
1131
1100
if (old_ddps != port->ddps) {
1132
1101
if (port->ddps) {
1133
-
drm_dp_check_port_guid(mstb, port);
1134
1102
if (!port->input)
1135
1103
drm_dp_send_enum_path_resources(mstb->mgr, mstb, port);
1136
1104
} else {
1137
-
port->guid_valid = false;
1138
1105
port->available_pbn = 0;
1139
1106
}
1140
1107
}
···
1159
1130
drm_dp_put_port(port);
1160
1131
goto out;
1161
1132
}
1162
-
if (port->port_num >= DP_MST_LOGICAL_PORT_0) {
1163
-
port->cached_edid = drm_get_edid(port->connector, &port->aux.ddc);
1164
-
drm_mode_connector_set_tile_property(port->connector);
1165
-
}
1133
+
1134
+
drm_mode_connector_set_tile_property(port->connector);
1135
+
1166
1136
(*mstb->mgr->cbs->register_connector)(port->connector);
1167
1137
}
1168
-
1169
1138
out:
1170
1139
/* put reference to this port */
1171
1140
drm_dp_put_port(port);
···
1188
1161
port->ddps = conn_stat->displayport_device_plug_status;
1189
1162
1190
1163
if (old_ddps != port->ddps) {
1164
+
dowork = true;
1191
1165
if (port->ddps) {
1192
-
drm_dp_check_port_guid(mstb, port);
1193
-
dowork = true;
1194
1166
} else {
1195
-
port->guid_valid = false;
1196
1167
port->available_pbn = 0;
1197
1168
}
1198
1169
}
···
1247
1222
struct drm_dp_mst_branch *found_mstb;
1248
1223
struct drm_dp_mst_port *port;
1249
1224
1225
+
if (memcmp(mstb->guid, guid, 16) == 0)
1226
+
return mstb;
1227
+
1228
+
1250
1229
list_for_each_entry(port, &mstb->ports, next) {
1251
1230
if (!port->mstb)
1252
1231
continue;
1253
-
1254
-
if (port->guid_valid && memcmp(port->guid, guid, 16) == 0)
1255
-
return port->mstb;
1256
1232
1257
1233
found_mstb = get_mst_branch_device_by_guid_helper(port->mstb, guid);
1258
1234
···
1273
1247
/* find the port by iterating down */
1274
1248
mutex_lock(&mgr->lock);
1275
1249
1276
-
if (mgr->guid_valid && memcmp(mgr->guid, guid, 16) == 0)
1277
-
mstb = mgr->mst_primary;
1278
-
else
1279
-
mstb = get_mst_branch_device_by_guid_helper(mgr->mst_primary, guid);
1250
+
mstb = get_mst_branch_device_by_guid_helper(mgr->mst_primary, guid);
1280
1251
1281
1252
if (mstb)
1282
1253
kref_get(&mstb->kref);
···
1294
1271
if (port->input)
1295
1272
continue;
1296
1273
1297
-
if (!port->ddps)
1274
+
if (!port->ddps) {
1275
+
if (port->cached_edid) {
1276
+
kfree(port->cached_edid);
1277
+
port->cached_edid = NULL;
1278
+
}
1298
1279
continue;
1280
+
}
1299
1281
1300
1282
if (!port->available_pbn)
1301
1283
drm_dp_send_enum_path_resources(mgr, mstb, port);
···
1310
1282
if (mstb_child) {
1311
1283
drm_dp_check_and_send_link_address(mgr, mstb_child);
1312
1284
drm_dp_put_mst_branch_device(mstb_child);
1285
+
}
1286
+
} else if (port->pdt == DP_PEER_DEVICE_SST_SINK ||
1287
+
port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV) {
1288
+
if (!port->cached_edid) {
1289
+
port->cached_edid =
1290
+
drm_get_edid(port->connector, &port->aux.ddc);
1313
1291
}
1314
1292
}
1315
1293
}
···
1336
1302
drm_dp_check_and_send_link_address(mgr, mstb);
1337
1303
drm_dp_put_mst_branch_device(mstb);
1338
1304
}
1305
+
1306
+
(*mgr->cbs->hotplug)(mgr);
1339
1307
}
1340
1308
1341
1309
static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr,
···
1591
1555
txmsg->reply.u.link_addr.ports[i].num_sdp_streams,
1592
1556
txmsg->reply.u.link_addr.ports[i].num_sdp_stream_sinks);
1593
1557
}
1558
+
1559
+
drm_dp_check_mstb_guid(mstb, txmsg->reply.u.link_addr.guid);
1560
+
1594
1561
for (i = 0; i < txmsg->reply.u.link_addr.nports; i++) {
1595
1562
drm_dp_add_port(mstb, mgr->dev, &txmsg->reply.u.link_addr.ports[i]);
1596
1563
}
1597
-
(*mgr->cbs->hotplug)(mgr);
1598
1564
}
1599
1565
} else {
1600
1566
mstb->link_address_sent = false;
···
1640
1602
return 0;
1641
1603
}
1642
1604
1605
+
static struct drm_dp_mst_port *drm_dp_get_last_connected_port_to_mstb(struct drm_dp_mst_branch *mstb)
1606
+
{
1607
+
if (!mstb->port_parent)
1608
+
return NULL;
1609
+
1610
+
if (mstb->port_parent->mstb != mstb)
1611
+
return mstb->port_parent;
1612
+
1613
+
return drm_dp_get_last_connected_port_to_mstb(mstb->port_parent->parent);
1614
+
}
1615
+
1616
+
static struct drm_dp_mst_branch *drm_dp_get_last_connected_port_and_mstb(struct drm_dp_mst_topology_mgr *mgr,
1617
+
struct drm_dp_mst_branch *mstb,
1618
+
int *port_num)
1619
+
{
1620
+
struct drm_dp_mst_branch *rmstb = NULL;
1621
+
struct drm_dp_mst_port *found_port;
1622
+
mutex_lock(&mgr->lock);
1623
+
if (mgr->mst_primary) {
1624
+
found_port = drm_dp_get_last_connected_port_to_mstb(mstb);
1625
+
1626
+
if (found_port) {
1627
+
rmstb = found_port->parent;
1628
+
kref_get(&rmstb->kref);
1629
+
*port_num = found_port->port_num;
1630
+
}
1631
+
}
1632
+
mutex_unlock(&mgr->lock);
1633
+
return rmstb;
1634
+
}
1635
+
1643
1636
static int drm_dp_payload_send_msg(struct drm_dp_mst_topology_mgr *mgr,
1644
1637
struct drm_dp_mst_port *port,
1645
1638
int id,
···
1678
1609
{
1679
1610
struct drm_dp_sideband_msg_tx *txmsg;
1680
1611
struct drm_dp_mst_branch *mstb;
1681
-
int len, ret;
1612
+
int len, ret, port_num;
1682
1613
u8 sinks[DRM_DP_MAX_SDP_STREAMS];
1683
1614
int i;
1684
1615
1616
+
port_num = port->port_num;
1685
1617
mstb = drm_dp_get_validated_mstb_ref(mgr, port->parent);
1686
-
if (!mstb)
1687
-
return -EINVAL;
1618
+
if (!mstb) {
1619
+
mstb = drm_dp_get_last_connected_port_and_mstb(mgr, port->parent, &port_num);
1620
+
1621
+
if (!mstb)
1622
+
return -EINVAL;
1623
+
}
1688
1624
1689
1625
txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
1690
1626
if (!txmsg) {
···
1701
1627
sinks[i] = i;
1702
1628
1703
1629
txmsg->dst = mstb;
1704
-
len = build_allocate_payload(txmsg, port->port_num,
1630
+
len = build_allocate_payload(txmsg, port_num,
1705
1631
id,
1706
1632
pbn, port->num_sdp_streams, sinks);
1707
1633
···
2057
1983
mgr->mst_primary = mstb;
2058
1984
kref_get(&mgr->mst_primary->kref);
2059
1985
1986
+
ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
1987
+
DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC);
1988
+
if (ret < 0) {
1989
+
goto out_unlock;
1990
+
}
1991
+
2060
1992
{
2061
1993
struct drm_dp_payload reset_pay;
2062
1994
reset_pay.start_slot = 0;
2063
1995
reset_pay.num_slots = 0x3f;
2064
1996
drm_dp_dpcd_write_payload(mgr, 0, &reset_pay);
2065
-
}
2066
-
2067
-
ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,
2068
-
DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC);
2069
-
if (ret < 0) {
2070
-
goto out_unlock;
2071
-
}
2072
-
2073
-
2074
-
/* sort out guid */
2075
-
ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, mgr->guid, 16);
2076
-
if (ret != 16) {
2077
-
DRM_DEBUG_KMS("failed to read DP GUID %d\n", ret);
2078
-
goto out_unlock;
2079
-
}
2080
-
2081
-
mgr->guid_valid = drm_dp_validate_guid(mgr, mgr->guid);
2082
-
if (!mgr->guid_valid) {
2083
-
ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, mgr->guid, 16);
2084
-
mgr->guid_valid = true;
2085
1997
}
2086
1998
2087
1999
queue_work(system_long_wq, &mgr->work);
···
2291
2231
}
2292
2232
2293
2233
drm_dp_update_port(mstb, &msg.u.conn_stat);
2294
-
DRM_DEBUG_KMS("Got CSN: pn: %d ldps:%d ddps: %d mcs: %d ip: %d pdt: %d\n", msg.u.conn_stat.port_number, msg.u.conn_stat.legacy_device_plug_status, msg.u.conn_stat.displayport_device_plug_status, msg.u.conn_stat.message_capability_status, msg.u.conn_stat.input_port, msg.u.conn_stat.peer_device_type);
2295
-
(*mgr->cbs->hotplug)(mgr);
2296
2234
2235
+
DRM_DEBUG_KMS("Got CSN: pn: %d ldps:%d ddps: %d mcs: %d ip: %d pdt: %d\n", msg.u.conn_stat.port_number, msg.u.conn_stat.legacy_device_plug_status, msg.u.conn_stat.displayport_device_plug_status, msg.u.conn_stat.message_capability_status, msg.u.conn_stat.input_port, msg.u.conn_stat.peer_device_type);
2297
2236
} else if (msg.req_type == DP_RESOURCE_STATUS_NOTIFY) {
2298
2237
drm_dp_send_up_ack_reply(mgr, mgr->mst_primary, msg.req_type, seqno, false);
2299
2238
if (!mstb)
···
2379
2320
2380
2321
case DP_PEER_DEVICE_SST_SINK:
2381
2322
status = connector_status_connected;
2382
-
/* for logical ports - cache the EDID */
2383
-
if (port->port_num >= 8 && !port->cached_edid) {
2384
-
port->cached_edid = drm_get_edid(connector, &port->aux.ddc);
2385
-
}
2386
2323
break;
2387
2324
case DP_PEER_DEVICE_DP_LEGACY_CONV:
2388
2325
if (port->ldps)
···
2433
2378
2434
2379
if (port->cached_edid)
2435
2380
edid = drm_edid_duplicate(port->cached_edid);
2436
-
else {
2437
-
edid = drm_get_edid(connector, &port->aux.ddc);
2438
-
drm_mode_connector_set_tile_property(connector);
2439
-
}
2381
+
2440
2382
port->has_audio = drm_detect_monitor_audio(edid);
2441
2383
drm_dp_put_port(port);
2442
2384
return edid;
···
2498
2446
DRM_DEBUG_KMS("payload: vcpi %d already allocated for pbn %d - requested pbn %d\n", port->vcpi.vcpi, port->vcpi.pbn, pbn);
2499
2447
if (pbn == port->vcpi.pbn) {
2500
2448
*slots = port->vcpi.num_slots;
2449
+
drm_dp_put_port(port);
2501
2450
return true;
2502
2451
}
2503
2452
}
···
2658
2605
*/
2659
2606
int drm_dp_calc_pbn_mode(int clock, int bpp)
2660
2607
{
2661
-
fixed20_12 pix_bw;
2662
-
fixed20_12 fbpp;
2663
-
fixed20_12 result;
2664
-
fixed20_12 margin, tmp;
2665
-
u32 res;
2608
+
u64 kbps;
2609
+
s64 peak_kbps;
2610
+
u32 numerator;
2611
+
u32 denominator;
2666
2612
2667
-
pix_bw.full = dfixed_const(clock);
2668
-
fbpp.full = dfixed_const(bpp);
2669
-
tmp.full = dfixed_const(8);
2670
-
fbpp.full = dfixed_div(fbpp, tmp);
2613
+
kbps = clock * bpp;
2671
2614
2672
-
result.full = dfixed_mul(pix_bw, fbpp);
2673
-
margin.full = dfixed_const(54);
2674
-
tmp.full = dfixed_const(64);
2675
-
margin.full = dfixed_div(margin, tmp);
2676
-
result.full = dfixed_div(result, margin);
2615
+
/*
2616
+
* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2617
+
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2618
+
* common multiplier to render an integer PBN for all link rate/lane
2619
+
* counts combinations
2620
+
* calculate
2621
+
* peak_kbps *= (1006/1000)
2622
+
* peak_kbps *= (64/54)
2623
+
* peak_kbps *= 8 convert to bytes
2624
+
*/
2677
2625
2678
-
margin.full = dfixed_const(1006);
2679
-
tmp.full = dfixed_const(1000);
2680
-
margin.full = dfixed_div(margin, tmp);
2681
-
result.full = dfixed_mul(result, margin);
2626
+
numerator = 64 * 1006;
2627
+
denominator = 54 * 8 * 1000 * 1000;
2682
2628
2683
-
result.full = dfixed_div(result, tmp);
2684
-
result.full = dfixed_ceil(result);
2685
-
res = dfixed_trunc(result);
2686
-
return res;
2629
+
kbps *= numerator;
2630
+
peak_kbps = drm_fixp_from_fraction(kbps, denominator);
2631
+
2632
+
return drm_fixp2int_ceil(peak_kbps);
2687
2633
}
2688
2634
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
2689
2635
···
2690
2638
{
2691
2639
int ret;
2692
2640
ret = drm_dp_calc_pbn_mode(154000, 30);
2693
-
if (ret != 689)
2641
+
if (ret != 689) {
2642
+
DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n",
2643
+
154000, 30, 689, ret);
2694
2644
return -EINVAL;
2645
+
}
2695
2646
ret = drm_dp_calc_pbn_mode(234000, 30);
2696
-
if (ret != 1047)
2647
+
if (ret != 1047) {
2648
+
DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n",
2649
+
234000, 30, 1047, ret);
2697
2650
return -EINVAL;
2651
+
}
2652
+
ret = drm_dp_calc_pbn_mode(297000, 24);
2653
+
if (ret != 1063) {
2654
+
DRM_ERROR("PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n",
2655
+
297000, 24, 1063, ret);
2656
+
return -EINVAL;
2657
+
}
2698
2658
return 0;
2699
2659
}
2700
2660
···
2847
2783
mutex_unlock(&mgr->qlock);
2848
2784
}
2849
2785
2786
+
static void drm_dp_free_mst_port(struct kref *kref)
2787
+
{
2788
+
struct drm_dp_mst_port *port = container_of(kref, struct drm_dp_mst_port, kref);
2789
+
kref_put(&port->parent->kref, drm_dp_free_mst_branch_device);
2790
+
kfree(port);
2791
+
}
2792
+
2850
2793
static void drm_dp_destroy_connector_work(struct work_struct *work)
2851
2794
{
2852
2795
struct drm_dp_mst_topology_mgr *mgr = container_of(work, struct drm_dp_mst_topology_mgr, destroy_connector_work);
···
2874
2803
list_del(&port->next);
2875
2804
mutex_unlock(&mgr->destroy_connector_lock);
2876
2805
2806
+
kref_init(&port->kref);
2807
+
INIT_LIST_HEAD(&port->next);
2808
+
2877
2809
mgr->cbs->destroy_connector(mgr, port->connector);
2878
2810
2879
2811
drm_dp_port_teardown_pdt(port, port->pdt);
2880
2812
2881
-
if (!port->input && port->vcpi.vcpi > 0)
2882
-
drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi);
2883
-
kfree(port);
2813
+
if (!port->input && port->vcpi.vcpi > 0) {
2814
+
if (mgr->mst_state) {
2815
+
drm_dp_mst_reset_vcpi_slots(mgr, port);
2816
+
drm_dp_update_payload_part1(mgr);
2817
+
drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi);
2818
+
}
2819
+
}
2820
+
2821
+
kref_put(&port->kref, drm_dp_free_mst_port);
2884
2822
send_hotplug = true;
2885
2823
}
2886
2824
if (send_hotplug)
···
2927
2847
mgr->max_dpcd_transaction_bytes = max_dpcd_transaction_bytes;
2928
2848
mgr->max_payloads = max_payloads;
2929
2849
mgr->conn_base_id = conn_base_id;
2850
+
if (max_payloads + 1 > sizeof(mgr->payload_mask) * 8 ||
2851
+
max_payloads + 1 > sizeof(mgr->vcpi_mask) * 8)
2852
+
return -EINVAL;
2930
2853
mgr->payloads = kcalloc(max_payloads, sizeof(struct drm_dp_payload), GFP_KERNEL);
2931
2854
if (!mgr->payloads)
2932
2855
return -ENOMEM;
···
2937
2854
if (!mgr->proposed_vcpis)
2938
2855
return -ENOMEM;
2939
2856
set_bit(0, &mgr->payload_mask);
2940
-
test_calc_pbn_mode();
2857
+
if (test_calc_pbn_mode() < 0)
2858
+
DRM_ERROR("MST PBN self-test failed\n");
2859
+
2941
2860
return 0;
2942
2861
}
2943
2862
EXPORT_SYMBOL(drm_dp_mst_topology_mgr_init);
+25
-30
drivers/gpu/drm/exynos/exynos_dp_core.c
+25
-30
drivers/gpu/drm/exynos/exynos_dp_core.c
···
1392
1392
static int exynos_dp_probe(struct platform_device *pdev)
1393
1393
{
1394
1394
struct device *dev = &pdev->dev;
1395
-
struct device_node *panel_node = NULL, *bridge_node, *endpoint = NULL;
1395
+
struct device_node *np = NULL, *endpoint = NULL;
1396
1396
struct exynos_dp_device *dp;
1397
1397
int ret;
1398
1398
···
1404
1404
platform_set_drvdata(pdev, dp);
1405
1405
1406
1406
/* This is for the backward compatibility. */
1407
-
panel_node = of_parse_phandle(dev->of_node, "panel", 0);
1408
-
if (panel_node) {
1409
-
dp->panel = of_drm_find_panel(panel_node);
1410
-
of_node_put(panel_node);
1407
+
np = of_parse_phandle(dev->of_node, "panel", 0);
1408
+
if (np) {
1409
+
dp->panel = of_drm_find_panel(np);
1410
+
of_node_put(np);
1411
1411
if (!dp->panel)
1412
1412
return -EPROBE_DEFER;
1413
-
} else {
1414
-
endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1415
-
if (endpoint) {
1416
-
panel_node = of_graph_get_remote_port_parent(endpoint);
1417
-
if (panel_node) {
1418
-
dp->panel = of_drm_find_panel(panel_node);
1419
-
of_node_put(panel_node);
1420
-
if (!dp->panel)
1421
-
return -EPROBE_DEFER;
1422
-
} else {
1423
-
DRM_ERROR("no port node for panel device.\n");
1424
-
return -EINVAL;
1425
-
}
1426
-
}
1427
-
}
1428
-
1429
-
if (endpoint)
1430
1413
goto out;
1414
+
}
1431
1415
1432
1416
endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1433
1417
if (endpoint) {
1434
-
bridge_node = of_graph_get_remote_port_parent(endpoint);
1435
-
if (bridge_node) {
1436
-
dp->ptn_bridge = of_drm_find_bridge(bridge_node);
1437
-
of_node_put(bridge_node);
1438
-
if (!dp->ptn_bridge)
1439
-
return -EPROBE_DEFER;
1440
-
} else
1441
-
return -EPROBE_DEFER;
1418
+
np = of_graph_get_remote_port_parent(endpoint);
1419
+
if (np) {
1420
+
/* The remote port can be either a panel or a bridge */
1421
+
dp->panel = of_drm_find_panel(np);
1422
+
if (!dp->panel) {
1423
+
dp->ptn_bridge = of_drm_find_bridge(np);
1424
+
if (!dp->ptn_bridge) {
1425
+
of_node_put(np);
1426
+
return -EPROBE_DEFER;
1427
+
}
1428
+
}
1429
+
of_node_put(np);
1430
+
} else {
1431
+
DRM_ERROR("no remote endpoint device node found.\n");
1432
+
return -EINVAL;
1433
+
}
1434
+
} else {
1435
+
DRM_ERROR("no port endpoint subnode found.\n");
1436
+
return -EINVAL;
1442
1437
}
1443
1438
1444
1439
out:
+2
-4
drivers/gpu/drm/exynos/exynos_drm_dsi.c
+2
-4
drivers/gpu/drm/exynos/exynos_drm_dsi.c
···
1906
1906
return 0;
1907
1907
}
1908
1908
1909
-
#ifdef CONFIG_PM
1910
-
static int exynos_dsi_suspend(struct device *dev)
1909
+
static int __maybe_unused exynos_dsi_suspend(struct device *dev)
1911
1910
{
1912
1911
struct drm_encoder *encoder = dev_get_drvdata(dev);
1913
1912
struct exynos_dsi *dsi = encoder_to_dsi(encoder);
···
1937
1938
return 0;
1938
1939
}
1939
1940
1940
-
static int exynos_dsi_resume(struct device *dev)
1941
+
static int __maybe_unused exynos_dsi_resume(struct device *dev)
1941
1942
{
1942
1943
struct drm_encoder *encoder = dev_get_drvdata(dev);
1943
1944
struct exynos_dsi *dsi = encoder_to_dsi(encoder);
···
1971
1972
1972
1973
return ret;
1973
1974
}
1974
-
#endif
1975
1975
1976
1976
static const struct dev_pm_ops exynos_dsi_pm_ops = {
1977
1977
SET_RUNTIME_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume, NULL)
+2
-4
drivers/gpu/drm/exynos/exynos_mixer.c
+2
-4
drivers/gpu/drm/exynos/exynos_mixer.c
···
1289
1289
return 0;
1290
1290
}
1291
1291
1292
-
#ifdef CONFIG_PM_SLEEP
1293
-
static int exynos_mixer_suspend(struct device *dev)
1292
+
static int __maybe_unused exynos_mixer_suspend(struct device *dev)
1294
1293
{
1295
1294
struct mixer_context *ctx = dev_get_drvdata(dev);
1296
1295
struct mixer_resources *res = &ctx->mixer_res;
···
1305
1306
return 0;
1306
1307
}
1307
1308
1308
-
static int exynos_mixer_resume(struct device *dev)
1309
+
static int __maybe_unused exynos_mixer_resume(struct device *dev)
1309
1310
{
1310
1311
struct mixer_context *ctx = dev_get_drvdata(dev);
1311
1312
struct mixer_resources *res = &ctx->mixer_res;
···
1341
1342
1342
1343
return 0;
1343
1344
}
1344
-
#endif
1345
1345
1346
1346
static const struct dev_pm_ops exynos_mixer_pm_ops = {
1347
1347
SET_RUNTIME_PM_OPS(exynos_mixer_suspend, exynos_mixer_resume, NULL)
+29
-19
drivers/gpu/drm/i2c/adv7511.c
+29
-19
drivers/gpu/drm/i2c/adv7511.c
···
136
136
case ADV7511_REG_BKSV(3):
137
137
case ADV7511_REG_BKSV(4):
138
138
case ADV7511_REG_DDC_STATUS:
139
+
case ADV7511_REG_EDID_READ_CTRL:
139
140
case ADV7511_REG_BSTATUS(0):
140
141
case ADV7511_REG_BSTATUS(1):
141
142
case ADV7511_REG_CHIP_ID_HIGH:
···
363
362
{
364
363
adv7511->current_edid_segment = -1;
365
364
366
-
regmap_write(adv7511->regmap, ADV7511_REG_INT(0),
367
-
ADV7511_INT0_EDID_READY);
368
-
regmap_write(adv7511->regmap, ADV7511_REG_INT(1),
369
-
ADV7511_INT1_DDC_ERROR);
370
365
regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
371
366
ADV7511_POWER_POWER_DOWN, 0);
367
+
if (adv7511->i2c_main->irq) {
368
+
/*
369
+
* Documentation says the INT_ENABLE registers are reset in
370
+
* POWER_DOWN mode. My 7511w preserved the bits, however.
371
+
* Still, let's be safe and stick to the documentation.
372
+
*/
373
+
regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(0),
374
+
ADV7511_INT0_EDID_READY);
375
+
regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(1),
376
+
ADV7511_INT1_DDC_ERROR);
377
+
}
372
378
373
379
/*
374
-
* Per spec it is allowed to pulse the HDP signal to indicate that the
380
+
* Per spec it is allowed to pulse the HPD signal to indicate that the
375
381
* EDID information has changed. Some monitors do this when they wakeup
376
-
* from standby or are enabled. When the HDP goes low the adv7511 is
382
+
* from standby or are enabled. When the HPD goes low the adv7511 is
377
383
* reset and the outputs are disabled which might cause the monitor to
378
-
* go to standby again. To avoid this we ignore the HDP pin for the
384
+
* go to standby again. To avoid this we ignore the HPD pin for the
379
385
* first few seconds after enabling the output.
380
386
*/
381
387
regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2,
382
-
ADV7511_REG_POWER2_HDP_SRC_MASK,
383
-
ADV7511_REG_POWER2_HDP_SRC_NONE);
388
+
ADV7511_REG_POWER2_HPD_SRC_MASK,
389
+
ADV7511_REG_POWER2_HPD_SRC_NONE);
384
390
385
391
/*
386
392
* Most of the registers are reset during power down or when HPD is low.
···
421
413
if (ret < 0)
422
414
return false;
423
415
424
-
if (irq0 & ADV7511_INT0_HDP) {
416
+
if (irq0 & ADV7511_INT0_HPD) {
425
417
regmap_write(adv7511->regmap, ADV7511_REG_INT(0),
426
-
ADV7511_INT0_HDP);
418
+
ADV7511_INT0_HPD);
427
419
return true;
428
420
}
429
421
···
446
438
regmap_write(adv7511->regmap, ADV7511_REG_INT(0), irq0);
447
439
regmap_write(adv7511->regmap, ADV7511_REG_INT(1), irq1);
448
440
449
-
if (irq0 & ADV7511_INT0_HDP && adv7511->encoder)
441
+
if (irq0 & ADV7511_INT0_HPD && adv7511->encoder)
450
442
drm_helper_hpd_irq_event(adv7511->encoder->dev);
451
443
452
444
if (irq0 & ADV7511_INT0_EDID_READY || irq1 & ADV7511_INT1_DDC_ERROR) {
···
575
567
576
568
/* Reading the EDID only works if the device is powered */
577
569
if (!adv7511->powered) {
578
-
regmap_write(adv7511->regmap, ADV7511_REG_INT(0),
579
-
ADV7511_INT0_EDID_READY);
580
-
regmap_write(adv7511->regmap, ADV7511_REG_INT(1),
581
-
ADV7511_INT1_DDC_ERROR);
582
570
regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
583
571
ADV7511_POWER_POWER_DOWN, 0);
572
+
if (adv7511->i2c_main->irq) {
573
+
regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(0),
574
+
ADV7511_INT0_EDID_READY);
575
+
regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(1),
576
+
ADV7511_INT1_DDC_ERROR);
577
+
}
584
578
adv7511->current_edid_segment = -1;
585
579
}
586
580
···
648
638
if (adv7511->status == connector_status_connected)
649
639
status = connector_status_disconnected;
650
640
} else {
651
-
/* Renable HDP sensing */
641
+
/* Renable HPD sensing */
652
642
regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2,
653
-
ADV7511_REG_POWER2_HDP_SRC_MASK,
654
-
ADV7511_REG_POWER2_HDP_SRC_BOTH);
643
+
ADV7511_REG_POWER2_HPD_SRC_MASK,
644
+
ADV7511_REG_POWER2_HPD_SRC_BOTH);
655
645
}
656
646
657
647
adv7511->status = status;
+6
-6
drivers/gpu/drm/i2c/adv7511.h
+6
-6
drivers/gpu/drm/i2c/adv7511.h
···
90
90
#define ADV7511_CSC_ENABLE BIT(7)
91
91
#define ADV7511_CSC_UPDATE_MODE BIT(5)
92
92
93
-
#define ADV7511_INT0_HDP BIT(7)
93
+
#define ADV7511_INT0_HPD BIT(7)
94
94
#define ADV7511_INT0_VSYNC BIT(5)
95
95
#define ADV7511_INT0_AUDIO_FIFO_FULL BIT(4)
96
96
#define ADV7511_INT0_EDID_READY BIT(2)
···
157
157
#define ADV7511_PACKET_ENABLE_SPARE2 BIT(1)
158
158
#define ADV7511_PACKET_ENABLE_SPARE1 BIT(0)
159
159
160
-
#define ADV7511_REG_POWER2_HDP_SRC_MASK 0xc0
161
-
#define ADV7511_REG_POWER2_HDP_SRC_BOTH 0x00
162
-
#define ADV7511_REG_POWER2_HDP_SRC_HDP 0x40
163
-
#define ADV7511_REG_POWER2_HDP_SRC_CEC 0x80
164
-
#define ADV7511_REG_POWER2_HDP_SRC_NONE 0xc0
160
+
#define ADV7511_REG_POWER2_HPD_SRC_MASK 0xc0
161
+
#define ADV7511_REG_POWER2_HPD_SRC_BOTH 0x00
162
+
#define ADV7511_REG_POWER2_HPD_SRC_HPD 0x40
163
+
#define ADV7511_REG_POWER2_HPD_SRC_CEC 0x80
164
+
#define ADV7511_REG_POWER2_HPD_SRC_NONE 0xc0
165
165
#define ADV7511_REG_POWER2_TDMS_ENABLE BIT(4)
166
166
#define ADV7511_REG_POWER2_GATE_INPUT_CLK BIT(0)
167
167
-1
drivers/gpu/drm/i915/Kconfig
-1
drivers/gpu/drm/i915/Kconfig
+3
-1
drivers/gpu/drm/i915/i915_drv.c
+3
-1
drivers/gpu/drm/i915/i915_drv.c
···
501
501
WARN_ON(!IS_SKYLAKE(dev) &&
502
502
!IS_KABYLAKE(dev));
503
503
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
504
-
(id == INTEL_PCH_QEMU_DEVICE_ID_TYPE)) {
504
+
((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
505
+
pch->subsystem_vendor == 0x1af4 &&
506
+
pch->subsystem_device == 0x1100)) {
505
507
dev_priv->pch_type = intel_virt_detect_pch(dev);
506
508
} else
507
509
continue;
+22
-11
drivers/gpu/drm/i915/intel_display.c
+22
-11
drivers/gpu/drm/i915/intel_display.c
···
2946
2946
struct i915_vma *vma;
2947
2947
u64 offset;
2948
2948
2949
-
intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2949
+
intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2950
2950
intel_plane->base.state);
2951
2951
2952
2952
vma = i915_gem_obj_to_ggtt_view(obj, &view);
···
12075
12075
pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12076
12076
}
12077
12077
12078
-
/* Clamp bpp to 8 on screens without EDID 1.4 */
12079
-
if (connector->base.display_info.bpc == 0 && bpp > 24) {
12080
-
DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12081
-
bpp);
12082
-
pipe_config->pipe_bpp = 24;
12078
+
/* Clamp bpp to default limit on screens without EDID 1.4 */
12079
+
if (connector->base.display_info.bpc == 0) {
12080
+
int type = connector->base.connector_type;
12081
+
int clamp_bpp = 24;
12082
+
12083
+
/* Fall back to 18 bpp when DP sink capability is unknown. */
12084
+
if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12085
+
type == DRM_MODE_CONNECTOR_eDP)
12086
+
clamp_bpp = 18;
12087
+
12088
+
if (bpp > clamp_bpp) {
12089
+
DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12090
+
bpp, clamp_bpp);
12091
+
pipe_config->pipe_bpp = clamp_bpp;
12092
+
}
12083
12093
}
12084
12094
}
12085
12095
···
13893
13883
int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13894
13884
bool can_position = false;
13895
13885
13896
-
/* use scaler when colorkey is not required */
13897
-
if (INTEL_INFO(plane->dev)->gen >= 9 &&
13898
-
state->ckey.flags == I915_SET_COLORKEY_NONE) {
13899
-
min_scale = 1;
13900
-
max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13886
+
if (INTEL_INFO(plane->dev)->gen >= 9) {
13887
+
/* use scaler when colorkey is not required */
13888
+
if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13889
+
min_scale = 1;
13890
+
max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13891
+
}
13901
13892
can_position = true;
13902
13893
}
13903
13894
+1
drivers/gpu/drm/i915/intel_lrc.c
+1
drivers/gpu/drm/i915/intel_lrc.c
+2
drivers/gpu/drm/i915/intel_ringbuffer.c
+2
drivers/gpu/drm/i915/intel_ringbuffer.c
···
331
331
if (flush_domains) {
332
332
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
333
333
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
334
+
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
334
335
flags |= PIPE_CONTROL_FLUSH_ENABLE;
335
336
}
336
337
if (invalidate_domains) {
···
404
403
if (flush_domains) {
405
404
flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
406
405
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
406
+
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
407
407
flags |= PIPE_CONTROL_FLUSH_ENABLE;
408
408
}
409
409
if (invalidate_domains) {
+7
drivers/gpu/drm/radeon/radeon_object.c
+7
drivers/gpu/drm/radeon/radeon_object.c
···
33
33
#include <linux/slab.h>
34
34
#include <drm/drmP.h>
35
35
#include <drm/radeon_drm.h>
36
+
#include <drm/drm_cache.h>
36
37
#include "radeon.h"
37
38
#include "radeon_trace.h"
38
39
···
246
245
DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
247
246
"better performance thanks to write-combining\n");
248
247
bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
248
+
#else
249
+
/* For architectures that don't support WC memory,
250
+
* mask out the WC flag from the BO
251
+
*/
252
+
if (!drm_arch_can_wc_memory())
253
+
bo->flags &= ~RADEON_GEM_GTT_WC;
249
254
#endif
250
255
251
256
radeon_ttm_placement_from_domain(bo, domain);
+9
include/drm/drm_cache.h
+9
include/drm/drm_cache.h
···
35
35
36
36
void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
37
37
38
+
static inline bool drm_arch_can_wc_memory(void)
39
+
{
40
+
#if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE)
41
+
return false;
42
+
#else
43
+
return true;
44
+
#endif
45
+
}
46
+
38
47
#endif
+10
-15
include/drm/drm_dp_mst_helper.h
+10
-15
include/drm/drm_dp_mst_helper.h
···
44
44
/**
45
45
* struct drm_dp_mst_port - MST port
46
46
* @kref: reference count for this port.
47
-
* @guid_valid: for DP 1.2 devices if we have validated the GUID.
48
-
* @guid: guid for DP 1.2 device on this port.
49
47
* @port_num: port number
50
48
* @input: if this port is an input port.
51
49
* @mcs: message capability status - DP 1.2 spec.
···
67
69
*/
68
70
struct drm_dp_mst_port {
69
71
struct kref kref;
70
-
71
-
/* if dpcd 1.2 device is on this port - its GUID info */
72
-
bool guid_valid;
73
-
u8 guid[16];
74
72
75
73
u8 port_num;
76
74
bool input;
···
104
110
* @tx_slots: transmission slots for this device.
105
111
* @last_seqno: last sequence number used to talk to this.
106
112
* @link_address_sent: if a link address message has been sent to this device yet.
113
+
* @guid: guid for DP 1.2 branch device. port under this branch can be
114
+
* identified by port #.
107
115
*
108
116
* This structure represents an MST branch device, there is one
109
-
* primary branch device at the root, along with any others connected
110
-
* to downstream ports
117
+
* primary branch device at the root, along with any other branches connected
118
+
* to downstream port of parent branches.
111
119
*/
112
120
struct drm_dp_mst_branch {
113
121
struct kref kref;
···
128
132
struct drm_dp_sideband_msg_tx *tx_slots[2];
129
133
int last_seqno;
130
134
bool link_address_sent;
135
+
136
+
/* global unique identifier to identify branch devices */
137
+
u8 guid[16];
131
138
};
132
139
133
140
···
405
406
* @conn_base_id: DRM connector ID this mgr is connected to.
406
407
* @down_rep_recv: msg receiver state for down replies.
407
408
* @up_req_recv: msg receiver state for up requests.
408
-
* @lock: protects mst state, primary, guid, dpcd.
409
+
* @lock: protects mst state, primary, dpcd.
409
410
* @mst_state: if this manager is enabled for an MST capable port.
410
411
* @mst_primary: pointer to the primary branch device.
411
-
* @guid_valid: GUID valid for the primary branch device.
412
-
* @guid: GUID for primary port.
413
412
* @dpcd: cache of DPCD for primary port.
414
413
* @pbn_div: PBN to slots divisor.
415
414
*
···
429
432
struct drm_dp_sideband_msg_rx up_req_recv;
430
433
431
434
/* pointer to info about the initial MST device */
432
-
struct mutex lock; /* protects mst_state + primary + guid + dpcd */
435
+
struct mutex lock; /* protects mst_state + primary + dpcd */
433
436
434
437
bool mst_state;
435
438
struct drm_dp_mst_branch *mst_primary;
436
-
/* primary MST device GUID */
437
-
bool guid_valid;
438
-
u8 guid[16];
439
+
439
440
u8 dpcd[DP_RECEIVER_CAP_SIZE];
440
441
u8 sink_count;
441
442
int pbn_div;
+51
-2
include/drm/drm_fixed.h
+51
-2
include/drm/drm_fixed.h
···
73
73
#define DRM_FIXED_ONE (1ULL << DRM_FIXED_POINT)
74
74
#define DRM_FIXED_DECIMAL_MASK (DRM_FIXED_ONE - 1)
75
75
#define DRM_FIXED_DIGITS_MASK (~DRM_FIXED_DECIMAL_MASK)
76
+
#define DRM_FIXED_EPSILON 1LL
77
+
#define DRM_FIXED_ALMOST_ONE (DRM_FIXED_ONE - DRM_FIXED_EPSILON)
76
78
77
79
static inline s64 drm_int2fixp(int a)
78
80
{
79
81
return ((s64)a) << DRM_FIXED_POINT;
80
82
}
81
83
82
-
static inline int drm_fixp2int(int64_t a)
84
+
static inline int drm_fixp2int(s64 a)
83
85
{
84
86
return ((s64)a) >> DRM_FIXED_POINT;
85
87
}
86
88
87
-
static inline unsigned drm_fixp_msbset(int64_t a)
89
+
static inline int drm_fixp2int_ceil(s64 a)
90
+
{
91
+
if (a > 0)
92
+
return drm_fixp2int(a + DRM_FIXED_ALMOST_ONE);
93
+
else
94
+
return drm_fixp2int(a - DRM_FIXED_ALMOST_ONE);
95
+
}
96
+
97
+
static inline unsigned drm_fixp_msbset(s64 a)
88
98
{
89
99
unsigned shift, sign = (a >> 63) & 1;
90
100
···
144
134
return result >> (shift - DRM_FIXED_POINT);
145
135
146
136
return result;
137
+
}
138
+
139
+
static inline s64 drm_fixp_from_fraction(s64 a, s64 b)
140
+
{
141
+
s64 res;
142
+
bool a_neg = a < 0;
143
+
bool b_neg = b < 0;
144
+
u64 a_abs = a_neg ? -a : a;
145
+
u64 b_abs = b_neg ? -b : b;
146
+
u64 rem;
147
+
148
+
/* determine integer part */
149
+
u64 res_abs = div64_u64_rem(a_abs, b_abs, &rem);
150
+
151
+
/* determine fractional part */
152
+
{
153
+
u32 i = DRM_FIXED_POINT;
154
+
155
+
do {
156
+
rem <<= 1;
157
+
res_abs <<= 1;
158
+
if (rem >= b_abs) {
159
+
res_abs |= 1;
160
+
rem -= b_abs;
161
+
}
162
+
} while (--i != 0);
163
+
}
164
+
165
+
/* round up LSB */
166
+
{
167
+
u64 summand = (rem << 1) >= b_abs;
168
+
169
+
res_abs += summand;
170
+
}
171
+
172
+
res = (s64) res_abs;
173
+
if (a_neg ^ b_neg)
174
+
res = -res;
175
+
return res;
147
176
}
148
177
149
178
static inline s64 drm_fixp_exp(s64 x)