tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/msm/dpu: remove DSPP_SC7180_MASK

Stop declaring DPU_DSPP_PCC as a part of the DSPP features, use the
presence of the PCC sblk to check whether PCC is present in the hardware
or not.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655373/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-7-3b2085a07884@oss.qualcomm.com

authored by

Dmitry Baryshkov and committed by
Dmitry Baryshkov 9b2a5bff a150c904

+1 -73
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
··· 189 189 { 190 190 .name = "dspp_0", .id = DSPP_0, 191 191 .base = 0x54000, .len = 0x1800, 192 - .features = DSPP_SC7180_MASK, 193 192 .sblk = &sdm845_dspp_sblk, 194 193 }, { 195 194 .name = "dspp_1", .id = DSPP_1, 196 195 .base = 0x56000, .len = 0x1800, 197 - .features = DSPP_SC7180_MASK, 198 196 .sblk = &sdm845_dspp_sblk, 199 197 }, { 200 198 .name = "dspp_2", .id = DSPP_2, 201 199 .base = 0x58000, .len = 0x1800, 202 - .features = DSPP_SC7180_MASK, 203 200 .sblk = &sdm845_dspp_sblk, 204 201 }, { 205 202 .name = "dspp_3", .id = DSPP_3, 206 203 .base = 0x5a000, .len = 0x1800, 207 - .features = DSPP_SC7180_MASK, 208 204 .sblk = &sdm845_dspp_sblk, 209 205 }, 210 206 };
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h
··· 116 116 { 117 117 .name = "dspp_0", .id = DSPP_0, 118 118 .base = 0x54000, .len = 0x1800, 119 - .features = DSPP_SC7180_MASK, 120 119 .sblk = &msm8998_dspp_sblk, 121 120 }, 122 121 };
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h
··· 103 103 { 104 104 .name = "dspp_0", .id = DSPP_0, 105 105 .base = 0x54000, .len = 0x1800, 106 - .features = DSPP_SC7180_MASK, 107 106 .sblk = &msm8998_dspp_sblk, 108 107 }, 109 108 };
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h
··· 116 116 { 117 117 .name = "dspp_0", .id = DSPP_0, 118 118 .base = 0x54000, .len = 0x1800, 119 - .features = DSPP_SC7180_MASK, 120 119 .sblk = &msm8998_dspp_sblk, 121 120 }, 122 121 };
-2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h
··· 223 223 { 224 224 .name = "dspp_0", .id = DSPP_0, 225 225 .base = 0x54000, .len = 0x1800, 226 - .features = DSPP_SC7180_MASK, 227 226 .sblk = &msm8998_dspp_sblk, 228 227 }, { 229 228 .name = "dspp_1", .id = DSPP_1, 230 229 .base = 0x56000, .len = 0x1800, 231 - .features = DSPP_SC7180_MASK, 232 230 .sblk = &msm8998_dspp_sblk, 233 231 }, 234 232 };
-2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
··· 212 212 { 213 213 .name = "dspp_0", .id = DSPP_0, 214 214 .base = 0x54000, .len = 0x1800, 215 - .features = DSPP_SC7180_MASK, 216 215 .sblk = &msm8998_dspp_sblk, 217 216 }, { 218 217 .name = "dspp_1", .id = DSPP_1, 219 218 .base = 0x56000, .len = 0x1800, 220 - .features = DSPP_SC7180_MASK, 221 219 .sblk = &msm8998_dspp_sblk, 222 220 }, 223 221 };
-2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h
··· 183 183 { 184 184 .name = "dspp_0", .id = DSPP_0, 185 185 .base = 0x54000, .len = 0x1800, 186 - .features = DSPP_SC7180_MASK, 187 186 .sblk = &msm8998_dspp_sblk, 188 187 }, { 189 188 .name = "dspp_1", .id = DSPP_1, 190 189 .base = 0x56000, .len = 0x1800, 191 - .features = DSPP_SC7180_MASK, 192 190 .sblk = &msm8998_dspp_sblk, 193 191 }, 194 192 };
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h
··· 133 133 { 134 134 .name = "dspp_0", .id = DSPP_0, 135 135 .base = 0x54000, .len = 0x1800, 136 - .features = DSPP_SC7180_MASK, 137 136 .sblk = &msm8998_dspp_sblk, 138 137 }, 139 138 };
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
··· 170 170 { 171 171 .name = "dspp_0", .id = DSPP_0, 172 172 .base = 0x54000, .len = 0x1800, 173 - .features = DSPP_SC7180_MASK, 174 173 .sblk = &sdm845_dspp_sblk, 175 174 }, { 176 175 .name = "dspp_1", .id = DSPP_1, 177 176 .base = 0x56000, .len = 0x1800, 178 - .features = DSPP_SC7180_MASK, 179 177 .sblk = &sdm845_dspp_sblk, 180 178 }, { 181 179 .name = "dspp_2", .id = DSPP_2, 182 180 .base = 0x58000, .len = 0x1800, 183 - .features = DSPP_SC7180_MASK, 184 181 .sblk = &sdm845_dspp_sblk, 185 182 }, { 186 183 .name = "dspp_3", .id = DSPP_3, 187 184 .base = 0x5a000, .len = 0x1800, 188 - .features = DSPP_SC7180_MASK, 189 185 .sblk = &sdm845_dspp_sblk, 190 186 }, 191 187 };
-2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_1_sdm670.h
··· 103 103 { 104 104 .name = "dspp_0", .id = DSPP_0, 105 105 .base = 0x54000, .len = 0x1800, 106 - .features = DSPP_SC7180_MASK, 107 106 .sblk = &sdm845_dspp_sblk, 108 107 }, { 109 108 .name = "dspp_1", .id = DSPP_1, 110 109 .base = 0x56000, .len = 0x1800, 111 - .features = DSPP_SC7180_MASK, 112 110 .sblk = &sdm845_dspp_sblk, 113 111 }, 114 112 };
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
··· 193 193 { 194 194 .name = "dspp_0", .id = DSPP_0, 195 195 .base = 0x54000, .len = 0x1800, 196 - .features = DSPP_SC7180_MASK, 197 196 .sblk = &sdm845_dspp_sblk, 198 197 }, { 199 198 .name = "dspp_1", .id = DSPP_1, 200 199 .base = 0x56000, .len = 0x1800, 201 - .features = DSPP_SC7180_MASK, 202 200 .sblk = &sdm845_dspp_sblk, 203 201 }, { 204 202 .name = "dspp_2", .id = DSPP_2, 205 203 .base = 0x58000, .len = 0x1800, 206 - .features = DSPP_SC7180_MASK, 207 204 .sblk = &sdm845_dspp_sblk, 208 205 }, { 209 206 .name = "dspp_3", .id = DSPP_3, 210 207 .base = 0x5a000, .len = 0x1800, 211 - .features = DSPP_SC7180_MASK, 212 208 .sblk = &sdm845_dspp_sblk, 213 209 }, 214 210 };
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
··· 193 193 { 194 194 .name = "dspp_0", .id = DSPP_0, 195 195 .base = 0x54000, .len = 0x1800, 196 - .features = DSPP_SC7180_MASK, 197 196 .sblk = &sdm845_dspp_sblk, 198 197 }, { 199 198 .name = "dspp_1", .id = DSPP_1, 200 199 .base = 0x56000, .len = 0x1800, 201 - .features = DSPP_SC7180_MASK, 202 200 .sblk = &sdm845_dspp_sblk, 203 201 }, { 204 202 .name = "dspp_2", .id = DSPP_2, 205 203 .base = 0x58000, .len = 0x1800, 206 - .features = DSPP_SC7180_MASK, 207 204 .sblk = &sdm845_dspp_sblk, 208 205 }, { 209 206 .name = "dspp_3", .id = DSPP_3, 210 207 .base = 0x5a000, .len = 0x1800, 211 - .features = DSPP_SC7180_MASK, 212 208 .sblk = &sdm845_dspp_sblk, 213 209 }, 214 210 };
-2
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
··· 150 150 { 151 151 .name = "dspp_0", .id = DSPP_0, 152 152 .base = 0x54000, .len = 0x1800, 153 - .features = DSPP_SC7180_MASK, 154 153 .sblk = &sdm845_dspp_sblk, 155 154 }, { 156 155 .name = "dspp_1", .id = DSPP_1, 157 156 .base = 0x56000, .len = 0x1800, 158 - .features = DSPP_SC7180_MASK, 159 157 .sblk = &sdm845_dspp_sblk, 160 158 }, 161 159 };
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
··· 136 136 { 137 137 .name = "dspp_0", .id = DSPP_0, 138 138 .base = 0x54000, .len = 0x1800, 139 - .features = DSPP_SC7180_MASK, 140 139 .sblk = &sdm845_dspp_sblk, 141 140 }, 142 141 };
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
··· 117 117 { 118 118 .name = "dspp_0", .id = DSPP_0, 119 119 .base = 0x54000, .len = 0x1800, 120 - .features = DSPP_SC7180_MASK, 121 120 .sblk = &sdm845_dspp_sblk, 122 121 }, 123 122 };
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
··· 191 191 { 192 192 .name = "dspp_0", .id = DSPP_0, 193 193 .base = 0x54000, .len = 0x1800, 194 - .features = DSPP_SC7180_MASK, 195 194 .sblk = &sdm845_dspp_sblk, 196 195 }, { 197 196 .name = "dspp_1", .id = DSPP_1, 198 197 .base = 0x56000, .len = 0x1800, 199 - .features = DSPP_SC7180_MASK, 200 198 .sblk = &sdm845_dspp_sblk, 201 199 }, { 202 200 .name = "dspp_2", .id = DSPP_2, 203 201 .base = 0x58000, .len = 0x1800, 204 - .features = DSPP_SC7180_MASK, 205 202 .sblk = &sdm845_dspp_sblk, 206 203 }, { 207 204 .name = "dspp_3", .id = DSPP_3, 208 205 .base = 0x5a000, .len = 0x1800, 209 - .features = DSPP_SC7180_MASK, 210 206 .sblk = &sdm845_dspp_sblk, 211 207 }, 212 208 };
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
··· 106 106 { 107 107 .name = "dspp_0", .id = DSPP_0, 108 108 .base = 0x54000, .len = 0x1800, 109 - .features = DSPP_SC7180_MASK, 110 109 .sblk = &sdm845_dspp_sblk, 111 110 }, 112 111 };
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
··· 69 69 { 70 70 .name = "dspp_0", .id = DSPP_0, 71 71 .base = 0x54000, .len = 0x1800, 72 - .features = DSPP_SC7180_MASK, 73 72 .sblk = &sdm845_dspp_sblk, 74 73 }, 75 74 };
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
··· 115 115 { 116 116 .name = "dspp_0", .id = DSPP_0, 117 117 .base = 0x54000, .len = 0x1800, 118 - .features = DSPP_SC7180_MASK, 119 118 .sblk = &sdm845_dspp_sblk, 120 119 }, 121 120 };
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
··· 69 69 { 70 70 .name = "dspp_0", .id = DSPP_0, 71 71 .base = 0x54000, .len = 0x1800, 72 - .features = DSPP_SC7180_MASK, 73 72 .sblk = &sdm845_dspp_sblk, 74 73 }, 75 74 };
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
··· 71 71 { 72 72 .name = "dspp_0", .id = DSPP_0, 73 73 .base = 0x54000, .len = 0x1800, 74 - .features = DSPP_SC7180_MASK, 75 74 .sblk = &sdm845_dspp_sblk, 76 75 }, 77 76 };
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
··· 191 191 { 192 192 .name = "dspp_0", .id = DSPP_0, 193 193 .base = 0x54000, .len = 0x1800, 194 - .features = DSPP_SC7180_MASK, 195 194 .sblk = &sdm845_dspp_sblk, 196 195 }, { 197 196 .name = "dspp_1", .id = DSPP_1, 198 197 .base = 0x56000, .len = 0x1800, 199 - .features = DSPP_SC7180_MASK, 200 198 .sblk = &sdm845_dspp_sblk, 201 199 }, { 202 200 .name = "dspp_2", .id = DSPP_2, 203 201 .base = 0x58000, .len = 0x1800, 204 - .features = DSPP_SC7180_MASK, 205 202 .sblk = &sdm845_dspp_sblk, 206 203 }, { 207 204 .name = "dspp_3", .id = DSPP_3, 208 205 .base = 0x5a000, .len = 0x1800, 209 - .features = DSPP_SC7180_MASK, 210 206 .sblk = &sdm845_dspp_sblk, 211 207 }, 212 208 };
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
··· 117 117 { 118 118 .name = "dspp_0", .id = DSPP_0, 119 119 .base = 0x54000, .len = 0x1800, 120 - .features = DSPP_SC7180_MASK, 121 120 .sblk = &sdm845_dspp_sblk, 122 121 }, 123 122 };
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
··· 191 191 { 192 192 .name = "dspp_0", .id = DSPP_0, 193 193 .base = 0x54000, .len = 0x1800, 194 - .features = DSPP_SC7180_MASK, 195 194 .sblk = &sdm845_dspp_sblk, 196 195 }, { 197 196 .name = "dspp_1", .id = DSPP_1, 198 197 .base = 0x56000, .len = 0x1800, 199 - .features = DSPP_SC7180_MASK, 200 198 .sblk = &sdm845_dspp_sblk, 201 199 }, { 202 200 .name = "dspp_2", .id = DSPP_2, 203 201 .base = 0x58000, .len = 0x1800, 204 - .features = DSPP_SC7180_MASK, 205 202 .sblk = &sdm845_dspp_sblk, 206 203 }, { 207 204 .name = "dspp_3", .id = DSPP_3, 208 205 .base = 0x5a000, .len = 0x1800, 209 - .features = DSPP_SC7180_MASK, 210 206 .sblk = &sdm845_dspp_sblk, 211 207 }, 212 208 };
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
··· 192 192 { 193 193 .name = "dspp_0", .id = DSPP_0, 194 194 .base = 0x54000, .len = 0x1800, 195 - .features = DSPP_SC7180_MASK, 196 195 .sblk = &sdm845_dspp_sblk, 197 196 }, { 198 197 .name = "dspp_1", .id = DSPP_1, 199 198 .base = 0x56000, .len = 0x1800, 200 - .features = DSPP_SC7180_MASK, 201 199 .sblk = &sdm845_dspp_sblk, 202 200 }, { 203 201 .name = "dspp_2", .id = DSPP_2, 204 202 .base = 0x58000, .len = 0x1800, 205 - .features = DSPP_SC7180_MASK, 206 203 .sblk = &sdm845_dspp_sblk, 207 204 }, { 208 205 .name = "dspp_3", .id = DSPP_3, 209 206 .base = 0x5a000, .len = 0x1800, 210 - .features = DSPP_SC7180_MASK, 211 207 .sblk = &sdm845_dspp_sblk, 212 208 }, 213 209 };
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
··· 191 191 { 192 192 .name = "dspp_0", .id = DSPP_0, 193 193 .base = 0x54000, .len = 0x1800, 194 - .features = DSPP_SC7180_MASK, 195 194 .sblk = &sdm845_dspp_sblk, 196 195 }, { 197 196 .name = "dspp_1", .id = DSPP_1, 198 197 .base = 0x56000, .len = 0x1800, 199 - .features = DSPP_SC7180_MASK, 200 198 .sblk = &sdm845_dspp_sblk, 201 199 }, { 202 200 .name = "dspp_2", .id = DSPP_2, 203 201 .base = 0x58000, .len = 0x1800, 204 - .features = DSPP_SC7180_MASK, 205 202 .sblk = &sdm845_dspp_sblk, 206 203 }, { 207 204 .name = "dspp_3", .id = DSPP_3, 208 205 .base = 0x5a000, .len = 0x1800, 209 - .features = DSPP_SC7180_MASK, 210 206 .sblk = &sdm845_dspp_sblk, 211 207 }, 212 208 };
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
··· 189 189 { 190 190 .name = "dspp_0", .id = DSPP_0, 191 191 .base = 0x54000, .len = 0x1800, 192 - .features = DSPP_SC7180_MASK, 193 192 .sblk = &sdm845_dspp_sblk, 194 193 }, { 195 194 .name = "dspp_1", .id = DSPP_1, 196 195 .base = 0x56000, .len = 0x1800, 197 - .features = DSPP_SC7180_MASK, 198 196 .sblk = &sdm845_dspp_sblk, 199 197 }, { 200 198 .name = "dspp_2", .id = DSPP_2, 201 199 .base = 0x58000, .len = 0x1800, 202 - .features = DSPP_SC7180_MASK, 203 200 .sblk = &sdm845_dspp_sblk, 204 201 }, { 205 202 .name = "dspp_3", .id = DSPP_3, 206 203 .base = 0x5a000, .len = 0x1800, 207 - .features = DSPP_SC7180_MASK, 208 204 .sblk = &sdm845_dspp_sblk, 209 205 }, 210 206 };
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
··· 189 189 { 190 190 .name = "dspp_0", .id = DSPP_0, 191 191 .base = 0x54000, .len = 0x1800, 192 - .features = DSPP_SC7180_MASK, 193 192 .sblk = &sdm845_dspp_sblk, 194 193 }, { 195 194 .name = "dspp_1", .id = DSPP_1, 196 195 .base = 0x56000, .len = 0x1800, 197 - .features = DSPP_SC7180_MASK, 198 196 .sblk = &sdm845_dspp_sblk, 199 197 }, { 200 198 .name = "dspp_2", .id = DSPP_2, 201 199 .base = 0x58000, .len = 0x1800, 202 - .features = DSPP_SC7180_MASK, 203 200 .sblk = &sdm845_dspp_sblk, 204 201 }, { 205 202 .name = "dspp_3", .id = DSPP_3, 206 203 .base = 0x5a000, .len = 0x1800, 207 - .features = DSPP_SC7180_MASK, 208 204 .sblk = &sdm845_dspp_sblk, 209 205 }, 210 206 };
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
··· 188 188 { 189 189 .name = "dspp_0", .id = DSPP_0, 190 190 .base = 0x54000, .len = 0x1800, 191 - .features = DSPP_SC7180_MASK, 192 191 .sblk = &sdm845_dspp_sblk, 193 192 }, { 194 193 .name = "dspp_1", .id = DSPP_1, 195 194 .base = 0x56000, .len = 0x1800, 196 - .features = DSPP_SC7180_MASK, 197 195 .sblk = &sdm845_dspp_sblk, 198 196 }, { 199 197 .name = "dspp_2", .id = DSPP_2, 200 198 .base = 0x58000, .len = 0x1800, 201 - .features = DSPP_SC7180_MASK, 202 199 .sblk = &sdm845_dspp_sblk, 203 200 }, { 204 201 .name = "dspp_3", .id = DSPP_3, 205 202 .base = 0x5a000, .len = 0x1800, 206 - .features = DSPP_SC7180_MASK, 207 203 .sblk = &sdm845_dspp_sblk, 208 204 }, 209 205 };
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
··· 113 113 #define CTL_SM8550_MASK \ 114 114 (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) 115 115 116 - #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) 117 - 118 116 #define INTF_SC7180_MASK \ 119 117 (BIT(DPU_INTF_INPUT_CTRL) | \ 120 118 BIT(DPU_INTF_STATUS_SUPPORTED) | \
+1 -1
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.c
··· 90 90 /* Assign ops */ 91 91 c->idx = cfg->id; 92 92 c->cap = cfg; 93 - if (test_bit(DPU_DSPP_PCC, &c->cap->features)) 93 + if (c->cap->sblk->pcc.base) 94 94 c->ops.setup_pcc = dpu_setup_dspp_pcc; 95 95 96 96 return c;