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dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator
Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
authored by
Xingyu Wu
and committed by
Conor Dooley
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14b14a57
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Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml
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Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh7110-ispcrg
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reg:
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maxItems: 1
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clocks:
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items:
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- description: ISP Top core
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- description: ISP Top Axi
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- description: NOC ISP Bus
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- description: external DVP
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clock-names:
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items:
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- const: isp_top_core
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- const: isp_top_axi
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- const: noc_bus_isp_axi
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- const: dvp_clk
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resets:
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items:
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- description: ISP Top core
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- description: ISP Top Axi
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- description: NOC ISP Bus
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'#clock-cells':
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const: 1
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description:
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See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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'#reset-cells':
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const: 1
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description:
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See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
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power-domains:
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maxItems: 1
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description:
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ISP domain power
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- '#clock-cells'
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- '#reset-cells'
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/starfive,jh7110-crg.h>
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#include <dt-bindings/power/starfive,jh7110-pmu.h>
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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ispcrg: clock-controller@19810000 {
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compatible = "starfive,jh7110-ispcrg";
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reg = <0x19810000 0x10000>;
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clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
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<&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
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<&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
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<&dvp_clk>;
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clock-names = "isp_top_core", "isp_top_axi",
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"noc_bus_isp_axi", "dvp_clk";
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resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
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<&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
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<&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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power-domains = <&pwrc JH7110_PD_ISP>;
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};
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include/dt-bindings/clock/starfive,jh7110-crg.h
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include/dt-bindings/clock/starfive,jh7110-crg.h
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#define JH7110_STGCLK_END 29
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/* ISPCRG clocks */
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#define JH7110_ISPCLK_DOM4_APB_FUNC 0
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#define JH7110_ISPCLK_MIPI_RX0_PXL 1
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#define JH7110_ISPCLK_DVP_INV 2
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#define JH7110_ISPCLK_M31DPHY_CFG_IN 3
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#define JH7110_ISPCLK_M31DPHY_REF_IN 4
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#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5
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#define JH7110_ISPCLK_VIN_APB 6
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#define JH7110_ISPCLK_VIN_SYS 7
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#define JH7110_ISPCLK_VIN_PIXEL_IF0 8
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#define JH7110_ISPCLK_VIN_PIXEL_IF1 9
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#define JH7110_ISPCLK_VIN_PIXEL_IF2 10
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#define JH7110_ISPCLK_VIN_PIXEL_IF3 11
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#define JH7110_ISPCLK_VIN_P_AXI_WR 12
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#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13
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#define JH7110_ISPCLK_END 14
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#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
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include/dt-bindings/reset/starfive,jh7110-crg.h
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include/dt-bindings/reset/starfive,jh7110-crg.h
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#define JH7110_STGRST_END 23
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/* ISPCRG resets */
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#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0
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#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1
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#define JH7110_ISPRST_M31DPHY_HW 2
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#define JH7110_ISPRST_M31DPHY_B09_AON 3
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#define JH7110_ISPRST_VIN_APB 4
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#define JH7110_ISPRST_VIN_PIXEL_IF0 5
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#define JH7110_ISPRST_VIN_PIXEL_IF1 6
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#define JH7110_ISPRST_VIN_PIXEL_IF2 7
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#define JH7110_ISPRST_VIN_PIXEL_IF3 8
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#define JH7110_ISPRST_VIN_SYS 9
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#define JH7110_ISPRST_VIN_P_AXI_RD 10
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#define JH7110_ISPRST_VIN_P_AXI_WR 11
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#define JH7110_ISPRST_END 12
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#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */