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perf/x86/intel: Change macro GLOBAL_CTRL_EN_PERF_METRICS to BIT_ULL(48)

Macro GLOBAL_CTRL_EN_PERF_METRICS is defined to 48 instead of
BIT_ULL(48), it's inconsistent with other similar macros. This leads to
this macro is quite easily used wrongly since users thinks it's a
bit-mask just like other similar macros.

Thus change GLOBAL_CTRL_EN_PERF_METRICS to BIT_ULL(48) and eliminate
this potential misuse.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Tested-by: Yi Lai <yi1.lai@intel.com>
Link: https://lore.kernel.org/r/20250820023032.17128-6-dapeng1.mi@linux.intel.com

authored by

Dapeng Mi and committed by
Peter Zijlstra 9b3e1197 0c5caea7

+5 -5
+4 -4
arch/x86/events/intel/core.c
··· 5319 5319 0, x86_pmu_num_counters(&pmu->pmu), 0, 0); 5320 5320 5321 5321 if (pmu->intel_cap.perf_metrics) 5322 - pmu->intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 5322 + pmu->intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS; 5323 5323 else 5324 - pmu->intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 5324 + pmu->intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS; 5325 5325 5326 5326 intel_pmu_check_event_constraints(pmu->event_constraints, 5327 5327 pmu->cntr_mask64, ··· 5456 5456 rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities); 5457 5457 if (!perf_cap.perf_metrics) { 5458 5458 x86_pmu.intel_cap.perf_metrics = 0; 5459 - x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS); 5459 + x86_pmu.intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS; 5460 5460 } 5461 5461 } 5462 5462 ··· 7790 7790 } 7791 7791 7792 7792 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) 7793 - x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS; 7793 + x86_pmu.intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS; 7794 7794 7795 7795 if (x86_pmu.intel_cap.pebs_timing_info) 7796 7796 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY;
+1 -1
arch/x86/include/asm/perf_event.h
··· 430 430 #define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT) 431 431 #define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48 432 432 433 - #define GLOBAL_CTRL_EN_PERF_METRICS 48 433 + #define GLOBAL_CTRL_EN_PERF_METRICS BIT_ULL(48) 434 434 /* 435 435 * We model guest LBR event tracing as another fixed-mode PMC like BTS. 436 436 *