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ASoC: rt722: fix pop noise at the beginning of DMIC recording

This patch added the PDE status check which makes sure the PDE transition is done.
It will decrease the pop noise at the beginning of DMIC recording.

Signed-off-by: Shuming Fan <shumingf@realtek.com>
Link: https://patch.msgid.link/20250416092547.737879-1-shumingf@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Shuming Fan and committed by
Mark Brown 9b62b7a6 7ed50dc5

+46
+12
sound/soc/codecs/rt722-sdca-sdw.c
··· 43 43 RT722_SDCA_CTL_FU_MUTE, CH_R): 44 44 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 45 45 RT722_SDCA_CTL_REQ_POWER_STATE, 0): 46 + case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 47 + RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 46 48 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 47 49 RT722_SDCA_CTL_REQ_POWER_STATE, 0): 50 + case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 51 + RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 48 52 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, 49 53 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): 50 54 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, ··· 61 57 RT722_SDCA_CTL_VENDOR_DEF, 0): 62 58 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 63 59 RT722_SDCA_CTL_REQ_POWER_STATE, 0): 60 + case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 61 + RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 64 62 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 65 63 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, 66 64 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): ··· 78 72 RT722_SDCA_CTL_VENDOR_DEF, CH_08): 79 73 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 80 74 RT722_SDCA_CTL_REQ_POWER_STATE, 0): 75 + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 76 + RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 81 77 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 82 78 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, 83 79 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0): ··· 162 154 case 0x2f01: 163 155 case 0x2f54: 164 156 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 157 + case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 158 + case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 165 159 case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE, 166 160 0): 167 161 case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 162 + case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 168 163 case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 169 164 0) ... SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, 170 165 RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0): 171 166 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0): 167 + case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0): 172 168 case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2: 173 169 case 0x2000000: 174 170 case 0x200000d:
+33
sound/soc/codecs/rt722-sdca.c
··· 842 842 case SND_SOC_DAPM_POST_PMU: 843 843 rt722->fu1e_dapm_mute = false; 844 844 rt722_sdca_set_fu1e_capture_ctl(rt722); 845 + usleep_range(150000, 160000); 845 846 break; 846 847 case SND_SOC_DAPM_PRE_PMD: 847 848 rt722->fu1e_dapm_mute = true; ··· 872 871 return 0; 873 872 } 874 873 874 + static void rt722_pde_transition_delay(struct rt722_sdca_priv *rt722, unsigned char func, 875 + unsigned char entity, unsigned char ps) 876 + { 877 + unsigned int delay = 1000, val; 878 + 879 + pm_runtime_mark_last_busy(&rt722->slave->dev); 880 + 881 + /* waiting for Actual PDE becomes to PS0/PS3 */ 882 + while (delay) { 883 + regmap_read(rt722->regmap, 884 + SDW_SDCA_CTL(func, entity, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val); 885 + if (val == ps) 886 + break; 887 + 888 + usleep_range(1000, 1500); 889 + delay--; 890 + } 891 + if (!delay) { 892 + dev_warn(&rt722->slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0"); 893 + } 894 + } 895 + 875 896 static int rt722_sdca_pde47_event(struct snd_soc_dapm_widget *w, 876 897 struct snd_kcontrol *kcontrol, int event) 877 898 { ··· 907 884 regmap_write(rt722->regmap, 908 885 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 909 886 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 887 + rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, ps0); 910 888 break; 911 889 case SND_SOC_DAPM_PRE_PMD: 912 890 regmap_write(rt722->regmap, 913 891 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, 914 892 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 893 + rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, ps3); 915 894 break; 916 895 } 917 896 return 0; ··· 932 907 regmap_write(rt722->regmap, 933 908 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 934 909 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 910 + rt722_pde_transition_delay(rt722, FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, ps0); 935 911 break; 936 912 case SND_SOC_DAPM_PRE_PMD: 937 913 regmap_write(rt722->regmap, 938 914 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, 939 915 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 916 + rt722_pde_transition_delay(rt722, FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, ps3); 940 917 break; 941 918 } 942 919 return 0; ··· 957 930 regmap_write(rt722->regmap, 958 931 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 959 932 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 933 + rt722_pde_transition_delay(rt722, FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, ps0); 960 934 break; 961 935 case SND_SOC_DAPM_PRE_PMD: 962 936 regmap_write(rt722->regmap, 963 937 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, 964 938 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 939 + rt722_pde_transition_delay(rt722, FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, ps3); 965 940 break; 966 941 } 967 942 return 0; ··· 982 953 regmap_write(rt722->regmap, 983 954 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 984 955 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0); 956 + rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, ps0); 985 957 break; 986 958 case SND_SOC_DAPM_PRE_PMD: 987 959 regmap_write(rt722->regmap, 988 960 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, 989 961 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3); 962 + rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, ps3); 990 963 break; 991 964 } 992 965 return 0; ··· 1374 1343 RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01); 1375 1344 /* Fine tune PDE2A latency */ 1376 1345 regmap_write(rt722->regmap, 0x2f5c, 0x25); 1346 + /* PHYtiming TDZ/TZD control */ 1347 + regmap_write(rt722->regmap, 0x2f03, 0x06); 1377 1348 1378 1349 /* clear flag */ 1379 1350 regmap_write(rt722->regmap,
+1
sound/soc/codecs/rt722-sdca.h
··· 199 199 #define RT722_SDCA_CTL_VENDOR_DEF 0x30 200 200 #define RT722_SDCA_CTL_FU_CH_GAIN 0x0b 201 201 #define RT722_SDCA_CTL_FUNC_STATUS 0x10 202 + #define RT722_SDCA_CTL_ACTUAL_POWER_STATE 0x10 202 203 203 204 /* RT722 SDCA channel */ 204 205 #define CH_L 0x01