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phy: exynos5-usbdrd: use GENMASK and FIELD_PREP for Exynos5 PHY registers

Most Exynos850 and Exynos9 (GS101) DRD PHY registers use GENMASK for masks
and FIELD_PREP for writing values to registers.

Rewrite the register definitions which don't follow this approach to follow
it as much as possible. This patch doesn't introduce any fixes or
functional changes, it's merely an attempt to introduce some uniformity and
consistency in the driver code.

The CRPORT SuperSpeed control registers have been exempted from this
change. Since the writing of register values do not require any masking
operations, implementing it would unnecessarily complicate things.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Link: https://lore.kernel.org/r/20250410-exynos7870-usbphy-v2-1-2eb005987455@disroot.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Kaustabh Chakraborty and committed by
Vinod Koul 9b6662a0 070d5462

+75 -72
+75 -72
drivers/phy/samsung/phy-exynos5-usbdrd.c
··· 39 39 /* Exynos5: USB 3.0 DRD PHY registers */ 40 40 #define EXYNOS5_DRD_LINKSYSTEM 0x04 41 41 #define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27) 42 - #define LINKSYSTEM_FLADJ_MASK (0x3f << 1) 43 - #define LINKSYSTEM_FLADJ(_x) ((_x) << 1) 42 + #define LINKSYSTEM_FLADJ GENMASK(6, 1) 44 43 45 44 #define EXYNOS5_DRD_PHYUTMI 0x08 46 45 #define PHYUTMI_OTGDISABLE BIT(6) ··· 50 51 51 52 #define EXYNOS5_DRD_PHYCLKRST 0x10 52 53 #define PHYCLKRST_EN_UTMISUSPEND BIT(31) 53 - #define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23) 54 - #define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23) 55 - #define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21) 56 - #define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21) 54 + #define PHYCLKRST_SSC_REFCLKSEL GENMASK(30, 23) 55 + #define PHYCLKRST_SSC_RANGE GENMASK(22, 21) 57 56 #define PHYCLKRST_SSC_EN BIT(20) 58 57 #define PHYCLKRST_REF_SSP_EN BIT(19) 59 58 #define PHYCLKRST_REF_CLKDIV2 BIT(18) 60 - #define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11) 61 - #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11) 62 - #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11) 63 - #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11) 64 - #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11) 65 - #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11) 66 - #define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8) 67 - #define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5) 68 - #define PHYCLKRST_FSEL(_x) ((_x) << 5) 69 - #define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5) 70 - #define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5) 71 - #define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5) 72 - #define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5) 59 + #define PHYCLKRST_MPLL_MULTIPLIER GENMASK(17, 11) 60 + #define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF 0x19 61 + #define PHYCLKRST_MPLL_MULTIPLIER_50M_REF 0x32 62 + #define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF 0x68 63 + #define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF 0x7d 64 + #define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF 0x02 65 + #define PHYCLKRST_FSEL_PIPE GENMASK(10, 8) 66 + #define PHYCLKRST_FSEL_UTMI GENMASK(7, 5) 67 + #define PHYCLKRST_FSEL_PAD_100MHZ 0x27 68 + #define PHYCLKRST_FSEL_PAD_24MHZ 0x2a 69 + #define PHYCLKRST_FSEL_PAD_20MHZ 0x31 70 + #define PHYCLKRST_FSEL_PAD_19_2MHZ 0x38 73 71 #define PHYCLKRST_RETENABLEN BIT(4) 74 - #define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2) 75 - #define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2) 76 - #define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2) 72 + #define PHYCLKRST_REFCLKSEL GENMASK(3, 2) 73 + #define PHYCLKRST_REFCLKSEL_PAD_REFCLK 0x2 74 + #define PHYCLKRST_REFCLKSEL_EXT_REFCLK 0x3 77 75 #define PHYCLKRST_PORTRESET BIT(1) 78 76 #define PHYCLKRST_COMMONONN BIT(0) 79 77 ··· 79 83 #define PHYREG0_SSC_RANGE BIT(20) 80 84 #define PHYREG0_CR_WRITE BIT(19) 81 85 #define PHYREG0_CR_READ BIT(18) 82 - #define PHYREG0_CR_DATA_IN(_x) ((_x) << 2) 86 + #define PHYREG0_CR_DATA_IN GENMASK(17, 2) 83 87 #define PHYREG0_CR_CAP_DATA BIT(1) 84 88 #define PHYREG0_CR_CAP_ADDR BIT(0) 85 89 86 90 #define EXYNOS5_DRD_PHYREG1 0x18 87 - #define PHYREG1_CR_DATA_OUT(_x) ((_x) << 1) 91 + #define PHYREG0_CR_DATA_OUT GENMASK(16, 1) 88 92 #define PHYREG1_CR_ACK BIT(0) 89 93 90 94 #define EXYNOS5_DRD_PHYPARAM0 0x1c 91 95 #define PHYPARAM0_REF_USE_PAD BIT(31) 92 - #define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26) 93 - #define PHYPARAM0_REF_LOSLEVEL (0x9 << 26) 96 + #define PHYPARAM0_REF_LOSLEVEL GENMASK(30, 26) 97 + #define PHYPARAM0_REF_LOSLEVEL_VAL 0x9 94 98 95 99 #define EXYNOS5_DRD_PHYPARAM1 0x20 96 - #define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0) 97 - #define PHYPARAM1_PCS_TXDEEMPH (0x1c) 100 + #define PHYPARAM1_PCS_TXDEEMPH GENMASK(4, 0) 101 + #define PHYPARAM1_PCS_TXDEEMPH_VAL 0x1c 98 102 99 103 #define EXYNOS5_DRD_PHYTERM 0x24 100 104 ··· 136 140 #define LINKCTRL_FORCE_PHYSTATUS BIT(17) 137 141 #define LINKCTRL_FORCE_PIPE_EN BIT(16) 138 142 #define LINKCTRL_FORCE_QACT BIT(8) 139 - #define LINKCTRL_BUS_FILTER_BYPASS(_x) ((_x) << 4) 143 + #define LINKCTRL_BUS_FILTER_BYPASS GENMASK(7, 4) 140 144 141 145 #define EXYNOS850_DRD_LINKPORT 0x08 142 146 #define LINKPORT_HOST_NUM_U3 GENMASK(19, 16) ··· 493 497 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 494 498 495 499 /* Use EXTREFCLK as ref clock */ 496 - reg &= ~PHYCLKRST_REFCLKSEL_MASK; 497 - reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK; 500 + reg &= ~PHYCLKRST_REFCLKSEL; 501 + reg |= FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL, 502 + PHYCLKRST_REFCLKSEL_EXT_REFCLK); 498 503 499 504 /* FSEL settings corresponding to reference clock */ 500 - reg &= ~(PHYCLKRST_FSEL_PIPE_MASK | 501 - PHYCLKRST_MPLL_MULTIPLIER_MASK | 502 - PHYCLKRST_SSC_REFCLKSEL_MASK); 505 + reg &= ~(PHYCLKRST_FSEL_PIPE | 506 + PHYCLKRST_MPLL_MULTIPLIER | 507 + PHYCLKRST_SSC_REFCLKSEL); 503 508 switch (phy_drd->extrefclk) { 504 509 case EXYNOS5_FSEL_50MHZ: 505 - reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF | 506 - PHYCLKRST_SSC_REFCLKSEL(0x00)); 510 + reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x00) | 511 + FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, 512 + PHYCLKRST_MPLL_MULTIPLIER_50M_REF)); 507 513 break; 508 514 case EXYNOS5_FSEL_24MHZ: 509 - reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF | 510 - PHYCLKRST_SSC_REFCLKSEL(0x88)); 515 + reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x88) | 516 + FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, 517 + PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF)); 511 518 break; 512 519 case EXYNOS5_FSEL_20MHZ: 513 - reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF | 514 - PHYCLKRST_SSC_REFCLKSEL(0x00)); 520 + reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x00) | 521 + FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, 522 + PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF)); 515 523 break; 516 524 case EXYNOS5_FSEL_19MHZ2: 517 - reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF | 518 - PHYCLKRST_SSC_REFCLKSEL(0x88)); 525 + reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x88) | 526 + FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, 527 + PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF)); 519 528 break; 520 529 default: 521 530 dev_dbg(phy_drd->dev, "unsupported ref clk\n"); ··· 543 542 /* restore any previous reference clock settings */ 544 543 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 545 544 546 - reg &= ~PHYCLKRST_REFCLKSEL_MASK; 547 - reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK; 545 + reg &= ~PHYCLKRST_REFCLKSEL; 546 + reg |= FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL, 547 + PHYCLKRST_REFCLKSEL_EXT_REFCLK); 548 548 549 - reg &= ~(PHYCLKRST_FSEL_UTMI_MASK | 550 - PHYCLKRST_MPLL_MULTIPLIER_MASK | 551 - PHYCLKRST_SSC_REFCLKSEL_MASK); 552 - reg |= PHYCLKRST_FSEL(phy_drd->extrefclk); 549 + reg &= ~(PHYCLKRST_FSEL_UTMI | 550 + PHYCLKRST_MPLL_MULTIPLIER | 551 + PHYCLKRST_SSC_REFCLKSEL); 552 + reg |= FIELD_PREP(PHYCLKRST_FSEL_UTMI, phy_drd->extrefclk); 553 553 554 554 return reg; 555 555 } ··· 600 598 601 599 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); 602 600 /* Set Tx De-Emphasis level */ 603 - reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK; 604 - reg |= PHYPARAM1_PCS_TXDEEMPH; 601 + reg &= ~PHYPARAM1_PCS_TXDEEMPH; 602 + reg |= FIELD_PREP_CONST(PHYPARAM1_PCS_TXDEEMPH, 603 + PHYPARAM1_PCS_TXDEEMPH_VAL); 605 604 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); 606 605 607 606 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); ··· 623 620 624 621 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); 625 622 reg &= ~SECPMACTL_PMA_REF_FREQ_SEL; 626 - reg |= FIELD_PREP(SECPMACTL_PMA_REF_FREQ_SEL, 1); 623 + reg |= FIELD_PREP_CONST(SECPMACTL_PMA_REF_FREQ_SEL, 1); 627 624 /* SFR reset */ 628 625 reg |= (SECPMACTL_PMA_LOW_PWR | SECPMACTL_PMA_APB_SW_RST); 629 626 reg &= ~(SECPMACTL_PMA_ROPLL_REF_CLK_SEL | ··· 752 749 753 750 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); 754 751 /* Set Loss-of-Signal Detector sensitivity */ 755 - reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK; 756 - reg |= PHYPARAM0_REF_LOSLEVEL; 752 + reg &= ~PHYPARAM0_REF_LOSLEVEL; 753 + reg |= FIELD_PREP_CONST(PHYPARAM0_REF_LOSLEVEL, 754 + PHYPARAM0_REF_LOSLEVEL_VAL); 757 755 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); 758 756 759 757 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); 760 758 /* Set Tx De-Emphasis level */ 761 - reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK; 762 - reg |= PHYPARAM1_PCS_TXDEEMPH; 759 + reg &= ~PHYPARAM1_PCS_TXDEEMPH; 760 + reg |= FIELD_PREP_CONST(PHYPARAM1_PCS_TXDEEMPH, 761 + PHYPARAM1_PCS_TXDEEMPH_VAL); 763 762 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); 764 763 765 764 /* UTMI Power Control */ ··· 792 787 * See xHCI 1.0 spec, 5.2.4 793 788 */ 794 789 reg = LINKSYSTEM_XHCI_VERSION_CONTROL | 795 - LINKSYSTEM_FLADJ(0x20); 790 + FIELD_PREP_CONST(LINKSYSTEM_FLADJ, 0x20); 796 791 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); 797 792 798 793 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); ··· 951 946 static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd, 952 947 u32 addr, u32 data) 953 948 { 949 + u32 val; 954 950 int ret; 955 951 956 952 /* Write Address */ 957 - writel(PHYREG0_CR_DATA_IN(addr), 958 - phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); 959 - ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr), 960 - PHYREG0_CR_CAP_ADDR); 953 + val = FIELD_PREP(PHYREG0_CR_DATA_IN, addr); 954 + writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); 955 + ret = crport_handshake(phy_drd, val, PHYREG0_CR_CAP_ADDR); 961 956 if (ret) 962 957 return ret; 963 958 964 959 /* Write Data */ 965 - writel(PHYREG0_CR_DATA_IN(data), 966 - phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); 967 - ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data), 968 - PHYREG0_CR_CAP_DATA); 960 + val = FIELD_PREP(PHYREG0_CR_DATA_IN, data); 961 + writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); 962 + ret = crport_handshake(phy_drd, val, PHYREG0_CR_CAP_DATA); 969 963 if (ret) 970 964 return ret; 971 965 972 - ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data), 973 - PHYREG0_CR_WRITE); 966 + ret = crport_handshake(phy_drd, val, PHYREG0_CR_WRITE); 974 967 975 968 return ret; 976 969 } ··· 1137 1134 1138 1135 /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */ 1139 1136 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); 1140 - reg |= LINKCTRL_BUS_FILTER_BYPASS(0xf); 1137 + reg |= FIELD_PREP_CONST(LINKCTRL_BUS_FILTER_BYPASS, 0xf); 1141 1138 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); 1142 1139 1143 1140 if (!phy_drd->sw) { ··· 1154 1151 reg &= ~SSPPLLCTL_FSEL; 1155 1152 switch (phy_drd->extrefclk) { 1156 1153 case EXYNOS5_FSEL_50MHZ: 1157 - reg |= FIELD_PREP(SSPPLLCTL_FSEL, 7); 1154 + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7); 1158 1155 break; 1159 1156 case EXYNOS5_FSEL_26MHZ: 1160 - reg |= FIELD_PREP(SSPPLLCTL_FSEL, 6); 1157 + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6); 1161 1158 break; 1162 1159 case EXYNOS5_FSEL_24MHZ: 1163 - reg |= FIELD_PREP(SSPPLLCTL_FSEL, 2); 1160 + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2); 1164 1161 break; 1165 1162 case EXYNOS5_FSEL_20MHZ: 1166 - reg |= FIELD_PREP(SSPPLLCTL_FSEL, 1); 1163 + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1); 1167 1164 break; 1168 1165 case EXYNOS5_FSEL_19MHZ2: 1169 - reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0); 1166 + reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0); 1170 1167 break; 1171 1168 default: 1172 1169 dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n",