Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2018-11-23' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"Regular drm fixes:
amdgpu:
- Vega20 fixes
- firmware loading fix
- panel display fix
- override fix
i915:
- Sandybridge lockup fix
- fastboot DSI panel fix
- GPU hang on Broxton
- GPU reloc fixes on pineview/bearlake
ast:
- screen blurring fix
- cursor appearance fix
udmabuf:
- mmap fix
vc4:
- NULL deref fix
- async cursor update fix
All seems pretty normal at this stage"
* tag 'drm-fixes-2018-11-23' of git://anongit.freedesktop.org/drm/drm:
drm/ast: fixed cursor may disappear sometimes
drm/ast: change resolution may cause screen blurred
drm/i915: Add rotation readout for plane initial config
drm/i915: Force a LUT update in intel_initial_commit()
drm/fb-helper: Blacklist writeback when adding connectors to fbdev
drm/i915: Write GPU relocs harder with gen3
drm/amdgpu: Enable HDP memory light sleep
drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture
drm/amd/pp: handle negative values when reading OD
drm/amdgpu: Add missing firmware entry for HAINAN
drm/amd/powerplay: disable Vega20 DS related features
drm/amdgpu: Fix oops when pp_funcs->switch_power_profile is unset
drm/i915: Disable LP3 watermarks on all SNB machines
drm/ast: Remove existing framebuffers before loading driver
udmabuf: set read/write flag when exporting
drm/amd/display: Support amdgpu "max bpc" connector property (v2)
drm/amdgpu: Add amdgpu "max bpc" connector property (v2)
drm/vc4: Set ->legacy_cursor_update to false when doing non-async updates
drm/vc4: Fix NULL pointer dereference in the async update path
+273
-63
+1
drivers/dma-buf/udmabuf.c
+1
drivers/dma-buf/udmabuf.c
+5
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+5
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
···
501
501
{
502
502
struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
503
503
504
-
amdgpu_dpm_switch_power_profile(adev,
505
-
PP_SMC_POWER_PROFILE_COMPUTE, !idle);
504
+
if (adev->powerplay.pp_funcs &&
505
+
adev->powerplay.pp_funcs->switch_power_profile)
506
+
amdgpu_dpm_switch_power_profile(adev,
507
+
PP_SMC_POWER_PROFILE_COMPUTE,
508
+
!idle);
506
509
}
507
510
508
511
bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
+7
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+7
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
···
626
626
"dither",
627
627
amdgpu_dither_enum_list, sz);
628
628
629
+
if (amdgpu_device_has_dc_support(adev)) {
630
+
adev->mode_info.max_bpc_property =
631
+
drm_property_create_range(adev->ddev, 0, "max bpc", 8, 16);
632
+
if (!adev->mode_info.max_bpc_property)
633
+
return -ENOMEM;
634
+
}
635
+
629
636
return 0;
630
637
}
631
638
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
···
339
339
struct drm_property *audio_property;
340
340
/* FMT dithering */
341
341
struct drm_property *dither_property;
342
+
/* maximum number of bits per channel for monitor color */
343
+
struct drm_property *max_bpc_property;
342
344
/* hardcoded DFP edid from BIOS */
343
345
struct edid *bios_hardcoded_edid;
344
346
int bios_hardcoded_edid_size;
+1
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+1
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+32
-7
drivers/gpu/drm/amd/amdgpu/soc15.c
+32
-7
drivers/gpu/drm/amd/amdgpu/soc15.c
···
65
65
#define mmMP0_MISC_LIGHT_SLEEP_CTRL 0x01ba
66
66
#define mmMP0_MISC_LIGHT_SLEEP_CTRL_BASE_IDX 0
67
67
68
+
/* for Vega20 register name change */
69
+
#define mmHDP_MEM_POWER_CTRL 0x00d4
70
+
#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK 0x00000001L
71
+
#define HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK 0x00000002L
72
+
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK 0x00010000L
73
+
#define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L
74
+
#define mmHDP_MEM_POWER_CTRL_BASE_IDX 0
68
75
/*
69
76
* Indirect registers accessor
70
77
*/
···
877
870
{
878
871
uint32_t def, data;
879
872
880
-
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
873
+
if (adev->asic_type == CHIP_VEGA20) {
874
+
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
881
875
882
-
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
883
-
data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
884
-
else
885
-
data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
876
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
877
+
data |= HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
878
+
HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
879
+
HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
880
+
HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK;
881
+
else
882
+
data &= ~(HDP_MEM_POWER_CTRL__IPH_MEM_POWER_CTRL_EN_MASK |
883
+
HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK |
884
+
HDP_MEM_POWER_CTRL__RC_MEM_POWER_CTRL_EN_MASK |
885
+
HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK);
886
886
887
-
if (def != data)
888
-
WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
887
+
if (def != data)
888
+
WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);
889
+
} else {
890
+
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
891
+
892
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
893
+
data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
894
+
else
895
+
data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
896
+
897
+
if (def != data)
898
+
WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);
899
+
}
889
900
}
890
901
891
902
static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable)
+16
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+16
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
2358
2358
static enum dc_color_depth
2359
2359
convert_color_depth_from_display_info(const struct drm_connector *connector)
2360
2360
{
2361
+
struct dm_connector_state *dm_conn_state =
2362
+
to_dm_connector_state(connector->state);
2361
2363
uint32_t bpc = connector->display_info.bpc;
2364
+
2365
+
/* TODO: Remove this when there's support for max_bpc in drm */
2366
+
if (dm_conn_state && bpc > dm_conn_state->max_bpc)
2367
+
/* Round down to nearest even number. */
2368
+
bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1);
2362
2369
2363
2370
switch (bpc) {
2364
2371
case 0:
···
2950
2943
} else if (property == adev->mode_info.underscan_property) {
2951
2944
dm_new_state->underscan_enable = val;
2952
2945
ret = 0;
2946
+
} else if (property == adev->mode_info.max_bpc_property) {
2947
+
dm_new_state->max_bpc = val;
2948
+
ret = 0;
2953
2949
}
2954
2950
2955
2951
return ret;
···
2994
2984
ret = 0;
2995
2985
} else if (property == adev->mode_info.underscan_property) {
2996
2986
*val = dm_state->underscan_enable;
2987
+
ret = 0;
2988
+
} else if (property == adev->mode_info.max_bpc_property) {
2989
+
*val = dm_state->max_bpc;
2997
2990
ret = 0;
2998
2991
}
2999
2992
return ret;
···
3807
3794
0);
3808
3795
drm_object_attach_property(&aconnector->base.base,
3809
3796
adev->mode_info.underscan_vborder_property,
3797
+
0);
3798
+
drm_object_attach_property(&aconnector->base.base,
3799
+
adev->mode_info.max_bpc_property,
3810
3800
0);
3811
3801
3812
3802
}
+1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+10
-10
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+10
-10
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
···
4525
4525
struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
4526
4526
struct smu7_single_dpm_table *golden_sclk_table =
4527
4527
&(data->golden_dpm_table.sclk_table);
4528
-
int value;
4528
+
int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
4529
+
int golden_value = golden_sclk_table->dpm_levels
4530
+
[golden_sclk_table->count - 1].value;
4529
4531
4530
-
value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
4531
-
golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
4532
-
100 /
4533
-
golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
4532
+
value -= golden_value;
4533
+
value = DIV_ROUND_UP(value * 100, golden_value);
4534
4534
4535
4535
return value;
4536
4536
}
···
4567
4567
struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
4568
4568
struct smu7_single_dpm_table *golden_mclk_table =
4569
4569
&(data->golden_dpm_table.mclk_table);
4570
-
int value;
4570
+
int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
4571
+
int golden_value = golden_mclk_table->dpm_levels
4572
+
[golden_mclk_table->count - 1].value;
4571
4573
4572
-
value = (mclk_table->dpm_levels[mclk_table->count - 1].value -
4573
-
golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) *
4574
-
100 /
4575
-
golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value;
4574
+
value -= golden_value;
4575
+
value = DIV_ROUND_UP(value * 100, golden_value);
4576
4576
4577
4577
return value;
4578
4578
}
+10
-15
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+10
-15
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
···
4522
4522
struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
4523
4523
struct vega10_single_dpm_table *golden_sclk_table =
4524
4524
&(data->golden_dpm_table.gfx_table);
4525
-
int value;
4526
-
4527
-
value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
4528
-
golden_sclk_table->dpm_levels
4529
-
[golden_sclk_table->count - 1].value) *
4530
-
100 /
4531
-
golden_sclk_table->dpm_levels
4525
+
int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
4526
+
int golden_value = golden_sclk_table->dpm_levels
4532
4527
[golden_sclk_table->count - 1].value;
4528
+
4529
+
value -= golden_value;
4530
+
value = DIV_ROUND_UP(value * 100, golden_value);
4533
4531
4534
4532
return value;
4535
4533
}
···
4573
4575
struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
4574
4576
struct vega10_single_dpm_table *golden_mclk_table =
4575
4577
&(data->golden_dpm_table.mem_table);
4576
-
int value;
4577
-
4578
-
value = (mclk_table->dpm_levels
4579
-
[mclk_table->count - 1].value -
4580
-
golden_mclk_table->dpm_levels
4581
-
[golden_mclk_table->count - 1].value) *
4582
-
100 /
4583
-
golden_mclk_table->dpm_levels
4578
+
int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
4579
+
int golden_value = golden_mclk_table->dpm_levels
4584
4580
[golden_mclk_table->count - 1].value;
4581
+
4582
+
value -= golden_value;
4583
+
value = DIV_ROUND_UP(value * 100, golden_value);
4585
4584
4586
4585
return value;
4587
4586
}
+10
-13
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+10
-13
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
···
2243
2243
struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2244
2244
struct vega12_single_dpm_table *golden_sclk_table =
2245
2245
&(data->golden_dpm_table.gfx_table);
2246
-
int value;
2246
+
int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
2247
+
int golden_value = golden_sclk_table->dpm_levels
2248
+
[golden_sclk_table->count - 1].value;
2247
2249
2248
-
value = (sclk_table->dpm_levels[sclk_table->count - 1].value -
2249
-
golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) *
2250
-
100 /
2251
-
golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value;
2250
+
value -= golden_value;
2251
+
value = DIV_ROUND_UP(value * 100, golden_value);
2252
2252
2253
2253
return value;
2254
2254
}
···
2264
2264
struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2265
2265
struct vega12_single_dpm_table *golden_mclk_table =
2266
2266
&(data->golden_dpm_table.mem_table);
2267
-
int value;
2268
-
2269
-
value = (mclk_table->dpm_levels
2270
-
[mclk_table->count - 1].value -
2271
-
golden_mclk_table->dpm_levels
2272
-
[golden_mclk_table->count - 1].value) *
2273
-
100 /
2274
-
golden_mclk_table->dpm_levels
2267
+
int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
2268
+
int golden_value = golden_mclk_table->dpm_levels
2275
2269
[golden_mclk_table->count - 1].value;
2270
+
2271
+
value -= golden_value;
2272
+
value = DIV_ROUND_UP(value * 100, golden_value);
2276
2273
2277
2274
return value;
2278
2275
}
+21
-9
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+21
-9
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
···
75
75
data->phy_clk_quad_eqn_b = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
76
76
data->phy_clk_quad_eqn_c = PPREGKEY_VEGA20QUADRATICEQUATION_DFLT;
77
77
78
-
data->registry_data.disallowed_features = 0x0;
78
+
/*
79
+
* Disable the following features for now:
80
+
* GFXCLK DS
81
+
* SOCLK DS
82
+
* LCLK DS
83
+
* DCEFCLK DS
84
+
* FCLK DS
85
+
* MP1CLK DS
86
+
* MP0CLK DS
87
+
*/
88
+
data->registry_data.disallowed_features = 0xE0041C00;
79
89
data->registry_data.od_state_in_dc_support = 0;
80
90
data->registry_data.thermal_support = 1;
81
91
data->registry_data.skip_baco_hardware = 0;
···
1323
1313
&(data->dpm_table.gfx_table);
1324
1314
struct vega20_single_dpm_table *golden_sclk_table =
1325
1315
&(data->golden_dpm_table.gfx_table);
1326
-
int value;
1316
+
int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
1317
+
int golden_value = golden_sclk_table->dpm_levels
1318
+
[golden_sclk_table->count - 1].value;
1327
1319
1328
1320
/* od percentage */
1329
-
value = DIV_ROUND_UP((sclk_table->dpm_levels[sclk_table->count - 1].value -
1330
-
golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * 100,
1331
-
golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value);
1321
+
value -= golden_value;
1322
+
value = DIV_ROUND_UP(value * 100, golden_value);
1332
1323
1333
1324
return value;
1334
1325
}
···
1369
1358
&(data->dpm_table.mem_table);
1370
1359
struct vega20_single_dpm_table *golden_mclk_table =
1371
1360
&(data->golden_dpm_table.mem_table);
1372
-
int value;
1361
+
int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
1362
+
int golden_value = golden_mclk_table->dpm_levels
1363
+
[golden_mclk_table->count - 1].value;
1373
1364
1374
1365
/* od percentage */
1375
-
value = DIV_ROUND_UP((mclk_table->dpm_levels[mclk_table->count - 1].value -
1376
-
golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * 100,
1377
-
golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value);
1366
+
value -= golden_value;
1367
+
value = DIV_ROUND_UP(value * 100, golden_value);
1378
1368
1379
1369
return value;
1380
1370
}
+21
drivers/gpu/drm/ast/ast_drv.c
+21
drivers/gpu/drm/ast/ast_drv.c
···
60
60
61
61
MODULE_DEVICE_TABLE(pci, pciidlist);
62
62
63
+
static void ast_kick_out_firmware_fb(struct pci_dev *pdev)
64
+
{
65
+
struct apertures_struct *ap;
66
+
bool primary = false;
67
+
68
+
ap = alloc_apertures(1);
69
+
if (!ap)
70
+
return;
71
+
72
+
ap->ranges[0].base = pci_resource_start(pdev, 0);
73
+
ap->ranges[0].size = pci_resource_len(pdev, 0);
74
+
75
+
#ifdef CONFIG_X86
76
+
primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
77
+
#endif
78
+
drm_fb_helper_remove_conflicting_framebuffers(ap, "astdrmfb", primary);
79
+
kfree(ap);
80
+
}
81
+
63
82
static int ast_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
64
83
{
84
+
ast_kick_out_firmware_fb(pdev);
85
+
65
86
return drm_get_pci_dev(pdev, ent, &driver);
66
87
}
67
88
+2
-1
drivers/gpu/drm/ast/ast_mode.c
+2
-1
drivers/gpu/drm/ast/ast_mode.c
···
568
568
}
569
569
ast_bo_unreserve(bo);
570
570
571
+
ast_set_offset_reg(crtc);
571
572
ast_set_start_address_crt1(crtc, (u32)gpu_addr);
572
573
573
574
return 0;
···
1255
1254
ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
1256
1255
1257
1256
/* dummy write to fire HWC */
1258
-
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00);
1257
+
ast_show_cursor(crtc);
1259
1258
1260
1259
return 0;
1261
1260
}
+3
drivers/gpu/drm/drm_fb_helper.c
+3
drivers/gpu/drm/drm_fb_helper.c
···
219
219
mutex_lock(&fb_helper->lock);
220
220
drm_connector_list_iter_begin(dev, &conn_iter);
221
221
drm_for_each_connector_iter(connector, &conn_iter) {
222
+
if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
223
+
continue;
224
+
222
225
ret = __drm_fb_helper_add_one_connector(fb_helper, connector);
223
226
if (ret)
224
227
goto fail;
+6
-1
drivers/gpu/drm/i915/i915_gem_execbuffer.c
+6
-1
drivers/gpu/drm/i915/i915_gem_execbuffer.c
···
1268
1268
else if (gen >= 4)
1269
1269
len = 4;
1270
1270
else
1271
-
len = 3;
1271
+
len = 6;
1272
1272
1273
1273
batch = reloc_gpu(eb, vma, len);
1274
1274
if (IS_ERR(batch))
···
1306
1306
*batch++ = addr;
1307
1307
*batch++ = target_offset;
1308
1308
} else {
1309
+
*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1310
+
*batch++ = addr;
1311
+
*batch++ = target_offset;
1312
+
1313
+
/* And again for good measure (blb/pnv) */
1309
1314
*batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
1310
1315
*batch++ = addr;
1311
1316
*batch++ = target_offset;
+5
drivers/gpu/drm/i915/i915_gem_gtt.c
+5
drivers/gpu/drm/i915/i915_gem_gtt.c
···
3413
3413
ggtt->vm.insert_page = bxt_vtd_ggtt_insert_page__BKL;
3414
3414
if (ggtt->vm.clear_range != nop_clear_range)
3415
3415
ggtt->vm.clear_range = bxt_vtd_ggtt_clear_range__BKL;
3416
+
3417
+
/* Prevent recursively calling stop_machine() and deadlocks. */
3418
+
dev_info(dev_priv->drm.dev,
3419
+
"Disabling error capture for VT-d workaround\n");
3420
+
i915_disable_error_state(dev_priv, -ENODEV);
3416
3421
}
3417
3422
3418
3423
ggtt->invalidate = gen6_ggtt_invalidate;
+14
-1
drivers/gpu/drm/i915/i915_gpu_error.c
+14
-1
drivers/gpu/drm/i915/i915_gpu_error.c
···
648
648
return 0;
649
649
}
650
650
651
+
if (IS_ERR(error))
652
+
return PTR_ERR(error);
653
+
651
654
if (*error->error_msg)
652
655
err_printf(m, "%s\n", error->error_msg);
653
656
err_printf(m, "Kernel: " UTS_RELEASE "\n");
···
1862
1859
error = i915_capture_gpu_state(i915);
1863
1860
if (!error) {
1864
1861
DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1862
+
i915_disable_error_state(i915, -ENOMEM);
1865
1863
return;
1866
1864
}
1867
1865
···
1918
1914
i915->gpu_error.first_error = NULL;
1919
1915
spin_unlock_irq(&i915->gpu_error.lock);
1920
1916
1921
-
i915_gpu_state_put(error);
1917
+
if (!IS_ERR(error))
1918
+
i915_gpu_state_put(error);
1919
+
}
1920
+
1921
+
void i915_disable_error_state(struct drm_i915_private *i915, int err)
1922
+
{
1923
+
spin_lock_irq(&i915->gpu_error.lock);
1924
+
if (!i915->gpu_error.first_error)
1925
+
i915->gpu_error.first_error = ERR_PTR(err);
1926
+
spin_unlock_irq(&i915->gpu_error.lock);
1922
1927
}
+7
-1
drivers/gpu/drm/i915/i915_gpu_error.h
+7
-1
drivers/gpu/drm/i915/i915_gpu_error.h
···
343
343
344
344
struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
345
345
void i915_reset_error_state(struct drm_i915_private *i915);
346
+
void i915_disable_error_state(struct drm_i915_private *i915, int err);
346
347
347
348
#else
348
349
···
356
355
static inline struct i915_gpu_state *
357
356
i915_first_error_state(struct drm_i915_private *i915)
358
357
{
359
-
return NULL;
358
+
return ERR_PTR(-ENODEV);
360
359
}
361
360
362
361
static inline void i915_reset_error_state(struct drm_i915_private *i915)
362
+
{
363
+
}
364
+
365
+
static inline void i915_disable_error_state(struct drm_i915_private *i915,
366
+
int err)
363
367
{
364
368
}
365
369
+39
drivers/gpu/drm/i915/intel_display.c
+39
drivers/gpu/drm/i915/intel_display.c
···
2890
2890
return;
2891
2891
2892
2892
valid_fb:
2893
+
intel_state->base.rotation = plane_config->rotation;
2893
2894
intel_fill_fb_ggtt_view(&intel_state->view, fb,
2894
2895
intel_state->base.rotation);
2895
2896
intel_state->color_plane[0].stride =
···
7883
7882
plane_config->tiling = I915_TILING_X;
7884
7883
fb->modifier = I915_FORMAT_MOD_X_TILED;
7885
7884
}
7885
+
7886
+
if (val & DISPPLANE_ROTATE_180)
7887
+
plane_config->rotation = DRM_MODE_ROTATE_180;
7886
7888
}
7889
+
7890
+
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
7891
+
val & DISPPLANE_MIRROR)
7892
+
plane_config->rotation |= DRM_MODE_REFLECT_X;
7887
7893
7888
7894
pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7889
7895
fourcc = i9xx_format_to_fourcc(pixel_format);
···
8959
8951
MISSING_CASE(tiling);
8960
8952
goto error;
8961
8953
}
8954
+
8955
+
/*
8956
+
* DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
8957
+
* while i915 HW rotation is clockwise, thats why this swapping.
8958
+
*/
8959
+
switch (val & PLANE_CTL_ROTATE_MASK) {
8960
+
case PLANE_CTL_ROTATE_0:
8961
+
plane_config->rotation = DRM_MODE_ROTATE_0;
8962
+
break;
8963
+
case PLANE_CTL_ROTATE_90:
8964
+
plane_config->rotation = DRM_MODE_ROTATE_270;
8965
+
break;
8966
+
case PLANE_CTL_ROTATE_180:
8967
+
plane_config->rotation = DRM_MODE_ROTATE_180;
8968
+
break;
8969
+
case PLANE_CTL_ROTATE_270:
8970
+
plane_config->rotation = DRM_MODE_ROTATE_90;
8971
+
break;
8972
+
}
8973
+
8974
+
if (INTEL_GEN(dev_priv) >= 10 &&
8975
+
val & PLANE_CTL_FLIP_HORIZONTAL)
8976
+
plane_config->rotation |= DRM_MODE_REFLECT_X;
8962
8977
8963
8978
base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000;
8964
8979
plane_config->base = base;
···
15298
15267
ret = drm_atomic_add_affected_planes(state, crtc);
15299
15268
if (ret)
15300
15269
goto out;
15270
+
15271
+
/*
15272
+
* FIXME hack to force a LUT update to avoid the
15273
+
* plane update forcing the pipe gamma on without
15274
+
* having a proper LUT loaded. Remove once we
15275
+
* have readout for pipe gamma enable.
15276
+
*/
15277
+
crtc_state->color_mgmt_changed = true;
15301
15278
}
15302
15279
}
15303
15280
+1
drivers/gpu/drm/i915/intel_drv.h
+1
drivers/gpu/drm/i915/intel_drv.h
+40
-1
drivers/gpu/drm/i915/intel_pm.c
+40
-1
drivers/gpu/drm/i915/intel_pm.c
···
2493
2493
uint32_t method1, method2;
2494
2494
int cpp;
2495
2495
2496
+
if (mem_value == 0)
2497
+
return U32_MAX;
2498
+
2496
2499
if (!intel_wm_plane_visible(cstate, pstate))
2497
2500
return 0;
2498
2501
···
2525
2522
uint32_t method1, method2;
2526
2523
int cpp;
2527
2524
2525
+
if (mem_value == 0)
2526
+
return U32_MAX;
2527
+
2528
2528
if (!intel_wm_plane_visible(cstate, pstate))
2529
2529
return 0;
2530
2530
···
2550
2544
uint32_t mem_value)
2551
2545
{
2552
2546
int cpp;
2547
+
2548
+
if (mem_value == 0)
2549
+
return U32_MAX;
2553
2550
2554
2551
if (!intel_wm_plane_visible(cstate, pstate))
2555
2552
return 0;
···
3017
3008
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3018
3009
}
3019
3010
3011
+
static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
3012
+
{
3013
+
/*
3014
+
* On some SNB machines (Thinkpad X220 Tablet at least)
3015
+
* LP3 usage can cause vblank interrupts to be lost.
3016
+
* The DEIIR bit will go high but it looks like the CPU
3017
+
* never gets interrupted.
3018
+
*
3019
+
* It's not clear whether other interrupt source could
3020
+
* be affected or if this is somehow limited to vblank
3021
+
* interrupts only. To play it safe we disable LP3
3022
+
* watermarks entirely.
3023
+
*/
3024
+
if (dev_priv->wm.pri_latency[3] == 0 &&
3025
+
dev_priv->wm.spr_latency[3] == 0 &&
3026
+
dev_priv->wm.cur_latency[3] == 0)
3027
+
return;
3028
+
3029
+
dev_priv->wm.pri_latency[3] = 0;
3030
+
dev_priv->wm.spr_latency[3] = 0;
3031
+
dev_priv->wm.cur_latency[3] = 0;
3032
+
3033
+
DRM_DEBUG_KMS("LP3 watermarks disabled due to potential for lost interrupts\n");
3034
+
intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3035
+
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3036
+
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3037
+
}
3038
+
3020
3039
static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
3021
3040
{
3022
3041
intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
···
3061
3024
intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3062
3025
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3063
3026
3064
-
if (IS_GEN6(dev_priv))
3027
+
if (IS_GEN6(dev_priv)) {
3065
3028
snb_wm_latency_quirk(dev_priv);
3029
+
snb_wm_lp3_irq_quirk(dev_priv);
3030
+
}
3066
3031
}
3067
3032
3068
3033
static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
+6
drivers/gpu/drm/vc4/vc4_kms.c
+6
drivers/gpu/drm/vc4/vc4_kms.c
···
214
214
return 0;
215
215
}
216
216
217
+
/* We know for sure we don't want an async update here. Set
218
+
* state->legacy_cursor_update to false to prevent
219
+
* drm_atomic_helper_setup_commit() from auto-completing
220
+
* commit->flip_done.
221
+
*/
222
+
state->legacy_cursor_update = false;
217
223
ret = drm_atomic_helper_setup_commit(state, nonblock);
218
224
if (ret)
219
225
return ret;
+13
-2
drivers/gpu/drm/vc4/vc4_plane.c
+13
-2
drivers/gpu/drm/vc4/vc4_plane.c
···
807
807
static void vc4_plane_atomic_async_update(struct drm_plane *plane,
808
808
struct drm_plane_state *state)
809
809
{
810
-
struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
810
+
struct vc4_plane_state *vc4_state, *new_vc4_state;
811
811
812
812
if (plane->state->fb != state->fb) {
813
813
vc4_plane_async_set_fb(plane, state->fb);
···
828
828
plane->state->src_y = state->src_y;
829
829
830
830
/* Update the display list based on the new crtc_x/y. */
831
-
vc4_plane_atomic_check(plane, plane->state);
831
+
vc4_plane_atomic_check(plane, state);
832
+
833
+
new_vc4_state = to_vc4_plane_state(state);
834
+
vc4_state = to_vc4_plane_state(plane->state);
835
+
836
+
/* Update the current vc4_state pos0, pos2 and ptr0 dlist entries. */
837
+
vc4_state->dlist[vc4_state->pos0_offset] =
838
+
new_vc4_state->dlist[vc4_state->pos0_offset];
839
+
vc4_state->dlist[vc4_state->pos2_offset] =
840
+
new_vc4_state->dlist[vc4_state->pos2_offset];
841
+
vc4_state->dlist[vc4_state->ptr0_offset] =
842
+
new_vc4_state->dlist[vc4_state->ptr0_offset];
832
843
833
844
/* Note that we can't just call vc4_plane_write_dlist()
834
845
* because that would smash the context data that the HVS is