Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu/psp: Use Indirect access address for GFX to PSP mailbox
The reason the RAP is not granting access to 0x58200 is that
a dedicated RSMU slot would have to be spent for this address range,
and MPASP is close to running out of RSMU slots.
This will help to fix PSP TOC load failure during secureboot.
GFX Driver Need to use indirect access for SMN address regs.
Signed-off-by: sguttula <suresh.guttula@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
sguttula
and committed by
Alex Deucher
9b822e26
a95dfb0c
+28
-10
+10
-10
drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
+10
-10
drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
···
69
69
0x80000000, 0x80000000, false);
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70
} else {
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71
/* Write the ring destroy command*/
72
-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
72
+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64,
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GFX_CTRL_CMD_ID_DESTROY_RINGS);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) */
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-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
77
+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
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0x80000000, 0x80000000, false);
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}
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80
···
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} else {
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/* Wait for sOS ready for ring creation */
119
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
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+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
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0x80000000, 0x80000000, false);
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if (ret) {
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DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
···
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/* Write low address of the ring to C2PMSG_69 */
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psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
128
-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg);
128
+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, psp_ring_reg);
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/* Write high address of the ring to C2PMSG_70 */
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psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
131
-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg);
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+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_70, psp_ring_reg);
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/* Write size of ring to C2PMSG_71 */
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psp_ring_reg = ring->ring_size;
134
-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg);
134
+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_71, psp_ring_reg);
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/* Write the ring initialization command to C2PMSG_64 */
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psp_ring_reg = ring_type;
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psp_ring_reg = psp_ring_reg << 16;
138
-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg);
138
+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, psp_ring_reg);
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/* there might be handshake issue with hardware which needs delay */
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mdelay(20);
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/* Wait for response flag (bit 31) in C2PMSG_64 */
144
-
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
144
+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
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0x80000000, 0x8000FFFF, false);
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}
147
147
···
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if (amdgpu_sriov_vf(adev))
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data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
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else
177
-
data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);
177
+
data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67);
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return data;
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}
···
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WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
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GFX_CTRL_CMD_ID_CONSUME_CMD);
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} else
191
-
WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);
191
+
WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value);
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}
193
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static const struct psp_funcs psp_v15_0_0_funcs = {
+18
drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h
+18
drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h
···
82
82
#define regMPASP_SMN_IH_SW_INT_CTRL 0x0142
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83
#define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX 0
84
84
85
+
// addressBlock: mp_SmuMpASPPub_PcruDec
86
+
// base address: 0x3800000
87
+
#define regMPASP_PCRU1_MPASP_C2PMSG_64 0x4280
88
+
#define regMPASP_PCRU1_MPASP_C2PMSG_64_BASE_IDX 3
89
+
#define regMPASP_PCRU1_MPASP_C2PMSG_65 0x4281
90
+
#define regMPASP_PCRU1_MPASP_C2PMSG_65_BASE_IDX 3
91
+
#define regMPASP_PCRU1_MPASP_C2PMSG_66 0x4282
92
+
#define regMPASP_PCRU1_MPASP_C2PMSG_66_BASE_IDX 3
93
+
#define regMPASP_PCRU1_MPASP_C2PMSG_67 0x4283
94
+
#define regMPASP_PCRU1_MPASP_C2PMSG_67_BASE_IDX 3
95
+
#define regMPASP_PCRU1_MPASP_C2PMSG_68 0x4284
96
+
#define regMPASP_PCRU1_MPASP_C2PMSG_68_BASE_IDX 3
97
+
#define regMPASP_PCRU1_MPASP_C2PMSG_69 0x4285
98
+
#define regMPASP_PCRU1_MPASP_C2PMSG_69_BASE_IDX 3
99
+
#define regMPASP_PCRU1_MPASP_C2PMSG_70 0x4286
100
+
#define regMPASP_PCRU1_MPASP_C2PMSG_70_BASE_IDX 3
101
+
#define regMPASP_PCRU1_MPASP_C2PMSG_71 0x4287
102
+
#define regMPASP_PCRU1_MPASP_C2PMSG_71_BASE_IDX 3
85
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// addressBlock: mp_SmuMp1_SmnDec
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// base address: 0x0