Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpio: move gpio-mmio-specific fields out of struct gpio_chip
With all users of bgpio_init() converted to using the modernized generic
GPIO chip API, we can now move the gpio-mmio-specific fields out of
struct gpio_chip and into the dedicated struct gpio_generic_chip. To
that end: adjust the gpio-mmio driver to the new layout, update the
docs, etc.
The changes in gpio-mlxbf2.c and gpio-mpc8xxx.c are here and not in their
respective conversion commits because the former passes the address of
the generic chip's lock to the __releases() annotation and we cannot
really hide it while gpio-mpc8xxx.c accesses the shadow registers in a
driver-specific workaround and there's no reason to make them available
in a public API.
Also: drop the relevant task from TODO as it's now done.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20250910-gpio-mmio-gpio-conv-part4-v2-15-f3d1a4c57124@linaro.org
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
+211
-233
-5
drivers/gpio/TODO
-5
drivers/gpio/TODO
···
131
131
helpers (x86 inb()/outb()) and convert port-mapped I/O drivers to use
132
132
this with dry-coding and sending to maintainers to test
133
133
134
-
- Move the MMIO GPIO specific fields out of struct gpio_chip into a
135
-
dedicated structure. Currently every GPIO chip has them if gpio-mmio is
136
-
enabled in Kconfig even if it itself doesn't register with the helper
137
-
library.
138
-
139
134
-------------------------------------------------------------------------------
140
135
141
136
Generic regmap GPIO
+1
-1
drivers/gpio/gpio-mlxbf2.c
+1
-1
drivers/gpio/gpio-mlxbf2.c
···
156
156
* Release the YU arm_gpio_lock after changing the direction mode.
157
157
*/
158
158
static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs)
159
-
__releases(&gs->chip.gc.bgpio_lock)
159
+
__releases(&gs->chip.lock)
160
160
__releases(yu_arm_gpio_lock_param.lock)
161
161
{
162
162
writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io);
+162
-159
drivers/gpio/gpio-mmio.c
+162
-159
drivers/gpio/gpio-mmio.c
···
125
125
126
126
static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
127
127
{
128
-
if (gc->be_bits)
129
-
return BIT(gc->bgpio_bits - 1 - line);
128
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
129
+
130
+
if (chip->be_bits)
131
+
return BIT(chip->bits - 1 - line);
130
132
return BIT(line);
131
133
}
132
134
133
135
static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
134
136
{
137
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
135
138
unsigned long pinmask = bgpio_line2mask(gc, gpio);
136
-
bool dir = !!(gc->bgpio_dir & pinmask);
139
+
bool dir = !!(chip->sdir & pinmask);
137
140
138
141
if (dir)
139
-
return !!(gc->read_reg(gc->reg_set) & pinmask);
140
-
else
141
-
return !!(gc->read_reg(gc->reg_dat) & pinmask);
142
+
return !!(chip->read_reg(chip->reg_set) & pinmask);
143
+
144
+
return !!(chip->read_reg(chip->reg_dat) & pinmask);
142
145
}
143
146
144
147
/*
···
151
148
static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
152
149
unsigned long *bits)
153
150
{
154
-
unsigned long get_mask = 0;
155
-
unsigned long set_mask = 0;
151
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
152
+
unsigned long get_mask = 0, set_mask = 0;
156
153
157
154
/* Make sure we first clear any bits that are zero when we read the register */
158
155
*bits &= ~*mask;
159
156
160
-
set_mask = *mask & gc->bgpio_dir;
161
-
get_mask = *mask & ~gc->bgpio_dir;
157
+
set_mask = *mask & chip->sdir;
158
+
get_mask = *mask & ~chip->sdir;
162
159
163
160
if (set_mask)
164
-
*bits |= gc->read_reg(gc->reg_set) & set_mask;
161
+
*bits |= chip->read_reg(chip->reg_set) & set_mask;
165
162
if (get_mask)
166
-
*bits |= gc->read_reg(gc->reg_dat) & get_mask;
163
+
*bits |= chip->read_reg(chip->reg_dat) & get_mask;
167
164
168
165
return 0;
169
166
}
170
167
171
168
static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
172
169
{
173
-
return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
170
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
171
+
172
+
return !!(chip->read_reg(chip->reg_dat) & bgpio_line2mask(gc, gpio));
174
173
}
175
174
176
175
/*
···
181
176
static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
182
177
unsigned long *bits)
183
178
{
179
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
180
+
184
181
/* Make sure we first clear any bits that are zero when we read the register */
185
182
*bits &= ~*mask;
186
-
*bits |= gc->read_reg(gc->reg_dat) & *mask;
183
+
*bits |= chip->read_reg(chip->reg_dat) & *mask;
187
184
return 0;
188
185
}
189
186
···
195
188
static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
196
189
unsigned long *bits)
197
190
{
191
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
198
192
unsigned long readmask = 0;
199
193
unsigned long val;
200
194
int bit;
···
208
200
readmask |= bgpio_line2mask(gc, bit);
209
201
210
202
/* Read the register */
211
-
val = gc->read_reg(gc->reg_dat) & readmask;
203
+
val = chip->read_reg(chip->reg_dat) & readmask;
212
204
213
205
/*
214
206
* Mirror the result into the "bits" result, this will give line 0
···
227
219
228
220
static int bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
229
221
{
222
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
230
223
unsigned long mask = bgpio_line2mask(gc, gpio);
231
224
unsigned long flags;
232
225
233
-
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
226
+
raw_spin_lock_irqsave(&chip->lock, flags);
234
227
235
228
if (val)
236
-
gc->bgpio_data |= mask;
229
+
chip->sdata |= mask;
237
230
else
238
-
gc->bgpio_data &= ~mask;
231
+
chip->sdata &= ~mask;
239
232
240
-
gc->write_reg(gc->reg_dat, gc->bgpio_data);
233
+
chip->write_reg(chip->reg_dat, chip->sdata);
241
234
242
-
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
235
+
raw_spin_unlock_irqrestore(&chip->lock, flags);
243
236
244
237
return 0;
245
238
}
···
248
239
static int bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
249
240
int val)
250
241
{
242
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
251
243
unsigned long mask = bgpio_line2mask(gc, gpio);
252
244
253
245
if (val)
254
-
gc->write_reg(gc->reg_set, mask);
246
+
chip->write_reg(chip->reg_set, mask);
255
247
else
256
-
gc->write_reg(gc->reg_clr, mask);
248
+
chip->write_reg(chip->reg_clr, mask);
257
249
258
250
return 0;
259
251
}
260
252
261
253
static int bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
262
254
{
263
-
unsigned long mask = bgpio_line2mask(gc, gpio);
264
-
unsigned long flags;
255
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
256
+
unsigned long mask = bgpio_line2mask(gc, gpio), flags;
265
257
266
-
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
258
+
raw_spin_lock_irqsave(&chip->lock, flags);
267
259
268
260
if (val)
269
-
gc->bgpio_data |= mask;
261
+
chip->sdata |= mask;
270
262
else
271
-
gc->bgpio_data &= ~mask;
263
+
chip->sdata &= ~mask;
272
264
273
-
gc->write_reg(gc->reg_set, gc->bgpio_data);
265
+
chip->write_reg(chip->reg_set, chip->sdata);
274
266
275
-
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
267
+
raw_spin_unlock_irqrestore(&chip->lock, flags);
276
268
277
269
return 0;
278
270
}
···
283
273
unsigned long *set_mask,
284
274
unsigned long *clear_mask)
285
275
{
276
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
286
277
int i;
287
278
288
279
*set_mask = 0;
289
280
*clear_mask = 0;
290
281
291
-
for_each_set_bit(i, mask, gc->bgpio_bits) {
282
+
for_each_set_bit(i, mask, chip->bits) {
292
283
if (test_bit(i, bits))
293
284
*set_mask |= bgpio_line2mask(gc, i);
294
285
else
···
302
291
unsigned long *bits,
303
292
void __iomem *reg)
304
293
{
305
-
unsigned long flags;
306
-
unsigned long set_mask, clear_mask;
294
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
295
+
unsigned long flags, set_mask, clear_mask;
307
296
308
-
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
297
+
raw_spin_lock_irqsave(&chip->lock, flags);
309
298
310
299
bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
311
300
312
-
gc->bgpio_data |= set_mask;
313
-
gc->bgpio_data &= ~clear_mask;
301
+
chip->sdata |= set_mask;
302
+
chip->sdata &= ~clear_mask;
314
303
315
-
gc->write_reg(reg, gc->bgpio_data);
304
+
chip->write_reg(reg, chip->sdata);
316
305
317
-
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
306
+
raw_spin_unlock_irqrestore(&chip->lock, flags);
318
307
}
319
308
320
309
static int bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
321
310
unsigned long *bits)
322
311
{
323
-
bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
312
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
313
+
314
+
bgpio_set_multiple_single_reg(gc, mask, bits, chip->reg_dat);
324
315
325
316
return 0;
326
317
}
···
330
317
static int bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
331
318
unsigned long *bits)
332
319
{
333
-
bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
320
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
321
+
322
+
bgpio_set_multiple_single_reg(gc, mask, bits, chip->reg_set);
334
323
335
324
return 0;
336
325
}
···
341
326
unsigned long *mask,
342
327
unsigned long *bits)
343
328
{
329
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
344
330
unsigned long set_mask, clear_mask;
345
331
346
332
bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
347
333
348
334
if (set_mask)
349
-
gc->write_reg(gc->reg_set, set_mask);
335
+
chip->write_reg(chip->reg_set, set_mask);
350
336
if (clear_mask)
351
-
gc->write_reg(gc->reg_clr, clear_mask);
337
+
chip->write_reg(chip->reg_clr, clear_mask);
352
338
353
339
return 0;
354
340
}
355
341
356
342
static int bgpio_dir_return(struct gpio_chip *gc, unsigned int gpio, bool dir_out)
357
343
{
358
-
if (!gc->bgpio_pinctrl)
344
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
345
+
346
+
if (!chip->pinctrl)
359
347
return 0;
360
348
361
349
if (dir_out)
···
393
375
394
376
static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
395
377
{
378
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
396
379
unsigned long flags;
397
380
398
-
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
381
+
raw_spin_lock_irqsave(&chip->lock, flags);
399
382
400
-
gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
383
+
chip->sdir &= ~bgpio_line2mask(gc, gpio);
401
384
402
-
if (gc->reg_dir_in)
403
-
gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
404
-
if (gc->reg_dir_out)
405
-
gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
385
+
if (chip->reg_dir_in)
386
+
chip->write_reg(chip->reg_dir_in, ~chip->sdir);
387
+
if (chip->reg_dir_out)
388
+
chip->write_reg(chip->reg_dir_out, chip->sdir);
406
389
407
-
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
390
+
raw_spin_unlock_irqrestore(&chip->lock, flags);
408
391
409
392
return bgpio_dir_return(gc, gpio, false);
410
393
}
411
394
412
395
static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
413
396
{
397
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
398
+
414
399
/* Return 0 if output, 1 if input */
415
-
if (gc->bgpio_dir_unreadable) {
416
-
if (gc->bgpio_dir & bgpio_line2mask(gc, gpio))
400
+
if (chip->dir_unreadable) {
401
+
if (chip->sdir & bgpio_line2mask(gc, gpio))
417
402
return GPIO_LINE_DIRECTION_OUT;
418
403
return GPIO_LINE_DIRECTION_IN;
419
404
}
420
405
421
-
if (gc->reg_dir_out) {
422
-
if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio))
406
+
if (chip->reg_dir_out) {
407
+
if (chip->read_reg(chip->reg_dir_out) & bgpio_line2mask(gc, gpio))
423
408
return GPIO_LINE_DIRECTION_OUT;
424
409
return GPIO_LINE_DIRECTION_IN;
425
410
}
426
411
427
-
if (gc->reg_dir_in)
428
-
if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio)))
412
+
if (chip->reg_dir_in)
413
+
if (!(chip->read_reg(chip->reg_dir_in) & bgpio_line2mask(gc, gpio)))
429
414
return GPIO_LINE_DIRECTION_OUT;
430
415
431
416
return GPIO_LINE_DIRECTION_IN;
···
436
415
437
416
static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
438
417
{
418
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
439
419
unsigned long flags;
440
420
441
-
raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
421
+
raw_spin_lock_irqsave(&chip->lock, flags);
442
422
443
-
gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
423
+
chip->sdir |= bgpio_line2mask(gc, gpio);
444
424
445
-
if (gc->reg_dir_in)
446
-
gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
447
-
if (gc->reg_dir_out)
448
-
gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
425
+
if (chip->reg_dir_in)
426
+
chip->write_reg(chip->reg_dir_in, ~chip->sdir);
427
+
if (chip->reg_dir_out)
428
+
chip->write_reg(chip->reg_dir_out, chip->sdir);
449
429
450
-
raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
430
+
raw_spin_unlock_irqrestore(&chip->lock, flags);
451
431
}
452
432
453
433
static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
···
468
446
}
469
447
470
448
static int bgpio_setup_accessors(struct device *dev,
471
-
struct gpio_chip *gc,
449
+
struct gpio_generic_chip *chip,
472
450
bool byte_be)
473
451
{
474
-
475
-
switch (gc->bgpio_bits) {
452
+
switch (chip->bits) {
476
453
case 8:
477
-
gc->read_reg = bgpio_read8;
478
-
gc->write_reg = bgpio_write8;
454
+
chip->read_reg = bgpio_read8;
455
+
chip->write_reg = bgpio_write8;
479
456
break;
480
457
case 16:
481
458
if (byte_be) {
482
-
gc->read_reg = bgpio_read16be;
483
-
gc->write_reg = bgpio_write16be;
459
+
chip->read_reg = bgpio_read16be;
460
+
chip->write_reg = bgpio_write16be;
484
461
} else {
485
-
gc->read_reg = bgpio_read16;
486
-
gc->write_reg = bgpio_write16;
462
+
chip->read_reg = bgpio_read16;
463
+
chip->write_reg = bgpio_write16;
487
464
}
488
465
break;
489
466
case 32:
490
467
if (byte_be) {
491
-
gc->read_reg = bgpio_read32be;
492
-
gc->write_reg = bgpio_write32be;
468
+
chip->read_reg = bgpio_read32be;
469
+
chip->write_reg = bgpio_write32be;
493
470
} else {
494
-
gc->read_reg = bgpio_read32;
495
-
gc->write_reg = bgpio_write32;
471
+
chip->read_reg = bgpio_read32;
472
+
chip->write_reg = bgpio_write32;
496
473
}
497
474
break;
498
475
#if BITS_PER_LONG >= 64
···
501
480
"64 bit big endian byte order unsupported\n");
502
481
return -EINVAL;
503
482
} else {
504
-
gc->read_reg = bgpio_read64;
505
-
gc->write_reg = bgpio_write64;
483
+
chip->read_reg = bgpio_read64;
484
+
chip->write_reg = bgpio_write64;
506
485
}
507
486
break;
508
487
#endif /* BITS_PER_LONG >= 64 */
509
488
default:
510
-
dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
489
+
dev_err(dev, "unsupported data width %u bits\n", chip->bits);
511
490
return -EINVAL;
512
491
}
513
492
···
536
515
* - an input direction register (named "dirin") where a 1 bit indicates
537
516
* the GPIO is an input.
538
517
*/
539
-
static int bgpio_setup_io(struct gpio_chip *gc,
540
-
void __iomem *dat,
541
-
void __iomem *set,
542
-
void __iomem *clr,
543
-
unsigned long flags)
518
+
static int bgpio_setup_io(struct gpio_generic_chip *chip,
519
+
const struct gpio_generic_chip_config *cfg)
544
520
{
521
+
struct gpio_chip *gc = &chip->gc;
545
522
546
-
gc->reg_dat = dat;
547
-
if (!gc->reg_dat)
523
+
chip->reg_dat = cfg->dat;
524
+
if (!chip->reg_dat)
548
525
return -EINVAL;
549
526
550
-
if (set && clr) {
551
-
gc->reg_set = set;
552
-
gc->reg_clr = clr;
527
+
if (cfg->set && cfg->clr) {
528
+
chip->reg_set = cfg->set;
529
+
chip->reg_clr = cfg->clr;
553
530
gc->set = bgpio_set_with_clear;
554
531
gc->set_multiple = bgpio_set_multiple_with_clear;
555
-
} else if (set && !clr) {
556
-
gc->reg_set = set;
532
+
} else if (cfg->set && !cfg->clr) {
533
+
chip->reg_set = cfg->set;
557
534
gc->set = bgpio_set_set;
558
535
gc->set_multiple = bgpio_set_multiple_set;
559
-
} else if (flags & BGPIOF_NO_OUTPUT) {
536
+
} else if (cfg->flags & BGPIOF_NO_OUTPUT) {
560
537
gc->set = bgpio_set_none;
561
538
gc->set_multiple = NULL;
562
539
} else {
···
562
543
gc->set_multiple = bgpio_set_multiple;
563
544
}
564
545
565
-
if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
566
-
(flags & BGPIOF_READ_OUTPUT_REG_SET)) {
546
+
if (!(cfg->flags & BGPIOF_UNREADABLE_REG_SET) &&
547
+
(cfg->flags & BGPIOF_READ_OUTPUT_REG_SET)) {
567
548
gc->get = bgpio_get_set;
568
-
if (!gc->be_bits)
549
+
if (!chip->be_bits)
569
550
gc->get_multiple = bgpio_get_set_multiple;
570
551
/*
571
552
* We deliberately avoid assigning the ->get_multiple() call
···
576
557
*/
577
558
} else {
578
559
gc->get = bgpio_get;
579
-
if (gc->be_bits)
560
+
if (chip->be_bits)
580
561
gc->get_multiple = bgpio_get_multiple_be;
581
562
else
582
563
gc->get_multiple = bgpio_get_multiple;
···
585
566
return 0;
586
567
}
587
568
588
-
static int bgpio_setup_direction(struct gpio_chip *gc,
589
-
void __iomem *dirout,
590
-
void __iomem *dirin,
591
-
unsigned long flags)
569
+
static int bgpio_setup_direction(struct gpio_generic_chip *chip,
570
+
const struct gpio_generic_chip_config *cfg)
592
571
{
593
-
if (dirout || dirin) {
594
-
gc->reg_dir_out = dirout;
595
-
gc->reg_dir_in = dirin;
596
-
if (flags & BGPIOF_NO_SET_ON_INPUT)
572
+
struct gpio_chip *gc = &chip->gc;
573
+
574
+
if (cfg->dirout || cfg->dirin) {
575
+
chip->reg_dir_out = cfg->dirout;
576
+
chip->reg_dir_in = cfg->dirin;
577
+
if (cfg->flags & BGPIOF_NO_SET_ON_INPUT)
597
578
gc->direction_output = bgpio_dir_out_dir_first;
598
579
else
599
580
gc->direction_output = bgpio_dir_out_val_first;
600
581
gc->direction_input = bgpio_dir_in;
601
582
gc->get_direction = bgpio_get_dir;
602
583
} else {
603
-
if (flags & BGPIOF_NO_OUTPUT)
584
+
if (cfg->flags & BGPIOF_NO_OUTPUT)
604
585
gc->direction_output = bgpio_dir_out_err;
605
586
else
606
587
gc->direction_output = bgpio_simple_dir_out;
607
588
608
-
if (flags & BGPIOF_NO_INPUT)
589
+
if (cfg->flags & BGPIOF_NO_INPUT)
609
590
gc->direction_input = bgpio_dir_in_err;
610
591
else
611
592
gc->direction_input = bgpio_simple_dir_in;
···
614
595
return 0;
615
596
}
616
597
617
-
static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
598
+
static int bgpio_request(struct gpio_chip *gc, unsigned int gpio_pin)
618
599
{
619
-
if (gpio_pin >= chip->ngpio)
600
+
struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
601
+
602
+
if (gpio_pin >= gc->ngpio)
620
603
return -EINVAL;
621
604
622
-
if (chip->bgpio_pinctrl)
623
-
return gpiochip_generic_request(chip, gpio_pin);
605
+
if (chip->pinctrl)
606
+
return gpiochip_generic_request(gc, gpio_pin);
624
607
625
608
return 0;
626
609
}
627
610
628
611
/**
629
-
* bgpio_init() - Initialize generic GPIO accessor functions
630
-
* @gc: the GPIO chip to set up
631
-
* @dev: the parent device of the new GPIO chip (compulsory)
632
-
* @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
633
-
* @dat: MMIO address for the register to READ the value of the GPIO lines, it
634
-
* is expected that a 1 in the corresponding bit in this register means the
635
-
* line is asserted
636
-
* @set: MMIO address for the register to SET the value of the GPIO lines, it is
637
-
* expected that we write the line with 1 in this register to drive the GPIO line
638
-
* high.
639
-
* @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
640
-
* expected that we write the line with 1 in this register to drive the GPIO line
641
-
* low. It is allowed to leave this address as NULL, in that case the SET register
642
-
* will be assumed to also clear the GPIO lines, by actively writing the line
643
-
* with 0.
644
-
* @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
645
-
* that setting a line to 1 in this register will turn that line into an
646
-
* output line. Conversely, setting the line to 0 will turn that line into
647
-
* an input.
648
-
* @dirin: MMIO address for the register to set this line as INPUT. It is assumed
649
-
* that setting a line to 1 in this register will turn that line into an
650
-
* input line. Conversely, setting the line to 0 will turn that line into
651
-
* an output.
652
-
* @flags: Different flags that will affect the behaviour of the device, such as
653
-
* endianness etc.
612
+
* gpio_generic_chip_init() - Initialize a generic GPIO chip.
613
+
* @chip: Generic GPIO chip to set up.
614
+
* @cfg: Generic GPIO chip configuration.
615
+
*
616
+
* Returns 0 on success, negative error number on failure.
654
617
*/
655
-
int bgpio_init(struct gpio_chip *gc, struct device *dev,
656
-
unsigned long sz, void __iomem *dat, void __iomem *set,
657
-
void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
658
-
unsigned long flags)
618
+
int gpio_generic_chip_init(struct gpio_generic_chip *chip,
619
+
const struct gpio_generic_chip_config *cfg)
659
620
{
621
+
struct gpio_chip *gc = &chip->gc;
622
+
unsigned long flags = cfg->flags;
623
+
struct device *dev = cfg->dev;
660
624
int ret;
661
625
662
-
if (!is_power_of_2(sz))
626
+
if (!is_power_of_2(cfg->sz))
663
627
return -EINVAL;
664
628
665
-
gc->bgpio_bits = sz * 8;
666
-
if (gc->bgpio_bits > BITS_PER_LONG)
629
+
chip->bits = cfg->sz * 8;
630
+
if (chip->bits > BITS_PER_LONG)
667
631
return -EINVAL;
668
632
669
-
raw_spin_lock_init(&gc->bgpio_lock);
633
+
raw_spin_lock_init(&chip->lock);
670
634
gc->parent = dev;
671
635
gc->label = dev_name(dev);
672
636
gc->base = -1;
673
637
gc->request = bgpio_request;
674
-
gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
638
+
chip->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
675
639
676
640
ret = gpiochip_get_ngpios(gc, dev);
677
641
if (ret)
678
-
gc->ngpio = gc->bgpio_bits;
642
+
gc->ngpio = chip->bits;
679
643
680
-
ret = bgpio_setup_io(gc, dat, set, clr, flags);
644
+
ret = bgpio_setup_io(chip, cfg);
681
645
if (ret)
682
646
return ret;
683
647
684
-
ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
648
+
ret = bgpio_setup_accessors(dev, chip,
649
+
flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
685
650
if (ret)
686
651
return ret;
687
652
688
-
ret = bgpio_setup_direction(gc, dirout, dirin, flags);
653
+
ret = bgpio_setup_direction(chip, cfg);
689
654
if (ret)
690
655
return ret;
691
656
692
657
if (flags & BGPIOF_PINCTRL_BACKEND) {
693
-
gc->bgpio_pinctrl = true;
658
+
chip->pinctrl = true;
694
659
/* Currently this callback is only used for pincontrol */
695
660
gc->free = gpiochip_generic_free;
696
661
}
697
662
698
-
gc->bgpio_data = gc->read_reg(gc->reg_dat);
663
+
chip->sdata = chip->read_reg(chip->reg_dat);
699
664
if (gc->set == bgpio_set_set &&
700
665
!(flags & BGPIOF_UNREADABLE_REG_SET))
701
-
gc->bgpio_data = gc->read_reg(gc->reg_set);
666
+
chip->sdata = chip->read_reg(chip->reg_set);
702
667
703
668
if (flags & BGPIOF_UNREADABLE_REG_DIR)
704
-
gc->bgpio_dir_unreadable = true;
669
+
chip->dir_unreadable = true;
705
670
706
671
/*
707
672
* Inspect hardware to find initial direction setting.
708
673
*/
709
-
if ((gc->reg_dir_out || gc->reg_dir_in) &&
674
+
if ((chip->reg_dir_out || chip->reg_dir_in) &&
710
675
!(flags & BGPIOF_UNREADABLE_REG_DIR)) {
711
-
if (gc->reg_dir_out)
712
-
gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
713
-
else if (gc->reg_dir_in)
714
-
gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
676
+
if (chip->reg_dir_out)
677
+
chip->sdir = chip->read_reg(chip->reg_dir_out);
678
+
else if (chip->reg_dir_in)
679
+
chip->sdir = ~chip->read_reg(chip->reg_dir_in);
715
680
/*
716
681
* If we have two direction registers, synchronise
717
682
* input setting to output setting, the library
718
683
* can not handle a line being input and output at
719
684
* the same time.
720
685
*/
721
-
if (gc->reg_dir_out && gc->reg_dir_in)
722
-
gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
686
+
if (chip->reg_dir_out && chip->reg_dir_in)
687
+
chip->write_reg(chip->reg_dir_in, ~chip->sdir);
723
688
}
724
689
725
690
return ret;
726
691
}
727
-
EXPORT_SYMBOL_GPL(bgpio_init);
692
+
EXPORT_SYMBOL_GPL(gpio_generic_chip_init);
728
693
729
694
#if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
730
695
+3
-2
drivers/gpio/gpio-mpc8xxx.c
+3
-2
drivers/gpio/gpio-mpc8xxx.c
···
71
71
mpc8xxx_gc->regs + GPIO_DIR);
72
72
val = gpio_generic_read_reg(&mpc8xxx_gc->chip,
73
73
mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
74
-
out_shadow = gc->bgpio_data & out_mask;
74
+
out_shadow = mpc8xxx_gc->chip.sdata & out_mask;
75
75
76
76
return !!((val | out_shadow) & mpc_pin2mask(gpio));
77
77
}
···
399
399
gpio_generic_write_reg(&mpc8xxx_gc->chip,
400
400
mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
401
401
/* Also, latch state of GPIOs configured as output by bootloader. */
402
-
gc->bgpio_data = gpio_generic_read_reg(&mpc8xxx_gc->chip,
402
+
mpc8xxx_gc->chip.sdata =
403
+
gpio_generic_read_reg(&mpc8xxx_gc->chip,
403
404
mpc8xxx_gc->regs + GPIO_DAT) &
404
405
gpio_generic_read_reg(&mpc8xxx_gc->chip,
405
406
mpc8xxx_gc->regs + GPIO_DIR);
-44
include/linux/gpio/driver.h
-44
include/linux/gpio/driver.h
···
388
388
* implies that if the chip supports IRQs, these IRQs need to be threaded
389
389
* as the chip access may sleep when e.g. reading out the IRQ status
390
390
* registers.
391
-
* @read_reg: reader function for generic GPIO
392
-
* @write_reg: writer function for generic GPIO
393
-
* @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
394
-
* line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
395
-
* generic GPIO core. It is for internal housekeeping only.
396
-
* @reg_dat: data (in) register for generic GPIO
397
-
* @reg_set: output set register (out=high) for generic GPIO
398
-
* @reg_clr: output clear register (out=low) for generic GPIO
399
-
* @reg_dir_out: direction out setting register for generic GPIO
400
-
* @reg_dir_in: direction in setting register for generic GPIO
401
-
* @bgpio_dir_unreadable: indicates that the direction register(s) cannot
402
-
* be read and we need to rely on out internal state tracking.
403
-
* @bgpio_pinctrl: the generic GPIO uses a pin control backend.
404
-
* @bgpio_bits: number of register bits used for a generic GPIO i.e.
405
-
* <register width> * 8
406
-
* @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
407
-
* shadowed and real data registers writes together.
408
-
* @bgpio_data: shadowed data register for generic GPIO to clear/set bits
409
-
* safely.
410
-
* @bgpio_dir: shadowed direction register for generic GPIO to clear/set
411
-
* direction safely. A "1" in this word means the line is set as
412
-
* output.
413
391
*
414
392
* A gpio_chip can help platforms abstract various sources of GPIOs so
415
393
* they can all be accessed through a common programming interface.
···
452
474
u16 offset;
453
475
const char *const *names;
454
476
bool can_sleep;
455
-
456
-
#if IS_ENABLED(CONFIG_GPIO_GENERIC)
457
-
unsigned long (*read_reg)(void __iomem *reg);
458
-
void (*write_reg)(void __iomem *reg, unsigned long data);
459
-
bool be_bits;
460
-
void __iomem *reg_dat;
461
-
void __iomem *reg_set;
462
-
void __iomem *reg_clr;
463
-
void __iomem *reg_dir_out;
464
-
void __iomem *reg_dir_in;
465
-
bool bgpio_dir_unreadable;
466
-
bool bgpio_pinctrl;
467
-
int bgpio_bits;
468
-
raw_spinlock_t bgpio_lock;
469
-
unsigned long bgpio_data;
470
-
unsigned long bgpio_dir;
471
-
#endif /* CONFIG_GPIO_GENERIC */
472
477
473
478
#ifdef CONFIG_GPIOLIB_IRQCHIP
474
479
/*
···
683
722
unsigned int parent_type);
684
723
685
724
#endif /* CONFIG_IRQ_DOMAIN_HIERARCHY */
686
-
687
-
int bgpio_init(struct gpio_chip *gc, struct device *dev,
688
-
unsigned long sz, void __iomem *dat, void __iomem *set,
689
-
void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
690
-
unsigned long flags);
691
725
692
726
#define BGPIOF_BIG_ENDIAN BIT(0)
693
727
#define BGPIOF_UNREADABLE_REG_SET BIT(1) /* reg_set is unreadable */
+45
-22
include/linux/gpio/generic.h
+45
-22
include/linux/gpio/generic.h
···
50
50
* struct gpio_generic_chip - Generic GPIO chip implementation.
51
51
* @gc: The underlying struct gpio_chip object, implementing low-level GPIO
52
52
* chip routines.
53
+
* @read_reg: reader function for generic GPIO
54
+
* @write_reg: writer function for generic GPIO
55
+
* @be_bits: if the generic GPIO has big endian bit order (bit 31 is
56
+
* representing line 0, bit 30 is line 1 ... bit 0 is line 31) this
57
+
* is set to true by the generic GPIO core. It is for internal
58
+
* housekeeping only.
59
+
* @reg_dat: data (in) register for generic GPIO
60
+
* @reg_set: output set register (out=high) for generic GPIO
61
+
* @reg_clr: output clear register (out=low) for generic GPIO
62
+
* @reg_dir_out: direction out setting register for generic GPIO
63
+
* @reg_dir_in: direction in setting register for generic GPIO
64
+
* @dir_unreadable: indicates that the direction register(s) cannot be read and
65
+
* we need to rely on out internal state tracking.
66
+
* @pinctrl: the generic GPIO uses a pin control backend.
67
+
* @bits: number of register bits used for a generic GPIO
68
+
* i.e. <register width> * 8
69
+
* @lock: used to lock chip->sdata. Also, this is needed to keep
70
+
* shadowed and real data registers writes together.
71
+
* @sdata: shadowed data register for generic GPIO to clear/set bits safely.
72
+
* @sdir: shadowed direction register for generic GPIO to clear/set direction
73
+
* safely. A "1" in this word means the line is set as output.
53
74
*/
54
75
struct gpio_generic_chip {
55
76
struct gpio_chip gc;
77
+
unsigned long (*read_reg)(void __iomem *reg);
78
+
void (*write_reg)(void __iomem *reg, unsigned long data);
79
+
bool be_bits;
80
+
void __iomem *reg_dat;
81
+
void __iomem *reg_set;
82
+
void __iomem *reg_clr;
83
+
void __iomem *reg_dir_out;
84
+
void __iomem *reg_dir_in;
85
+
bool dir_unreadable;
86
+
bool pinctrl;
87
+
int bits;
88
+
raw_spinlock_t lock;
89
+
unsigned long sdata;
90
+
unsigned long sdir;
56
91
};
57
92
58
93
static inline struct gpio_generic_chip *
···
96
61
return container_of(gc, struct gpio_generic_chip, gc);
97
62
}
98
63
99
-
/**
100
-
* gpio_generic_chip_init() - Initialize a generic GPIO chip.
101
-
* @chip: Generic GPIO chip to set up.
102
-
* @cfg: Generic GPIO chip configuration.
103
-
*
104
-
* Returns 0 on success, negative error number on failure.
105
-
*/
106
-
static inline int
107
-
gpio_generic_chip_init(struct gpio_generic_chip *chip,
108
-
const struct gpio_generic_chip_config *cfg)
109
-
{
110
-
return bgpio_init(&chip->gc, cfg->dev, cfg->sz, cfg->dat, cfg->set,
111
-
cfg->clr, cfg->dirout, cfg->dirin, cfg->flags);
112
-
}
64
+
int gpio_generic_chip_init(struct gpio_generic_chip *chip,
65
+
const struct gpio_generic_chip_config *cfg);
113
66
114
67
/**
115
68
* gpio_generic_chip_set() - Set the GPIO line value of the generic GPIO chip.
···
133
110
static inline unsigned long
134
111
gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg)
135
112
{
136
-
if (WARN_ON(!chip->gc.read_reg))
113
+
if (WARN_ON(!chip->read_reg))
137
114
return 0;
138
115
139
-
return chip->gc.read_reg(reg);
116
+
return chip->read_reg(reg);
140
117
}
141
118
142
119
/**
···
148
125
static inline void gpio_generic_write_reg(struct gpio_generic_chip *chip,
149
126
void __iomem *reg, unsigned long val)
150
127
{
151
-
if (WARN_ON(!chip->gc.write_reg))
128
+
if (WARN_ON(!chip->write_reg))
152
129
return;
153
130
154
-
chip->gc.write_reg(reg, val);
131
+
chip->write_reg(reg, val);
155
132
}
156
133
157
134
#define gpio_generic_chip_lock(gen_gc) \
158
-
raw_spin_lock(&(gen_gc)->gc.bgpio_lock)
135
+
raw_spin_lock(&(gen_gc)->lock)
159
136
160
137
#define gpio_generic_chip_unlock(gen_gc) \
161
-
raw_spin_unlock(&(gen_gc)->gc.bgpio_lock)
138
+
raw_spin_unlock(&(gen_gc)->lock)
162
139
163
140
#define gpio_generic_chip_lock_irqsave(gen_gc, flags) \
164
-
raw_spin_lock_irqsave(&(gen_gc)->gc.bgpio_lock, flags)
141
+
raw_spin_lock_irqsave(&(gen_gc)->lock, flags)
165
142
166
143
#define gpio_generic_chip_unlock_irqrestore(gen_gc, flags) \
167
-
raw_spin_unlock_irqrestore(&(gen_gc)->gc.bgpio_lock, flags)
144
+
raw_spin_unlock_irqrestore(&(gen_gc)->lock, flags)
168
145
169
146
DEFINE_LOCK_GUARD_1(gpio_generic_lock,
170
147
struct gpio_generic_chip,