tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon:
"Apologies for this being so late, but we've uncovered a few nasty
issues on arm64 which didn't settle down until yesterday and the fixes
all look suitable for 4.3. Of the four patches, three of them are
Cc'd to stable, with the remaining patch fixing an issue that only
took effect during the merge window.

Summary:

- Fix corruption in SWP emulation when STXR fails due to contention
- Fix MMU re-initialisation when resuming from a low-power state
- Fix stack unwinding code to match what ftrace expects
- Fix relocation code in the EFI stub when DRAM base is not 2MB aligned"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64/efi: do not assume DRAM base is aligned to 2 MB
Revert "ARM64: unwind: Fix PC calculation"
arm64: kernel: fix tcr_el1.t0sz restore on systems with extended idmap
arm64: compat: fix stxr failure case in SWP emulation

Linus Torvalds 9b971e77 7c0f488f

+35 -23
+9 -7
arch/arm64/kernel/armv8_deprecated.c
··· 284 284 __asm__ __volatile__( \ 285 285 ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \ 286 286 CONFIG_ARM64_PAN) \ 287 - " mov %w2, %w1\n" \ 288 - "0: ldxr"B" %w1, [%3]\n" \ 289 - "1: stxr"B" %w0, %w2, [%3]\n" \ 287 + "0: ldxr"B" %w2, [%3]\n" \ 288 + "1: stxr"B" %w0, %w1, [%3]\n" \ 290 289 " cbz %w0, 2f\n" \ 291 290 " mov %w0, %w4\n" \ 291 + " b 3f\n" \ 292 292 "2:\n" \ 293 + " mov %w1, %w2\n" \ 294 + "3:\n" \ 293 295 " .pushsection .fixup,\"ax\"\n" \ 294 296 " .align 2\n" \ 295 - "3: mov %w0, %w5\n" \ 296 - " b 2b\n" \ 297 + "4: mov %w0, %w5\n" \ 298 + " b 3b\n" \ 297 299 " .popsection" \ 298 300 " .pushsection __ex_table,\"a\"\n" \ 299 301 " .align 3\n" \ 300 - " .quad 0b, 3b\n" \ 301 - " .quad 1b, 3b\n" \ 302 + " .quad 0b, 4b\n" \ 303 + " .quad 1b, 4b\n" \ 302 304 " .popsection\n" \ 303 305 ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \ 304 306 CONFIG_ARM64_PAN) \
+12 -2
arch/arm64/kernel/efi-stub.c
··· 25 25 unsigned long kernel_size, kernel_memsize = 0; 26 26 unsigned long nr_pages; 27 27 void *old_image_addr = (void *)*image_addr; 28 + unsigned long preferred_offset; 29 + 30 + /* 31 + * The preferred offset of the kernel Image is TEXT_OFFSET bytes beyond 32 + * a 2 MB aligned base, which itself may be lower than dram_base, as 33 + * long as the resulting offset equals or exceeds it. 34 + */ 35 + preferred_offset = round_down(dram_base, SZ_2M) + TEXT_OFFSET; 36 + if (preferred_offset < dram_base) 37 + preferred_offset += SZ_2M; 28 38 29 39 /* Relocate the image, if required. */ 30 40 kernel_size = _edata - _text; 31 - if (*image_addr != (dram_base + TEXT_OFFSET)) { 41 + if (*image_addr != preferred_offset) { 32 42 kernel_memsize = kernel_size + (_end - _edata); 33 43 34 44 /* ··· 52 42 * Mustang), we can still place the kernel at the address 53 43 * 'dram_base + TEXT_OFFSET'. 54 44 */ 55 - *image_addr = *reserve_addr = dram_base + TEXT_OFFSET; 45 + *image_addr = *reserve_addr = preferred_offset; 56 46 nr_pages = round_up(kernel_memsize, EFI_ALLOC_ALIGN) / 57 47 EFI_PAGE_SIZE; 58 48 status = efi_call_early(allocate_pages, EFI_ALLOCATE_ADDRESS,
+1 -5
arch/arm64/kernel/stacktrace.c
··· 48 48 49 49 frame->sp = fp + 0x10; 50 50 frame->fp = *(unsigned long *)(fp); 51 - /* 52 - * -4 here because we care about the PC at time of bl, 53 - * not where the return will go. 54 - */ 55 - frame->pc = *(unsigned long *)(fp + 8) - 4; 51 + frame->pc = *(unsigned long *)(fp + 8); 56 52 57 53 return 0; 58 54 }
+13 -9
arch/arm64/kernel/suspend.c
··· 80 80 if (ret == 0) { 81 81 /* 82 82 * We are resuming from reset with TTBR0_EL1 set to the 83 - * idmap to enable the MMU; restore the active_mm mappings in 84 - * TTBR0_EL1 unless the active_mm == &init_mm, in which case 85 - * the thread entered cpu_suspend with TTBR0_EL1 set to 86 - * reserved TTBR0 page tables and should be restored as such. 83 + * idmap to enable the MMU; set the TTBR0 to the reserved 84 + * page tables to prevent speculative TLB allocations, flush 85 + * the local tlb and set the default tcr_el1.t0sz so that 86 + * the TTBR0 address space set-up is properly restored. 87 + * If the current active_mm != &init_mm we entered cpu_suspend 88 + * with mappings in TTBR0 that must be restored, so we switch 89 + * them back to complete the address space configuration 90 + * restoration before returning. 87 91 */ 88 - if (mm == &init_mm) 89 - cpu_set_reserved_ttbr0(); 90 - else 91 - cpu_switch_mm(mm->pgd, mm); 92 - 92 + cpu_set_reserved_ttbr0(); 93 93 flush_tlb_all(); 94 + cpu_set_default_tcr_t0sz(); 95 + 96 + if (mm != &init_mm) 97 + cpu_switch_mm(mm->pgd, mm); 94 98 95 99 /* 96 100 * Restore per-cpu offset before any kernel