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dma-mapping: Clarify valid conditions for CPU cache line overlap

Rename the DMA_ATTR_CPU_CACHE_CLEAN attribute to better reflect that it
is debugging aid to inform DMA core code that CPU cache line overlaps are
allowed, and refine the documentation describing its use.

Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lore.kernel.org/r/20260316-dma-debug-overlap-v3-3-1dde90a7f08b@nvidia.com

authored by

Leon Romanovsky and committed by
Marek Szyprowski 9bb0a4d6 6f45b160

+24 -18
+13 -7
Documentation/core-api/dma-attributes.rst
··· 149 149 DMA_ATTR_MMIO will not perform any cache flushing. The address 150 150 provided must never be mapped cacheable into the CPU. 151 151 152 - DMA_ATTR_CPU_CACHE_CLEAN 153 - ------------------------ 152 + DMA_ATTR_DEBUGGING_IGNORE_CACHELINES 153 + ------------------------------------ 154 154 155 - This attribute indicates the CPU will not dirty any cacheline overlapping this 156 - DMA_FROM_DEVICE/DMA_BIDIRECTIONAL buffer while it is mapped. This allows 157 - multiple small buffers to safely share a cacheline without risk of data 158 - corruption, suppressing DMA debug warnings about overlapping mappings. 159 - All mappings sharing a cacheline should have this attribute. 155 + This attribute indicates that CPU cache lines may overlap for buffers mapped 156 + with DMA_FROM_DEVICE or DMA_BIDIRECTIONAL. 157 + 158 + Such overlap may occur when callers map multiple small buffers that reside 159 + within the same cache line. In this case, callers must guarantee that the CPU 160 + will not dirty these cache lines after the mappings are established. When this 161 + condition is met, multiple buffers can safely share a cache line without risking 162 + data corruption. 163 + 164 + All mappings that share a cache line must set this attribute to suppress DMA 165 + debug warnings about overlapping mappings.
+5 -5
drivers/virtio/virtio_ring.c
··· 2912 2912 * @data: the token identifying the buffer. 2913 2913 * @gfp: how to do memory allocations (if necessary). 2914 2914 * 2915 - * Same as virtqueue_add_inbuf but passes DMA_ATTR_CPU_CACHE_CLEAN to indicate 2916 - * that the CPU will not dirty any cacheline overlapping this buffer while it 2917 - * is available, and to suppress overlapping cacheline warnings in DMA debug 2918 - * builds. 2915 + * Same as virtqueue_add_inbuf but passes DMA_ATTR_DEBUGGING_IGNORE_CACHELINES 2916 + * to indicate that the CPU will not dirty any cacheline overlapping this buffer 2917 + * while it is available, and to suppress overlapping cacheline warnings in DMA 2918 + * debug builds. 2919 2919 * 2920 2920 * Caller must ensure we don't call this with other virtqueue operations 2921 2921 * at the same time (except where noted). ··· 2928 2928 gfp_t gfp) 2929 2929 { 2930 2930 return virtqueue_add(vq, &sg, num, 0, 1, data, NULL, false, gfp, 2931 - DMA_ATTR_CPU_CACHE_CLEAN); 2931 + DMA_ATTR_DEBUGGING_IGNORE_CACHELINES); 2932 2932 } 2933 2933 EXPORT_SYMBOL_GPL(virtqueue_add_inbuf_cache_clean); 2934 2934
+4 -4
include/linux/dma-mapping.h
··· 80 80 #define DMA_ATTR_MMIO (1UL << 10) 81 81 82 82 /* 83 - * DMA_ATTR_CPU_CACHE_CLEAN: Indicates the CPU will not dirty any cacheline 84 - * overlapping this buffer while it is mapped for DMA. All mappings sharing 85 - * a cacheline must have this attribute for this to be considered safe. 83 + * DMA_ATTR_DEBUGGING_IGNORE_CACHELINES: Indicates the CPU cache line can be 84 + * overlapped. All mappings sharing a cacheline must have this attribute for 85 + * this to be considered safe. 86 86 */ 87 - #define DMA_ATTR_CPU_CACHE_CLEAN (1UL << 11) 87 + #define DMA_ATTR_DEBUGGING_IGNORE_CACHELINES (1UL << 11) 88 88 89 89 /* 90 90 * A dma_addr_t can hold any valid DMA or bus address for the platform. It can
+1 -1
include/trace/events/dma.h
··· 33 33 { DMA_ATTR_NO_WARN, "NO_WARN" }, \ 34 34 { DMA_ATTR_PRIVILEGED, "PRIVILEGED" }, \ 35 35 { DMA_ATTR_MMIO, "MMIO" }, \ 36 - { DMA_ATTR_CPU_CACHE_CLEAN, "CACHE_CLEAN" }) 36 + { DMA_ATTR_DEBUGGING_IGNORE_CACHELINES, "CACHELINES_OVERLAP" }) 37 37 38 38 DECLARE_EVENT_CLASS(dma_map, 39 39 TP_PROTO(struct device *dev, phys_addr_t phys_addr, dma_addr_t dma_addr,
+1 -1
kernel/dma/debug.c
··· 601 601 unsigned long flags; 602 602 int rc; 603 603 604 - entry->is_cache_clean = !!(attrs & DMA_ATTR_CPU_CACHE_CLEAN); 604 + entry->is_cache_clean = attrs & DMA_ATTR_DEBUGGING_IGNORE_CACHELINES; 605 605 606 606 bucket = get_hash_bucket(entry, &flags); 607 607 hash_bucket_add(bucket, entry);