+11 -38

Documentation/devicetree/bindings/Makefile

reviewed

··· 3 3 DT_EXTRACT_EX ?= dt-extract-example 4 4 DT_MK_SCHEMA ?= dt-mk-schema 5 5 6 6 - DT_SCHEMA_LINT = $(shell which yamllint) 6 6 + DT_SCHEMA_LINT = $(shell which yamllint || \ 7 7 + echo "warning: python package 'yamllint' not installed, skipping" >&2) 7 8 8 8 - DT_SCHEMA_MIN_VERSION = 2021.2.1 9 9 + DT_SCHEMA_MIN_VERSION = 2022.3 9 10 10 11 PHONY += check_dtschema_version 11 12 check_dtschema_version: ··· 25 24 $(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE 26 25 $(call if_changed,extract_ex) 27 26 28 28 - # Use full schemas when checking %.example.dts 29 29 - DT_TMP_SCHEMA := $(obj)/processed-schema-examples.json 30 30 - 31 27 find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \ 32 32 - -name 'processed-schema*' ! \ 33 33 - -name '*.example.dt.yaml' \) 28 28 + -name 'processed-schema*' \) 34 29 35 35 - ifeq ($(DT_SCHEMA_FILES),) 36 36 - find_cmd = $(find_all_cmd) 37 37 - else 38 38 - find_cmd = echo $(addprefix $(srctree)/, $(DT_SCHEMA_FILES)) 39 39 - endif 30 30 + find_cmd = $(find_all_cmd) | grep -F "$(DT_SCHEMA_FILES)" 31 31 + CHK_DT_DOCS := $(shell $(find_cmd)) 40 32 41 33 quiet_cmd_yamllint = LINT $(src) 42 34 cmd_yamllint = ($(find_cmd) | \ ··· 66 72 # Disable undocumented compatible checks until warning free 67 73 override DT_CHECKER_FLAGS ?= 68 74 69 69 - $(obj)/processed-schema-examples.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE 75 75 + $(obj)/processed-schema.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE 70 76 $(call if_changed_rule,chkdt) 71 77 72 72 - ifeq ($(DT_SCHEMA_FILES),) 73 73 - 74 74 - # Unless DT_SCHEMA_FILES is specified, use the full schema for dtbs_check too. 75 75 - # Just copy processed-schema-examples.json 76 76 - 77 77 - $(obj)/processed-schema.json: $(obj)/processed-schema-examples.json FORCE 78 78 - $(call if_changed,copy) 79 79 - 80 80 - DT_SCHEMA_FILES = $(DT_DOCS) 81 81 - 82 82 - else 83 83 - 84 84 - # If DT_SCHEMA_FILES is specified, use it for processed-schema.json 85 85 - 86 86 - $(obj)/processed-schema.json: DT_MK_SCHEMA_FLAGS := -u 87 87 - $(obj)/processed-schema.json: $(DT_SCHEMA_FILES) check_dtschema_version FORCE 88 88 - $(call if_changed,mk_schema) 89 89 - 90 90 - endif 91 91 - 92 92 - always-$(CHECK_DT_BINDING) += processed-schema-examples.json 93 93 - always-$(CHECK_DTBS) += processed-schema.json 94 94 - always-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES)) 95 95 - always-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES)) 78 78 + always-y += processed-schema.json 79 79 + always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dts, $(CHK_DT_DOCS)) 80 80 + always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dtb, $(CHK_DT_DOCS)) 96 81 97 82 # Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of 98 83 # build artifacts here before they are processed by scripts/Makefile.clean 99 84 clean-files = $(shell find $(obj) \( -name '*.example.dts' -o \ 100 100 - -name '*.example.dt.yaml' \) -delete 2>/dev/null) 85 85 + -name '*.example.dtb' \) -delete 2>/dev/null)

+5

Documentation/devicetree/bindings/arm/arm,cci-400.yaml

reviewed

··· 119 119 arm,hbi = <0x249>; 120 120 interrupt-parent = <&gic>; 121 121 122 122 + gic: interrupt-controller { 123 123 + interrupt-controller; 124 124 + #interrupt-cells = <3>; 125 125 + }; 126 126 + 122 127 /* 123 128 * This CCI node corresponds to a CCI component whose control 124 129 * registers sits at address 0x000000002c090000.

+2 -2

Documentation/devicetree/bindings/arm/cpu-capacity.txt

reviewed

··· 62 62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024) 63 63 are 1024 and 578 for cluster0 and cluster1. Further normalization 64 64 is done by the operating system based on cluster0@max-freq=1100 and 65 65 - custer1@max-freq=850, final capacities are 1024 for cluster0 and 66 66 - 446 for cluster1 (576*850/1100). 65 65 + cluster1@max-freq=850, final capacities are 1024 for cluster0 and 66 66 + 446 for cluster1 (578*850/1100). 67 67 68 68 cpus { 69 69 #address-cells = <2>;

+7 -5

Documentation/devicetree/bindings/arm/cpus.yaml

reviewed

··· 233 233 - ti,am4372 234 234 235 235 cpu-release-addr: 236 236 - $ref: '/schemas/types.yaml#/definitions/uint64' 237 237 - 236 236 + oneOf: 237 237 + - $ref: '/schemas/types.yaml#/definitions/uint32' 238 238 + - $ref: '/schemas/types.yaml#/definitions/uint64' 238 239 description: 240 240 + The DT specification defines this as 64-bit always, but some 32-bit Arm 241 241 + systems have used a 32-bit value which must be supported. 239 242 Required for systems that have an "enable-method" 240 243 property value of "spin-table". 241 241 - On ARM v8 64-bit systems must be a two cell 242 242 - property identifying a 64-bit zero-initialised 243 243 - memory location. 244 244 245 245 cpu-idle-states: 246 246 $ref: '/schemas/types.yaml#/definitions/phandle-array' 247 247 + items: 248 248 + maxItems: 1 247 249 description: | 248 250 List of phandles to idle state nodes supported 249 251 by this cpu (see ./idle-states.yaml).

-38

Documentation/devicetree/bindings/arm/fw-cfg.txt

reviewed

··· 1 1 - * QEMU Firmware Configuration bindings for ARM 2 2 - 3 3 - QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets 4 4 - provide the following Firmware Configuration interface on the "virt" machine 5 5 - type: 6 6 - 7 7 - - A write-only, 16-bit wide selector (or control) register, 8 8 - - a read-write, 64-bit wide data register. 9 9 - 10 10 - QEMU exposes the control and data register to ARM guests as memory mapped 11 11 - registers; their location is communicated to the guest's UEFI firmware in the 12 12 - DTB that QEMU places at the bottom of the guest's DRAM. 13 13 - 14 14 - The authoritative guest-side hardware interface documentation to the fw_cfg 15 15 - device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree. 16 16 - 17 17 - 18 18 - Required properties: 19 19 - 20 20 - - compatible: "qemu,fw-cfg-mmio". 21 21 - 22 22 - - reg: the MMIO region used by the device. 23 23 - * Bytes 0x0 to 0x7 cover the data register. 24 24 - * Bytes 0x8 to 0x9 cover the selector register. 25 25 - * Further registers may be appended to the region in case of future interface 26 26 - revisions / feature bits. 27 27 - 28 28 - Example: 29 29 - 30 30 - / { 31 31 - #size-cells = <0x2>; 32 32 - #address-cells = <0x2>; 33 33 - 34 34 - fw-cfg@9020000 { 35 35 - compatible = "qemu,fw-cfg-mmio"; 36 36 - reg = <0x0 0x9020000 0x0 0xa>; 37 37 - }; 38 38 - };

+40 -40

Documentation/devicetree/bindings/arm/idle-states.yaml

reviewed

··· 337 337 compatible = "arm,cortex-a57"; 338 338 reg = <0x0 0x0>; 339 339 enable-method = "psci"; 340 340 - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 341 341 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; 340 340 + cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, 341 341 + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; 342 342 }; 343 343 344 344 cpu@1 { ··· 346 346 compatible = "arm,cortex-a57"; 347 347 reg = <0x0 0x1>; 348 348 enable-method = "psci"; 349 349 - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 350 350 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; 349 349 + cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, 350 350 + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; 351 351 }; 352 352 353 353 cpu@100 { ··· 355 355 compatible = "arm,cortex-a57"; 356 356 reg = <0x0 0x100>; 357 357 enable-method = "psci"; 358 358 - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 359 359 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; 358 358 + cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, 359 359 + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; 360 360 }; 361 361 362 362 cpu@101 { ··· 364 364 compatible = "arm,cortex-a57"; 365 365 reg = <0x0 0x101>; 366 366 enable-method = "psci"; 367 367 - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 368 368 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; 367 367 + cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, 368 368 + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; 369 369 }; 370 370 371 371 cpu@10000 { ··· 373 373 compatible = "arm,cortex-a57"; 374 374 reg = <0x0 0x10000>; 375 375 enable-method = "psci"; 376 376 - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 377 377 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; 376 376 + cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, 377 377 + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; 378 378 }; 379 379 380 380 cpu@10001 { ··· 382 382 compatible = "arm,cortex-a57"; 383 383 reg = <0x0 0x10001>; 384 384 enable-method = "psci"; 385 385 - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 386 386 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; 385 385 + cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, 386 386 + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; 387 387 }; 388 388 389 389 cpu@10100 { ··· 391 391 compatible = "arm,cortex-a57"; 392 392 reg = <0x0 0x10100>; 393 393 enable-method = "psci"; 394 394 - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 395 395 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; 394 394 + cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, 395 395 + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; 396 396 }; 397 397 398 398 cpu@10101 { ··· 400 400 compatible = "arm,cortex-a57"; 401 401 reg = <0x0 0x10101>; 402 402 enable-method = "psci"; 403 403 - cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 404 404 - &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; 403 403 + cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>, 404 404 + <&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>; 405 405 }; 406 406 407 407 cpu@100000000 { ··· 409 409 compatible = "arm,cortex-a53"; 410 410 reg = <0x1 0x0>; 411 411 enable-method = "psci"; 412 412 - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 413 413 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; 412 412 + cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, 413 413 + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; 414 414 }; 415 415 416 416 cpu@100000001 { ··· 418 418 compatible = "arm,cortex-a53"; 419 419 reg = <0x1 0x1>; 420 420 enable-method = "psci"; 421 421 - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 422 422 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; 421 421 + cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, 422 422 + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; 423 423 }; 424 424 425 425 cpu@100000100 { ··· 427 427 compatible = "arm,cortex-a53"; 428 428 reg = <0x1 0x100>; 429 429 enable-method = "psci"; 430 430 - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 431 431 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; 430 430 + cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, 431 431 + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; 432 432 }; 433 433 434 434 cpu@100000101 { ··· 436 436 compatible = "arm,cortex-a53"; 437 437 reg = <0x1 0x101>; 438 438 enable-method = "psci"; 439 439 - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 440 440 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; 439 439 + cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, 440 440 + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; 441 441 }; 442 442 443 443 cpu@100010000 { ··· 445 445 compatible = "arm,cortex-a53"; 446 446 reg = <0x1 0x10000>; 447 447 enable-method = "psci"; 448 448 - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 449 449 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; 448 448 + cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, 449 449 + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; 450 450 }; 451 451 452 452 cpu@100010001 { ··· 454 454 compatible = "arm,cortex-a53"; 455 455 reg = <0x1 0x10001>; 456 456 enable-method = "psci"; 457 457 - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 458 458 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; 457 457 + cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, 458 458 + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; 459 459 }; 460 460 461 461 cpu@100010100 { ··· 463 463 compatible = "arm,cortex-a53"; 464 464 reg = <0x1 0x10100>; 465 465 enable-method = "psci"; 466 466 - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 467 467 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; 466 466 + cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, 467 467 + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; 468 468 }; 469 469 470 470 cpu@100010101 { ··· 472 472 compatible = "arm,cortex-a53"; 473 473 reg = <0x1 0x10101>; 474 474 enable-method = "psci"; 475 475 - cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 476 476 - &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; 475 475 + cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>, 476 476 + <&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>; 477 477 }; 478 478 479 479 idle-states { ··· 567 567 device_type = "cpu"; 568 568 compatible = "arm,cortex-a15"; 569 569 reg = <0x0>; 570 570 - cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; 570 570 + cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>; 571 571 }; 572 572 573 573 cpu@1 { 574 574 device_type = "cpu"; 575 575 compatible = "arm,cortex-a15"; 576 576 reg = <0x1>; 577 577 - cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; 577 577 + cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>; 578 578 }; 579 579 580 580 cpu@2 { 581 581 device_type = "cpu"; 582 582 compatible = "arm,cortex-a15"; 583 583 reg = <0x2>; 584 584 - cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; 584 584 + cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>; 585 585 }; 586 586 587 587 cpu@3 { 588 588 device_type = "cpu"; 589 589 compatible = "arm,cortex-a15"; 590 590 reg = <0x3>; 591 591 - cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>; 591 591 + cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>; 592 592 }; 593 593 594 594 cpu@100 { 595 595 device_type = "cpu"; 596 596 compatible = "arm,cortex-a7"; 597 597 reg = <0x100>; 598 598 - cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; 598 598 + cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>; 599 599 }; 600 600 601 601 cpu@101 { 602 602 device_type = "cpu"; 603 603 compatible = "arm,cortex-a7"; 604 604 reg = <0x101>; 605 605 - cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; 605 605 + cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>; 606 606 }; 607 607 608 608 cpu@102 { 609 609 device_type = "cpu"; 610 610 compatible = "arm,cortex-a7"; 611 611 reg = <0x102>; 612 612 - cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; 612 612 + cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>; 613 613 }; 614 614 615 615 cpu@103 { 616 616 device_type = "cpu"; 617 617 compatible = "arm,cortex-a7"; 618 618 reg = <0x103>; 619 619 - cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>; 619 619 + cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>; 620 620 }; 621 621 622 622 idle-states {

+20

Documentation/devicetree/bindings/arm/linux,dummy-virt.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/arm/linux,dummy-virt.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: QEMU virt machine 8 8 + 9 9 + maintainers: 10 10 + - Rob Herring <robh@kernel.org> 11 11 + 12 12 + properties: 13 13 + $nodename: 14 14 + const: "/" 15 15 + compatible: 16 16 + const: linux,dummy-virt 17 17 + 18 18 + additionalProperties: true 19 19 + 20 20 + ...

+2

Documentation/devicetree/bindings/arm/pmu.yaml

reviewed

··· 68 68 69 69 interrupt-affinity: 70 70 $ref: /schemas/types.yaml#/definitions/phandle-array 71 71 + items: 72 72 + maxItems: 1 71 73 description: 72 74 When using SPIs, specifies a list of phandles to CPU 73 75 nodes corresponding directly to the affinity of

-79

Documentation/devicetree/bindings/ata/ahci-platform.txt

reviewed

··· 1 1 - * AHCI SATA Controller 2 2 - 3 3 - SATA nodes are defined to describe on-chip Serial ATA controllers. 4 4 - Each SATA controller should have its own node. 5 5 - 6 6 - It is possible, but not required, to represent each port as a sub-node. 7 7 - It allows to enable each port independently when dealing with multiple 8 8 - PHYs. 9 9 - 10 10 - Required properties: 11 11 - - compatible : compatible string, one of: 12 12 - - "brcm,iproc-ahci" 13 13 - - "hisilicon,hisi-ahci" 14 14 - - "cavium,octeon-7130-ahci" 15 15 - - "ibm,476gtr-ahci" 16 16 - - "marvell,armada-380-ahci" 17 17 - - "marvell,armada-3700-ahci" 18 18 - - "snps,dwc-ahci" 19 19 - - "snps,spear-ahci" 20 20 - - "generic-ahci" 21 21 - - interrupts : <interrupt mapping for SATA IRQ> 22 22 - - reg : <registers mapping> 23 23 - 24 24 - Please note that when using "generic-ahci" you must also specify a SoC specific 25 25 - compatible: 26 26 - compatible = "manufacturer,soc-model-ahci", "generic-ahci"; 27 27 - 28 28 - Optional properties: 29 29 - - dma-coherent : Present if dma operations are coherent 30 30 - - clocks : a list of phandle + clock specifier pairs 31 31 - - resets : a list of phandle + reset specifier pairs 32 32 - - target-supply : regulator for SATA target power 33 33 - - phy-supply : regulator for PHY power 34 34 - - phys : reference to the SATA PHY node 35 35 - - phy-names : must be "sata-phy" 36 36 - - ahci-supply : regulator for AHCI controller 37 37 - - ports-implemented : Mask that indicates which ports that the HBA supports 38 38 - are available for software to use. Useful if PORTS_IMPL 39 39 - is not programmed by the BIOS, which is true with 40 40 - some embedded SOC's. 41 41 - 42 42 - Required properties when using sub-nodes: 43 43 - - #address-cells : number of cells to encode an address 44 44 - - #size-cells : number of cells representing the size of an address 45 45 - 46 46 - Sub-nodes required properties: 47 47 - - reg : the port number 48 48 - And at least one of the following properties: 49 49 - - phys : reference to the SATA PHY node 50 50 - - target-supply : regulator for SATA target power 51 51 - 52 52 - Examples: 53 53 - sata@ffe08000 { 54 54 - compatible = "snps,spear-ahci"; 55 55 - reg = <0xffe08000 0x1000>; 56 56 - interrupts = <115>; 57 57 - }; 58 58 - 59 59 - With sub-nodes: 60 60 - sata@f7e90000 { 61 61 - compatible = "marvell,berlin2q-achi", "generic-ahci"; 62 62 - reg = <0xe90000 0x1000>; 63 63 - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 64 64 - clocks = <&chip CLKID_SATA>; 65 65 - #address-cells = <1>; 66 66 - #size-cells = <0>; 67 67 - 68 68 - sata0: sata-port@0 { 69 69 - reg = <0>; 70 70 - phys = <&sata_phy 0>; 71 71 - target-supply = <&reg_sata0>; 72 72 - }; 73 73 - 74 74 - sata1: sata-port@1 { 75 75 - reg = <1>; 76 76 - phys = <&sata_phy 1>; 77 77 - target-supply = <&reg_sata1>;; 78 78 - }; 79 79 - };

+189

Documentation/devicetree/bindings/ata/ahci-platform.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/ata/ahci-platform.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: AHCI SATA Controller 8 8 + 9 9 + description: | 10 10 + SATA nodes are defined to describe on-chip Serial ATA controllers. 11 11 + Each SATA controller should have its own node. 12 12 + 13 13 + It is possible, but not required, to represent each port as a sub-node. 14 14 + It allows to enable each port independently when dealing with multiple 15 15 + PHYs. 16 16 + 17 17 + maintainers: 18 18 + - Hans de Goede <hdegoede@redhat.com> 19 19 + - Jens Axboe <axboe@kernel.dk> 20 20 + 21 21 + select: 22 22 + properties: 23 23 + compatible: 24 24 + contains: 25 25 + enum: 26 26 + - brcm,iproc-ahci 27 27 + - cavium,octeon-7130-ahci 28 28 + - hisilicon,hisi-ahci 29 29 + - ibm,476gtr-ahci 30 30 + - marvell,armada-3700-ahci 31 31 + - marvell,armada-8k-ahci 32 32 + - marvell,berlin2q-ahci 33 33 + - snps,dwc-ahci 34 34 + - snps,spear-ahci 35 35 + required: 36 36 + - compatible 37 37 + 38 38 + allOf: 39 39 + - $ref: "sata-common.yaml#" 40 40 + 41 41 + 42 42 + properties: 43 43 + compatible: 44 44 + oneOf: 45 45 + - items: 46 46 + - enum: 47 47 + - brcm,iproc-ahci 48 48 + - marvell,armada-8k-ahci 49 49 + - marvell,berlin2-ahci 50 50 + - marvell,berlin2q-ahci 51 51 + - const: generic-ahci 52 52 + - items: 53 53 + - enum: 54 54 + - rockchip,rk3568-dwc-ahci 55 55 + - const: snps,dwc-ahci 56 56 + - enum: 57 57 + - cavium,octeon-7130-ahci 58 58 + - hisilicon,hisi-ahci 59 59 + - ibm,476gtr-ahci 60 60 + - marvell,armada-3700-ahci 61 61 + - snps,dwc-ahci 62 62 + - snps,spear-ahci 63 63 + 64 64 + reg: 65 65 + minItems: 1 66 66 + maxItems: 2 67 67 + 68 68 + reg-names: 69 69 + maxItems: 1 70 70 + 71 71 + clocks: 72 72 + description: 73 73 + Clock IDs array as required by the controller. 74 74 + minItems: 1 75 75 + maxItems: 3 76 76 + 77 77 + clock-names: 78 78 + description: 79 79 + Names of clocks corresponding to IDs in the clock property. 80 80 + minItems: 1 81 81 + maxItems: 3 82 82 + 83 83 + interrupts: 84 84 + maxItems: 1 85 85 + 86 86 + ahci-supply: 87 87 + description: 88 88 + regulator for AHCI controller 89 89 + 90 90 + dma-coherent: true 91 91 + 92 92 + phy-supply: 93 93 + description: 94 94 + regulator for PHY power 95 95 + 96 96 + phys: 97 97 + description: 98 98 + List of all PHYs on this controller 99 99 + maxItems: 1 100 100 + 101 101 + phy-names: 102 102 + description: 103 103 + Name specifier for the PHYs 104 104 + maxItems: 1 105 105 + 106 106 + ports-implemented: 107 107 + $ref: '/schemas/types.yaml#/definitions/uint32' 108 108 + description: | 109 109 + Mask that indicates which ports that the HBA supports 110 110 + are available for software to use. Useful if PORTS_IMPL 111 111 + is not programmed by the BIOS, which is true with 112 112 + some embedded SoCs. 113 113 + maximum: 0x1f 114 114 + 115 115 + power-domains: 116 116 + maxItems: 1 117 117 + 118 118 + resets: 119 119 + maxItems: 1 120 120 + 121 121 + target-supply: 122 122 + description: 123 123 + regulator for SATA target power 124 124 + 125 125 + required: 126 126 + - compatible 127 127 + - reg 128 128 + - interrupts 129 129 + 130 130 + patternProperties: 131 131 + "^sata-port@[0-9a-f]+$": 132 132 + type: object 133 133 + additionalProperties: false 134 134 + description: 135 135 + Subnode with configuration of the Ports. 136 136 + 137 137 + properties: 138 138 + reg: 139 139 + maxItems: 1 140 140 + 141 141 + phys: 142 142 + maxItems: 1 143 143 + 144 144 + phy-names: 145 145 + maxItems: 1 146 146 + 147 147 + target-supply: 148 148 + description: 149 149 + regulator for SATA target power 150 150 + 151 151 + required: 152 152 + - reg 153 153 + 154 154 + anyOf: 155 155 + - required: [ phys ] 156 156 + - required: [ target-supply ] 157 157 + 158 158 + unevaluatedProperties: false 159 159 + 160 160 + examples: 161 161 + - | 162 162 + sata@ffe08000 { 163 163 + compatible = "snps,spear-ahci"; 164 164 + reg = <0xffe08000 0x1000>; 165 165 + interrupts = <115>; 166 166 + }; 167 167 + - | 168 168 + #include <dt-bindings/interrupt-controller/arm-gic.h> 169 169 + #include <dt-bindings/clock/berlin2q.h> 170 170 + sata@f7e90000 { 171 171 + compatible = "marvell,berlin2q-ahci", "generic-ahci"; 172 172 + reg = <0xf7e90000 0x1000>; 173 173 + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 174 174 + clocks = <&chip CLKID_SATA>; 175 175 + #address-cells = <1>; 176 176 + #size-cells = <0>; 177 177 + 178 178 + sata0: sata-port@0 { 179 179 + reg = <0>; 180 180 + phys = <&sata_phy 0>; 181 181 + target-supply = <&reg_sata0>; 182 182 + }; 183 183 + 184 184 + sata1: sata-port@1 { 185 185 + reg = <1>; 186 186 + phys = <&sata_phy 1>; 187 187 + target-supply = <&reg_sata1>; 188 188 + }; 189 189 + };

-55

Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt

reviewed

··· 1 1 - * Cortina Systems Gemini SATA Bridge 2 2 - 3 3 - The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that 4 4 - takes two Faraday Technology FTIDE010 PATA controllers and bridges 5 5 - them in different configurations to two SATA ports. 6 6 - 7 7 - Required properties: 8 8 - - compatible: should be 9 9 - "cortina,gemini-sata-bridge" 10 10 - - reg: registers and size for the block 11 11 - - resets: phandles to the reset lines for both SATA bridges 12 12 - - reset-names: must be "sata0", "sata1" 13 13 - - clocks: phandles to the compulsory peripheral clocks 14 14 - - clock-names: must be "SATA0_PCLK", "SATA1_PCLK" 15 15 - - syscon: a phandle to the global Gemini system controller 16 16 - - cortina,gemini-ata-muxmode: tell the desired multiplexing mode for 17 17 - the ATA controller and SATA bridges. Values 0..3: 18 18 - Mode 0: ata0 master <-> sata0 19 19 - ata1 master <-> sata1 20 20 - ata0 slave interface brought out on IDE pads 21 21 - Mode 1: ata0 master <-> sata0 22 22 - ata1 master <-> sata1 23 23 - ata1 slave interface brought out on IDE pads 24 24 - Mode 2: ata1 master <-> sata1 25 25 - ata1 slave <-> sata0 26 26 - ata0 master and slave interfaces brought out 27 27 - on IDE pads 28 28 - Mode 3: ata0 master <-> sata0 29 29 - ata0 slave <-> sata1 30 30 - ata1 master and slave interfaces brought out 31 31 - on IDE pads 32 32 - 33 33 - Optional boolean properties: 34 34 - - cortina,gemini-enable-ide-pins: enables the PATA to IDE connection. 35 35 - The muxmode setting decides whether ATA0 or ATA1 is brought out, 36 36 - and whether master, slave or both interfaces get brought out. 37 37 - - cortina,gemini-enable-sata-bridge: enables the PATA to SATA bridge 38 38 - inside the Gemnini SoC. The Muxmode decides what PATA blocks will 39 39 - be muxed out and how. 40 40 - 41 41 - Example: 42 42 - 43 43 - sata: sata@46000000 { 44 44 - compatible = "cortina,gemini-sata-bridge"; 45 45 - reg = <0x46000000 0x100>; 46 46 - resets = <&rcon 26>, <&rcon 27>; 47 47 - reset-names = "sata0", "sata1"; 48 48 - clocks = <&gcc GEMINI_CLK_GATE_SATA0>, 49 49 - <&gcc GEMINI_CLK_GATE_SATA1>; 50 50 - clock-names = "SATA0_PCLK", "SATA1_PCLK"; 51 51 - syscon = <&syscon>; 52 52 - cortina,gemini-ata-muxmode = <3>; 53 53 - cortina,gemini-enable-ide-pins; 54 54 - cortina,gemini-enable-sata-bridge; 55 55 - };

+109

Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Cortina Systems Gemini SATA Bridge 8 8 + 9 9 + maintainers: 10 10 + - Linus Walleij <linus.walleij@linaro.org> 11 11 + 12 12 + description: | 13 13 + The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that 14 14 + takes two Faraday Technology FTIDE010 PATA controllers and bridges 15 15 + them in different configurations to two SATA ports. 16 16 + 17 17 + properties: 18 18 + compatible: 19 19 + const: cortina,gemini-sata-bridge 20 20 + 21 21 + reg: 22 22 + maxItems: 1 23 23 + 24 24 + resets: 25 25 + minItems: 2 26 26 + maxItems: 2 27 27 + description: phandles to the reset lines for both SATA bridges 28 28 + 29 29 + reset-names: 30 30 + items: 31 31 + - const: sata0 32 32 + - const: sata1 33 33 + 34 34 + clocks: 35 35 + minItems: 2 36 36 + maxItems: 2 37 37 + description: phandles to the compulsory peripheral clocks 38 38 + 39 39 + clock-names: 40 40 + items: 41 41 + - const: SATA0_PCLK 42 42 + - const: SATA1_PCLK 43 43 + 44 44 + syscon: 45 45 + $ref: /schemas/types.yaml#/definitions/phandle 46 46 + description: a phandle to the global Gemini system controller 47 47 + 48 48 + cortina,gemini-ata-muxmode: 49 49 + $ref: /schemas/types.yaml#/definitions/uint32 50 50 + enum: 51 51 + - 0 52 52 + - 1 53 53 + - 2 54 54 + - 3 55 55 + description: | 56 56 + Tell the desired multiplexing mode for the ATA controller and SATA 57 57 + bridges. 58 58 + Mode 0: ata0 master <-> sata0 59 59 + ata1 master <-> sata1 60 60 + ata0 slave interface brought out on IDE pads 61 61 + Mode 1: ata0 master <-> sata0 62 62 + ata1 master <-> sata1 63 63 + ata1 slave interface brought out on IDE pads 64 64 + Mode 2: ata1 master <-> sata1 65 65 + ata1 slave <-> sata0 66 66 + ata0 master and slave interfaces brought out on IDE pads 67 67 + Mode 3: ata0 master <-> sata0 68 68 + ata0 slave <-> sata1 69 69 + ata1 master and slave interfaces brought out on IDE pads 70 70 + 71 71 + cortina,gemini-enable-ide-pins: 72 72 + type: boolean 73 73 + description: Enables the PATA to IDE connection. 74 74 + The muxmode setting decides whether ATA0 or ATA1 is brought out, 75 75 + and whether master, slave or both interfaces get brought out. 76 76 + 77 77 + cortina,gemini-enable-sata-bridge: 78 78 + type: boolean 79 79 + description: Enables the PATA to SATA bridge inside the Gemnini SoC. 80 80 + The Muxmode decides what PATA blocks will be muxed out and how. 81 81 + 82 82 + required: 83 83 + - clocks 84 84 + - clock-names 85 85 + - cortina,gemini-ata-muxmode 86 86 + - resets 87 87 + - reset-names 88 88 + - compatible 89 89 + - reg 90 90 + - syscon 91 91 + 92 92 + additionalProperties: false 93 93 + 94 94 + examples: 95 95 + - | 96 96 + #include <dt-bindings/clock/cortina,gemini-clock.h> 97 97 + sata@46000000 { 98 98 + compatible = "cortina,gemini-sata-bridge"; 99 99 + reg = <0x46000000 0x100>; 100 100 + resets = <&rcon 26>, <&rcon 27>; 101 101 + reset-names = "sata0", "sata1"; 102 102 + clocks = <&gcc GEMINI_CLK_GATE_SATA0>, 103 103 + <&gcc GEMINI_CLK_GATE_SATA1>; 104 104 + clock-names = "SATA0_PCLK", "SATA1_PCLK"; 105 105 + syscon = <&syscon>; 106 106 + cortina,gemini-ata-muxmode = <3>; 107 107 + cortina,gemini-enable-ide-pins; 108 108 + cortina,gemini-enable-sata-bridge; 109 109 + };

+3

Documentation/devicetree/bindings/ata/sata_highbank.yaml

reviewed

··· 51 51 $ref: /schemas/types.yaml#/definitions/phandle-array 52 52 minItems: 1 53 53 maxItems: 8 54 54 + items: 55 55 + minItems: 2 56 56 + maxItems: 2 54 57 55 58 calxeda,tx-atten: 56 59 description: |

+4 -1

Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml

reviewed

··· 35 35 The SRAM that needs to be claimed to access the display engine 36 36 bus. 37 37 $ref: /schemas/types.yaml#/definitions/phandle-array 38 38 - maxItems: 1 38 38 + items: 39 39 + - items: 40 40 + - description: phandle to SRAM 41 41 + - description: register value for device 39 42 40 43 ranges: true 41 44

+51

Documentation/devicetree/bindings/clock/ti/ti,clksel.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Binding for TI clksel clock 8 8 + 9 9 + maintainers: 10 10 + - Tony Lindgren <tony@atomide.com> 11 11 + 12 12 + description: | 13 13 + The TI CLKSEL clocks consist of consist of input clock mux bits, and in some 14 14 + cases also has divider, multiplier and gate bits. 15 15 + 16 16 + properties: 17 17 + compatible: 18 18 + const: ti,clksel 19 19 + 20 20 + reg: 21 21 + maxItems: 1 22 22 + description: The CLKSEL register range 23 23 + 24 24 + '#address-cells': 25 25 + enum: [ 0, 1, 2 ] 26 26 + 27 27 + '#size-cells': 28 28 + enum: [ 0, 1, 2 ] 29 29 + 30 30 + ranges: true 31 31 + 32 32 + "#clock-cells": 33 33 + const: 2 34 34 + description: The CLKSEL register and bit offset 35 35 + 36 36 + required: 37 37 + - compatible 38 38 + - reg 39 39 + - "#clock-cells" 40 40 + 41 41 + additionalProperties: 42 42 + type: object 43 43 + 44 44 + examples: 45 45 + - | 46 46 + clksel_gfx_fclk: clock@52c { 47 47 + compatible = "ti,clksel"; 48 48 + reg = <0x25c 0x4>; 49 49 + #clock-cells = <2>; 50 50 + }; 51 51 + ...

+1 -2

Documentation/devicetree/bindings/connector/usb-connector.yaml

reviewed

··· 104 104 - "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB 105 105 Type-C Cable and Connector specification, when Power Delivery is not 106 106 supported. 107 107 - allOf: 108 108 - - $ref: /schemas/types.yaml#/definitions/string 107 107 + $ref: /schemas/types.yaml#/definitions/string 109 108 enum: 110 109 - default 111 110 - 1.5A

+66

Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries 3 3 + %YAML 1.2 4 4 + --- 5 5 + $id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-aes.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 + 8 8 + title: Atmel Advanced Encryption Standard (AES) HW cryptographic accelerator 9 9 + 10 10 + maintainers: 11 11 + - Tudor Ambarus <tudor.ambarus@microchip.com> 12 12 + 13 13 + properties: 14 14 + compatible: 15 15 + const: atmel,at91sam9g46-aes 16 16 + 17 17 + reg: 18 18 + maxItems: 1 19 19 + 20 20 + interrupts: 21 21 + maxItems: 1 22 22 + 23 23 + clocks: 24 24 + maxItems: 1 25 25 + 26 26 + clock-names: 27 27 + const: aes_clk 28 28 + 29 29 + dmas: 30 30 + items: 31 31 + - description: TX DMA Channel 32 32 + - description: RX DMA Channel 33 33 + 34 34 + dma-names: 35 35 + items: 36 36 + - const: tx 37 37 + - const: rx 38 38 + 39 39 + required: 40 40 + - compatible 41 41 + - reg 42 42 + - interrupts 43 43 + - clocks 44 44 + - clock-names 45 45 + - dmas 46 46 + - dma-names 47 47 + 48 48 + additionalProperties: false 49 49 + 50 50 + examples: 51 51 + - | 52 52 + #include <dt-bindings/interrupt-controller/irq.h> 53 53 + #include <dt-bindings/interrupt-controller/arm-gic.h> 54 54 + #include <dt-bindings/clock/at91.h> 55 55 + #include <dt-bindings/dma/at91.h> 56 56 + 57 57 + aes: crypto@e1810000 { 58 58 + compatible = "atmel,at91sam9g46-aes"; 59 59 + reg = <0xe1810000 0x100>; 60 60 + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 61 61 + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 62 62 + clock-names = "aes_clk"; 63 63 + dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, 64 64 + <&dma0 AT91_XDMAC_DT_PERID(2)>; 65 65 + dma-names = "tx", "rx"; 66 66 + };

+60

Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries 3 3 + %YAML 1.2 4 4 + --- 5 5 + $id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-sha.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 + 8 8 + title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator 9 9 + 10 10 + maintainers: 11 11 + - Tudor Ambarus <tudor.ambarus@microchip.com> 12 12 + 13 13 + properties: 14 14 + compatible: 15 15 + const: atmel,at91sam9g46-sha 16 16 + 17 17 + reg: 18 18 + maxItems: 1 19 19 + 20 20 + interrupts: 21 21 + maxItems: 1 22 22 + 23 23 + clocks: 24 24 + maxItems: 1 25 25 + 26 26 + clock-names: 27 27 + const: sha_clk 28 28 + 29 29 + dmas: 30 30 + maxItems: 1 31 31 + description: TX DMA Channel 32 32 + 33 33 + dma-names: 34 34 + const: tx 35 35 + 36 36 + required: 37 37 + - compatible 38 38 + - reg 39 39 + - interrupts 40 40 + - clocks 41 41 + - clock-names 42 42 + 43 43 + additionalProperties: false 44 44 + 45 45 + examples: 46 46 + - | 47 47 + #include <dt-bindings/interrupt-controller/irq.h> 48 48 + #include <dt-bindings/interrupt-controller/arm-gic.h> 49 49 + #include <dt-bindings/clock/at91.h> 50 50 + #include <dt-bindings/dma/at91.h> 51 51 + 52 52 + sha: crypto@e1814000 { 53 53 + compatible = "atmel,at91sam9g46-sha"; 54 54 + reg = <0xe1814000 0x100>; 55 55 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 56 56 + clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; 57 57 + clock-names = "sha_clk"; 58 58 + dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; 59 59 + dma-names = "tx"; 60 60 + };

+64

Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries 3 3 + %YAML 1.2 4 4 + --- 5 5 + $id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-tdes.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 + 8 8 + title: Atmel Triple Data Encryption Standard (TDES) HW cryptographic accelerator 9 9 + 10 10 + maintainers: 11 11 + - Tudor Ambarus <tudor.ambarus@microchip.com> 12 12 + 13 13 + properties: 14 14 + compatible: 15 15 + const: atmel,at91sam9g46-tdes 16 16 + 17 17 + reg: 18 18 + maxItems: 1 19 19 + 20 20 + interrupts: 21 21 + maxItems: 1 22 22 + 23 23 + clocks: 24 24 + maxItems: 1 25 25 + 26 26 + clock-names: 27 27 + const: tdes_clk 28 28 + 29 29 + dmas: 30 30 + items: 31 31 + - description: TX DMA Channel 32 32 + - description: RX DMA Channel 33 33 + 34 34 + dma-names: 35 35 + items: 36 36 + - const: tx 37 37 + - const: rx 38 38 + 39 39 + required: 40 40 + - compatible 41 41 + - reg 42 42 + - interrupts 43 43 + - clocks 44 44 + - clock-names 45 45 + 46 46 + additionalProperties: false 47 47 + 48 48 + examples: 49 49 + - | 50 50 + #include <dt-bindings/interrupt-controller/irq.h> 51 51 + #include <dt-bindings/interrupt-controller/arm-gic.h> 52 52 + #include <dt-bindings/clock/at91.h> 53 53 + #include <dt-bindings/dma/at91.h> 54 54 + 55 55 + tdes: crypto@e2014000 { 56 56 + compatible = "atmel,at91sam9g46-tdes"; 57 57 + reg = <0xe2014000 0x100>; 58 58 + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 59 59 + clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; 60 60 + clock-names = "tdes_clk"; 61 61 + dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, 62 62 + <&dma0 AT91_XDMAC_DT_PERID(53)>; 63 63 + dma-names = "tx", "rx"; 64 64 + };

-68

Documentation/devicetree/bindings/crypto/atmel-crypto.txt

reviewed

··· 1 1 - * Atmel HW cryptographic accelerators 2 2 - 3 3 - These are the HW cryptographic accelerators found on some Atmel products. 4 4 - 5 5 - * Advanced Encryption Standard (AES) 6 6 - 7 7 - Required properties: 8 8 - - compatible : Should be "atmel,at91sam9g46-aes". 9 9 - - reg: Should contain AES registers location and length. 10 10 - - interrupts: Should contain the IRQ line for the AES. 11 11 - - dmas: List of two DMA specifiers as described in 12 12 - atmel-dma.txt and dma.txt files. 13 13 - - dma-names: Contains one identifier string for each DMA specifier 14 14 - in the dmas property. 15 15 - 16 16 - Example: 17 17 - aes@f8038000 { 18 18 - compatible = "atmel,at91sam9g46-aes"; 19 19 - reg = <0xf8038000 0x100>; 20 20 - interrupts = <43 4 0>; 21 21 - dmas = <&dma1 2 18>, 22 22 - <&dma1 2 19>; 23 23 - dma-names = "tx", "rx"; 24 24 - 25 25 - * Triple Data Encryption Standard (Triple DES) 26 26 - 27 27 - Required properties: 28 28 - - compatible : Should be "atmel,at91sam9g46-tdes". 29 29 - - reg: Should contain TDES registers location and length. 30 30 - - interrupts: Should contain the IRQ line for the TDES. 31 31 - 32 32 - Optional properties: 33 33 - - dmas: List of two DMA specifiers as described in 34 34 - atmel-dma.txt and dma.txt files. 35 35 - - dma-names: Contains one identifier string for each DMA specifier 36 36 - in the dmas property. 37 37 - 38 38 - Example: 39 39 - tdes@f803c000 { 40 40 - compatible = "atmel,at91sam9g46-tdes"; 41 41 - reg = <0xf803c000 0x100>; 42 42 - interrupts = <44 4 0>; 43 43 - dmas = <&dma1 2 20>, 44 44 - <&dma1 2 21>; 45 45 - dma-names = "tx", "rx"; 46 46 - }; 47 47 - 48 48 - * Secure Hash Algorithm (SHA) 49 49 - 50 50 - Required properties: 51 51 - - compatible : Should be "atmel,at91sam9g46-sha". 52 52 - - reg: Should contain SHA registers location and length. 53 53 - - interrupts: Should contain the IRQ line for the SHA. 54 54 - 55 55 - Optional properties: 56 56 - - dmas: One DMA specifiers as described in 57 57 - atmel-dma.txt and dma.txt files. 58 58 - - dma-names: Contains one identifier string for each DMA specifier 59 59 - in the dmas property. Only one "tx" string needed. 60 60 - 61 61 - Example: 62 62 - sha@f8034000 { 63 63 - compatible = "atmel,at91sam9g46-sha"; 64 64 - reg = <0xf8034000 0x100>; 65 65 - interrupts = <42 4 0>; 66 66 - dmas = <&dma1 2 17>; 67 67 - dma-names = "tx"; 68 68 - };

+12 -3

Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml

reviewed

··· 22 22 23 23 intel,npe-handle: 24 24 $ref: '/schemas/types.yaml#/definitions/phandle-array' 25 25 - maxItems: 1 25 25 + items: 26 26 + - items: 27 27 + - description: phandle to the NPE this crypto engine 28 28 + - description: the NPE instance number 26 29 description: phandle to the NPE this crypto engine is using, the cell 27 30 describing the NPE instance to be used. 28 31 29 32 queue-rx: 30 33 $ref: /schemas/types.yaml#/definitions/phandle-array 31 31 - maxItems: 1 34 34 + items: 35 35 + - items: 36 36 + - description: phandle to the RX queue on the NPE 37 37 + - description: the queue instance number 32 38 description: phandle to the RX queue on the NPE, the cell describing 33 39 the queue instance to be used. 34 40 35 41 queue-txready: 36 42 $ref: /schemas/types.yaml#/definitions/phandle-array 37 37 - maxItems: 1 43 43 + items: 44 44 + - items: 45 45 + - description: phandle to the TX READY queue on the NPE 46 46 + - description: the queue instance number 38 47 description: phandle to the TX READY queue on the NPE, the cell describing 39 48 the queue instance to be used. 40 49

+2

Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml

reviewed

··· 69 69 $ref: /schemas/types.yaml#/definitions/phandle-array 70 70 minItems: 1 71 71 maxItems: 2 72 72 + items: 73 73 + maxItems: 1 72 74 description: | 73 75 Available display engine frontends (DE 1.0) or mixers (DE 74 76 2.0/3.0) available.

+1 -2

Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml

reviewed

··· 72 72 - const: hpd-removed 73 73 74 74 ddc: 75 75 - allOf: 76 76 - - $ref: /schemas/types.yaml#/definitions/phandle 75 75 + $ref: /schemas/types.yaml#/definitions/phandle 77 76 description: > 78 77 Phandle of the I2C controller used for DDC EDID probing 79 78

+2 -3

Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml

reviewed

··· 76 76 77 77 adi,input-depth: 78 78 description: Number of bits per color component at the input. 79 79 - allOf: 80 80 - - $ref: /schemas/types.yaml#/definitions/uint32 81 81 - - enum: [ 8, 10, 12 ] 79 79 + $ref: /schemas/types.yaml#/definitions/uint32 80 80 + enum: [ 8, 10, 12 ] 82 81 83 82 adi,input-colorspace: 84 83 description: Input color space.

+2 -3

Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml

reviewed

··· 26 26 reg-io-width: 27 27 description: 28 28 Width (in bytes) of the registers specified by the reg property. 29 29 - allOf: 30 30 - - $ref: /schemas/types.yaml#/definitions/uint32 31 31 - - enum: [1, 4] 29 29 + $ref: /schemas/types.yaml#/definitions/uint32 30 30 + enum: [1, 4] 32 31 default: 1 33 32 34 33 clocks:

+5 -2

Documentation/devicetree/bindings/display/bridge/toshiba,tc358768.yaml

reviewed

··· 77 77 - vddio-supply 78 78 - ports 79 79 80 80 - additionalProperties: false 80 80 + allOf: 81 81 + - $ref: ../dsi-controller.yaml# 82 82 + 83 83 + unevaluatedProperties: false 81 84 82 85 examples: 83 86 - | ··· 90 87 #address-cells = <1>; 91 88 #size-cells = <0>; 92 89 93 93 - dsi_bridge: dsi-bridge@e { 90 90 + dsi_bridge: dsi@e { 94 91 compatible = "toshiba,tc358768"; 95 92 reg = <0xe>; 96 93

-51

Documentation/devicetree/bindings/display/exynos/exynos-mic.txt

reviewed

··· 1 1 - Device-Tree bindings for Samsung Exynos SoC mobile image compressor (MIC) 2 2 - 3 3 - MIC (mobile image compressor) resides between decon and mipi dsi. Mipi dsi is 4 4 - not capable to transfer high resoltuion frame data as decon can send. MIC 5 5 - solves this problem by compressing the frame data by 1/2 before it is 6 6 - transferred through mipi dsi. The compressed frame data must be uncompressed in 7 7 - the panel PCB. 8 8 - 9 9 - Required properties: 10 10 - - compatible: value should be "samsung,exynos5433-mic". 11 11 - - reg: physical base address and length of the MIC registers set and system 12 12 - register of mic. 13 13 - - clocks: must include clock specifiers corresponding to entries in the 14 14 - clock-names property. 15 15 - - clock-names: list of clock names sorted in the same order as the clocks 16 16 - property. Must contain "pclk_mic0", "sclk_rgb_vclk_to_mic0". 17 17 - - samsung,disp-syscon: the reference node for syscon for DISP block. 18 18 - - ports: contains a port which is connected to decon node and dsi node. 19 19 - address-cells and size-cells must 1 and 0, respectively. 20 20 - - port: contains an endpoint node which is connected to the endpoint in the 21 21 - decon node or dsi node. The reg value must be 0 and 1 respectively. 22 22 - 23 23 - Example: 24 24 - SoC specific DT entry: 25 25 - mic: mic@13930000 { 26 26 - compatible = "samsung,exynos5433-mic"; 27 27 - reg = <0x13930000 0x48>; 28 28 - clocks = <&cmu_disp CLK_PCLK_MIC0>, 29 29 - <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; 30 30 - clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; 31 31 - samsung,disp-syscon = <&syscon_disp>; 32 32 - 33 33 - ports { 34 34 - #address-cells = <1>; 35 35 - #size-cells = <0>; 36 36 - 37 37 - port@0 { 38 38 - reg = <0>; 39 39 - mic_to_decon: endpoint { 40 40 - remote-endpoint = <&decon_to_mic>; 41 41 - }; 42 42 - }; 43 43 - 44 44 - port@1 { 45 45 - reg = <1>; 46 46 - mic_to_dsi: endpoint { 47 47 - remote-endpoint = <&dsi_to_mic>; 48 48 - }; 49 49 - }; 50 50 - }; 51 51 - };

-60

Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt

reviewed

··· 1 1 - Device-Tree bindings for Samsung Exynos SoC display controller (DECON) 2 2 - 3 3 - DECON (Display and Enhancement Controller) is the Display Controller for the 4 4 - Exynos series of SoCs which transfers the image data from a video memory 5 5 - buffer to an external LCD interface. 6 6 - 7 7 - Required properties: 8 8 - - compatible: value should be one of: 9 9 - "samsung,exynos5433-decon", "samsung,exynos5433-decon-tv"; 10 10 - - reg: physical base address and length of the DECON registers set. 11 11 - - interrupt-names: should contain the interrupt names depending on mode of work: 12 12 - video mode: "vsync", 13 13 - command mode: "lcd_sys", 14 14 - command mode with software trigger: "lcd_sys", "te". 15 15 - - interrupts or interrupts-extended: list of interrupt specifiers corresponding 16 16 - to names privided in interrupt-names, as described in 17 17 - interrupt-controller/interrupts.txt 18 18 - - clocks: must include clock specifiers corresponding to entries in the 19 19 - clock-names property. 20 20 - - clock-names: list of clock names sorted in the same order as the clocks 21 21 - property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x", 22 22 - "aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x", 23 23 - "aclk_xiu_decon1x", "pclk_smmu_decon1x", clk_decon_vclk", 24 24 - "sclk_decon_eclk" 25 25 - - ports: contains a port which is connected to mic node. address-cells and 26 26 - size-cells must 1 and 0, respectively. 27 27 - - port: contains an endpoint node which is connected to the endpoint in the mic 28 28 - node. The reg value muset be 0. 29 29 - 30 30 - Example: 31 31 - SoC specific DT entry: 32 32 - decon: decon@13800000 { 33 33 - compatible = "samsung,exynos5433-decon"; 34 34 - reg = <0x13800000 0x2104>; 35 35 - clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>, 36 36 - <&cmu_disp CLK_ACLK_XIU_DECON0X>, 37 37 - <&cmu_disp CLK_PCLK_SMMU_DECON0X>, 38 38 - <&cmu_disp CLK_ACLK_SMMU_DECON1X>, 39 39 - <&cmu_disp CLK_ACLK_XIU_DECON1X>, 40 40 - <&cmu_disp CLK_PCLK_SMMU_DECON1X>, 41 41 - <&cmu_disp CLK_SCLK_DECON_VCLK>, 42 42 - <&cmu_disp CLK_SCLK_DECON_ECLK>; 43 43 - clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", 44 44 - "pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x", 45 45 - "pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk"; 46 46 - interrupt-names = "vsync", "lcd_sys"; 47 47 - interrupts = <0 202 0>, <0 203 0>; 48 48 - 49 49 - ports { 50 50 - #address-cells = <1>; 51 51 - #size-cells = <0>; 52 52 - 53 53 - port@0 { 54 54 - reg = <0>; 55 55 - decon_to_mic: endpoint { 56 56 - remote-endpoint = <&mic_to_decon>; 57 57 - }; 58 58 - }; 59 59 - }; 60 60 - };

-65

Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt

reviewed

··· 1 1 - Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON) 2 2 - 3 3 - DECON (Display and Enhancement Controller) is the Display Controller for the 4 4 - Exynos7 series of SoCs which transfers the image data from a video memory 5 5 - buffer to an external LCD interface. 6 6 - 7 7 - Required properties: 8 8 - - compatible: value should be "samsung,exynos7-decon"; 9 9 - 10 10 - - reg: physical base address and length of the DECON registers set. 11 11 - 12 12 - - interrupts: should contain a list of all DECON IP block interrupts in the 13 13 - order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier 14 14 - format depends on the interrupt controller used. 15 15 - 16 16 - - interrupt-names: should contain the interrupt names: "fifo", "vsync", 17 17 - "lcd_sys", in the same order as they were listed in the interrupts 18 18 - property. 19 19 - 20 20 - - pinctrl-0: pin control group to be used for this controller. 21 21 - 22 22 - - pinctrl-names: must contain a "default" entry. 23 23 - 24 24 - - clocks: must include clock specifiers corresponding to entries in the 25 25 - clock-names property. 26 26 - 27 27 - - clock-names: list of clock names sorted in the same order as the clocks 28 28 - property. Must contain "pclk_decon0", "aclk_decon0", 29 29 - "decon0_eclk", "decon0_vclk". 30 30 - - i80-if-timings: timing configuration for lcd i80 interface support. 31 31 - 32 32 - Optional Properties: 33 33 - - power-domains: a phandle to DECON power domain node. 34 34 - - display-timings: timing settings for DECON, as described in document [1]. 35 35 - Can be used in case timings cannot be provided otherwise 36 36 - or to override timings provided by the panel. 37 37 - 38 38 - [1]: Documentation/devicetree/bindings/display/panel/display-timing.txt 39 39 - 40 40 - Example: 41 41 - 42 42 - SoC specific DT entry: 43 43 - 44 44 - decon@13930000 { 45 45 - compatible = "samsung,exynos7-decon"; 46 46 - interrupt-parent = <&combiner>; 47 47 - reg = <0x13930000 0x1000>; 48 48 - interrupt-names = "lcd_sys", "vsync", "fifo"; 49 49 - interrupts = <0 188 0>, <0 189 0>, <0 190 0>; 50 50 - clocks = <&clock_disp PCLK_DECON_INT>, 51 51 - <&clock_disp ACLK_DECON_INT>, 52 52 - <&clock_disp SCLK_DECON_INT_ECLK>, 53 53 - <&clock_disp SCLK_DECON_INT_EXTCLKPLL>; 54 54 - clock-names = "pclk_decon0", "aclk_decon0", "decon0_eclk", 55 55 - "decon0_vclk"; 56 56 - status = "disabled"; 57 57 - }; 58 58 - 59 59 - Board specific DT entry: 60 60 - 61 61 - decon@13930000 { 62 62 - pinctrl-0 = <&lcd_clk &pwm1_out>; 63 63 - pinctrl-names = "default"; 64 64 - status = "okay"; 65 65 - };

-64

Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt

reviewed

··· 1 1 - Device-Tree bindings for drm hdmi driver 2 2 - 3 3 - Required properties: 4 4 - - compatible: value should be one among the following: 5 5 - 1) "samsung,exynos4210-hdmi" 6 6 - 2) "samsung,exynos4212-hdmi" 7 7 - 3) "samsung,exynos5420-hdmi" 8 8 - 4) "samsung,exynos5433-hdmi" 9 9 - - reg: physical base address of the hdmi and length of memory mapped 10 10 - region. 11 11 - - interrupts: interrupt number to the cpu. 12 12 - - hpd-gpios: following information about the hotplug gpio pin. 13 13 - a) phandle of the gpio controller node. 14 14 - b) pin number within the gpio controller. 15 15 - c) optional flags and pull up/down. 16 16 - - ddc: phandle to the hdmi ddc node 17 17 - - phy: phandle to the hdmi phy node 18 18 - - samsung,syscon-phandle: phandle for system controller node for PMU. 19 19 - - #sound-dai-cells: should be 0. 20 20 - 21 21 - Required properties for Exynos 4210, 4212, 5420 and 5433: 22 22 - - clocks: list of clock IDs from SoC clock driver. 23 23 - a) hdmi: Gate of HDMI IP bus clock. 24 24 - b) sclk_hdmi: Gate of HDMI special clock. 25 25 - c) sclk_pixel: Pixel special clock, one of the two possible inputs of 26 26 - HDMI clock mux. 27 27 - d) sclk_hdmiphy: HDMI PHY clock output, one of two possible inputs of 28 28 - HDMI clock mux. 29 29 - e) mout_hdmi: It is required by the driver to switch between the 2 30 30 - parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable 31 31 - after configuration, parent is set to sclk_hdmiphy else 32 32 - sclk_pixel. 33 33 - - clock-names: aliases as per driver requirements for above clock IDs: 34 34 - "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi". 35 35 - 36 36 - Required properties for Exynos 5433: 37 37 - - clocks: list of clock specifiers according to common clock bindings. 38 38 - a) hdmi_pclk: Gate of HDMI IP APB bus. 39 39 - b) hdmi_i_pclk: Gate of HDMI-PHY IP APB bus. 40 40 - d) i_tmds_clk: Gate of HDMI TMDS clock. 41 41 - e) i_pixel_clk: Gate of HDMI pixel clock. 42 42 - f) i_spdif_clk: Gate of HDMI SPDIF clock. 43 43 - g) oscclk: Oscillator clock, used as parent of following *_user clocks 44 44 - in case HDMI-PHY is not operational. 45 45 - h) tmds_clko: TMDS clock generated by HDMI-PHY. 46 46 - i) tmds_clko_user: MUX used to switch between oscclk and tmds_clko, 47 47 - respectively if HDMI-PHY is off and operational. 48 48 - j) pixel_clko: Pixel clock generated by HDMI-PHY. 49 49 - k) pixel_clko_user: MUX used to switch between oscclk and pixel_clko, 50 50 - respectively if HDMI-PHY is off and operational. 51 51 - - clock-names: aliases for above clock specfiers. 52 52 - - samsung,sysreg: handle to syscon used to control the system registers. 53 53 - 54 54 - Example: 55 55 - 56 56 - hdmi { 57 57 - compatible = "samsung,exynos4212-hdmi"; 58 58 - reg = <0x14530000 0x100000>; 59 59 - interrupts = <0 95 0>; 60 60 - hpd-gpios = <&gpx3 7 1>; 61 61 - ddc = <&hdmi_ddc_node>; 62 62 - phy = <&hdmi_phy_node>; 63 63 - samsung,syscon-phandle = <&pmu_system_controller>; 64 64 - };

-15

Documentation/devicetree/bindings/display/exynos/exynos_hdmiddc.txt

reviewed

··· 1 1 - Device-Tree bindings for hdmiddc driver 2 2 - 3 3 - Required properties: 4 4 - - compatible: value should be one of the following 5 5 - 1) "samsung,exynos5-hdmiddc" <DEPRECATED> 6 6 - 2) "samsung,exynos4210-hdmiddc" 7 7 - 8 8 - - reg: I2C address of the hdmiddc device. 9 9 - 10 10 - Example: 11 11 - 12 12 - hdmiddc { 13 13 - compatible = "samsung,exynos4210-hdmiddc"; 14 14 - reg = <0x50>; 15 15 - };

-15

Documentation/devicetree/bindings/display/exynos/exynos_hdmiphy.txt

reviewed

··· 1 1 - Device-Tree bindings for hdmiphy driver 2 2 - 3 3 - Required properties: 4 4 - - compatible: value should be one of the following: 5 5 - 1) "samsung,exynos5-hdmiphy" <DEPRECATED> 6 6 - 2) "samsung,exynos4210-hdmiphy". 7 7 - 3) "samsung,exynos4212-hdmiphy". 8 8 - - reg: I2C address of the hdmiphy device. 9 9 - 10 10 - Example: 11 11 - 12 12 - hdmiphy { 13 13 - compatible = "samsung,exynos4210-hdmiphy"; 14 14 - reg = <0x38>; 15 15 - };

-26

Documentation/devicetree/bindings/display/exynos/exynos_mixer.txt

reviewed

··· 1 1 - Device-Tree bindings for mixer driver 2 2 - 3 3 - Required properties: 4 4 - - compatible: value should be one of the following: 5 5 - 1) "samsung,exynos5-mixer" <DEPRECATED> 6 6 - 2) "samsung,exynos4210-mixer" 7 7 - 3) "samsung,exynos4212-mixer" 8 8 - 4) "samsung,exynos5250-mixer" 9 9 - 5) "samsung,exynos5420-mixer" 10 10 - 11 11 - - reg: physical base address of the mixer and length of memory mapped 12 12 - region. 13 13 - - interrupts: interrupt number to the cpu. 14 14 - - clocks: list of clock IDs from SoC clock driver. 15 15 - a) mixer: Gate of Mixer IP bus clock. 16 16 - b) sclk_hdmi: HDMI Special clock, one of the two possible inputs of 17 17 - mixer mux. 18 18 - c) hdmi: Gate of HDMI IP bus clock, needed together with sclk_hdmi. 19 19 - 20 20 - Example: 21 21 - 22 22 - mixer { 23 23 - compatible = "samsung,exynos5250-mixer"; 24 24 - reg = <0x14450000 0x10000>; 25 25 - interrupts = <0 94 0>; 26 26 - };

-107

Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt

reviewed

··· 1 1 - Device-Tree bindings for Samsung SoC display controller (FIMD) 2 2 - 3 3 - FIMD (Fully Interactive Mobile Display) is the Display Controller for the 4 4 - Samsung series of SoCs which transfers the image data from a video memory 5 5 - buffer to an external LCD interface. 6 6 - 7 7 - Required properties: 8 8 - - compatible: value should be one of the following 9 9 - "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */ 10 10 - "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */ 11 11 - "samsung,s5pv210-fimd"; /* for S5PV210 SoC */ 12 12 - "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */ 13 13 - "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */ 14 14 - "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */ 15 15 - "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */ 16 16 - 17 17 - - reg: physical base address and length of the FIMD registers set. 18 18 - 19 19 - - interrupts: should contain a list of all FIMD IP block interrupts in the 20 20 - order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier 21 21 - format depends on the interrupt controller used. 22 22 - 23 23 - - interrupt-names: should contain the interrupt names: "fifo", "vsync", 24 24 - "lcd_sys", in the same order as they were listed in the interrupts 25 25 - property. 26 26 - 27 27 - - pinctrl-0: pin control group to be used for this controller. 28 28 - 29 29 - - pinctrl-names: must contain a "default" entry. 30 30 - 31 31 - - clocks: must include clock specifiers corresponding to entries in the 32 32 - clock-names property. 33 33 - 34 34 - - clock-names: list of clock names sorted in the same order as the clocks 35 35 - property. Must contain "sclk_fimd" and "fimd". 36 36 - 37 37 - Optional Properties: 38 38 - - power-domains: a phandle to FIMD power domain node. 39 39 - - samsung,invert-vden: video enable signal is inverted 40 40 - - samsung,invert-vclk: video clock signal is inverted 41 41 - - display-timings: timing settings for FIMD, as described in document [1]. 42 42 - Can be used in case timings cannot be provided otherwise 43 43 - or to override timings provided by the panel. 44 44 - - samsung,sysreg: handle to syscon used to control the system registers 45 45 - - i80-if-timings: timing configuration for lcd i80 interface support. 46 46 - - cs-setup: clock cycles for the active period of address signal is enabled 47 47 - until chip select is enabled. 48 48 - If not specified, the default value(0) will be used. 49 49 - - wr-setup: clock cycles for the active period of CS signal is enabled until 50 50 - write signal is enabled. 51 51 - If not specified, the default value(0) will be used. 52 52 - - wr-active: clock cycles for the active period of CS is enabled. 53 53 - If not specified, the default value(1) will be used. 54 54 - - wr-hold: clock cycles for the active period of CS is disabled until write 55 55 - signal is disabled. 56 56 - If not specified, the default value(0) will be used. 57 57 - 58 58 - The parameters are defined as: 59 59 - 60 60 - VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|?? 61 61 - : : : : : 62 62 - Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX 63 63 - | cs-setup+1 | : : : 64 64 - |<---------->| : : : 65 65 - Chip Select ???????????????|____________:____________:____________|?? 66 66 - | wr-setup+1 | | wr-hold+1 | 67 67 - |<---------->| |<---------->| 68 68 - Write Enable ????????????????????????????|____________|??????????????? 69 69 - | wr-active+1| 70 70 - |<---------->| 71 71 - Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>-- 72 72 - 73 73 - The device node can contain 'port' child nodes according to the bindings defined 74 74 - in [2]. The following are properties specific to those nodes: 75 75 - - reg: (required) port index, can be: 76 76 - 0 - for CAMIF0 input, 77 77 - 1 - for CAMIF1 input, 78 78 - 2 - for CAMIF2 input, 79 79 - 3 - for parallel output, 80 80 - 4 - for write-back interface 81 81 - 82 82 - [1]: Documentation/devicetree/bindings/display/panel/display-timing.txt 83 83 - [2]: Documentation/devicetree/bindings/media/video-interfaces.txt 84 84 - 85 85 - Example: 86 86 - 87 87 - SoC specific DT entry: 88 88 - 89 89 - fimd@11c00000 { 90 90 - compatible = "samsung,exynos4210-fimd"; 91 91 - interrupt-parent = <&combiner>; 92 92 - reg = <0x11c00000 0x20000>; 93 93 - interrupt-names = "fifo", "vsync", "lcd_sys"; 94 94 - interrupts = <11 0>, <11 1>, <11 2>; 95 95 - clocks = <&clock 140>, <&clock 283>; 96 96 - clock-names = "sclk_fimd", "fimd"; 97 97 - power-domains = <&pd_lcd0>; 98 98 - status = "disabled"; 99 99 - }; 100 100 - 101 101 - Board specific DT entry: 102 102 - 103 103 - fimd@11c00000 { 104 104 - pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>; 105 105 - pinctrl-names = "default"; 106 106 - status = "okay"; 107 107 - };

+4 -1

Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml

reviewed

··· 51 51 52 52 mediatek,syscon-hdmi: 53 53 $ref: '/schemas/types.yaml#/definitions/phandle-array' 54 54 - maxItems: 1 54 54 + items: 55 55 + - items: 56 56 + - description: phandle to system configuration registers 57 57 + - description: register offset in the system configuration registers 55 58 description: | 56 59 phandle link and register offset to the system configuration registers. 57 60

+2

Documentation/devicetree/bindings/display/msm/gpu.yaml

reviewed

··· 64 64 $ref: /schemas/types.yaml#/definitions/phandle-array 65 65 minItems: 1 66 66 maxItems: 4 67 67 + items: 68 68 + maxItems: 1 67 69 description: | 68 70 phandles to one or more reserved on-chip SRAM regions. 69 71 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and

-114

Documentation/devicetree/bindings/display/msm/mdp4.txt

reviewed

··· 1 1 - Qualcomm adreno/snapdragon MDP4 display controller 2 2 - 3 3 - Description: 4 4 - 5 5 - This is the bindings documentation for the MDP4 display controller found in 6 6 - SoCs like MSM8960, APQ8064 and MSM8660. 7 7 - 8 8 - Required properties: 9 9 - - compatible: 10 10 - * "qcom,mdp4" - mdp4 11 11 - - reg: Physical base address and length of the controller's registers. 12 12 - - interrupts: The interrupt signal from the display controller. 13 13 - - clocks: device clocks 14 14 - See ../clocks/clock-bindings.txt for details. 15 15 - - clock-names: the following clocks are required. 16 16 - * "core_clk" 17 17 - * "iface_clk" 18 18 - * "bus_clk" 19 19 - * "lut_clk" 20 20 - * "hdmi_clk" 21 21 - * "tv_clk" 22 22 - - ports: contains the list of output ports from MDP. These connect to interfaces 23 23 - that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a 24 24 - special case since it is a part of the MDP block itself). 25 25 - 26 26 - Each output port contains an endpoint that describes how it is connected to an 27 27 - external interface. These are described by the standard properties documented 28 28 - here: 29 29 - Documentation/devicetree/bindings/graph.txt 30 30 - Documentation/devicetree/bindings/media/video-interfaces.txt 31 31 - 32 32 - The output port mappings are: 33 33 - Port 0 -> LCDC/LVDS 34 34 - Port 1 -> DSI1 Cmd/Video 35 35 - Port 2 -> DSI2 Cmd/Video 36 36 - Port 3 -> DTV 37 37 - 38 38 - Optional properties: 39 39 - - clock-names: the following clocks are optional: 40 40 - * "lut_clk" 41 41 - - qcom,lcdc-align-lsb: Boolean value indicating that LSB alignment should be 42 42 - used for LCDC. This is only valid for 18bpp panels. 43 43 - 44 44 - Example: 45 45 - 46 46 - / { 47 47 - ... 48 48 - 49 49 - hdmi: hdmi@4a00000 { 50 50 - ... 51 51 - ports { 52 52 - ... 53 53 - port@0 { 54 54 - reg = <0>; 55 55 - hdmi_in: endpoint { 56 56 - remote-endpoint = <&mdp_dtv_out>; 57 57 - }; 58 58 - }; 59 59 - ... 60 60 - }; 61 61 - ... 62 62 - }; 63 63 - 64 64 - ... 65 65 - 66 66 - mdp: mdp@5100000 { 67 67 - compatible = "qcom,mdp4"; 68 68 - reg = <0x05100000 0xf0000>; 69 69 - interrupts = <GIC_SPI 75 0>; 70 70 - clock-names = 71 71 - "core_clk", 72 72 - "iface_clk", 73 73 - "lut_clk", 74 74 - "hdmi_clk", 75 75 - "tv_clk"; 76 76 - clocks = 77 77 - <&mmcc MDP_CLK>, 78 78 - <&mmcc MDP_AHB_CLK>, 79 79 - <&mmcc MDP_AXI_CLK>, 80 80 - <&mmcc MDP_LUT_CLK>, 81 81 - <&mmcc HDMI_TV_CLK>, 82 82 - <&mmcc MDP_TV_CLK>; 83 83 - 84 84 - ports { 85 85 - #address-cells = <1>; 86 86 - #size-cells = <0>; 87 87 - 88 88 - port@0 { 89 89 - reg = <0>; 90 90 - mdp_lvds_out: endpoint { 91 91 - }; 92 92 - }; 93 93 - 94 94 - port@1 { 95 95 - reg = <1>; 96 96 - mdp_dsi1_out: endpoint { 97 97 - }; 98 98 - }; 99 99 - 100 100 - port@2 { 101 101 - reg = <2>; 102 102 - mdp_dsi2_out: endpoint { 103 103 - }; 104 104 - }; 105 105 - 106 106 - port@3 { 107 107 - reg = <3>; 108 108 - mdp_dtv_out: endpoint { 109 109 - remote-endpoint = <&hdmi_in>; 110 110 - }; 111 111 - }; 112 112 - }; 113 113 - }; 114 114 - };

+124

Documentation/devicetree/bindings/display/msm/mdp4.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: "http://devicetree.org/schemas/display/msm/mdp4.yaml#" 5 5 + $schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 6 + 7 7 + title: Qualcomm Adreno/Snapdragon MDP4 display controller 8 8 + 9 9 + description: > 10 10 + MDP4 display controller found in SoCs like MSM8960, APQ8064 and MSM8660. 11 11 + 12 12 + maintainers: 13 13 + - Rob Clark <robdclark@gmail.com> 14 14 + 15 15 + properties: 16 16 + compatible: 17 17 + const: qcom,mdp4 18 18 + 19 19 + clocks: 20 20 + minItems: 6 21 21 + maxItems: 6 22 22 + 23 23 + clock-names: 24 24 + items: 25 25 + - const: core_clk 26 26 + - const: iface_clk 27 27 + - const: bus_clk 28 28 + - const: lut_clk 29 29 + - const: hdmi_clk 30 30 + - const: tv_clk 31 31 + 32 32 + reg: 33 33 + maxItems: 1 34 34 + 35 35 + interrupts: 36 36 + maxItems: 1 37 37 + 38 38 + iommus: 39 39 + maxItems: 1 40 40 + 41 41 + ports: 42 42 + $ref: /schemas/graph.yaml#/properties/ports 43 43 + properties: 44 44 + port@0: 45 45 + $ref: /schemas/graph.yaml#/properties/port 46 46 + description: LCDC/LVDS 47 47 + 48 48 + port@1: 49 49 + $ref: /schemas/graph.yaml#/properties/port 50 50 + description: DSI1 Cmd / Video 51 51 + 52 52 + port@2: 53 53 + $ref: /schemas/graph.yaml#/properties/port 54 54 + description: DSI2 Cmd / Video 55 55 + 56 56 + port@3: 57 57 + $ref: /schemas/graph.yaml#/properties/port 58 58 + description: Digital TV 59 59 + 60 60 + qcom,lcdc-align-lsb: 61 61 + type: boolean 62 62 + description: > 63 63 + Indication that LSB alignment should be used for LCDC. 64 64 + This is only valid for 18bpp panels. 65 65 + 66 66 + required: 67 67 + - compatible 68 68 + - reg 69 69 + - clocks 70 70 + - ports 71 71 + 72 72 + additionalProperties: false 73 73 + 74 74 + examples: 75 75 + - | 76 76 + mdp: mdp@5100000 { 77 77 + compatible = "qcom,mdp4"; 78 78 + reg = <0x05100000 0xf0000>; 79 79 + interrupts = <0 75 0>; 80 80 + clock-names = 81 81 + "core_clk", 82 82 + "iface_clk", 83 83 + "bus_clk", 84 84 + "lut_clk", 85 85 + "hdmi_clk", 86 86 + "tv_clk"; 87 87 + clocks = 88 88 + <&mmcc 77>, 89 89 + <&mmcc 86>, 90 90 + <&mmcc 102>, 91 91 + <&mmcc 75>, 92 92 + <&mmcc 97>, 93 93 + <&mmcc 12>; 94 94 + 95 95 + ports { 96 96 + #address-cells = <1>; 97 97 + #size-cells = <0>; 98 98 + 99 99 + port@0 { 100 100 + reg = <0>; 101 101 + mdp_lvds_out: endpoint { 102 102 + }; 103 103 + }; 104 104 + 105 105 + port@1 { 106 106 + reg = <1>; 107 107 + mdp_dsi1_out: endpoint { 108 108 + }; 109 109 + }; 110 110 + 111 111 + port@2 { 112 112 + reg = <2>; 113 113 + mdp_dsi2_out: endpoint { 114 114 + }; 115 115 + }; 116 116 + 117 117 + port@3 { 118 118 + reg = <3>; 119 119 + mdp_dtv_out: endpoint { 120 120 + remote-endpoint = <&hdmi_in>; 121 121 + }; 122 122 + }; 123 123 + }; 124 124 + };

+1 -2

Documentation/devicetree/bindings/display/panel/display-timings.yaml

reviewed

··· 31 31 patternProperties: 32 32 "^timing": 33 33 type: object 34 34 - allOf: 35 35 - - $ref: panel-timing.yaml# 34 34 + $ref: panel-timing.yaml# 36 35 37 36 additionalProperties: false 38 37

+1 -1

Documentation/devicetree/bindings/display/panel/leadtek,ltk050h3146w.yaml

reviewed

··· 7 7 title: Leadtek LTK050H3146W 5.0in 720x1280 DSI panel 8 8 9 9 maintainers: 10 10 - - Heiko Stuebner <heiko.stuebner@theobroma-systems.com> 10 10 + - Quentin Schulz <quentin.schulz@theobroma-systems.com> 11 11 12 12 allOf: 13 13 - $ref: panel-common.yaml#

+7 -3

Documentation/devicetree/bindings/display/renesas,du.yaml

reviewed

··· 76 76 77 77 renesas,cmms: 78 78 $ref: "/schemas/types.yaml#/definitions/phandle-array" 79 79 + items: 80 80 + maxItems: 1 79 81 description: 80 82 A list of phandles to the CMM instances present in the SoC, one for each 81 83 available DU channel. 82 84 83 85 renesas,vsps: 84 86 $ref: "/schemas/types.yaml#/definitions/phandle-array" 87 87 + items: 88 88 + items: 89 89 + - description: phandle to VSP instance that serves the DU channel 90 90 + - description: Channel index identifying the LIF instance in that VSP 85 91 description: 86 92 A list of phandle and channel index tuples to the VSPs that handle the 87 87 - memory interfaces for the DU channels. The phandle identifies the VSP 88 88 - instance that serves the DU channel, and the channel index identifies 89 89 - the LIF instance in that VSP. 93 93 + memory interfaces for the DU channels. 90 94 91 95 required: 92 96 - compatible

+2

Documentation/devicetree/bindings/display/rockchip/rockchip-drm.yaml

reviewed

··· 21 21 22 22 ports: 23 23 $ref: /schemas/types.yaml#/definitions/phandle-array 24 24 + items: 25 25 + maxItems: 1 24 26 description: | 25 27 Should contain a list of phandles pointing to display interface port 26 28 of vop devices. vop definitions as defined in

+42

Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi-ddc.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Samsung Exynos SoC HDMI DDC 8 8 + 9 9 + maintainers: 10 10 + - Inki Dae <inki.dae@samsung.com> 11 11 + - Joonyoung Shim <jy0922.shim@samsung.com> 12 12 + - Seung-Woo Kim <sw0312.kim@samsung.com> 13 13 + - Kyungmin Park <kyungmin.park@samsung.com> 14 14 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 15 15 + 16 16 + properties: 17 17 + compatible: 18 18 + oneOf: 19 19 + - const: samsung,exynos4210-hdmiddc 20 20 + - const: samsung,exynos5-hdmiddc 21 21 + deprecated: true 22 22 + 23 23 + reg: 24 24 + maxItems: 1 25 25 + 26 26 + required: 27 27 + - compatible 28 28 + - reg 29 29 + 30 30 + additionalProperties: false 31 31 + 32 32 + examples: 33 33 + - | 34 34 + i2c { 35 35 + #address-cells = <1>; 36 36 + #size-cells = <0>; 37 37 + 38 38 + ddc@50 { 39 39 + compatible = "samsung,exynos4210-hdmiddc"; 40 40 + reg = <0x50>; 41 41 + }; 42 42 + };

+227

Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Samsung Exynos SoC HDMI 8 8 + 9 9 + maintainers: 10 10 + - Inki Dae <inki.dae@samsung.com> 11 11 + - Joonyoung Shim <jy0922.shim@samsung.com> 12 12 + - Seung-Woo Kim <sw0312.kim@samsung.com> 13 13 + - Kyungmin Park <kyungmin.park@samsung.com> 14 14 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 15 15 + 16 16 + properties: 17 17 + compatible: 18 18 + enum: 19 19 + - samsung,exynos4210-hdmi 20 20 + - samsung,exynos4212-hdmi 21 21 + - samsung,exynos5420-hdmi 22 22 + - samsung,exynos5433-hdmi 23 23 + 24 24 + clocks: 25 25 + minItems: 5 26 26 + maxItems: 10 27 27 + 28 28 + clock-names: 29 29 + minItems: 5 30 30 + maxItems: 10 31 31 + 32 32 + ddc: 33 33 + $ref: /schemas/types.yaml#/definitions/phandle 34 34 + description: 35 35 + Phandle to the HDMI DDC node. 36 36 + 37 37 + hdmi-en-supply: 38 38 + description: 39 39 + Provides voltage source for DCC lines available on HDMI connector. When 40 40 + there is no power provided for DDC epprom, some TV-sets do not pulls up 41 41 + HPD (hot plug detect) line, what causes HDMI block to stay turned off. 42 42 + When provided, the regulator allows TV-set correctly signal HPD event. 43 43 + 44 44 + hpd-gpios: 45 45 + maxItems: 1 46 46 + description: 47 47 + A GPIO line connected to HPD 48 48 + 49 49 + interrupts: 50 50 + maxItems: 1 51 51 + 52 52 + phy: 53 53 + $ref: /schemas/types.yaml#/definitions/phandle 54 54 + description: Phandle to the HDMI PHY node. 55 55 + 56 56 + ports: 57 57 + $ref: /schemas/graph.yaml#/properties/ports 58 58 + description: 59 59 + Contains a port which is connected to mic node. 60 60 + 61 61 + power-domains: 62 62 + maxItems: 1 63 63 + 64 64 + reg: 65 65 + maxItems: 1 66 66 + 67 67 + samsung,syscon-phandle: 68 68 + $ref: /schemas/types.yaml#/definitions/phandle 69 69 + description: 70 70 + Phandle to the PMU system controller node. 71 71 + 72 72 + samsung,sysreg-phandle: 73 73 + $ref: /schemas/types.yaml#/definitions/phandle 74 74 + description: 75 75 + Phandle to DISP system controller interface. 76 76 + 77 77 + '#sound-dai-cells': 78 78 + const: 0 79 79 + 80 80 + vdd-supply: 81 81 + description: 82 82 + VDD 1.0V HDMI TX. 83 83 + 84 84 + vdd_osc-supply: 85 85 + description: 86 86 + VDD 1.8V HDMI OSC. 87 87 + 88 88 + vdd_pll-supply: 89 89 + description: 90 90 + VDD 1.0V HDMI PLL. 91 91 + 92 92 + required: 93 93 + - compatible 94 94 + - clocks 95 95 + - clock-names 96 96 + - ddc 97 97 + - hpd-gpios 98 98 + - interrupts 99 99 + - phy 100 100 + - reg 101 101 + - samsung,syscon-phandle 102 102 + - '#sound-dai-cells' 103 103 + - vdd-supply 104 104 + - vdd_osc-supply 105 105 + - vdd_pll-supply 106 106 + 107 107 + allOf: 108 108 + - if: 109 109 + properties: 110 110 + compatible: 111 111 + contains: 112 112 + const: samsung,exynos5433-hdmi 113 113 + then: 114 114 + properties: 115 115 + clocks: 116 116 + items: 117 117 + - description: Gate of HDMI IP APB bus. 118 118 + - description: Gate of HDMI-PHY IP APB bus. 119 119 + - description: Gate of HDMI TMDS clock. 120 120 + - description: Gate of HDMI pixel clock. 121 121 + - description: TMDS clock generated by HDMI-PHY. 122 122 + - description: MUX used to switch between oscclk and tmds_clko, 123 123 + respectively if HDMI-PHY is off and operational. 124 124 + - description: Pixel clock generated by HDMI-PHY. 125 125 + - description: MUX used to switch between oscclk and pixel_clko, 126 126 + respectively if HDMI-PHY is off and operational. 127 127 + - description: Oscillator clock, used as parent of following *_user 128 128 + clocks in case HDMI-PHY is not operational. 129 129 + - description: Gate of HDMI SPDIF clock. 130 130 + clock-names: 131 131 + items: 132 132 + - const: hdmi_pclk 133 133 + - const: hdmi_i_pclk 134 134 + - const: i_tmds_clk 135 135 + - const: i_pixel_clk 136 136 + - const: tmds_clko 137 137 + - const: tmds_clko_user 138 138 + - const: pixel_clko 139 139 + - const: pixel_clko_user 140 140 + - const: oscclk 141 141 + - const: i_spdif_clk 142 142 + required: 143 143 + - samsung,sysreg-phandle 144 144 + else: 145 145 + properties: 146 146 + clocks: 147 147 + items: 148 148 + - description: Gate of HDMI IP bus clock. 149 149 + - description: Gate of HDMI special clock. 150 150 + - description: Pixel special clock, one of the two possible inputs 151 151 + of HDMI clock mux. 152 152 + - description: HDMI PHY clock output, one of two possible inputs of 153 153 + HDMI clock mux. 154 154 + - description: It is required by the driver to switch between the 2 155 155 + parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable 156 156 + after configuration, parent is set to sclk_hdmiphy else 157 157 + sclk_pixel. 158 158 + clock-names: 159 159 + items: 160 160 + - const: hdmi 161 161 + - const: sclk_hdmi 162 162 + - const: sclk_pixel 163 163 + - const: sclk_hdmiphy 164 164 + - const: mout_hdmi 165 165 + 166 166 + additionalProperties: false 167 167 + 168 168 + examples: 169 169 + - | 170 170 + #include <dt-bindings/clock/exynos5433.h> 171 171 + #include <dt-bindings/gpio/gpio.h> 172 172 + #include <dt-bindings/interrupt-controller/arm-gic.h> 173 173 + 174 174 + hdmi@13970000 { 175 175 + compatible = "samsung,exynos5433-hdmi"; 176 176 + reg = <0x13970000 0x70000>; 177 177 + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 178 178 + clocks = <&cmu_disp CLK_PCLK_HDMI>, 179 179 + <&cmu_disp CLK_PCLK_HDMIPHY>, 180 180 + <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>, 181 181 + <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>, 182 182 + <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>, 183 183 + <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>, 184 184 + <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>, 185 185 + <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>, 186 186 + <&xxti>, 187 187 + <&cmu_disp CLK_SCLK_HDMI_SPDIF>; 188 188 + clock-names = "hdmi_pclk", 189 189 + "hdmi_i_pclk", 190 190 + "i_tmds_clk", 191 191 + "i_pixel_clk", 192 192 + "tmds_clko", 193 193 + "tmds_clko_user", 194 194 + "pixel_clko", 195 195 + "pixel_clko_user", 196 196 + "oscclk", 197 197 + "i_spdif_clk"; 198 198 + phy = <&hdmiphy>; 199 199 + ddc = <&hsi2c_11>; 200 200 + samsung,syscon-phandle = <&pmu_system_controller>; 201 201 + samsung,sysreg-phandle = <&syscon_disp>; 202 202 + #sound-dai-cells = <0>; 203 203 + 204 204 + hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>; 205 205 + vdd-supply = <&ldo6_reg>; 206 206 + vdd_osc-supply = <&ldo7_reg>; 207 207 + vdd_pll-supply = <&ldo6_reg>; 208 208 + 209 209 + ports { 210 210 + #address-cells = <1>; 211 211 + #size-cells = <0>; 212 212 + 213 213 + port@0 { 214 214 + reg = <0>; 215 215 + hdmi_to_tv: endpoint { 216 216 + remote-endpoint = <&tv_to_hdmi>; 217 217 + }; 218 218 + }; 219 219 + 220 220 + port@1 { 221 221 + reg = <1>; 222 222 + hdmi_to_mhl: endpoint { 223 223 + remote-endpoint = <&mhl_to_hdmi>; 224 224 + }; 225 225 + }; 226 226 + }; 227 227 + };

+143

Documentation/devicetree/bindings/display/samsung/samsung,exynos-mixer.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-mixer.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Samsung Exynos SoC Mixer 8 8 + 9 9 + maintainers: 10 10 + - Inki Dae <inki.dae@samsung.com> 11 11 + - Joonyoung Shim <jy0922.shim@samsung.com> 12 12 + - Seung-Woo Kim <sw0312.kim@samsung.com> 13 13 + - Kyungmin Park <kyungmin.park@samsung.com> 14 14 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 15 15 + 16 16 + description: 17 17 + Samsung Exynos SoC Mixer is responsible for mixing and blending multiple data 18 18 + inputs before passing it to an output device. The output is passed to HDMI. 19 19 + 20 20 + properties: 21 21 + compatible: 22 22 + oneOf: 23 23 + - enum: 24 24 + - samsung,exynos4210-mixer 25 25 + - samsung,exynos4212-mixer 26 26 + - samsung,exynos5250-mixer 27 27 + - samsung,exynos5420-mixer 28 28 + - const: samsung,exynos5-mixer 29 29 + deprecated: true 30 30 + 31 31 + clocks: 32 32 + minItems: 3 33 33 + items: 34 34 + - description: Gate of Mixer IP bus clock. 35 35 + - description: Gate of HDMI IP bus clock, needed together with sclk_hdmi. 36 36 + - description: HDMI Special clock, one of the two possible inputs of 37 37 + mixer mux. 38 38 + - description: Video Processor clock. 39 39 + - description: Mixer mux clock. 40 40 + - description: Mixer Special clock. 41 41 + 42 42 + clock-names: 43 43 + minItems: 3 44 44 + items: 45 45 + - const: mixer 46 46 + - const: hdmi 47 47 + - const: sclk_hdmi 48 48 + - const: vp 49 49 + - const: mout_mixer 50 50 + - const: sclk_mixer 51 51 + 52 52 + interconnects: 53 53 + maxItems: 1 54 54 + 55 55 + interrupts: 56 56 + maxItems: 1 57 57 + 58 58 + iommus: 59 59 + maxItems: 1 60 60 + 61 61 + power-domains: 62 62 + maxItems: 1 63 63 + 64 64 + reg: 65 65 + minItems: 1 66 66 + items: 67 67 + - description: Mixer memory region. 68 68 + - description: Video Processor memory region. 69 69 + 70 70 + required: 71 71 + - compatible 72 72 + - clocks 73 73 + - clock-names 74 74 + - interrupts 75 75 + - reg 76 76 + 77 77 + allOf: 78 78 + - if: 79 79 + properties: 80 80 + compatible: 81 81 + contains: 82 82 + const: samsung,exynos4210-mixer 83 83 + - samsung,exynos4212-mixer 84 84 + then: 85 85 + properties: 86 86 + clocks: 87 87 + minItems: 6 88 88 + maxItems: 6 89 89 + regs: 90 90 + minItems: 2 91 91 + maxItems: 2 92 92 + 93 93 + - if: 94 94 + properties: 95 95 + compatible: 96 96 + contains: 97 97 + const: samsung,exynos4212-mixer 98 98 + then: 99 99 + properties: 100 100 + clocks: 101 101 + minItems: 4 102 102 + maxItems: 4 103 103 + regs: 104 104 + minItems: 2 105 105 + maxItems: 2 106 106 + 107 107 + - if: 108 108 + properties: 109 109 + compatible: 110 110 + contains: 111 111 + enum: 112 112 + - samsung,exynos5-mixer 113 113 + - samsung,exynos5250-mixer 114 114 + - samsung,exynos5420-mixer 115 115 + then: 116 116 + properties: 117 117 + clocks: 118 118 + minItems: 3 119 119 + maxItems: 3 120 120 + regs: 121 121 + minItems: 1 122 122 + maxItems: 1 123 123 + 124 124 + additionalProperties: false 125 125 + 126 126 + examples: 127 127 + - | 128 128 + #include <dt-bindings/clock/exynos5250.h> 129 129 + #include <dt-bindings/interrupt-controller/arm-gic.h> 130 130 + 131 131 + mixer@14450000 { 132 132 + compatible = "samsung,exynos5250-mixer"; 133 133 + reg = <0x14450000 0x10000>; 134 134 + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 135 135 + clocks = <&clock CLK_MIXER>, 136 136 + <&clock CLK_HDMI>, 137 137 + <&clock CLK_SCLK_HDMI>; 138 138 + clock-names = "mixer", 139 139 + "hdmi", 140 140 + "sclk_hdmi"; 141 141 + iommus = <&sysmmu_tv>; 142 142 + power-domains = <&pd_disp1>; 143 143 + };

+148

Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-decon.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-decon.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON) 8 8 + 9 9 + maintainers: 10 10 + - Inki Dae <inki.dae@samsung.com> 11 11 + - Joonyoung Shim <jy0922.shim@samsung.com> 12 12 + - Seung-Woo Kim <sw0312.kim@samsung.com> 13 13 + - Kyungmin Park <kyungmin.park@samsung.com> 14 14 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 15 15 + 16 16 + description: | 17 17 + DECON (Display and Enhancement Controller) is the Display Controller for the 18 18 + Exynos5433 series of SoCs which transfers the image data from a video memory 19 19 + buffer to an external LCD interface. 20 20 + 21 21 + properties: 22 22 + compatible: 23 23 + enum: 24 24 + - samsung,exynos5433-decon 25 25 + - samsung,exynos5433-decon-tv 26 26 + 27 27 + clocks: 28 28 + minItems: 11 29 29 + maxItems: 11 30 30 + 31 31 + clock-names: 32 32 + items: 33 33 + - const: pclk 34 34 + - const: aclk_decon 35 35 + - const: aclk_smmu_decon0x 36 36 + - const: aclk_xiu_decon0x 37 37 + - const: pclk_smmu_decon0x 38 38 + - const: aclk_smmu_decon1x 39 39 + - const: aclk_xiu_decon1x 40 40 + - const: pclk_smmu_decon1x 41 41 + - const: sclk_decon_vclk 42 42 + - const: sclk_decon_eclk 43 43 + - const: dsd 44 44 + 45 45 + interrupts: 46 46 + minItems: 3 47 47 + maxItems: 4 48 48 + description: | 49 49 + Interrupts depend on mode of work: 50 50 + - video mode: vsync 51 51 + - command mode: lcd_sys 52 52 + - command mode with software trigger: lcd_sys, te 53 53 + 54 54 + interrupt-names: 55 55 + minItems: 3 56 56 + items: 57 57 + - const: fifo 58 58 + - const: vsync 59 59 + - const: lcd_sys 60 60 + - const: te 61 61 + 62 62 + iommus: 63 63 + minItems: 2 64 64 + maxItems: 2 65 65 + 66 66 + iommu-names: 67 67 + items: 68 68 + - const: m0 69 69 + - const: m1 70 70 + 71 71 + ports: 72 72 + $ref: /schemas/graph.yaml#/properties/ports 73 73 + description: 74 74 + Contains a port which is connected to mic node. 75 75 + 76 76 + power-domains: 77 77 + maxItems: 1 78 78 + 79 79 + reg: 80 80 + maxItems: 1 81 81 + 82 82 + samsung,disp-sysreg: 83 83 + $ref: /schemas/types.yaml#/definitions/phandle 84 84 + description: 85 85 + Phandle to DISP system controller interface. 86 86 + 87 87 + required: 88 88 + - compatible 89 89 + - clocks 90 90 + - clock-names 91 91 + - interrupts 92 92 + - interrupt-names 93 93 + - ports 94 94 + - reg 95 95 + 96 96 + additionalProperties: false 97 97 + 98 98 + examples: 99 99 + - | 100 100 + #include <dt-bindings/clock/exynos5433.h> 101 101 + #include <dt-bindings/interrupt-controller/arm-gic.h> 102 102 + 103 103 + display-controller@13800000 { 104 104 + compatible = "samsung,exynos5433-decon"; 105 105 + reg = <0x13800000 0x2104>; 106 106 + clocks = <&cmu_disp CLK_PCLK_DECON>, 107 107 + <&cmu_disp CLK_ACLK_DECON>, 108 108 + <&cmu_disp CLK_ACLK_SMMU_DECON0X>, 109 109 + <&cmu_disp CLK_ACLK_XIU_DECON0X>, 110 110 + <&cmu_disp CLK_PCLK_SMMU_DECON0X>, 111 111 + <&cmu_disp CLK_ACLK_SMMU_DECON1X>, 112 112 + <&cmu_disp CLK_ACLK_XIU_DECON1X>, 113 113 + <&cmu_disp CLK_PCLK_SMMU_DECON1X>, 114 114 + <&cmu_disp CLK_SCLK_DECON_VCLK>, 115 115 + <&cmu_disp CLK_SCLK_DECON_ECLK>, 116 116 + <&cmu_disp CLK_SCLK_DSD>; 117 117 + clock-names = "pclk", 118 118 + "aclk_decon", 119 119 + "aclk_smmu_decon0x", 120 120 + "aclk_xiu_decon0x", 121 121 + "pclk_smmu_decon0x", 122 122 + "aclk_smmu_decon1x", 123 123 + "aclk_xiu_decon1x", 124 124 + "pclk_smmu_decon1x", 125 125 + "sclk_decon_vclk", 126 126 + "sclk_decon_eclk", 127 127 + "dsd"; 128 128 + power-domains = <&pd_disp>; 129 129 + interrupt-names = "fifo", "vsync", "lcd_sys"; 130 130 + interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 131 131 + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 132 132 + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 133 133 + samsung,disp-sysreg = <&syscon_disp>; 134 134 + iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>; 135 135 + iommu-names = "m0", "m1"; 136 136 + 137 137 + ports { 138 138 + #address-cells = <1>; 139 139 + #size-cells = <0>; 140 140 + 141 141 + port@0 { 142 142 + reg = <0>; 143 143 + decon_to_mic: endpoint { 144 144 + remote-endpoint = <&mic_to_decon>; 145 145 + }; 146 146 + }; 147 147 + }; 148 148 + };

+95

Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-mic.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-mic.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Samsung Exynos5433 SoC Mobile Image Compressor (MIC) 8 8 + 9 9 + maintainers: 10 10 + - Inki Dae <inki.dae@samsung.com> 11 11 + - Joonyoung Shim <jy0922.shim@samsung.com> 12 12 + - Seung-Woo Kim <sw0312.kim@samsung.com> 13 13 + - Kyungmin Park <kyungmin.park@samsung.com> 14 14 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 15 15 + 16 16 + description: | 17 17 + MIC (Mobile Image Compressor) resides between DECON and MIPI DSI. MIPI DSI is 18 18 + not capable of transferring high resoltuion frame data as DECON can send. MIC 19 19 + solves this problem by compressing the frame data by 1/2 before it is 20 20 + transferred through MIPI DSI. The compressed frame data must be uncompressed 21 21 + in the panel PCB. 22 22 + 23 23 + properties: 24 24 + compatible: 25 25 + const: samsung,exynos5433-mic 26 26 + 27 27 + clocks: 28 28 + minItems: 2 29 29 + maxItems: 2 30 30 + 31 31 + clock-names: 32 32 + items: 33 33 + - const: pclk_mic0 34 34 + - const: sclk_rgb_vclk_to_mic0 35 35 + 36 36 + ports: 37 37 + $ref: /schemas/graph.yaml#/properties/ports 38 38 + description: 39 39 + Contains a port which is connected to mic node. 40 40 + 41 41 + power-domains: 42 42 + maxItems: 1 43 43 + 44 44 + reg: 45 45 + maxItems: 1 46 46 + 47 47 + samsung,disp-syscon: 48 48 + $ref: /schemas/types.yaml#/definitions/phandle 49 49 + description: 50 50 + Phandle to DISP system controller interface. 51 51 + 52 52 + required: 53 53 + - compatible 54 54 + - clocks 55 55 + - clock-names 56 56 + - ports 57 57 + - reg 58 58 + - samsung,disp-syscon 59 59 + 60 60 + additionalProperties: false 61 61 + 62 62 + examples: 63 63 + - | 64 64 + #include <dt-bindings/clock/exynos5433.h> 65 65 + #include <dt-bindings/interrupt-controller/arm-gic.h> 66 66 + 67 67 + image-processor@13930000 { 68 68 + compatible = "samsung,exynos5433-mic"; 69 69 + reg = <0x13930000 0x48>; 70 70 + clocks = <&cmu_disp CLK_PCLK_MIC0>, 71 71 + <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; 72 72 + clock-names = "pclk_mic0", 73 73 + "sclk_rgb_vclk_to_mic0"; 74 74 + power-domains = <&pd_disp>; 75 75 + samsung,disp-syscon = <&syscon_disp>; 76 76 + 77 77 + ports { 78 78 + #address-cells = <1>; 79 79 + #size-cells = <0>; 80 80 + 81 81 + port@0 { 82 82 + reg = <0>; 83 83 + mic_to_decon: endpoint { 84 84 + remote-endpoint = <&decon_to_mic>; 85 85 + }; 86 86 + }; 87 87 + 88 88 + port@1 { 89 89 + reg = <1>; 90 90 + mic_to_dsi: endpoint { 91 91 + remote-endpoint = <&dsi_to_mic>; 92 92 + }; 93 93 + }; 94 94 + }; 95 95 + };

+120

Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON) 8 8 + 9 9 + maintainers: 10 10 + - Inki Dae <inki.dae@samsung.com> 11 11 + - Joonyoung Shim <jy0922.shim@samsung.com> 12 12 + - Seung-Woo Kim <sw0312.kim@samsung.com> 13 13 + - Kyungmin Park <kyungmin.park@samsung.com> 14 14 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 15 15 + 16 16 + description: | 17 17 + DECON (Display and Enhancement Controller) is the Display Controller for the 18 18 + Exynos7 series of SoCs which transfers the image data from a video memory 19 19 + buffer to an external LCD interface. 20 20 + 21 21 + properties: 22 22 + compatible: 23 23 + const: samsung,exynos7-decon 24 24 + 25 25 + clocks: 26 26 + minItems: 4 27 27 + maxItems: 4 28 28 + 29 29 + clock-names: 30 30 + items: 31 31 + - const: pclk_decon0 32 32 + - const: aclk_decon0 33 33 + - const: decon0_eclk 34 34 + - const: decon0_vclk 35 35 + 36 36 + display-timings: 37 37 + $ref: ../panel/display-timings.yaml# 38 38 + 39 39 + i80-if-timings: 40 40 + type: object 41 41 + description: timing configuration for lcd i80 interface support 42 42 + properties: 43 43 + cs-setup: 44 44 + $ref: /schemas/types.yaml#/definitions/uint32 45 45 + description: 46 46 + Clock cycles for the active period of address signal is enabled until 47 47 + chip select is enabled. 48 48 + default: 0 49 49 + 50 50 + wr-active: 51 51 + $ref: /schemas/types.yaml#/definitions/uint32 52 52 + description: 53 53 + Clock cycles for the active period of CS is enabled. 54 54 + default: 1 55 55 + 56 56 + wr-hold: 57 57 + $ref: /schemas/types.yaml#/definitions/uint32 58 58 + description: 59 59 + Clock cycles for the active period of CS is disabled until write 60 60 + signal is disabled. 61 61 + default: 0 62 62 + 63 63 + wr-setup: 64 64 + $ref: /schemas/types.yaml#/definitions/uint32 65 65 + description: 66 66 + Clock cycles for the active period of CS signal is enabled until 67 67 + write signal is enabled. 68 68 + default: 0 69 69 + 70 70 + interrupts: 71 71 + items: 72 72 + - description: FIFO level 73 73 + - description: VSYNC 74 74 + - description: LCD system 75 75 + 76 76 + interrupt-names: 77 77 + items: 78 78 + - const: fifo 79 79 + - const: vsync 80 80 + - const: lcd_sys 81 81 + 82 82 + power-domains: 83 83 + maxItems: 1 84 84 + 85 85 + reg: 86 86 + maxItems: 1 87 87 + 88 88 + required: 89 89 + - compatible 90 90 + - clocks 91 91 + - clock-names 92 92 + - interrupts 93 93 + - interrupt-names 94 94 + - reg 95 95 + 96 96 + additionalProperties: false 97 97 + 98 98 + examples: 99 99 + - | 100 100 + #include <dt-bindings/clock/exynos7-clk.h> 101 101 + #include <dt-bindings/interrupt-controller/arm-gic.h> 102 102 + 103 103 + display-controller@13930000 { 104 104 + compatible = "samsung,exynos7-decon"; 105 105 + reg = <0x13930000 0x1000>; 106 106 + interrupt-names = "fifo", "vsync", "lcd_sys"; 107 107 + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 108 108 + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 109 109 + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 110 110 + clocks = <&clock_disp 100>, /* PCLK_DECON_INT */ 111 111 + <&clock_disp 101>, /* ACLK_DECON_INT */ 112 112 + <&clock_disp 102>, /* SCLK_DECON_INT_ECLK */ 113 113 + <&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */ 114 114 + clock-names = "pclk_decon0", 115 115 + "aclk_decon0", 116 116 + "decon0_eclk", 117 117 + "decon0_vclk"; 118 118 + pinctrl-0 = <&lcd_clk &pwm1_out>; 119 119 + pinctrl-names = "default"; 120 120 + };

+198

Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/display/samsung/samsung,fimd.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD) 8 8 + 9 9 + maintainers: 10 10 + - Inki Dae <inki.dae@samsung.com> 11 11 + - Joonyoung Shim <jy0922.shim@samsung.com> 12 12 + - Seung-Woo Kim <sw0312.kim@samsung.com> 13 13 + - Kyungmin Park <kyungmin.park@samsung.com> 14 14 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 15 15 + 16 16 + properties: 17 17 + compatible: 18 18 + enum: 19 19 + - samsung,s3c2443-fimd 20 20 + - samsung,s3c6400-fimd 21 21 + - samsung,s5pv210-fimd 22 22 + - samsung,exynos3250-fimd 23 23 + - samsung,exynos4210-fimd 24 24 + - samsung,exynos5250-fimd 25 25 + - samsung,exynos5420-fimd 26 26 + 27 27 + '#address-cells': 28 28 + const: 1 29 29 + 30 30 + clocks: 31 31 + minItems: 2 32 32 + maxItems: 2 33 33 + 34 34 + clock-names: 35 35 + items: 36 36 + - const: sclk_fimd 37 37 + - const: fimd 38 38 + 39 39 + display-timings: 40 40 + $ref: ../panel/display-timings.yaml# 41 41 + 42 42 + i80-if-timings: 43 43 + type: object 44 44 + description: | 45 45 + Timing configuration for lcd i80 interface support. 46 46 + The parameters are defined as:: 47 47 + VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|?? 48 48 + : : : : : 49 49 + Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX 50 50 + | cs-setup+1 | : : : 51 51 + |<---------->| : : : 52 52 + Chip Select ???????????????|____________:____________:____________|?? 53 53 + | wr-setup+1 | | wr-hold+1 | 54 54 + |<---------->| |<---------->| 55 55 + Write Enable ????????????????????????????|____________|??????????????? 56 56 + | wr-active+1| 57 57 + |<---------->| 58 58 + Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>-- 59 59 + 60 60 + properties: 61 61 + cs-setup: 62 62 + $ref: /schemas/types.yaml#/definitions/uint32 63 63 + description: 64 64 + Clock cycles for the active period of address signal is enabled until 65 65 + chip select is enabled. 66 66 + default: 0 67 67 + 68 68 + wr-active: 69 69 + $ref: /schemas/types.yaml#/definitions/uint32 70 70 + description: 71 71 + Clock cycles for the active period of CS is enabled. 72 72 + default: 1 73 73 + 74 74 + wr-hold: 75 75 + $ref: /schemas/types.yaml#/definitions/uint32 76 76 + description: 77 77 + Clock cycles for the active period of CS is disabled until write 78 78 + signal is disabled. 79 79 + default: 0 80 80 + 81 81 + wr-setup: 82 82 + $ref: /schemas/types.yaml#/definitions/uint32 83 83 + description: 84 84 + Clock cycles for the active period of CS signal is enabled until 85 85 + write signal is enabled. 86 86 + default: 0 87 87 + 88 88 + iommus: 89 89 + minItems: 1 90 90 + maxItems: 2 91 91 + 92 92 + iommu-names: 93 93 + items: 94 94 + - const: m0 95 95 + - const: m1 96 96 + 97 97 + interrupts: 98 98 + items: 99 99 + - description: FIFO level 100 100 + - description: VSYNC 101 101 + - description: LCD system 102 102 + 103 103 + interrupt-names: 104 104 + items: 105 105 + - const: fifo 106 106 + - const: vsync 107 107 + - const: lcd_sys 108 108 + 109 109 + power-domains: 110 110 + maxItems: 1 111 111 + 112 112 + reg: 113 113 + maxItems: 1 114 114 + 115 115 + samsung,invert-vden: 116 116 + type: boolean 117 117 + description: 118 118 + Video enable signal is inverted. 119 119 + 120 120 + samsung,invert-vclk: 121 121 + type: boolean 122 122 + description: 123 123 + Video clock signal is inverted. 124 124 + 125 125 + samsung,sysreg: 126 126 + $ref: /schemas/types.yaml#/definitions/phandle 127 127 + description: 128 128 + Phandle to System Register syscon. 129 129 + 130 130 + '#size-cells': 131 131 + const: 0 132 132 + 133 133 + patternProperties: 134 134 + "^port@[0-4]+$": 135 135 + $ref: /schemas/graph.yaml#/properties/port 136 136 + description: | 137 137 + Contains ports with port with index:: 138 138 + 0 - for CAMIF0 input, 139 139 + 1 - for CAMIF1 input, 140 140 + 2 - for CAMIF2 input, 141 141 + 3 - for parallel output, 142 142 + 4 - for write-back interface 143 143 + 144 144 + required: 145 145 + - compatible 146 146 + - clocks 147 147 + - clock-names 148 148 + - interrupts 149 149 + - interrupt-names 150 150 + - reg 151 151 + 152 152 + allOf: 153 153 + - if: 154 154 + properties: 155 155 + compatible: 156 156 + contains: 157 157 + const: samsung,exynos5420-fimd 158 158 + then: 159 159 + properties: 160 160 + iommus: 161 161 + minItems: 2 162 162 + maxItems: 2 163 163 + 164 164 + additionalProperties: false 165 165 + 166 166 + examples: 167 167 + - | 168 168 + #include <dt-bindings/clock/exynos4.h> 169 169 + 170 170 + fimd@11c00000 { 171 171 + compatible = "samsung,exynos4210-fimd"; 172 172 + interrupt-parent = <&combiner>; 173 173 + reg = <0x11c00000 0x20000>; 174 174 + interrupt-names = "fifo", "vsync", "lcd_sys"; 175 175 + interrupts = <11 0>, <11 1>, <11 2>; 176 176 + clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; 177 177 + clock-names = "sclk_fimd", "fimd"; 178 178 + power-domains = <&pd_lcd0>; 179 179 + iommus = <&sysmmu_fimd0>; 180 180 + samsung,sysreg = <&sys_reg>; 181 181 + 182 182 + #address-cells = <1>; 183 183 + #size-cells = <0>; 184 184 + 185 185 + samsung,invert-vden; 186 186 + samsung,invert-vclk; 187 187 + 188 188 + pinctrl-0 = <&lcd_clk>, <&lcd_data24>; 189 189 + pinctrl-names = "default"; 190 190 + 191 191 + port@3 { 192 192 + reg = <3>; 193 193 + 194 194 + fimd_dpi_ep: endpoint { 195 195 + remote-endpoint = <&lcd_ep>; 196 196 + }; 197 197 + }; 198 198 + };

+2

Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml

reviewed

··· 45 45 46 46 ports: 47 47 $ref: /schemas/types.yaml#/definitions/phandle-array 48 48 + items: 49 49 + maxItems: 1 48 50 description: 49 51 Should contain a list of phandles pointing to display interface port 50 52 of DPU devices.

+2 -2

Documentation/devicetree/bindings/display/ste,mcde.yaml

reviewed

··· 58 58 "^dsi@[0-9a-f]+$": 59 59 description: subnodes for the three DSI host adapters 60 60 type: object 61 61 - allOf: 62 62 - - $ref: dsi-controller.yaml# 61 61 + $ref: dsi-controller.yaml# 62 62 + 63 63 properties: 64 64 compatible: 65 65 const: ste,mcde-dsi

+1 -2

Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml

reviewed

··· 88 88 The DSS DPI output port node from video port 2 89 89 90 90 ti,am65x-oldi-io-ctrl: 91 91 - $ref: "/schemas/types.yaml#/definitions/phandle-array" 92 92 - maxItems: 1 91 91 + $ref: "/schemas/types.yaml#/definitions/phandle" 93 92 description: 94 93 phandle to syscon device node mapping OLDI IO_CTRL registers. 95 94 The mapped range should point to OLDI_DAT0_IO_CTRL, map it and

+2

Documentation/devicetree/bindings/dma/dma-router.yaml

reviewed

··· 24 24 25 25 dma-masters: 26 26 $ref: /schemas/types.yaml#/definitions/phandle-array 27 27 + items: 28 28 + maxItems: 1 27 29 description: 28 30 Array of phandles to the DMA controllers the router can direct 29 31 the signal to.

+5 -3

Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml

reviewed

··· 22 22 23 23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf 24 24 25 25 + allOf: 26 26 + - $ref: "dma-controller.yaml#" 27 27 + 25 28 properties: 26 29 compatible: 27 30 items: ··· 44 41 - compatible 45 42 - reg 46 43 - interrupts 47 47 - - '#dma-cells' 48 44 49 49 - additionalProperties: false 45 45 + unevaluatedProperties: false 50 46 51 47 examples: 52 48 - | 53 53 - dma@3000000 { 49 49 + dma-controller@3000000 { 54 50 compatible = "sifive,fu540-c000-pdma"; 55 51 reg = <0x3000000 0x8000>; 56 52 interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;

+1 -1

Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml

reviewed

··· 46 46 #dma-cells = <3>; 47 47 dma-requests = <128>; 48 48 dma-channels = <16>; 49 49 - dma-masters = <&dma1 &dma2>; 49 49 + dma-masters = <&dma1>, <&dma2>; 50 50 clocks = <&timer_clk>; 51 51 }; 52 52

+85

Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Xilinx ZynqMP DMA Engine 8 8 + 9 9 + description: | 10 10 + The Xilinx ZynqMP DMA engine supports memory to memory transfers, 11 11 + memory to device and device to memory transfers. It also has flow 12 12 + control and rate control support for slave/peripheral dma access. 13 13 + 14 14 + maintainers: 15 15 + - Michael Tretter <m.tretter@pengutronix.de> 16 16 + 17 17 + allOf: 18 18 + - $ref: "../dma-controller.yaml#" 19 19 + 20 20 + properties: 21 21 + "#dma-cells": 22 22 + const: 1 23 23 + 24 24 + compatible: 25 25 + const: xlnx,zynqmp-dma-1.0 26 26 + 27 27 + reg: 28 28 + description: memory map for gdma/adma module access 29 29 + maxItems: 1 30 30 + 31 31 + interrupts: 32 32 + description: DMA channel interrupt 33 33 + maxItems: 1 34 34 + 35 35 + clocks: 36 36 + description: input clocks 37 37 + minItems: 2 38 38 + maxItems: 2 39 39 + 40 40 + clock-names: 41 41 + items: 42 42 + - const: clk_main 43 43 + - const: clk_apb 44 44 + 45 45 + xlnx,bus-width: 46 46 + $ref: /schemas/types.yaml#/definitions/uint32 47 47 + enum: 48 48 + - 64 49 49 + - 128 50 50 + description: AXI bus width in bits 51 51 + 52 52 + iommus: 53 53 + maxItems: 1 54 54 + 55 55 + power-domains: 56 56 + maxItems: 1 57 57 + 58 58 + dma-coherent: 59 59 + description: present if dma operations are coherent 60 60 + 61 61 + required: 62 62 + - "#dma-cells" 63 63 + - compatible 64 64 + - reg 65 65 + - interrupts 66 66 + - clocks 67 67 + - clock-names 68 68 + 69 69 + additionalProperties: false 70 70 + 71 71 + examples: 72 72 + - | 73 73 + #include <dt-bindings/clock/xlnx-zynqmp-clk.h> 74 74 + 75 75 + fpd_dma_chan1: dma-controller@fd500000 { 76 76 + compatible = "xlnx,zynqmp-dma-1.0"; 77 77 + reg = <0xfd500000 0x1000>; 78 78 + interrupt-parent = <&gic>; 79 79 + interrupts = <0 117 0x4>; 80 80 + #dma-cells = <1>; 81 81 + clock-names = "clk_main", "clk_apb"; 82 82 + clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; 83 83 + xlnx,bus-width = <128>; 84 84 + dma-coherent; 85 85 + };

-26

Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt

reviewed

··· 1 1 - Xilinx ZynqMP DMA engine, it does support memory to memory transfers, 2 2 - memory to device and device to memory transfers. It also has flow 3 3 - control and rate control support for slave/peripheral dma access. 4 4 - 5 5 - Required properties: 6 6 - - compatible : Should be "xlnx,zynqmp-dma-1.0" 7 7 - - reg : Memory map for gdma/adma module access. 8 8 - - interrupts : Should contain DMA channel interrupt. 9 9 - - xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64 10 10 - - clock-names : List of input clocks "clk_main", "clk_apb" 11 11 - (see clock bindings for details) 12 12 - 13 13 - Optional properties: 14 14 - - dma-coherent : Present if dma operations are coherent. 15 15 - 16 16 - Example: 17 17 - ++++++++ 18 18 - fpd_dma_chan1: dma@fd500000 { 19 19 - compatible = "xlnx,zynqmp-dma-1.0"; 20 20 - reg = <0x0 0xFD500000 0x1000>; 21 21 - interrupt-parent = <&gic>; 22 22 - interrupts = <0 117 4>; 23 23 - clock-names = "clk_main", "clk_apb"; 24 24 - xlnx,bus-width = <128>; 25 25 - dma-coherent; 26 26 - };

-1

Documentation/devicetree/bindings/dvfs/performance-domain.yaml

reviewed

··· 43 43 44 44 performance-domains: 45 45 $ref: '/schemas/types.yaml#/definitions/phandle-array' 46 46 - maxItems: 1 47 46 description: 48 47 A phandle and performance domain specifier as defined by bindings of the 49 48 performance controller/provider specified by phandle.

+14

Documentation/devicetree/bindings/example-schema.yaml

reviewed

··· 162 162 don't need a type. 163 163 enum: [ 100, 200, 300 ] 164 164 165 165 + vendor,int-array-variable-length-and-constrained-values: 166 166 + description: Array might define what type of elements might be used (e.g. 167 167 + their range). 168 168 + $ref: /schemas/types.yaml#/definitions/uint32-array 169 169 + minItems: 2 170 170 + maxItems: 3 171 171 + items: 172 172 + minimum: 0 173 173 + maximum: 8 174 174 + 165 175 child-node: 166 176 description: Child nodes are just another property from a json-schema 167 177 perspective. ··· 217 207 then: 218 208 required: 219 209 - foo-supply 210 210 + else: 211 211 + # If otherwise the property is not allowed: 212 212 + properties: 213 213 + foo-supply: false 220 214 # Altering schema depending on presence of properties is usually done by 221 215 # dependencies (see above), however some adjustments might require if: 222 216 - if:

+1 -1

Documentation/devicetree/bindings/firmware/arm,scmi.yaml

reviewed

··· 364 364 firmware { 365 365 scmi { 366 366 compatible = "arm,scmi-smc"; 367 367 - shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>; 367 367 + shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>; 368 368 arm,smc-id = <0xc3000001>; 369 369 370 370 #address-cells = <1>;

+4 -2

Documentation/devicetree/bindings/firmware/arm,scpi.yaml

reviewed

··· 43 43 by remote SCP firmware for use by SCPI message protocol should be 44 44 specified in any order. 45 45 minItems: 1 46 46 + maxItems: 4 46 47 47 48 shmem: 48 49 description: ··· 52 51 be any memory reserved for the purpose of this communication between the 53 52 processors. 54 53 minItems: 1 54 54 + maxItems: 4 55 55 56 56 power-controller: 57 57 type: object ··· 237 235 firmware { 238 236 scpi { 239 237 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; 240 240 - mboxes = <&mailbox 1 &mailbox 2>; 241 241 - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 238 238 + mboxes = <&mailbox 1>, <&mailbox 2>; 239 239 + shmem = <&cpu_scp_lpri>, <&cpu_scp_hpri>; 242 240 243 241 scpi_sensors1: sensors { 244 242 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";

+54

Documentation/devicetree/bindings/firmware/qemu,fw-cfg-mmio.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/firmware/qemu,fw-cfg-mmio.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: QEMU Firmware Configuration bindings 8 8 + 9 9 + maintainers: 10 10 + - Rob Herring <robh@kernel.org> 11 11 + 12 12 + description: | 13 13 + Various QEMU emulation / virtualization targets provide the following 14 14 + Firmware Configuration interface on the "virt" machine type: 15 15 + 16 16 + - A write-only, 16-bit wide selector (or control) register, 17 17 + - a read-write, 64-bit wide data register. 18 18 + 19 19 + QEMU exposes the control and data register to guests as memory mapped 20 20 + registers; their location is communicated to the guest's UEFI firmware in the 21 21 + DTB that QEMU places at the bottom of the guest's DRAM. 22 22 + 23 23 + The authoritative guest-side hardware interface documentation to the fw_cfg 24 24 + device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree. 25 25 + 26 26 + 27 27 + properties: 28 28 + compatible: 29 29 + const: qemu,fw-cfg-mmio 30 30 + 31 31 + reg: 32 32 + maxItems: 1 33 33 + description: | 34 34 + * Bytes 0x0 to 0x7 cover the data register. 35 35 + * Bytes 0x8 to 0x9 cover the selector register. 36 36 + * Further registers may be appended to the region in case of future interface 37 37 + revisions / feature bits. 38 38 + 39 39 + dma-coherent: true 40 40 + 41 41 + required: 42 42 + - compatible 43 43 + - reg 44 44 + 45 45 + additionalProperties: false 46 46 + 47 47 + examples: 48 48 + - | 49 49 + 50 50 + fw-cfg@9020000 { 51 51 + compatible = "qemu,fw-cfg-mmio"; 52 52 + reg = <0x9020000 0xa>; 53 53 + }; 54 54 + ...

+55

Documentation/devicetree/bindings/gnss/gnss-common.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/gnss/gnss-common.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Common Properties for Global Navigation Satellite Systems (GNSS) 8 8 + receiver devices 9 9 + 10 10 + maintainers: 11 11 + - Johan Hovold <johan@kernel.org> 12 12 + 13 13 + description: | 14 14 + This document defines device tree properties common to Global Navigation 15 15 + Satellite System receivers. 16 16 + 17 17 + properties: 18 18 + $nodename: 19 19 + pattern: "^gnss(@.*)?$" 20 20 + 21 21 + lna-supply: 22 22 + description: A separate regulator supplying power for the Low Noise 23 23 + Amplifier (LNA). This is an amplifier connected between the GNSS 24 24 + device and the receiver antenna. 25 25 + 26 26 + enable-gpios: 27 27 + description: A GPIO line that will enable the GNSS receiver when 28 28 + asserted. If this line is active low, the GPIO phandle should 29 29 + consequently be tagged with the GPIO_ACTIVE_LOW flag so the operating 30 30 + system can rely on asserting the line to enable the GNSS device. 31 31 + maxItems: 1 32 32 + 33 33 + timepulse-gpios: 34 34 + description: When a timepulse is provided to the GNSS device using a 35 35 + GPIO line, this is used. 36 36 + maxItems: 1 37 37 + 38 38 + current-speed: 39 39 + description: The baudrate in bits per second of the device as it comes 40 40 + online, current active speed. 41 41 + $ref: /schemas/types.yaml#/definitions/uint32 42 42 + 43 43 + additionalProperties: true 44 44 + 45 45 + examples: 46 46 + - | 47 47 + #include <dt-bindings/gpio/gpio.h> 48 48 + serial { 49 49 + gnss { 50 50 + compatible = "u-blox,neo-8"; 51 51 + vcc-supply = <&gnss_reg>; 52 52 + timepulse-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; 53 53 + current-speed = <4800>; 54 54 + }; 55 55 + };

-37

Documentation/devicetree/bindings/gnss/gnss.txt

reviewed

··· 1 1 - GNSS Receiver DT binding 2 2 - 3 3 - This documents the binding structure and common properties for GNSS receiver 4 4 - devices. 5 5 - 6 6 - A GNSS receiver node is a node named "gnss" and typically resides on a serial 7 7 - bus (e.g. UART, I2C or SPI). 8 8 - 9 9 - Please refer to the following documents for generic properties: 10 10 - 11 11 - Documentation/devicetree/bindings/serial/serial.yaml 12 12 - Documentation/devicetree/bindings/spi/spi-bus.txt 13 13 - 14 14 - Required properties: 15 15 - 16 16 - - compatible : A string reflecting the vendor and specific device the node 17 17 - represents 18 18 - 19 19 - Optional properties: 20 20 - - lna-supply : Separate supply for an LNA 21 21 - - enable-gpios : GPIO used to enable the device 22 22 - - timepulse-gpios : Time pulse GPIO 23 23 - 24 24 - Example: 25 25 - 26 26 - serial@1234 { 27 27 - compatible = "ns16550a"; 28 28 - 29 29 - gnss { 30 30 - compatible = "u-blox,neo-8"; 31 31 - 32 32 - vcc-supply = <&gnss_reg>; 33 33 - timepulse-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; 34 34 - 35 35 - current-speed = <4800>; 36 36 - }; 37 37 - };

-46

Documentation/devicetree/bindings/gnss/sirfstar.txt

reviewed

··· 1 1 - SiRFstar-based GNSS Receiver DT binding 2 2 - 3 3 - SiRFstar chipsets are used in GNSS-receiver modules produced by several 4 4 - vendors and can use UART, SPI or I2C interfaces. 5 5 - 6 6 - Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic 7 7 - properties. 8 8 - 9 9 - Required properties: 10 10 - 11 11 - - compatible : Must be one of 12 12 - 13 13 - "fastrax,uc430" 14 14 - "linx,r4" 15 15 - "wi2wi,w2sg0004" 16 16 - "wi2wi,w2sg0008i" 17 17 - "wi2wi,w2sg0084i" 18 18 - 19 19 - - vcc-supply : Main voltage regulator (pin name: 3V3_IN, VCC, VDD) 20 20 - 21 21 - Required properties (I2C): 22 22 - - reg : I2C slave address 23 23 - 24 24 - Required properties (SPI): 25 25 - - reg : SPI chip select address 26 26 - 27 27 - Optional properties: 28 28 - 29 29 - - sirf,onoff-gpios : GPIO used to power on and off device (pin name: ON_OFF) 30 30 - - sirf,wakeup-gpios : GPIO used to determine device power state 31 31 - (pin name: RFPWRUP, WAKEUP) 32 32 - - timepulse-gpios : Time pulse GPIO (pin name: 1PPS, TM) 33 33 - 34 34 - Example: 35 35 - 36 36 - serial@1234 { 37 37 - compatible = "ns16550a"; 38 38 - 39 39 - gnss { 40 40 - compatible = "wi2wi,w2sg0084i"; 41 41 - 42 42 - vcc-supply = <&gnss_reg>; 43 43 - sirf,onoff-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; 44 44 - sirf,wakeup-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; 45 45 - }; 46 46 - };

+76

Documentation/devicetree/bindings/gnss/sirfstar.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/gnss/sirfstar.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: SiRFstar GNSS Receiver Device Tree Bindings 8 8 + 9 9 + maintainers: 10 10 + - Johan Hovold <johan@kernel.org> 11 11 + 12 12 + description: 13 13 + The SiRFstar GNSS receivers have incarnated over the years in different 14 14 + chips, starting from the SiRFstarIII which was a chip that was introduced in 15 15 + 2004 and used in a lot of dedicated GPS devices. In 2009 SiRF was acquired 16 16 + by CSR (Cambridge Silicon Radio) and in 2012 the CSR GPS business was 17 17 + acquired by Samsung, while some products remained with CSR. In 2014 CSR 18 18 + was acquired by Qualcomm who still sell some of the SiRF products. 19 19 + 20 20 + SiRF chips can be used over UART, I2C or SPI buses. 21 21 + 22 22 + allOf: 23 23 + - $ref: gnss-common.yaml# 24 24 + 25 25 + properties: 26 26 + compatible: 27 27 + enum: 28 28 + - csr,gsd4t 29 29 + - csr,csrg05ta03-icje-r 30 30 + - fastrax,uc430 31 31 + - linx,r4 32 32 + - wi2wi,w2sg0004 33 33 + - wi2wi,w2sg0008i 34 34 + - wi2wi,w2sg0084i 35 35 + 36 36 + reg: 37 37 + description: 38 38 + The I2C Address, SPI chip select address. Not required on UART buses. 39 39 + 40 40 + vcc-supply: 41 41 + description: 42 42 + Main voltage regulator, pin names such as 3V3_IN, VCC, VDD. 43 43 + 44 44 + reset-gpios: 45 45 + maxItems: 1 46 46 + description: An optional active low reset line, should be flagged with 47 47 + GPIO_ACTIVE_LOW. 48 48 + 49 49 + sirf,onoff-gpios: 50 50 + maxItems: 1 51 51 + description: GPIO used to power on and off device, pin name ON_OFF. 52 52 + 53 53 + sirf,wakeup-gpios: 54 54 + maxItems: 1 55 55 + description: GPIO used to determine device power state, pin names such 56 56 + as RFPWRUP, WAKEUP. 57 57 + 58 58 + required: 59 59 + - compatible 60 60 + - vcc-supply 61 61 + 62 62 + unevaluatedProperties: false 63 63 + 64 64 + examples: 65 65 + - | 66 66 + #include <dt-bindings/gpio/gpio.h> 67 67 + serial { 68 68 + gnss { 69 69 + compatible = "wi2wi,w2sg0084i"; 70 70 + vcc-supply = <&gnss_vcc_reg>; 71 71 + reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; 72 72 + sirf,onoff-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; 73 73 + sirf,wakeup-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; 74 74 + current-speed = <38400>; 75 75 + }; 76 76 + };

+5 -9

Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml

reviewed

··· 6 6 7 7 title: U-blox GNSS Receiver Device Tree Bindings 8 8 9 9 + allOf: 10 10 + - $ref: gnss-common.yaml# 11 11 + 9 12 maintainers: 10 13 - Johan Hovold <johan@kernel.org> 11 14 ··· 32 29 description: > 33 30 Main voltage regulator 34 31 35 35 - timepulse-gpios: 36 36 - maxItems: 1 37 37 - description: > 38 38 - Time pulse GPIO 39 39 - 40 32 u-blox,extint-gpios: 41 33 maxItems: 1 42 34 description: > 43 35 GPIO connected to the "external interrupt" input pin 44 44 - 36 36 + 45 37 v-bckp-supply: 46 38 description: > 47 39 Backup voltage regulator 48 48 - 49 49 - current-speed: true 50 40 51 41 required: 52 42 - compatible 53 43 - vcc-supply 54 44 55 55 - additionalProperties: false 45 45 + unevaluatedProperties: false 56 46 57 47 examples: 58 48 - |

-8

Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml

reviewed

··· 190 190 "chg-status+red", "green", "blue", "en-esata", 191 191 "fault1", "p26", "p27"; 192 192 }; 193 193 - 194 194 - ts3a227@3b { 195 195 - compatible = "ti,ts3a227e"; 196 196 - reg = <0x3b>; 197 197 - interrupt-parent = <&gpio99>; 198 198 - interrupts = <14 IRQ_TYPE_EDGE_RISING>; 199 199 - ti,micbias = <0>; /* 2.1V */ 200 200 - }; 201 193 }; 202 194 203 195 - |

+146

Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries 3 3 + %YAML 1.2 4 4 + --- 5 5 + $id: http://devicetree.org/schemas/i2c/atmel,at91sam-i2c.yaml# 6 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 7 + 8 8 + title: I2C for Atmel/Microchip platforms 9 9 + 10 10 + maintainers: 11 11 + - Alexandre Belloni <alexandre.belloni@bootlin.com> 12 12 + 13 13 + properties: 14 14 + compatible: 15 15 + oneOf: 16 16 + - items: 17 17 + - enum: 18 18 + - atmel,at91rm9200-i2c 19 19 + - atmel,at91sam9261-i2c 20 20 + - atmel,at91sam9260-i2c 21 21 + - atmel,at91sam9g20-i2c 22 22 + - atmel,at91sam9g10-i2c 23 23 + - atmel,at91sam9x5-i2c 24 24 + - atmel,sama5d4-i2c 25 25 + - atmel,sama5d2-i2c 26 26 + - microchip,sam9x60-i2c 27 27 + - items: 28 28 + - const: microchip,sama7g5-i2c 29 29 + - const: microchip,sam9x60-i2c 30 30 + 31 31 + reg: 32 32 + maxItems: 1 33 33 + 34 34 + interrupts: 35 35 + maxItems: 1 36 36 + 37 37 + "#address-cells": 38 38 + const: 1 39 39 + 40 40 + "#size-cells": 41 41 + const: 0 42 42 + 43 43 + clocks: 44 44 + maxItems: 1 45 45 + 46 46 + clock-frequency: 47 47 + default: 100000 48 48 + 49 49 + dmas: 50 50 + items: 51 51 + - description: TX DMA Channel Specifier 52 52 + - description: RX DMA Channel Specifier 53 53 + 54 54 + dma-names: 55 55 + items: 56 56 + - const: tx 57 57 + - const: rx 58 58 + 59 59 + atmel,fifo-size: 60 60 + $ref: /schemas/types.yaml#/definitions/uint32 61 61 + description: | 62 62 + Maximum number of data the RX and TX FIFOs can store for 63 63 + FIFO capable I2C controllers. 64 64 + 65 65 + scl-gpios: true 66 66 + 67 67 + sda-gpios: true 68 68 + 69 69 + required: 70 70 + - compatible 71 71 + - reg 72 72 + - interrupts 73 73 + - "#address-cells" 74 74 + - "#size-cells" 75 75 + - clocks 76 76 + 77 77 + allOf: 78 78 + - $ref: "i2c-controller.yaml" 79 79 + - if: 80 80 + properties: 81 81 + compatible: 82 82 + contains: 83 83 + enum: 84 84 + - atmel,sama5d4-i2c 85 85 + - atmel,sama5d2-i2c 86 86 + - microchip,sam9x60-i2c 87 87 + - microchip,sama7g5-i2c 88 88 + then: 89 89 + properties: 90 90 + i2c-sda-hold-time-ns: 91 91 + description: 92 92 + TWD hold time 93 93 + maxItems: 1 94 94 + 95 95 + unevaluatedProperties: false 96 96 + 97 97 + examples: 98 98 + - | 99 99 + #include <dt-bindings/interrupt-controller/irq.h> 100 100 + #include <dt-bindings/dma/at91.h> 101 101 + #include <dt-bindings/gpio/gpio.h> 102 102 + 103 103 + i2c0: i2c@fff84000 { 104 104 + compatible = "atmel,at91sam9g20-i2c"; 105 105 + reg = <0xfff84000 0x100>; 106 106 + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; 107 107 + #address-cells = <1>; 108 108 + #size-cells = <0>; 109 109 + clocks = <&twi0_clk>; 110 110 + clock-frequency = <400000>; 111 111 + 112 112 + eeprom@50 { 113 113 + compatible = "atmel,24c512"; 114 114 + reg = <0x50>; 115 115 + pagesize = <128>; 116 116 + }; 117 117 + }; 118 118 + 119 119 + i2c1: i2c@f8034600 { 120 120 + compatible = "atmel,sama5d2-i2c"; 121 121 + reg = <0xf8034600 0x100>; 122 122 + interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 123 123 + dmas = <&dma0 124 124 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) 125 125 + AT91_XDMAC_DT_PERID(11)>, 126 126 + <&dma0 127 127 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) 128 128 + AT91_XDMAC_DT_PERID(12)>; 129 129 + dma-names = "tx", "rx"; 130 130 + #address-cells = <1>; 131 131 + #size-cells = <0>; 132 132 + clocks = <&flx0>; 133 133 + atmel,fifo-size = <16>; 134 134 + i2c-sda-hold-time-ns = <336>; 135 135 + pinctrl-names = "default", "gpio"; 136 136 + pinctrl-0 = <&pinctrl_i2c0>; 137 137 + pinctrl-1 = <&pinctrl_i2c0_gpio>; 138 138 + sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; 139 139 + scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 140 140 + 141 141 + eeprom@54 { 142 142 + compatible = "atmel,24c02"; 143 143 + reg = <0x54>; 144 144 + pagesize = <16>; 145 145 + }; 146 146 + };

-82

Documentation/devicetree/bindings/i2c/i2c-at91.txt

reviewed

··· 1 1 - I2C for Atmel platforms 2 2 - 3 3 - Required properties : 4 4 - - compatible : Must be one of: 5 5 - "atmel,at91rm9200-i2c", 6 6 - "atmel,at91sam9261-i2c", 7 7 - "atmel,at91sam9260-i2c", 8 8 - "atmel,at91sam9g20-i2c", 9 9 - "atmel,at91sam9g10-i2c", 10 10 - "atmel,at91sam9x5-i2c", 11 11 - "atmel,sama5d4-i2c", 12 12 - "atmel,sama5d2-i2c", 13 13 - "microchip,sam9x60-i2c". 14 14 - - reg: physical base address of the controller and length of memory mapped 15 15 - region. 16 16 - - interrupts: interrupt number to the cpu. 17 17 - - #address-cells = <1>; 18 18 - - #size-cells = <0>; 19 19 - - clocks: phandles to input clocks. 20 20 - 21 21 - Optional properties: 22 22 - - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 23 23 - - dmas: A list of two dma specifiers, one for each entry in dma-names. 24 24 - - dma-names: should contain "tx" and "rx". 25 25 - - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO 26 26 - capable I2C controllers. 27 27 - - i2c-sda-hold-time-ns: TWD hold time, only available for: 28 28 - "atmel,sama5d4-i2c", 29 29 - "atmel,sama5d2-i2c", 30 30 - "microchip,sam9x60-i2c". 31 31 - - scl-gpios: specify the gpio related to SCL pin 32 32 - - sda-gpios: specify the gpio related to SDA pin 33 33 - - pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c 34 34 - bus recovery, call it "gpio" state 35 35 - - Child nodes conforming to i2c bus binding 36 36 - 37 37 - 38 38 - Examples : 39 39 - 40 40 - i2c0: i2c@fff84000 { 41 41 - compatible = "atmel,at91sam9g20-i2c"; 42 42 - reg = <0xfff84000 0x100>; 43 43 - interrupts = <12 4 6>; 44 44 - #address-cells = <1>; 45 45 - #size-cells = <0>; 46 46 - clocks = <&twi0_clk>; 47 47 - clock-frequency = <400000>; 48 48 - 49 49 - 24c512@50 { 50 50 - compatible = "atmel,24c512"; 51 51 - reg = <0x50>; 52 52 - pagesize = <128>; 53 53 - } 54 54 - } 55 55 - 56 56 - i2c0: i2c@f8034600 { 57 57 - compatible = "atmel,sama5d2-i2c"; 58 58 - reg = <0xf8034600 0x100>; 59 59 - interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 60 60 - dmas = <&dma0 61 61 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) 62 62 - AT91_XDMAC_DT_PERID(11)>, 63 63 - <&dma0 64 64 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) 65 65 - AT91_XDMAC_DT_PERID(12)>; 66 66 - dma-names = "tx", "rx"; 67 67 - #address-cells = <1>; 68 68 - #size-cells = <0>; 69 69 - clocks = <&flx0>; 70 70 - atmel,fifo-size = <16>; 71 71 - i2c-sda-hold-time-ns = <336>; 72 72 - pinctrl-names = "default", "gpio"; 73 73 - pinctrl-0 = <&pinctrl_i2c0>; 74 74 - pinctrl-1 = <&pinctrl_i2c0_gpio>; 75 75 - sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; 76 76 - scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 77 77 - 78 78 - wm8731: wm8731@1a { 79 79 - compatible = "wm8731"; 80 80 - reg = <0x1a>; 81 81 - }; 82 82 - };

+4 -3

Documentation/devicetree/bindings/i2c/i2c-imx.yaml

reviewed

··· 88 88 examples: 89 89 - | 90 90 #include <dt-bindings/clock/imx5-clock.h> 91 91 - #include <dt-bindings/clock/vf610-clock.h> 92 92 - #include <dt-bindings/gpio/gpio.h> 93 93 - #include <dt-bindings/interrupt-controller/arm-gic.h> 91 91 + #include <dt-bindings/interrupt-controller/irq.h> 94 92 95 93 i2c@83fc4000 { 96 94 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; ··· 96 98 interrupts = <63>; 97 99 clocks = <&clks IMX5_CLK_I2C2_GATE>; 98 100 }; 101 101 + 102 102 + - | 103 103 + #include <dt-bindings/clock/vf610-clock.h> 99 104 100 105 i2c@40066000 { 101 106 compatible = "fsl,vf610-i2c";

+2

Documentation/devicetree/bindings/i2c/i2c-mpc.yaml

reviewed

··· 73 73 clock-frequency = <100000>; 74 74 }; 75 75 76 76 + - | 76 77 /* MPC5200B based board */ 77 78 i2c@3d00 { 78 79 #address-cells = <1>; ··· 85 84 fsl,preserve-clocking; 86 85 }; 87 86 87 87 + - | 88 88 /* MPC8544 base board */ 89 89 i2c@3100 { 90 90 #address-cells = <1>;

-58

Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt

reviewed

··· 1 1 - * Samsung's I2C controller 2 2 - 3 3 - The Samsung's I2C controller is used to interface with I2C devices. 4 4 - 5 5 - Required properties: 6 6 - - compatible: value should be either of the following. 7 7 - (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c. 8 8 - (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c. 9 9 - (c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used 10 10 - inside HDMIPHY block found on several samsung SoCs 11 11 - (d) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as 12 12 - a host to SATA PHY controller on an internal bus. 13 13 - - reg: physical base address of the controller and length of memory mapped 14 14 - region. 15 15 - - interrupts: interrupt number to the cpu. 16 16 - - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges. 17 17 - 18 18 - Required for all cases except "samsung,s3c2440-hdmiphy-i2c": 19 19 - - Samsung GPIO variant (deprecated): 20 20 - - gpios: The order of the gpios should be the following: <SDA, SCL>. 21 21 - The gpio specifier depends on the gpio controller. Required in all 22 22 - cases except for "samsung,s3c2440-hdmiphy-i2c" whose input/output 23 23 - lines are permanently wired to the respective clienta 24 24 - - Pinctrl variant (preferred, if available): 25 25 - - pinctrl-0: Pin control group to be used for this controller. 26 26 - - pinctrl-names: Should contain only one value - "default". 27 27 - 28 28 - Optional properties: 29 29 - - samsung,i2c-slave-addr: Slave address in multi-master environment. If not 30 30 - specified, default value is 0. 31 31 - - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not 32 32 - specified, the default value in Hz is 100000. 33 33 - - samsung,sysreg-phandle - handle to syscon used to control the system registers 34 34 - 35 35 - Example: 36 36 - 37 37 - i2c@13870000 { 38 38 - compatible = "samsung,s3c2440-i2c"; 39 39 - reg = <0x13870000 0x100>; 40 40 - interrupts = <345>; 41 41 - samsung,i2c-sda-delay = <100>; 42 42 - samsung,i2c-max-bus-freq = <100000>; 43 43 - /* Samsung GPIO variant begins here */ 44 44 - gpios = <&gpd1 2 0 /* SDA */ 45 45 - &gpd1 3 0 /* SCL */>; 46 46 - /* Samsung GPIO variant ends here */ 47 47 - /* Pinctrl variant begins here */ 48 48 - pinctrl-0 = <&i2c3_bus>; 49 49 - pinctrl-names = "default"; 50 50 - /* Pinctrl variant ends here */ 51 51 - #address-cells = <1>; 52 52 - #size-cells = <0>; 53 53 - 54 54 - wm8994@1a { 55 55 - compatible = "wlf,wm8994"; 56 56 - reg = <0x1a>; 57 57 - }; 58 58 - };

+1 -3

Documentation/devicetree/bindings/i2c/ingenic,i2c.yaml

reviewed

··· 69 69 #size-cells = <0>; 70 70 reg = <0x10054000 0x1000>; 71 71 72 72 - interrupt-parent = <&intc>; 73 73 - interrupts = <56>; 72 72 + interrupts = <56 IRQ_TYPE_LEVEL_LOW>; 74 73 75 74 clocks = <&cgu JZ4780_CLK_SMB4>; 76 75 pinctrl-names = "default"; ··· 85 86 compatible = "nxp,pcf8563"; 86 87 reg = <0x51>; 87 88 88 88 - interrupt-parent = <&gpf>; 89 89 interrupts = <30 IRQ_TYPE_LEVEL_LOW>; 90 90 }; 91 91 };

+2

Documentation/devicetree/bindings/i2c/renesas,riic.yaml

reviewed

··· 20 20 - renesas,riic-r7s72100 # RZ/A1H 21 21 - renesas,riic-r7s9210 # RZ/A2M 22 22 - renesas,riic-r9a07g044 # RZ/G2{L,LC} 23 23 + - renesas,riic-r9a07g054 # RZ/V2L 23 24 - const: renesas,riic-rz # RZ/A or RZ/G2L 24 25 25 26 reg: ··· 76 75 contains: 77 76 enum: 78 77 - renesas,riic-r9a07g044 78 78 + - renesas,riic-r9a07g054 79 79 then: 80 80 required: 81 81 - resets

+164

Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/i2c/samsung,s3c2410-i2c.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Samsung S3C/S5P/Exynos SoC I2C Controller 8 8 + 9 9 + maintainers: 10 10 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 11 11 + 12 12 + properties: 13 13 + compatible: 14 14 + enum: 15 15 + - samsung,s3c2410-i2c 16 16 + - samsung,s3c2440-i2c 17 17 + # For s3c2440-like I2C used inside HDMIPHY block found on several SoCs: 18 18 + - samsung,s3c2440-hdmiphy-i2c 19 19 + # For s3c2440-like I2C used as a host to SATA PHY controller on an 20 20 + # internal bus: 21 21 + - samsung,exynos5-sata-phy-i2c 22 22 + 23 23 + '#address-cells': 24 24 + const: 1 25 25 + 26 26 + clocks: 27 27 + maxItems: 1 28 28 + 29 29 + clock-names: 30 30 + items: 31 31 + - const: i2c 32 32 + 33 33 + gpios: 34 34 + description: | 35 35 + The order of the GPIOs should be the following:: <SDA, SCL>. The GPIO 36 36 + specifier depends on the gpio controller. Required in all cases except 37 37 + for "samsung,s3c2440-hdmiphy-i2c" whose input/output lines are 38 38 + permanently wired to the respective client. 39 39 + This property is deprecated. Use "pinctrl-0" and "pinctrl-names" instead. 40 40 + deprecated: yes 41 41 + 42 42 + interrupts: 43 43 + maxItems: 1 44 44 + 45 45 + reg: 46 46 + maxItems: 1 47 47 + 48 48 + samsung,i2c-max-bus-freq: 49 49 + $ref: /schemas/types.yaml#/definitions/uint32 50 50 + description: 51 51 + Desired frequency in Hz of the bus. 52 52 + default: 100000 53 53 + 54 54 + samsung,i2c-sda-delay: 55 55 + $ref: /schemas/types.yaml#/definitions/uint32 56 56 + description: 57 57 + Delay (in ns) applied to data line (SDA) edges. 58 58 + default: 0 59 59 + 60 60 + samsung,i2c-slave-addr: 61 61 + $ref: /schemas/types.yaml#/definitions/uint32 62 62 + description: 63 63 + Slave address in multi-master environment. 64 64 + default: 0 65 65 + 66 66 + samsung,sysreg-phandle: 67 67 + $ref: /schemas/types.yaml#/definitions/phandle 68 68 + description: Pandle to syscon used to control the system registers. 69 69 + 70 70 + '#size-cells': 71 71 + const: 0 72 72 + 73 73 + required: 74 74 + - compatible 75 75 + - reg 76 76 + 77 77 + allOf: 78 78 + - $ref: /schemas/i2c/i2c-controller.yaml# 79 79 + - if: 80 80 + properties: 81 81 + compatible: 82 82 + contains: 83 83 + enum: 84 84 + - samsung,s3c2440-hdmiphy-i2c 85 85 + - samsung,exynos5-sata-phy-i2c 86 86 + then: 87 87 + properties: 88 88 + gpios: false 89 89 + 90 90 + - if: 91 91 + properties: 92 92 + compatible: 93 93 + contains: 94 94 + enum: 95 95 + - samsung,s3c2410-i2c 96 96 + - samsung,s3c2440-i2c 97 97 + - samsung,s3c2440-hdmiphy-i2c 98 98 + then: 99 99 + required: 100 100 + - interrupts 101 101 + 102 102 + unevaluatedProperties: false 103 103 + 104 104 + examples: 105 105 + - | 106 106 + #include <dt-bindings/clock/exynos5250.h> 107 107 + #include <dt-bindings/interrupt-controller/arm-gic.h> 108 108 + 109 109 + i2c@12c60000 { 110 110 + compatible = "samsung,s3c2440-i2c"; 111 111 + reg = <0x12C60000 0x100>; 112 112 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 113 113 + #address-cells = <1>; 114 114 + #size-cells = <0>; 115 115 + clocks = <&clock CLK_I2C0>; 116 116 + clock-names = "i2c"; 117 117 + pinctrl-names = "default"; 118 118 + pinctrl-0 = <&i2c0_bus>; 119 119 + 120 120 + samsung,sysreg-phandle = <&sysreg_system_controller>; 121 121 + samsung,i2c-sda-delay = <100>; 122 122 + samsung,i2c-max-bus-freq = <20000>; 123 123 + samsung,i2c-slave-addr = <0x66>; 124 124 + 125 125 + eeprom@50 { 126 126 + compatible = "samsung,s524ad0xd1"; 127 127 + reg = <0x50>; 128 128 + }; 129 129 + }; 130 130 + 131 131 + i2c@12ce0000 { 132 132 + compatible = "samsung,s3c2440-hdmiphy-i2c"; 133 133 + reg = <0x12CE0000 0x1000>; 134 134 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 135 135 + #address-cells = <1>; 136 136 + #size-cells = <0>; 137 137 + clocks = <&clock CLK_I2C_HDMI>; 138 138 + clock-names = "i2c"; 139 139 + 140 140 + samsung,i2c-sda-delay = <100>; 141 141 + samsung,i2c-max-bus-freq = <66000>; 142 142 + 143 143 + phy-i2c@38 { 144 144 + compatible = "samsung,exynos4212-hdmiphy"; 145 145 + reg = <0x38>; 146 146 + }; 147 147 + }; 148 148 + 149 149 + i2c@121d0000 { 150 150 + compatible = "samsung,exynos5-sata-phy-i2c"; 151 151 + reg = <0x121D0000 0x100>; 152 152 + #address-cells = <1>; 153 153 + #size-cells = <0>; 154 154 + clocks = <&clock CLK_SATA_PHYI2C>; 155 155 + clock-names = "i2c"; 156 156 + 157 157 + samsung,i2c-sda-delay = <100>; 158 158 + samsung,i2c-max-bus-freq = <40000>; 159 159 + 160 160 + phy-i2c@38 { 161 161 + compatible = "samsung,exynos-sataphy-i2c"; 162 162 + reg = <0x38>; 163 163 + }; 164 164 + };

+13 -11

Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml

reviewed

··· 25 25 26 26 i2c-scl-falling-time-ns: 27 27 default: 10 28 28 - 29 29 - st,syscfg-fmp: 30 30 - description: Use to set Fast Mode Plus bit within SYSCFG when 31 31 - Fast Mode Plus speed is selected by slave. 32 32 - Format is phandle to syscfg / register offset within 33 33 - syscfg / register bitmask for FMP bit. 34 34 - $ref: "/schemas/types.yaml#/definitions/phandle-array" 35 35 - items: 36 36 - minItems: 3 37 37 - maxItems: 3 28 28 + else: 29 29 + properties: 30 30 + st,syscfg-fmp: false 38 31 39 32 - if: 40 33 properties: ··· 79 86 default: 100000 80 87 minimum: 1 81 88 maximum: 1000000 89 89 + 90 90 + st,syscfg-fmp: 91 91 + description: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode 92 92 + Plus speed is selected by slave. 93 93 + $ref: "/schemas/types.yaml#/definitions/phandle-array" 94 94 + items: 95 95 + - items: 96 96 + - description: phandle to syscfg 97 97 + - description: register offset within syscfg 98 98 + - description: register bitmask for FMP bit 82 99 83 100 required: 84 101 - compatible ··· 150 147 i2c-scl-falling-time-ns = <20>; 151 148 st,syscfg-fmp = <&syscfg 0x4 0x2>; 152 149 }; 153 153 - ...

+4 -5

Documentation/devicetree/bindings/input/adc-joystick.yaml

reviewed

··· 61 61 description: EV_ABS specific event code generated by the axis. 62 62 63 63 abs-range: 64 64 - allOf: 65 65 - - $ref: /schemas/types.yaml#/definitions/uint32-array 66 66 - - items: 67 67 - - description: minimum value 68 68 - - description: maximum value 64 64 + $ref: /schemas/types.yaml#/definitions/uint32-array 65 65 + items: 66 66 + - description: minimum value 67 67 + - description: maximum value 69 68 description: > 70 69 Minimum and maximum values produced by the axis. 71 70 For an ABS_X axis this will be the left-most and right-most

+2

Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml

reviewed

··· 121 121 122 122 qcom,bcm-voters: 123 123 $ref: /schemas/types.yaml#/definitions/phandle-array 124 124 + items: 125 125 + maxItems: 1 124 126 description: | 125 127 List of phandles to qcom,bcm-voter nodes that are required by 126 128 this interconnect to send RPMh commands.

+4 -2

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

reviewed

··· 138 138 properties: 139 139 affinity: 140 140 $ref: /schemas/types.yaml#/definitions/phandle-array 141 141 + items: 142 142 + maxItems: 1 141 143 description: 142 144 Should be a list of phandles to CPU nodes (as described in 143 145 Documentation/devicetree/bindings/arm/cpus.yaml). ··· 275 273 276 274 ppi-partitions { 277 275 part0: interrupt-partition-0 { 278 278 - affinity = <&cpu0 &cpu2>; 276 276 + affinity = <&cpu0>, <&cpu2>; 279 277 }; 280 278 281 279 part1: interrupt-partition-1 { 282 282 - affinity = <&cpu1 &cpu3>; 280 280 + affinity = <&cpu1>, <&cpu3>; 283 281 }; 284 282 }; 285 283 };

+2

Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml

reviewed

··· 77 77 78 78 ti,unmapped-event-sources: 79 79 $ref: /schemas/types.yaml#/definitions/phandle-array 80 80 + items: 81 81 + maxItems: 1 80 82 description: 81 83 Array of phandles to DMA controllers where the unmapped events originate. 82 84

+4 -2

Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml

reviewed

··· 101 101 $ref: /schemas/types.yaml#/definitions/phandle-array 102 102 minItems: 1 103 103 maxItems: 32 104 104 + items: 105 105 + maxItems: 1 104 106 description: | 105 107 List of phandle to the local arbiters in the current Socs. 106 108 Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort ··· 169 167 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 170 168 clocks = <&infracfg CLK_INFRA_M4U>; 171 169 clock-names = "bclk"; 172 172 - mediatek,larbs = <&larb0 &larb1 &larb2 173 173 - &larb3 &larb4 &larb5>; 170 170 + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 171 171 + <&larb3>, <&larb4>, <&larb5>; 174 172 #iommu-cells = <1>; 175 173 }; 176 174

+6

Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml

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··· 70 70 71 71 renesas,ipmmu-main: 72 72 $ref: /schemas/types.yaml#/definitions/phandle-array 73 73 + items: 74 74 + - items: 75 75 + - description: phandle to main IPMMU 76 76 + - description: the interrupt bit number associated with the particular 77 77 + cache IPMMU device. The interrupt bit number needs to match the main 78 78 + IPMMU IMSSTR register. Only used by cache IPMMU instances. 73 79 description: 74 80 Reference to the main IPMMU phandle plus 1 cell. The cell is 75 81 the interrupt bit number associated with the particular cache IPMMU

+2

Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml

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··· 23 23 leds: 24 24 description: A list of LED nodes 25 25 $ref: /schemas/types.yaml#/definitions/phandle-array 26 26 + items: 27 27 + maxItems: 1 26 28 27 29 brightness-levels: 28 30 description:

+1 -2

Documentation/devicetree/bindings/leds/cznic,turris-omnia-leds.yaml

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··· 32 32 patternProperties: 33 33 "^multi-led@[0-9a-b]$": 34 34 type: object 35 35 - allOf: 36 36 - - $ref: leds-class-multicolor.yaml# 35 35 + $ref: leds-class-multicolor.yaml# 37 36 description: 38 37 This node represents one of the RGB LED devices on Turris Omnia. 39 38 No subnodes need to be added for subchannels since this controller only

+1 -2

Documentation/devicetree/bindings/leds/leds-lp50xx.yaml

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··· 55 55 patternProperties: 56 56 '^multi-led@[0-9a-f]$': 57 57 type: object 58 58 - allOf: 59 59 - - $ref: leds-class-multicolor.yaml# 58 58 + $ref: leds-class-multicolor.yaml# 60 59 properties: 61 60 reg: 62 61 minItems: 1

+4

Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml

reviewed

··· 48 48 49 49 allwinner,sram: 50 50 $ref: /schemas/types.yaml#/definitions/phandle-array 51 51 + items: 52 52 + - items: 53 53 + - description: phandle to SRAM 54 54 + - description: register value for device 51 55 description: Phandle to the device SRAM 52 56 53 57 iommus:

+5 -5

Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml

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··· 58 58 req_gpr is the gpr register offset of RX_ENABLE for the mipi phy. 59 59 $ref: /schemas/types.yaml#/definitions/phandle-array 60 60 items: 61 61 - items: 62 62 - - description: The 'gpr' is the phandle to general purpose register node. 63 63 - - description: The 'req_gpr' is the gpr register offset containing 64 64 - CSI2_1_RX_ENABLE or CSI2_2_RX_ENABLE respectively. 65 65 - maximum: 0xff 61 61 + - items: 62 62 + - description: The 'gpr' is the phandle to general purpose register node. 63 63 + - description: The 'req_gpr' is the gpr register offset containing 64 64 + CSI2_1_RX_ENABLE or CSI2_2_RX_ENABLE respectively. 65 65 + maximum: 0xff 66 66 67 67 interconnects: 68 68 maxItems: 1

+4

Documentation/devicetree/bindings/media/ti,cal.yaml

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··· 48 48 49 49 ti,camerrx-control: 50 50 $ref: "/schemas/types.yaml#/definitions/phandle-array" 51 51 + items: 52 52 + - items: 53 53 + - description: phandle to device control module 54 54 + - description: offset to the control_camerarx_core register 51 55 description: 52 56 phandle to the device control module and offset to the 53 57 control_camerarx_core register

+1 -1

Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml

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··· 53 53 maxItems: 1 54 54 55 55 mediatek,smi: 56 56 - $ref: /schemas/types.yaml#/definitions/phandle-array 56 56 + $ref: /schemas/types.yaml#/definitions/phandle 57 57 description: a phandle to the smi_common node. 58 58 59 59 mediatek,larb-id:

+2

Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml

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··· 45 45 $ref: '/schemas/types.yaml#/definitions/phandle-array' 46 46 minItems: 1 47 47 maxItems: 16 48 48 + items: 49 49 + maxItems: 1 48 50 description: phandles of the PPMU events used by the controller. 49 51 50 52 device-handle:

+4 -8

Documentation/devicetree/bindings/mfd/google,cros-ec.yaml

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··· 38 38 description: 39 39 This property specifies the delay in usecs between the 40 40 assertion of the CS and the first clock pulse. 41 41 - allOf: 42 42 - - $ref: /schemas/types.yaml#/definitions/uint32 43 43 - - default: 0 44 44 - - minimum: 0 41 41 + $ref: /schemas/types.yaml#/definitions/uint32 42 42 + default: 0 45 43 46 44 google,cros-ec-spi-msg-delay: 47 45 description: 48 46 This property specifies the delay in usecs between messages. 49 49 - allOf: 50 50 - - $ref: /schemas/types.yaml#/definitions/uint32 51 51 - - default: 0 52 52 - - minimum: 0 47 47 + $ref: /schemas/types.yaml#/definitions/uint32 48 48 + default: 0 53 49 54 50 google,has-vbc-nvram: 55 51 description:

+1 -2

Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml

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··· 96 96 97 97 rockchip,boot-ecc-strength: 98 98 enum: [16, 24, 40, 60, 70] 99 99 - allOf: 100 100 - - $ref: /schemas/types.yaml#/definitions/uint32 99 99 + $ref: /schemas/types.yaml#/definitions/uint32 101 100 description: | 102 101 If specified it indicates that a different BCH/ECC setting is 103 102 supported by the boot ROM.

+4

Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml

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··· 29 29 allwinner,sram: 30 30 description: Phandle to the device SRAM 31 31 $ref: /schemas/types.yaml#/definitions/phandle-array 32 32 + items: 33 33 + - items: 34 34 + - description: phandle to SRAM 35 35 + - description: register value for device 32 36 33 37 required: 34 38 - compatible

+4 -4

Documentation/devicetree/bindings/net/can/bosch,c_can.yaml

reviewed

··· 56 56 offset). 57 57 $ref: /schemas/types.yaml#/definitions/phandle-array 58 58 items: 59 59 - items: 60 60 - - description: The phandle to the system control region. 61 61 - - description: The register offset. 62 62 - - description: The CAN instance number. 59 59 + - items: 60 60 + - description: The phandle to the system control region. 61 61 + - description: The register offset. 62 62 + - description: The CAN instance number. 63 63 64 64 resets: 65 65 maxItems: 1

+1

Documentation/devicetree/bindings/net/can/bosch,m_can.yaml

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··· 104 104 - description: Tx Buffers 0-32 elements / 0-576 words 105 105 minimum: 0 106 106 maximum: 32 107 107 + minItems: 1 107 108 108 109 power-domains: 109 110 description:

+6 -6

Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml

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··· 84 84 req_bit is the bit offset of CAN stop request. 85 85 $ref: /schemas/types.yaml#/definitions/phandle-array 86 86 items: 87 87 - items: 88 88 - - description: The 'gpr' is the phandle to general purpose register node. 89 89 - - description: The 'req_gpr' is the gpr register offset of CAN stop request. 90 90 - maximum: 0xff 91 91 - - description: The 'req_bit' is the bit offset of CAN stop request. 92 92 - maximum: 0x1f 87 87 + - items: 88 88 + - description: The 'gpr' is the phandle to general purpose register node. 89 89 + - description: The 'req_gpr' is the gpr register offset of CAN stop request. 90 90 + maximum: 0xff 91 91 + - description: The 'req_bit' is the bit offset of CAN stop request. 92 92 + maximum: 0x1f 93 93 94 94 fsl,clk-source: 95 95 description: |

+1

Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml

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··· 33 33 - items: 34 34 - enum: 35 35 - renesas,r9a07g044-canfd # RZ/G2{L,LC} 36 36 + - renesas,r9a07g054-canfd # RZ/V2L 36 37 - const: renesas,rzg2l-canfd # RZ/G2L family 37 38 38 39 - const: renesas,r8a779a0-canfd # R-Car V3U

-92

Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt

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··· 1 1 - Cortina Systems Gemini Ethernet Controller 2 2 - ========================================== 3 3 - 4 4 - This ethernet controller is found in the Gemini SoC family: 5 5 - StorLink SL3512 and SL3516, also known as Cortina Systems 6 6 - CS3512 and CS3516. 7 7 - 8 8 - Required properties: 9 9 - - compatible: must be "cortina,gemini-ethernet" 10 10 - - reg: must contain the global registers and the V-bit and A-bit 11 11 - memory areas, in total three register sets. 12 12 - - syscon: a phandle to the system controller 13 13 - - #address-cells: must be specified, must be <1> 14 14 - - #size-cells: must be specified, must be <1> 15 15 - - ranges: should be state like this giving a 1:1 address translation 16 16 - for the subnodes 17 17 - 18 18 - The subnodes represents the two ethernet ports in this device. 19 19 - They are not independent of each other since they share resources 20 20 - in the parent node, and are thus children. 21 21 - 22 22 - Required subnodes: 23 23 - - port0: contains the resources for ethernet port 0 24 24 - - port1: contains the resources for ethernet port 1 25 25 - 26 26 - Required subnode properties: 27 27 - - compatible: must be "cortina,gemini-ethernet-port" 28 28 - - reg: must contain two register areas: the DMA/TOE memory and 29 29 - the GMAC memory area of the port 30 30 - - interrupts: should contain the interrupt line of the port. 31 31 - this is nominally a level interrupt active high. 32 32 - - resets: this must provide an SoC-integrated reset line for 33 33 - the port. 34 34 - - clocks: this should contain a handle to the PCLK clock for 35 35 - clocking the silicon in this port 36 36 - - clock-names: must be "PCLK" 37 37 - 38 38 - Optional subnode properties: 39 39 - - phy-mode: see ethernet.txt 40 40 - - phy-handle: see ethernet.txt 41 41 - 42 42 - Example: 43 43 - 44 44 - mdio-bus { 45 45 - (...) 46 46 - phy0: ethernet-phy@1 { 47 47 - reg = <1>; 48 48 - device_type = "ethernet-phy"; 49 49 - }; 50 50 - phy1: ethernet-phy@3 { 51 51 - reg = <3>; 52 52 - device_type = "ethernet-phy"; 53 53 - }; 54 54 - }; 55 55 - 56 56 - 57 57 - ethernet@60000000 { 58 58 - compatible = "cortina,gemini-ethernet"; 59 59 - reg = <0x60000000 0x4000>, /* Global registers, queue */ 60 60 - <0x60004000 0x2000>, /* V-bit */ 61 61 - <0x60006000 0x2000>; /* A-bit */ 62 62 - syscon = <&syscon>; 63 63 - #address-cells = <1>; 64 64 - #size-cells = <1>; 65 65 - ranges; 66 66 - 67 67 - gmac0: ethernet-port@0 { 68 68 - compatible = "cortina,gemini-ethernet-port"; 69 69 - reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ 70 70 - <0x6000a000 0x2000>; /* Port 0 GMAC */ 71 71 - interrupt-parent = <&intcon>; 72 72 - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 73 73 - resets = <&syscon GEMINI_RESET_GMAC0>; 74 74 - clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; 75 75 - clock-names = "PCLK"; 76 76 - phy-mode = "rgmii"; 77 77 - phy-handle = <&phy0>; 78 78 - }; 79 79 - 80 80 - gmac1: ethernet-port@1 { 81 81 - compatible = "cortina,gemini-ethernet-port"; 82 82 - reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ 83 83 - <0x6000e000 0x2000>; /* Port 1 GMAC */ 84 84 - interrupt-parent = <&intcon>; 85 85 - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 86 86 - resets = <&syscon GEMINI_RESET_GMAC1>; 87 87 - clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; 88 88 - clock-names = "PCLK"; 89 89 - phy-mode = "rgmii"; 90 90 - phy-handle = <&phy1>; 91 91 - }; 92 92 - };

+137

Documentation/devicetree/bindings/net/cortina,gemini-ethernet.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Cortina Systems Gemini Ethernet Controller 8 8 + 9 9 + maintainers: 10 10 + - Linus Walleij <linus.walleij@linaro.org> 11 11 + 12 12 + description: | 13 13 + This ethernet controller is found in the Gemini SoC family: 14 14 + StorLink SL3512 and SL3516, also known as Cortina Systems 15 15 + CS3512 and CS3516. 16 16 + 17 17 + properties: 18 18 + compatible: 19 19 + const: cortina,gemini-ethernet 20 20 + 21 21 + reg: 22 22 + minItems: 3 23 23 + description: must contain the global registers and the V-bit and A-bit 24 24 + memory areas, in total three register sets. 25 25 + 26 26 + "#address-cells": 27 27 + const: 1 28 28 + 29 29 + "#size-cells": 30 30 + const: 1 31 31 + 32 32 + ranges: true 33 33 + 34 34 + #The subnodes represents the two ethernet ports in this device. 35 35 + #They are not independent of each other since they share resources 36 36 + #in the parent node, and are thus children. 37 37 + patternProperties: 38 38 + "^ethernet-port@[0-9]+$": 39 39 + type: object 40 40 + description: contains the resources for ethernet port 41 41 + allOf: 42 42 + - $ref: ethernet-controller.yaml# 43 43 + properties: 44 44 + compatible: 45 45 + const: cortina,gemini-ethernet-port 46 46 + 47 47 + reg: 48 48 + items: 49 49 + - description: DMA/TOE memory 50 50 + - description: GMAC memory area of the port 51 51 + 52 52 + interrupts: 53 53 + maxItems: 1 54 54 + description: should contain the interrupt line of the port. 55 55 + this is nominally a level interrupt active high. 56 56 + 57 57 + resets: 58 58 + maxItems: 1 59 59 + description: this must provide an SoC-integrated reset line for the port. 60 60 + 61 61 + clocks: 62 62 + maxItems: 1 63 63 + description: this should contain a handle to the PCLK clock for 64 64 + clocking the silicon in this port 65 65 + 66 66 + clock-names: 67 67 + const: PCLK 68 68 + 69 69 + required: 70 70 + - reg 71 71 + - compatible 72 72 + - interrupts 73 73 + - resets 74 74 + - clocks 75 75 + - clock-names 76 76 + 77 77 + required: 78 78 + - compatible 79 79 + - reg 80 80 + - ranges 81 81 + 82 82 + additionalProperties: false 83 83 + 84 84 + examples: 85 85 + - | 86 86 + #include <dt-bindings/interrupt-controller/irq.h> 87 87 + #include <dt-bindings/clock/cortina,gemini-clock.h> 88 88 + #include <dt-bindings/reset/cortina,gemini-reset.h> 89 89 + mdio0: mdio { 90 90 + #address-cells = <1>; 91 91 + #size-cells = <0>; 92 92 + phy0: ethernet-phy@1 { 93 93 + reg = <1>; 94 94 + device_type = "ethernet-phy"; 95 95 + }; 96 96 + phy1: ethernet-phy@3 { 97 97 + reg = <3>; 98 98 + device_type = "ethernet-phy"; 99 99 + }; 100 100 + }; 101 101 + 102 102 + 103 103 + ethernet@60000000 { 104 104 + compatible = "cortina,gemini-ethernet"; 105 105 + reg = <0x60000000 0x4000>, /* Global registers, queue */ 106 106 + <0x60004000 0x2000>, /* V-bit */ 107 107 + <0x60006000 0x2000>; /* A-bit */ 108 108 + #address-cells = <1>; 109 109 + #size-cells = <1>; 110 110 + ranges; 111 111 + 112 112 + gmac0: ethernet-port@0 { 113 113 + compatible = "cortina,gemini-ethernet-port"; 114 114 + reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ 115 115 + <0x6000a000 0x2000>; /* Port 0 GMAC */ 116 116 + interrupt-parent = <&intcon>; 117 117 + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 118 118 + resets = <&syscon GEMINI_RESET_GMAC0>; 119 119 + clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; 120 120 + clock-names = "PCLK"; 121 121 + phy-mode = "rgmii"; 122 122 + phy-handle = <&phy0>; 123 123 + }; 124 124 + 125 125 + gmac1: ethernet-port@1 { 126 126 + compatible = "cortina,gemini-ethernet-port"; 127 127 + reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ 128 128 + <0x6000e000 0x2000>; /* Port 1 GMAC */ 129 129 + interrupt-parent = <&intcon>; 130 130 + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 131 131 + resets = <&syscon GEMINI_RESET_GMAC1>; 132 132 + clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; 133 133 + clock-names = "PCLK"; 134 134 + phy-mode = "rgmii"; 135 135 + phy-handle = <&phy1>; 136 136 + }; 137 137 + };

+2

Documentation/devicetree/bindings/net/dsa/dsa-port.yaml

reviewed

··· 34 34 full routing information must be given, not just the one hop 35 35 routes to neighbouring switches 36 36 $ref: /schemas/types.yaml#/definitions/phandle-array 37 37 + items: 38 38 + maxItems: 1 37 39 38 40 ethernet: 39 41 description:

+4

Documentation/devicetree/bindings/net/ethernet-controller.yaml

reviewed

··· 13 13 $nodename: 14 14 pattern: "^ethernet(@.*)?$" 15 15 16 16 + label: 17 17 + $ref: /schemas/types.yaml#/definitions/string 18 18 + description: Human readable label on a port of a box. 19 19 + 16 20 local-mac-address: 17 21 description: 18 22 Specifies the MAC address that was assigned to the network device.

+5 -3

Documentation/devicetree/bindings/net/fsl,fec.yaml

reviewed

··· 158 158 159 159 fsl,stop-mode: 160 160 $ref: /schemas/types.yaml#/definitions/phandle-array 161 161 + items: 162 162 + - items: 163 163 + - description: phandle to general purpose register node 164 164 + - description: the gpr register offset for ENET stop request 165 165 + - description: the gpr bit offset for ENET stop request 161 166 description: 162 167 Register bits of stop mode control, the format is <&gpr req_gpr req_bit>. 163 163 - gpr is the phandle to general purpose register node. 164 164 - req_gpr is the gpr register offset for ENET stop request. 165 165 - req_bit is the gpr bit offset for ENET stop request. 166 168 167 169 mdio: 168 170 $ref: mdio.yaml#

+12 -3

Documentation/devicetree/bindings/net/intel,ixp4xx-ethernet.yaml

reviewed

··· 29 29 30 30 queue-rx: 31 31 $ref: '/schemas/types.yaml#/definitions/phandle-array' 32 32 - maxItems: 1 32 32 + items: 33 33 + - items: 34 34 + - description: phandle to the RX queue node 35 35 + - description: RX queue instance to use 33 36 description: phandle to the RX queue on the NPE 34 37 35 38 queue-txready: 36 39 $ref: '/schemas/types.yaml#/definitions/phandle-array' 37 37 - maxItems: 1 40 40 + items: 41 41 + - items: 42 42 + - description: phandle to the TX READY queue node 43 43 + - description: TX READY queue instance to use 38 44 description: phandle to the TX READY queue on the NPE 39 45 40 46 phy-mode: true ··· 49 43 50 44 intel,npe-handle: 51 45 $ref: '/schemas/types.yaml#/definitions/phandle-array' 52 52 - maxItems: 1 46 46 + items: 47 47 + - items: 48 48 + - description: phandle to the NPE this ethernet instance is using 49 49 + - description: the NPE instance to use 53 50 description: phandle to the NPE this ethernet instance is using 54 51 and the instance to use in the second cell 55 52

+28 -5

Documentation/devicetree/bindings/net/intel,ixp4xx-hss.yaml

reviewed

··· 25 25 26 26 intel,npe-handle: 27 27 $ref: '/schemas/types.yaml#/definitions/phandle-array' 28 28 - maxItems: 1 28 28 + items: 29 29 + items: 30 30 + - description: phandle to the NPE this HSS instance is using 31 31 + - description: the NPE instance number 29 32 description: phandle to the NPE this HSS instance is using 30 33 and the instance to use in the second cell 31 34 32 35 intel,queue-chl-rxtrig: 33 36 $ref: '/schemas/types.yaml#/definitions/phandle-array' 34 34 - maxItems: 1 37 37 + items: 38 38 + - items: 39 39 + - description: phandle to the RX trigger queue on the NPE 40 40 + - description: the queue instance number 35 41 description: phandle to the RX trigger queue on the NPE 36 42 37 43 intel,queue-chl-txready: 38 44 $ref: '/schemas/types.yaml#/definitions/phandle-array' 39 39 - maxItems: 1 45 45 + items: 46 46 + - items: 47 47 + - description: phandle to the TX ready queue on the NPE 48 48 + - description: the queue instance number 40 49 description: phandle to the TX ready queue on the NPE 41 50 42 51 intel,queue-pkt-rx: 43 52 $ref: '/schemas/types.yaml#/definitions/phandle-array' 44 44 - maxItems: 1 53 53 + items: 54 54 + - items: 55 55 + - description: phandle to the RX queue on the NPE 56 56 + - description: the queue instance number 45 57 description: phandle to the packet RX queue on the NPE 46 58 47 59 intel,queue-pkt-tx: 48 60 $ref: '/schemas/types.yaml#/definitions/phandle-array' 49 61 maxItems: 4 62 62 + items: 63 63 + items: 64 64 + - description: phandle to the TX queue on the NPE 65 65 + - description: the queue instance number 50 66 description: phandle to the packet TX0, TX1, TX2 and TX3 queues on the NPE 51 67 52 68 intel,queue-pkt-rxfree: 53 69 $ref: '/schemas/types.yaml#/definitions/phandle-array' 54 70 maxItems: 4 71 71 + items: 72 72 + items: 73 73 + - description: phandle to the RXFREE queue on the NPE 74 74 + - description: the queue instance number 55 75 description: phandle to the packet RXFREE0, RXFREE1, RXFREE2 and 56 76 RXFREE3 queues on the NPE 57 77 58 78 intel,queue-pkt-txdone: 59 79 $ref: '/schemas/types.yaml#/definitions/phandle-array' 60 60 - maxItems: 1 80 80 + items: 81 81 + - items: 82 82 + - description: phandle to the TXDONE queue on the NPE 83 83 + - description: the queue instance number 61 84 description: phandle to the packet TXDONE queue on the NPE 62 85 63 86 cts-gpios:

+191

Documentation/devicetree/bindings/net/mscc,vsc7514-switch.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/net/mscc,vsc7514-switch.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Microchip VSC7514 Ethernet switch controller 8 8 + 9 9 + maintainers: 10 10 + - Vladimir Oltean <vladimir.oltean@nxp.com> 11 11 + - Claudiu Manoil <claudiu.manoil@nxp.com> 12 12 + - Alexandre Belloni <alexandre.belloni@bootlin.com> 13 13 + 14 14 + description: | 15 15 + Bindings for the Microchip VSC7514 switch driver 16 16 + 17 17 + The VSC7514 switch driver handles up to 11 ports and can inject/extract 18 18 + packets using CPU. Additionally, PTP is supported as well as FDMA for faster 19 19 + packet extraction/injection. 20 20 + 21 21 + properties: 22 22 + $nodename: 23 23 + pattern: "^switch@[0-9a-f]+$" 24 24 + 25 25 + compatible: 26 26 + const: mscc,vsc7514-switch 27 27 + 28 28 + reg: 29 29 + items: 30 30 + - description: system target 31 31 + - description: rewriter target 32 32 + - description: qs target 33 33 + - description: PTP target 34 34 + - description: Port0 target 35 35 + - description: Port1 target 36 36 + - description: Port2 target 37 37 + - description: Port3 target 38 38 + - description: Port4 target 39 39 + - description: Port5 target 40 40 + - description: Port6 target 41 41 + - description: Port7 target 42 42 + - description: Port8 target 43 43 + - description: Port9 target 44 44 + - description: Port10 target 45 45 + - description: QSystem target 46 46 + - description: Analyzer target 47 47 + - description: S0 target 48 48 + - description: S1 target 49 49 + - description: S2 target 50 50 + - description: fdma target 51 51 + 52 52 + reg-names: 53 53 + items: 54 54 + - const: sys 55 55 + - const: rew 56 56 + - const: qs 57 57 + - const: ptp 58 58 + - const: port0 59 59 + - const: port1 60 60 + - const: port2 61 61 + - const: port3 62 62 + - const: port4 63 63 + - const: port5 64 64 + - const: port6 65 65 + - const: port7 66 66 + - const: port8 67 67 + - const: port9 68 68 + - const: port10 69 69 + - const: qsys 70 70 + - const: ana 71 71 + - const: s0 72 72 + - const: s1 73 73 + - const: s2 74 74 + - const: fdma 75 75 + 76 76 + interrupts: 77 77 + minItems: 1 78 78 + items: 79 79 + - description: PTP ready 80 80 + - description: register based extraction 81 81 + - description: frame dma based extraction 82 82 + 83 83 + interrupt-names: 84 84 + minItems: 1 85 85 + items: 86 86 + - const: ptp_rdy 87 87 + - const: xtr 88 88 + - const: fdma 89 89 + 90 90 + ethernet-ports: 91 91 + type: object 92 92 + 93 93 + properties: 94 94 + '#address-cells': 95 95 + const: 1 96 96 + '#size-cells': 97 97 + const: 0 98 98 + 99 99 + additionalProperties: false 100 100 + 101 101 + patternProperties: 102 102 + "^port@[0-9a-f]+$": 103 103 + type: object 104 104 + description: Ethernet ports handled by the switch 105 105 + 106 106 + $ref: ethernet-controller.yaml# 107 107 + 108 108 + unevaluatedProperties: false 109 109 + 110 110 + properties: 111 111 + reg: 112 112 + description: Switch port number 113 113 + 114 114 + phy-handle: true 115 115 + 116 116 + phy-mode: true 117 117 + 118 118 + fixed-link: true 119 119 + 120 120 + mac-address: true 121 121 + 122 122 + required: 123 123 + - reg 124 124 + - phy-mode 125 125 + 126 126 + oneOf: 127 127 + - required: 128 128 + - phy-handle 129 129 + - required: 130 130 + - fixed-link 131 131 + 132 132 + required: 133 133 + - compatible 134 134 + - reg 135 135 + - reg-names 136 136 + - interrupts 137 137 + - interrupt-names 138 138 + - ethernet-ports 139 139 + 140 140 + additionalProperties: false 141 141 + 142 142 + examples: 143 143 + - | 144 144 + switch@1010000 { 145 145 + compatible = "mscc,vsc7514-switch"; 146 146 + reg = <0x1010000 0x10000>, 147 147 + <0x1030000 0x10000>, 148 148 + <0x1080000 0x100>, 149 149 + <0x10e0000 0x10000>, 150 150 + <0x11e0000 0x100>, 151 151 + <0x11f0000 0x100>, 152 152 + <0x1200000 0x100>, 153 153 + <0x1210000 0x100>, 154 154 + <0x1220000 0x100>, 155 155 + <0x1230000 0x100>, 156 156 + <0x1240000 0x100>, 157 157 + <0x1250000 0x100>, 158 158 + <0x1260000 0x100>, 159 159 + <0x1270000 0x100>, 160 160 + <0x1280000 0x100>, 161 161 + <0x1800000 0x80000>, 162 162 + <0x1880000 0x10000>, 163 163 + <0x1040000 0x10000>, 164 164 + <0x1050000 0x10000>, 165 165 + <0x1060000 0x10000>, 166 166 + <0x1a0 0x1c4>; 167 167 + reg-names = "sys", "rew", "qs", "ptp", "port0", "port1", 168 168 + "port2", "port3", "port4", "port5", "port6", 169 169 + "port7", "port8", "port9", "port10", "qsys", 170 170 + "ana", "s0", "s1", "s2", "fdma"; 171 171 + interrupts = <18 21 16>; 172 172 + interrupt-names = "ptp_rdy", "xtr", "fdma"; 173 173 + 174 174 + ethernet-ports { 175 175 + #address-cells = <1>; 176 176 + #size-cells = <0>; 177 177 + 178 178 + port0: port@0 { 179 179 + reg = <0>; 180 180 + phy-handle = <&phy0>; 181 181 + phy-mode = "internal"; 182 182 + }; 183 183 + port1: port@1 { 184 184 + reg = <1>; 185 185 + phy-handle = <&phy1>; 186 186 + phy-mode = "internal"; 187 187 + }; 188 188 + }; 189 189 + }; 190 190 + 191 191 + ...

-83

Documentation/devicetree/bindings/net/mscc-ocelot.txt

reviewed

··· 1 1 - Microsemi Ocelot network Switch 2 2 - =============================== 3 3 - 4 4 - The Microsemi Ocelot network switch can be found on Microsemi SoCs (VSC7513, 5 5 - VSC7514) 6 6 - 7 7 - Required properties: 8 8 - - compatible: Should be "mscc,vsc7514-switch" 9 9 - - reg: Must contain an (offset, length) pair of the register set for each 10 10 - entry in reg-names. 11 11 - - reg-names: Must include the following entries: 12 12 - - "sys" 13 13 - - "rew" 14 14 - - "qs" 15 15 - - "ptp" (optional due to backward compatibility) 16 16 - - "qsys" 17 17 - - "ana" 18 18 - - "portX" with X from 0 to the number of last port index available on that 19 19 - switch 20 20 - - interrupts: Should contain the switch interrupts for frame extraction, 21 21 - frame injection and PTP ready. 22 22 - - interrupt-names: should contain the interrupt names: "xtr", "inj". Can contain 23 23 - "ptp_rdy" which is optional due to backward compatibility. 24 24 - - ethernet-ports: A container for child nodes representing switch ports. 25 25 - 26 26 - The ethernet-ports container has the following properties 27 27 - 28 28 - Required properties: 29 29 - 30 30 - - #address-cells: Must be 1 31 31 - - #size-cells: Must be 0 32 32 - 33 33 - Each port node must have the following mandatory properties: 34 34 - - reg: Describes the port address in the switch 35 35 - 36 36 - Port nodes may also contain the following optional standardised 37 37 - properties, described in binding documents: 38 38 - 39 39 - - phy-handle: Phandle to a PHY on an MDIO bus. See 40 40 - Documentation/devicetree/bindings/net/ethernet.txt for details. 41 41 - 42 42 - Example: 43 43 - 44 44 - switch@1010000 { 45 45 - compatible = "mscc,vsc7514-switch"; 46 46 - reg = <0x1010000 0x10000>, 47 47 - <0x1030000 0x10000>, 48 48 - <0x1080000 0x100>, 49 49 - <0x10e0000 0x10000>, 50 50 - <0x11e0000 0x100>, 51 51 - <0x11f0000 0x100>, 52 52 - <0x1200000 0x100>, 53 53 - <0x1210000 0x100>, 54 54 - <0x1220000 0x100>, 55 55 - <0x1230000 0x100>, 56 56 - <0x1240000 0x100>, 57 57 - <0x1250000 0x100>, 58 58 - <0x1260000 0x100>, 59 59 - <0x1270000 0x100>, 60 60 - <0x1280000 0x100>, 61 61 - <0x1800000 0x80000>, 62 62 - <0x1880000 0x10000>; 63 63 - reg-names = "sys", "rew", "qs", "ptp", "port0", "port1", 64 64 - "port2", "port3", "port4", "port5", "port6", 65 65 - "port7", "port8", "port9", "port10", "qsys", 66 66 - "ana"; 67 67 - interrupts = <18 21 22>; 68 68 - interrupt-names = "ptp_rdy", "xtr", "inj"; 69 69 - 70 70 - ethernet-ports { 71 71 - #address-cells = <1>; 72 72 - #size-cells = <0>; 73 73 - 74 74 - port0: port@0 { 75 75 - reg = <0>; 76 76 - phy-handle = <&phy0>; 77 77 - }; 78 78 - port1: port@1 { 79 79 - reg = <1>; 80 80 - phy-handle = <&phy1>; 81 81 - }; 82 82 - }; 83 83 - };

+4

Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml

reviewed

··· 54 54 55 55 intf_mode: 56 56 $ref: /schemas/types.yaml#/definitions/phandle-array 57 57 + items: 58 58 + - items: 59 59 + - description: phandle to the GPR syscon 60 60 + - description: the offset of the GPR register 57 61 description: 58 62 Should be phandle/offset pair. The phandle to the syscon node which 59 63 encompases the GPR register, and the offset of the GPR register.

+4

Documentation/devicetree/bindings/net/socionext,uniphier-ave4.yaml

reviewed

··· 66 66 67 67 socionext,syscon-phy-mode: 68 68 $ref: /schemas/types.yaml#/definitions/phandle-array 69 69 + items: 70 70 + - items: 71 71 + - description: phandle to syscon that configures phy mode 72 72 + - description: ID of MAC instance 69 73 description: 70 74 A phandle to syscon with one argument that configures phy mode. 71 75 The argument is the ID of MAC instance.

+4

Documentation/devicetree/bindings/net/stm32-dwmac.yaml

reviewed

··· 74 74 75 75 st,syscon: 76 76 $ref: "/schemas/types.yaml#/definitions/phandle-array" 77 77 + items: 78 78 + - items: 79 79 + - description: phandle to the syscon node which encompases the glue register 80 80 + - description: offset of the control register 77 81 description: 78 82 Should be phandle/offset pair. The phandle to the syscon node which 79 83 encompases the glue register, and the offset of the control register

+1 -2

Documentation/devicetree/bindings/net/ti,cpsw-switch.yaml

reviewed

··· 88 88 type: object 89 89 description: CPSW external ports 90 90 91 91 - allOf: 92 92 - - $ref: ethernet-controller.yaml# 91 91 + $ref: ethernet-controller.yaml# 93 92 94 93 properties: 95 94 reg:

+5

Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml

reviewed

··· 136 136 137 137 ti,syscon-efuse: 138 138 $ref: /schemas/types.yaml#/definitions/phandle-array 139 139 + items: 140 140 + - items: 141 141 + - description: Phandle to the system control device node which 142 142 + provides access to efuse 143 143 + - description: offset to efuse registers??? 139 144 description: 140 145 Phandle to the system control device node which provides access 141 146 to efuse IO range with MAC addresses

-6

Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml

reviewed

··· 103 103 clocks: 104 104 maxItems: 8 105 105 106 106 - assigned-clocks: 107 107 - maxItems: 1 108 108 - 109 109 - assigned-clocks-parents: 110 110 - maxItems: 1 111 111 - 112 106 required: 113 107 - clocks 114 108

+4

Documentation/devicetree/bindings/net/wireless/mediatek,mt76.yaml

reviewed

··· 69 69 70 70 mediatek,mtd-eeprom: 71 71 $ref: /schemas/types.yaml#/definitions/phandle-array 72 72 + items: 73 73 + - items: 74 74 + - description: phandle to MTD partition 75 75 + - description: offset containing EEPROM data 72 76 description: 73 77 Phandle to a MTD partition + offset containing EEPROM data 74 78

-28

Documentation/devicetree/bindings/nvmem/qcom,spmi-sdam.yaml

reviewed

··· 38 38 - reg 39 39 - ranges 40 40 41 41 - patternProperties: 42 42 - "^.*@[0-9a-f]+$": 43 43 - type: object 44 44 - 45 45 - properties: 46 46 - reg: 47 47 - maxItems: 1 48 48 - description: 49 49 - Offset and size in bytes within the storage device. 50 50 - 51 51 - bits: 52 52 - $ref: /schemas/types.yaml#/definitions/uint32-array 53 53 - maxItems: 1 54 54 - items: 55 55 - items: 56 56 - - minimum: 0 57 57 - maximum: 7 58 58 - description: 59 59 - Offset in bit within the address range specified by reg. 60 60 - - minimum: 1 61 61 - description: 62 62 - Size in bit within the address range specified by reg. 63 63 - 64 64 - required: 65 65 - - reg 66 66 - 67 67 - additionalProperties: false 68 68 - 69 41 unevaluatedProperties: false 70 42 71 43 examples:

+62

Documentation/devicetree/bindings/nvmem/u-boot,env.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/nvmem/u-boot,env.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: U-Boot environment variables 8 8 + 9 9 + description: | 10 10 + U-Boot uses environment variables to store device parameters and 11 11 + configuration. They may be used for booting process, setup or keeping end user 12 12 + info. 13 13 + 14 14 + Data is stored using U-Boot specific formats (variant specific header and NUL 15 15 + separated key-value pairs). 16 16 + 17 17 + Environment data can be stored on various storage entities, e.g.: 18 18 + 1. Raw flash partition 19 19 + 2. UBI volume 20 20 + 21 21 + This binding allows marking storage device (as containing env data) and 22 22 + specifying used format. 23 23 + 24 24 + Right now only flash partition case is covered but it may be extended to e.g. 25 25 + UBI volumes in the future. 26 26 + 27 27 + maintainers: 28 28 + - Rafał Miłecki <rafal@milecki.pl> 29 29 + 30 30 + properties: 31 31 + compatible: 32 32 + oneOf: 33 33 + - description: A standalone env data block 34 34 + const: u-boot,env 35 35 + - description: Two redundant blocks with active one flagged 36 36 + const: u-boot,env-redundant-bool 37 37 + - description: Two redundant blocks with active having higher counter 38 38 + const: u-boot,env-redundant-count 39 39 + 40 40 + reg: 41 41 + maxItems: 1 42 42 + 43 43 + additionalProperties: false 44 44 + 45 45 + examples: 46 46 + - | 47 47 + partitions { 48 48 + compatible = "fixed-partitions"; 49 49 + #address-cells = <1>; 50 50 + #size-cells = <1>; 51 51 + 52 52 + partition@0 { 53 53 + reg = <0x0 0x40000>; 54 54 + label = "u-boot"; 55 55 + read-only; 56 56 + }; 57 57 + 58 58 + env: partition@40000 { 59 59 + compatible = "u-boot,env"; 60 60 + reg = <0x40000 0x10000>; 61 61 + }; 62 62 + };

+2

Documentation/devicetree/bindings/opp/opp-v2-base.yaml

reviewed

··· 177 177 for the functioning of the current device at the current OPP (where 178 178 this property is present). 179 179 $ref: /schemas/types.yaml#/definitions/phandle-array 180 180 + items: 181 181 + maxItems: 1 180 182 181 183 patternProperties: 182 184 '^opp-microvolt-':

+2

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml

reviewed

··· 25 25 - fsl,imx6qp-pcie 26 26 - fsl,imx7d-pcie 27 27 - fsl,imx8mq-pcie 28 28 + - fsl,imx8mm-pcie 29 29 + - fsl,imx8mp-pcie 28 30 29 31 reg: 30 32 items:

+2

Documentation/devicetree/bindings/perf/arm,dsu-pmu.yaml

reviewed

··· 35 35 $ref: /schemas/types.yaml#/definitions/phandle-array 36 36 minItems: 1 37 37 maxItems: 12 38 38 + items: 39 39 + maxItems: 1 38 40 description: List of phandles for the CPUs connected to this DSU instance. 39 41 40 42 required:

+8

Documentation/devicetree/bindings/phy/intel,combo-phy.yaml

reviewed

··· 47 47 48 48 intel,syscfg: 49 49 $ref: /schemas/types.yaml#/definitions/phandle-array 50 50 + items: 51 51 + - items: 52 52 + - description: phandle to Chip configuration registers 53 53 + - description: ComboPhy instance id 50 54 description: Chip configuration registers handle and ComboPhy instance id 51 55 52 56 intel,hsio: 53 57 $ref: /schemas/types.yaml#/definitions/phandle-array 58 58 + items: 59 59 + - items: 60 60 + - description: phandle to HSIO registers 61 61 + - description: ComboPhy instance id 54 62 description: HSIO registers handle and ComboPhy instance id on NOC 55 63 56 64 intel,aggregation:

+1 -2

Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml

reviewed

··· 76 76 77 77 connector: 78 78 type: object 79 79 - allOf: 80 80 - - $ref: ../connector/usb-connector.yaml 79 79 + $ref: /schemas/connector/usb-connector.yaml 81 80 properties: 82 81 vbus-supply: true 83 82

+44

Documentation/devicetree/bindings/phy/samsung,exynos-hdmi-phy.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/phy/samsung,exynos-hdmi-phy.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Samsung Exynos SoC HDMI PHY 8 8 + 9 9 + maintainers: 10 10 + - Inki Dae <inki.dae@samsung.com> 11 11 + - Joonyoung Shim <jy0922.shim@samsung.com> 12 12 + - Seung-Woo Kim <sw0312.kim@samsung.com> 13 13 + - Kyungmin Park <kyungmin.park@samsung.com> 14 14 + - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> 15 15 + 16 16 + properties: 17 17 + compatible: 18 18 + oneOf: 19 19 + - enum: 20 20 + - samsung,exynos4210-hdmiphy 21 21 + - samsung,exynos4212-hdmiphy 22 22 + - const: samsung,exynos5-hdmiphy 23 23 + deprecated: true 24 24 + 25 25 + reg: 26 26 + maxItems: 1 27 27 + 28 28 + required: 29 29 + - compatible 30 30 + - reg 31 31 + 32 32 + additionalProperties: false 33 33 + 34 34 + examples: 35 35 + - | 36 36 + i2c { 37 37 + #address-cells = <1>; 38 38 + #size-cells = <0>; 39 39 + 40 40 + hdmi-phy@38 { 41 41 + compatible = "samsung,exynos4210-hdmiphy"; 42 42 + reg = <0x38>; 43 43 + }; 44 44 + };

+4

Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml

reviewed

··· 45 45 46 46 syscon-phy-power: 47 47 $ref: /schemas/types.yaml#/definitions/phandle-array 48 48 + items: 49 49 + - items: 50 50 + - description: phandle to the system control module 51 51 + - description: register offset to power on/off the PHY 48 52 description: 49 53 phandle/offset pair. Phandle to the system control module and 50 54 register offset to power on/off the PHY.

+2

Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml

reviewed

··· 29 29 aspeed,external-nodes: 30 30 minItems: 2 31 31 maxItems: 2 32 32 + items: 33 33 + maxItems: 1 32 34 $ref: /schemas/types.yaml#/definitions/phandle-array 33 35 description: | 34 36 A cell of phandles to external controller nodes:

+4

Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml

reviewed

··· 39 39 40 40 canaan,k210-sysctl-power: 41 41 $ref: /schemas/types.yaml#/definitions/phandle-array 42 42 + items: 43 43 + - items: 44 44 + - description: phandle of the K210 system controller node 45 45 + - description: offset of its power domain control register 42 46 description: | 43 47 phandle of the K210 system controller node and offset of its 44 48 power domain control register.

+2

Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml

reviewed

··· 44 44 45 45 mediatek,pctl-regmap: 46 46 $ref: /schemas/types.yaml#/definitions/phandle-array 47 47 + items: 48 48 + maxItems: 1 47 49 minItems: 1 48 50 maxItems: 2 49 51 description: |

+6 -4

Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml

reviewed

··· 41 41 maxItems: 1 42 42 43 43 st,syscfg: 44 44 - description: Should be phandle/offset/mask 45 45 - - Phandle to the syscon node which includes IRQ mux selection. 46 46 - - The offset of the IRQ mux selection register. 47 47 - - The field mask of IRQ mux, needed if different of 0xf. 44 44 + description: Phandle+args to the syscon node which includes IRQ mux selection. 48 45 $ref: "/schemas/types.yaml#/definitions/phandle-array" 46 46 + items: 47 47 + - items: 48 48 + - description: syscon node which includes IRQ mux selection 49 49 + - description: The offset of the IRQ mux selection register 50 50 + - description: The field mask of IRQ mux, needed if different of 0xf 49 51 50 52 st,package: 51 53 description:

+4

Documentation/devicetree/bindings/power/power-domain.yaml

reviewed

··· 29 29 30 30 domain-idle-states: 31 31 $ref: /schemas/types.yaml#/definitions/phandle-array 32 32 + items: 33 33 + maxItems: 1 32 34 description: | 33 35 Phandles of idle states that defines the available states for the 34 36 power-domain provider. The idle state definitions are compatible with the ··· 44 42 45 43 operating-points-v2: 46 44 $ref: /schemas/types.yaml#/definitions/phandle-array 45 45 + items: 46 46 + maxItems: 1 47 47 description: 48 48 Phandles to the OPP tables of power domains provided by a power domain 49 49 provider. If the provider provides a single power domain only or all

+2

Documentation/devicetree/bindings/power/renesas,apmu.yaml

reviewed

··· 35 35 36 36 cpus: 37 37 $ref: /schemas/types.yaml#/definitions/phandle-array 38 38 + items: 39 39 + maxItems: 1 38 40 description: | 39 41 Array of phandles pointing to CPU cores, which should match the order of 40 42 CPU cores used by the WUPCR and PSTR registers in the Advanced Power

+2

Documentation/devicetree/bindings/power/rockchip,power-controller.yaml

reviewed

··· 129 129 130 130 pm_qos: 131 131 $ref: /schemas/types.yaml#/definitions/phandle-array 132 132 + items: 133 133 + maxItems: 1 132 134 description: | 133 135 A number of phandles to qos blocks which need to be saved and restored 134 136 while power domain switches state.

+3 -3

Documentation/devicetree/bindings/power/supply/cw2015_battery.yaml

reviewed

··· 14 14 phandle in monitored-battery. If specified the driver uses the 15 15 charge-full-design-microamp-hours property of the battery. 16 16 17 17 + allOf: 18 18 + - $ref: power-supply.yaml# 19 19 + 17 20 properties: 18 21 compatible: 19 22 const: cellwise,cw2015 ··· 40 37 minimum: 250 41 38 42 39 power-supplies: 43 43 - description: 44 44 - Specifies supplies used for charging the battery connected to this gauge 45 45 - $ref: /schemas/types.yaml#/definitions/phandle-array 46 40 minItems: 1 47 41 maxItems: 8 # Should be enough 48 42

+2

Documentation/devicetree/bindings/power/supply/power-supply.yaml

reviewed

··· 12 12 properties: 13 13 power-supplies: 14 14 $ref: /schemas/types.yaml#/definitions/phandle-array 15 15 + items: 16 16 + maxItems: 1 15 17 description: 16 18 This property is added to a supply in order to list the devices which 17 19 supply it power, referenced by their phandles.

+1 -3

Documentation/devicetree/bindings/power/supply/sbs,sbs-manager.yaml

reviewed

··· 46 46 patternProperties: 47 47 "^i2c@[1-4]$": 48 48 type: object 49 49 - 50 50 - allOf: 51 51 - - $ref: /schemas/i2c/i2c-controller.yaml# 49 49 + $ref: /schemas/i2c/i2c-controller.yaml# 52 50 53 51 examples: 54 52 - |

+2

Documentation/devicetree/bindings/regulator/regulator.yaml

reviewed

··· 213 213 is 2-way - all coupled regulators should be linked with each other. 214 214 A regulator should not be coupled with its supplier. 215 215 $ref: "/schemas/types.yaml#/definitions/phandle-array" 216 216 + items: 217 217 + maxItems: 1 216 218 217 219 regulator-coupled-max-spread: 218 220 description: Array of maximum spread between voltages of coupled regulators

+1 -1

Documentation/devicetree/bindings/regulator/st,stm32-booster.yaml

reviewed

··· 23 23 - st,stm32mp1-booster 24 24 25 25 st,syscfg: 26 26 - $ref: "/schemas/types.yaml#/definitions/phandle-array" 26 26 + $ref: "/schemas/types.yaml#/definitions/phandle" 27 27 description: phandle to system configuration controller. 28 28 29 29 vdda-supply:

+6

Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml

reviewed

··· 119 119 120 120 qcom,halt-regs: 121 121 $ref: /schemas/types.yaml#/definitions/phandle-array 122 122 + items: 123 123 + - items: 124 124 + - description: Phandle reference to a syscon representing TCSR 125 125 + - description: offsets within syscon for q6 halt registers 126 126 + - description: offsets within syscon for modem halt registers 127 127 + - description: offsets within syscon for nc halt registers 122 128 description: 123 129 Phandle reference to a syscon representing TCSR followed by the 124 130 three offsets within syscon for q6, modem and nc halt registers.

+25 -8

Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml

reviewed

··· 29 29 30 30 st,syscfg-holdboot: 31 31 description: remote processor reset hold boot 32 32 - - Phandle of syscon block. 33 33 - - The offset of the hold boot setting register. 34 34 - - The field mask of the hold boot. 35 32 $ref: "/schemas/types.yaml#/definitions/phandle-array" 36 36 - maxItems: 1 33 33 + items: 34 34 + - items: 35 35 + - description: Phandle of syscon block 36 36 + - description: The offset of the hold boot setting register 37 37 + - description: The field mask of the hold boot 37 38 38 39 st,syscfg-tz: 39 40 description: 40 41 Reference to the system configuration which holds the RCC trust zone mode 41 42 $ref: "/schemas/types.yaml#/definitions/phandle-array" 42 42 - maxItems: 1 43 43 + items: 44 44 + - items: 45 45 + - description: Phandle of syscon block 46 46 + - description: FIXME 47 47 + - description: FIXME 43 48 44 49 interrupts: 45 50 description: Should contain the WWDG1 watchdog reset interrupt ··· 98 93 $ref: "/schemas/types.yaml#/definitions/phandle-array" 99 94 description: | 100 95 Reference to the system configuration which holds the remote 101 101 - maxItems: 1 96 96 + items: 97 97 + - items: 98 98 + - description: Phandle of syscon block 99 99 + - description: FIXME 100 100 + - description: FIXME 102 101 103 102 st,syscfg-m4-state: 104 103 $ref: "/schemas/types.yaml#/definitions/phandle-array" 105 104 description: | 106 105 Reference to the tamp register which exposes the Cortex-M4 state. 107 107 - maxItems: 1 106 106 + items: 107 107 + - items: 108 108 + - description: Phandle of syscon block with the tamp register 109 109 + - description: FIXME 110 110 + - description: FIXME 108 111 109 112 st,syscfg-rsc-tbl: 110 113 $ref: "/schemas/types.yaml#/definitions/phandle-array" 111 114 description: | 112 115 Reference to the tamp register which references the Cortex-M4 113 116 resource table address. 114 114 - maxItems: 1 117 117 + items: 118 118 + - items: 119 119 + - description: Phandle of syscon block with the tamp register 120 120 + - description: FIXME 121 121 + - description: FIXME 115 122 116 123 st,auto-boot: 117 124 $ref: /schemas/types.yaml#/definitions/flag

+10

Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml

reviewed

··· 79 79 $ref: /schemas/types.yaml#/definitions/phandle-array 80 80 minItems: 1 81 81 maxItems: 4 82 82 + items: 83 83 + maxItems: 1 82 84 description: | 83 85 phandles to one or more reserved on-chip SRAM regions. The regions 84 86 should be defined as child nodes of the respective SRAM node, and ··· 141 139 soc { 142 140 #address-cells = <2>; 143 141 #size-cells = <2>; 142 142 + 143 143 + mailbox0_cluster3: mailbox-0 { 144 144 + #mbox-cells = <1>; 145 145 + }; 146 146 + 147 147 + mailbox0_cluster4: mailbox-1 { 148 148 + #mbox-cells = <1>; 149 149 + }; 144 150 145 151 bus@100000 { 146 152 compatible = "simple-bus";

+11 -2

Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml

reviewed

··· 95 95 addresses. Cache and memory access settings are provided through a 96 96 Memory Protection Unit (MPU), programmable only from the R5Fs. 97 97 98 98 - allOf: 99 99 - - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# 98 98 + $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# 100 99 101 100 properties: 102 101 compatible: ··· 188 189 $ref: /schemas/types.yaml#/definitions/phandle-array 189 190 minItems: 1 190 191 maxItems: 4 192 192 + items: 193 193 + maxItems: 1 191 194 description: | 192 195 phandles to one or more reserved on-chip SRAM regions. The regions 193 196 should be defined as child nodes of the respective SRAM node, and ··· 236 235 soc { 237 236 #address-cells = <2>; 238 237 #size-cells = <2>; 238 238 + 239 239 + mailbox0: mailbox-0 { 240 240 + #mbox-cells = <1>; 241 241 + }; 242 242 + 243 243 + mailbox1: mailbox-1 { 244 244 + #mbox-cells = <1>; 245 245 + }; 239 246 240 247 bus@100000 { 241 248 compatible = "simple-bus";

+12 -7

Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml

reviewed

··· 123 123 124 124 ti,bootreg: 125 125 $ref: /schemas/types.yaml#/definitions/phandle-array 126 126 - description: | 127 127 - Should be a triple of the phandle to the System Control 128 128 - Configuration region that contains the boot address 129 129 - register, the register offset of the boot address 130 130 - register within the System Control module, and the bit 131 131 - shift within the register. This property is required for 132 132 - all the DSP instances on OMAP4, OMAP5 and DRA7xx SoCs. 126 126 + items: 127 127 + - items: 128 128 + - description: phandle to the System Control Configuration region 129 129 + - description: register offset of the boot address register 130 130 + - description: the bit shift within the register 131 131 + description: 132 132 + This property is required for all the DSP instances on OMAP4, OMAP5 133 133 + and DRA7xx SoCs. 133 134 134 135 ti,autosuspend-delay-ms: 135 136 description: | ··· 141 140 142 141 ti,timers: 143 142 $ref: /schemas/types.yaml#/definitions/phandle-array 143 143 + items: 144 144 + maxItems: 1 144 145 description: | 145 146 One or more phandles to OMAP DMTimer nodes, that serve 146 147 as System/Tick timers for the OS running on the remote ··· 159 156 160 157 ti,watchdog-timers: 161 158 $ref: /schemas/types.yaml#/definitions/phandle-array 159 159 + items: 160 160 + maxItems: 1 162 161 description: | 163 162 One or more phandles to OMAP DMTimer nodes, used to 164 163 serve as Watchdog timers for the processor cores. This

+10

Documentation/devicetree/bindings/reserved-memory/shared-dma-pool.yaml

reviewed

··· 56 56 If this property is present, then Linux will use the region for 57 57 the default pool of the consistent DMA allocator. 58 58 59 59 + if: 60 60 + properties: 61 61 + compatible: 62 62 + contains: 63 63 + const: restricted-dma-pool 64 64 + then: 65 65 + properties: 66 66 + no-map: false 67 67 + reusable: false 68 68 + 59 69 unevaluatedProperties: false 60 70 61 71 examples:

+2 -1

Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml

reviewed

··· 4 4 $id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 7 - title: Renesas RZ/G2L USBPHY Control 7 7 + title: Renesas RZ/{G2L,V2L} USBPHY Control 8 8 9 9 maintainers: 10 10 - Biju Das <biju.das.jz@bp.renesas.com> ··· 18 18 items: 19 19 - enum: 20 20 - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC} 21 21 + - renesas,r9a07g054-usbphy-ctrl # RZ/V2L 21 22 - const: renesas,rzg2l-usbphy-ctrl 22 23 23 24 reg:

+1 -1

Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml

reviewed

··· 9 9 maintainers: 10 10 - Nicolas Ferre <nicolas.ferre@microchip.com> 11 11 - Alexandre Belloni <alexandre.belloni@bootlin.com> 12 12 - - Ludovic Desroches <ludovic.desroches@microchip.com> 12 12 + - Claudiu Beznea <claudiu.beznea@microchip.com> 13 13 14 14 properties: 15 15 compatible:

-17

Documentation/devicetree/bindings/serial/rda,8810pl-uart.txt

reviewed

··· 1 1 - RDA Micro UART 2 2 - 3 3 - Required properties: 4 4 - - compatible : "rda,8810pl-uart" for RDA8810PL SoCs. 5 5 - - reg : Offset and length of the register set for the device. 6 6 - - interrupts : Should contain UART interrupt. 7 7 - - clocks : Phandle to the input clock. 8 8 - 9 9 - 10 10 - Example: 11 11 - 12 12 - uart2: serial@20a90000 { 13 13 - compatible = "rda,8810pl-uart"; 14 14 - reg = <0x20a90000 0x1000>; 15 15 - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 16 16 - clocks = <&uart_clk>; 17 17 - };

+46

Documentation/devicetree/bindings/serial/rda,8810pl-uart.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/serial/rda,8810pl-uart.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: RDA Micro UART Interface 8 8 + 9 9 + maintainers: 10 10 + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 11 11 + 12 12 + allOf: 13 13 + - $ref: serial.yaml# 14 14 + 15 15 + properties: 16 16 + compatible: 17 17 + const: rda,8810pl-uart 18 18 + 19 19 + reg: 20 20 + maxItems: 1 21 21 + 22 22 + interrupts: 23 23 + maxItems: 1 24 24 + 25 25 + clocks: 26 26 + maxItems: 1 27 27 + 28 28 + required: 29 29 + - compatible 30 30 + - reg 31 31 + - interrupts 32 32 + - clocks 33 33 + 34 34 + unevaluatedProperties: false 35 35 + 36 36 + examples: 37 37 + - | 38 38 + #include <dt-bindings/interrupt-controller/irq.h> 39 39 + 40 40 + uart3: serial@20a90000 { 41 41 + compatible = "rda,8810pl-uart"; 42 42 + reg = <0x20a90000 0x1000>; 43 43 + interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 44 44 + clocks = <&uart_clk>; 45 45 + }; 46 46 + ...

+4

Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml

reviewed

··· 41 41 42 42 samsung,sysreg: 43 43 $ref: /schemas/types.yaml#/definitions/phandle-array 44 44 + items: 45 45 + - items: 46 46 + - description: phandle to System Register syscon node 47 47 + - description: offset of SW_CONF register for this USI controller 44 48 description: 45 49 Should be phandle/offset pair. The phandle to System Register syscon node 46 50 (for the same domain where this USI controller resides) and the offset

+3 -12

Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml

reviewed

··· 281 281 PRUSS INTC Node. Each PRUSS has a single interrupt controller instance 282 282 that is common to all the PRU cores. This should be represented as an 283 283 interrupt-controller node. 284 284 - 285 285 - allOf: 286 286 - - $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml# 287 287 - 284 284 + $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml# 288 285 type: object 289 286 290 287 mdio@[a-f0-9]+$: ··· 289 292 MDIO Node. Each PRUSS has an MDIO module that can be used to control 290 293 external PHYs. The MDIO module used within the PRU-ICSS is an instance of 291 294 the MDIO Controller used in TI Davinci SoCs. 292 292 - 293 293 - allOf: 294 294 - - $ref: /schemas/net/ti,davinci-mdio.yaml# 295 295 - 295 295 + $ref: /schemas/net/ti,davinci-mdio.yaml# 296 296 type: object 297 297 298 298 "^(pru|rtu|txpru)@[0-9a-f]+$": ··· 299 305 inactive by using the standard DT string property, "status". The ICSSG IP 300 306 present on K3 SoCs have additional auxiliary PRU cores with slightly 301 307 different IP integration. 302 302 - 303 303 - allOf: 304 304 - - $ref: /schemas/remoteproc/ti,pru-rproc.yaml# 305 305 - 308 308 + $ref: /schemas/remoteproc/ti,pru-rproc.yaml# 306 309 type: object 307 310 308 311 required:

+2 -2

Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml

reviewed

··· 57 57 rate 58 58 59 59 sound-dai: 60 60 - $ref: /schemas/types.yaml#/definitions/phandle-array 60 60 + maxItems: 1 61 61 description: phandle of the CPU DAI 62 62 63 63 patternProperties: ··· 71 71 72 72 properties: 73 73 sound-dai: 74 74 - $ref: /schemas/types.yaml#/definitions/phandle-array 74 74 + maxItems: 1 75 75 description: phandle of the codec DAI 76 76 77 77 required:

+4 -2

Documentation/devicetree/bindings/sound/google,sc7180-trogdor.yaml

reviewed

··· 62 62 description: Holds subnode which indicates cpu dai. 63 63 type: object 64 64 properties: 65 65 - sound-dai: true 65 65 + sound-dai: 66 66 + maxItems: 1 66 67 67 68 codec: 68 69 description: Holds subnode which indicates codec dai. 69 70 type: object 70 71 properties: 71 71 - sound-dai: true 72 72 + sound-dai: 73 73 + maxItems: 1 72 74 73 75 required: 74 76 - link-name

+5 -2

Documentation/devicetree/bindings/sound/imx-audio-card.yaml

reviewed

··· 59 59 description: Holds subnode which indicates cpu dai. 60 60 type: object 61 61 properties: 62 62 - sound-dai: true 62 62 + sound-dai: 63 63 + maxItems: 1 63 64 64 65 codec: 65 66 description: Holds subnode which indicates codec dai. 66 67 type: object 67 68 properties: 68 68 - sound-dai: true 69 69 + sound-dai: 70 70 + minItems: 1 71 71 + maxItems: 2 69 72 70 73 fsl,mclk-equal-bclk: 71 74 description: Indicates mclk can be equal to bclk, especially for sai interface

+7 -3

Documentation/devicetree/bindings/sound/qcom,sm8250.yaml

reviewed

··· 69 69 description: Holds subnode which indicates cpu dai. 70 70 type: object 71 71 properties: 72 72 - sound-dai: true 72 72 + sound-dai: 73 73 + maxItems: 1 73 74 74 75 platform: 75 76 description: Holds subnode which indicates platform dai. 76 77 type: object 77 78 properties: 78 78 - sound-dai: true 79 79 + sound-dai: 80 80 + maxItems: 1 79 81 80 82 codec: 81 83 description: Holds subnode which indicates codec dai. 82 84 type: object 83 85 properties: 84 84 - sound-dai: true 86 86 + sound-dai: 87 87 + minItems: 1 88 88 + maxItems: 4 85 89 86 90 required: 87 91 - link-name

+1 -2

Documentation/devicetree/bindings/sound/samsung,aries-wm8994.yaml

reviewed

··· 27 27 sound-dai: 28 28 minItems: 2 29 29 maxItems: 2 30 30 - $ref: /schemas/types.yaml#/definitions/phandle-array 31 30 description: | 32 31 phandles to the I2S controller and bluetooth codec, 33 32 in that order ··· 37 38 type: object 38 39 properties: 39 40 sound-dai: 40 40 - $ref: /schemas/types.yaml#/definitions/phandle-array 41 41 + maxItems: 1 41 42 description: phandle to the WM8994 CODEC 42 43 required: 43 44 - sound-dai

-2

Documentation/devicetree/bindings/sound/samsung,midas-audio.yaml

reviewed

··· 21 21 type: object 22 22 properties: 23 23 sound-dai: 24 24 - $ref: /schemas/types.yaml#/definitions/phandle-array 25 24 maxItems: 1 26 25 description: phandle to the I2S controller 27 26 required: ··· 30 31 type: object 31 32 properties: 32 33 sound-dai: 33 33 - $ref: /schemas/types.yaml#/definitions/phandle-array 34 34 maxItems: 1 35 35 description: phandle to the WM1811 CODEC 36 36 required:

+3 -6

Documentation/devicetree/bindings/sound/samsung,odroid.yaml

reviewed

··· 37 37 type: object 38 38 properties: 39 39 sound-dai: 40 40 - $ref: /schemas/types.yaml#/definitions/phandle-array 41 40 description: phandles to the I2S controllers 42 41 43 42 codec: 44 43 type: object 45 44 properties: 46 45 sound-dai: 47 47 - $ref: /schemas/types.yaml#/definitions/phandle-array 48 48 - description: | 49 49 - List of phandles to the CODEC nodes, 50 50 - first entry must be corresponding to the MAX98090 CODEC and 51 51 - the second entry must be the phandle of the HDMI IP block node. 46 46 + items: 47 47 + - description: phandle of the MAX98090 CODEC 48 48 + - description: phandle of the HDMI IP block node 52 49 53 50 samsung,audio-routing: 54 51 $ref: /schemas/types.yaml#/definitions/non-unique-string-array

+20

Documentation/devicetree/bindings/sound/sound-dai.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/sound/sound-dai.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Digital Audio Interface consumer Device Tree Bindings 8 8 + 9 9 + maintainers: 10 10 + - Rob Herring <robh@kernel.org> 11 11 + 12 12 + select: true 13 13 + 14 14 + properties: 15 15 + sound-dai: 16 16 + $ref: /schemas/types.yaml#/definitions/phandle-array 17 17 + description: A phandle plus args to digital audio interface provider(s) 18 18 + 19 19 + additionalProperties: true 20 20 + ...

+6 -5

Documentation/devicetree/bindings/sound/st,stm32-sai.yaml

reviewed

··· 102 102 By default SAI sub-block is in asynchronous mode. 103 103 Must contain the phandle and index of the SAI sub-block providing 104 104 the synchronization. 105 105 - allOf: 106 106 - - $ref: /schemas/types.yaml#/definitions/phandle-array 107 107 - - maxItems: 1 105 105 + $ref: /schemas/types.yaml#/definitions/phandle-array 106 106 + items: 107 107 + - items: 108 108 + - description: phandle of the SAI sub-block 109 109 + - description: index of the SAI sub-block 108 110 109 111 st,iec60958: 110 112 description: ··· 115 113 By default, custom protocol is assumed, meaning that protocol is 116 114 configured according to protocol defined in related DAI link node, 117 115 such as i2s, left justified, right justified, dsp and pdm protocols. 118 118 - allOf: 119 119 - - $ref: /schemas/types.yaml#/definitions/flag 116 116 + $ref: /schemas/types.yaml#/definitions/flag 120 117 121 118 "#clock-cells": 122 119 description: Configure the SAI device as master clock provider.

+6 -7

Documentation/devicetree/bindings/sound/tlv320adcx140.yaml

reviewed

··· 176 176 4 - Drive weak low and active high 177 177 5 - Drive Hi-Z and active high 178 178 179 179 - allOf: 180 180 - - $ref: /schemas/types.yaml#/definitions/uint32-array 181 181 - - minItems: 2 182 182 - maxItems: 2 183 183 - items: 184 184 - maximum: 15 185 185 - default: [2, 2] 179 179 + $ref: /schemas/types.yaml#/definitions/uint32-array 180 180 + minItems: 2 181 181 + maxItems: 2 182 182 + items: 183 183 + maximum: 15 184 184 + default: [2, 2] 186 185 187 186 required: 188 187 - compatible

+1 -3

Documentation/devicetree/bindings/spi/spi-controller.yaml

reviewed

··· 93 93 patternProperties: 94 94 "^.*@[0-9a-f]+$": 95 95 type: object 96 96 - 97 97 - allOf: 98 98 - - $ref: spi-peripheral-props.yaml 96 96 + $ref: spi-peripheral-props.yaml 99 97 100 98 required: 101 99 - compatible

+3 -3

Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml

reviewed

··· 66 66 compatible = "qcom,kryo385"; 67 67 reg = <0x0 0x0>; 68 68 enable-method = "psci"; 69 69 - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 70 70 - &LITTLE_CPU_SLEEP_1 71 71 - &CLUSTER_SLEEP_0>; 69 69 + cpu-idle-states = <&LITTLE_CPU_SLEEP_0>, 70 70 + <&LITTLE_CPU_SLEEP_1>, 71 71 + <&CLUSTER_SLEEP_0>; 72 72 capacity-dmips-mhz = <607>; 73 73 dynamic-power-coefficient = <100>; 74 74 qcom,freq-domain = <&cpufreq_hw 0>;

+4 -4

Documentation/devicetree/bindings/thermal/thermal-idle.yaml

reviewed

··· 37 37 38 38 exit-latency-us: 39 39 description: | 40 40 - The exit latency constraint in microsecond for the injected idle state 41 41 - for the device. It is the latency constraint to apply when selecting an 40 40 + The exit latency constraint in microsecond for the injected idle state 41 41 + for the device. It is the latency constraint to apply when selecting an 42 42 idle state from among all the present ones. 43 43 44 44 required: ··· 65 65 capacity-dmips-mhz = <1024>; 66 66 dynamic-power-coefficient = <436>; 67 67 #cooling-cells = <2>; /* min followed by max */ 68 68 - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 68 68 + cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>; 69 69 thermal-idle { 70 70 #cooling-cells = <2>; 71 71 duration-us = <10000>; ··· 81 81 capacity-dmips-mhz = <1024>; 82 82 dynamic-power-coefficient = <436>; 83 83 #cooling-cells = <2>; /* min followed by max */ 84 84 - cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 84 84 + cpu-idle-states = <&CPU_SLEEP>, <&CLUSTER_SLEEP>; 85 85 thermal-idle { 86 86 #cooling-cells = <2>; 87 87 duration-us = <10000>;

-26

Documentation/devicetree/bindings/timer/arm,armv7m-systick.txt

reviewed

··· 1 1 - * ARMv7M System Timer 2 2 - 3 3 - ARMv7-M includes a system timer, known as SysTick. Current driver only 4 4 - implements the clocksource feature. 5 5 - 6 6 - Required properties: 7 7 - - compatible : Should be "arm,armv7m-systick" 8 8 - - reg : The address range of the timer 9 9 - 10 10 - Required clocking property, have to be one of: 11 11 - - clocks : The input clock of the timer 12 12 - - clock-frequency : The rate in HZ in input of the ARM SysTick 13 13 - 14 14 - Examples: 15 15 - 16 16 - systick: timer@e000e010 { 17 17 - compatible = "arm,armv7m-systick"; 18 18 - reg = <0xe000e010 0x10>; 19 19 - clocks = <&clk_systick>; 20 20 - }; 21 21 - 22 22 - systick: timer@e000e010 { 23 23 - compatible = "arm,armv7m-systick"; 24 24 - reg = <0xe000e010 0x10>; 25 25 - clock-frequency = <90000000>; 26 26 - };

+54

Documentation/devicetree/bindings/timer/arm,armv7m-systick.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/timer/arm,armv7m-systick.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: ARMv7M System Timer 8 8 + 9 9 + maintainers: 10 10 + - Alexandre Torgue <alexandre.torgue@foss.st.com> 11 11 + - Fabrice Gasnier <fabrice.gasnier@foss.st.com> 12 12 + 13 13 + description: ARMv7-M includes a system timer, known as SysTick. 14 14 + 15 15 + properties: 16 16 + compatible: 17 17 + const: arm,armv7m-systick 18 18 + 19 19 + reg: 20 20 + maxItems: 1 21 21 + 22 22 + clocks: 23 23 + maxItems: 1 24 24 + 25 25 + clock-frequency: true 26 26 + 27 27 + oneOf: 28 28 + - required: 29 29 + - clocks 30 30 + - required: 31 31 + - clock-frequency 32 32 + 33 33 + required: 34 34 + - compatible 35 35 + - reg 36 36 + 37 37 + additionalProperties: false 38 38 + 39 39 + examples: 40 40 + - | 41 41 + timer@e000e010 { 42 42 + compatible = "arm,armv7m-systick"; 43 43 + reg = <0xe000e010 0x10>; 44 44 + clocks = <&clk_systick>; 45 45 + }; 46 46 + 47 47 + - | 48 48 + timer@e000e010 { 49 49 + compatible = "arm,armv7m-systick"; 50 50 + reg = <0xe000e010 0x10>; 51 51 + clock-frequency = <90000000>; 52 52 + }; 53 53 + 54 54 + ...

-21

Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.txt

reviewed

··· 1 1 - Nuvoton NPCM7xx timer 2 2 - 3 3 - Nuvoton NPCM7xx have three timer modules, each timer module provides five 24-bit 4 4 - timer counters. 5 5 - 6 6 - Required properties: 7 7 - - compatible : "nuvoton,npcm750-timer" for Poleg NPCM750, or 8 8 - "nuvoton,wpcm450-timer" for Hermon WPCM450. 9 9 - - reg : Offset and length of the register set for the device. 10 10 - - interrupts : Contain the timer interrupt of timer 0. 11 11 - - clocks : phandle of timer reference clock (usually a 25 MHz clock). 12 12 - 13 13 - Example: 14 14 - 15 15 - timer@f0008000 { 16 16 - compatible = "nuvoton,npcm750-timer"; 17 17 - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 18 18 - reg = <0xf0008000 0x50>; 19 19 - clocks = <&clk NPCM7XX_CLK_TIMER>; 20 20 - }; 21 21 -

+46

Documentation/devicetree/bindings/timer/nuvoton,npcm7xx-timer.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/timer/nuvoton,npcm7xx-timer.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Nuvoton NPCM7xx timer 8 8 + 9 9 + maintainers: 10 10 + - Jonathan Neuschäfer <j.neuschaefer@gmx.net> 11 11 + 12 12 + properties: 13 13 + compatible: 14 14 + enum: 15 15 + - nuvoton,wpcm450-timer # for Hermon WPCM450 16 16 + - nuvoton,npcm750-timer # for Poleg NPCM750 17 17 + 18 18 + reg: 19 19 + maxItems: 1 20 20 + 21 21 + interrupts: 22 22 + items: 23 23 + - description: The timer interrupt of timer 0 24 24 + 25 25 + clocks: 26 26 + maxItems: 1 27 27 + 28 28 + required: 29 29 + - compatible 30 30 + - reg 31 31 + - interrupts 32 32 + - clocks 33 33 + 34 34 + additionalProperties: false 35 35 + 36 36 + examples: 37 37 + - | 38 38 + #include <dt-bindings/interrupt-controller/irq.h> 39 39 + #include <dt-bindings/interrupt-controller/arm-gic.h> 40 40 + #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> 41 41 + timer@f0008000 { 42 42 + compatible = "nuvoton,npcm750-timer"; 43 43 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 44 44 + reg = <0xf0008000 0x50>; 45 45 + clocks = <&clk NPCM7XX_CLK_TIMER>; 46 46 + };

+2

Documentation/devicetree/bindings/timer/renesas,ostm.yaml

reviewed

··· 24 24 - renesas,r7s72100-ostm # RZ/A1H 25 25 - renesas,r7s9210-ostm # RZ/A2M 26 26 - renesas,r9a07g044-ostm # RZ/G2{L,LC} 27 27 + - renesas,r9a07g054-ostm # RZ/V2L 27 28 - const: renesas,ostm # Generic 28 29 29 30 reg: ··· 55 54 contains: 56 55 enum: 57 56 - renesas,r9a07g044-ostm 57 57 + - renesas,r9a07g054-ostm 58 58 then: 59 59 required: 60 60 - resets

+5 -4

Documentation/devicetree/bindings/timer/sifive,clint.yaml

reviewed

··· 44 44 45 45 interrupts-extended: 46 46 minItems: 1 47 47 + maxItems: 4095 47 48 48 49 additionalProperties: false 49 50 ··· 57 56 - | 58 57 timer@2000000 { 59 58 compatible = "sifive,fu540-c000-clint", "sifive,clint0"; 60 60 - interrupts-extended = <&cpu1intc 3 &cpu1intc 7 61 61 - &cpu2intc 3 &cpu2intc 7 62 62 - &cpu3intc 3 &cpu3intc 7 63 63 - &cpu4intc 3 &cpu4intc 7>; 59 59 + interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>, 60 60 + <&cpu2intc 3>, <&cpu2intc 7>, 61 61 + <&cpu3intc 3>, <&cpu3intc 7>, 62 62 + <&cpu4intc 3>, <&cpu4intc 7>; 64 63 reg = <0x2000000 0x10000>; 65 64 }; 66 65 ...

+4 -4

Documentation/devicetree/bindings/trivial-devices.yaml

reviewed

··· 77 77 - delta,ahe50dc-fan 78 78 # Delta Electronics DPS-650-AB power supply 79 79 - delta,dps650ab 80 80 - # Delta Electronics DPS920AB 920W 54V Power Supply 80 80 + # Delta Electronics DPS920AB 920W 54V Power Supply 81 81 - delta,dps920ab 82 82 # 1/4 Brick DC/DC Regulated Power Module 83 83 - delta,q54sj108a2 ··· 123 123 - ibm,cffps2 124 124 # Infineon IR36021 digital POL buck controller 125 125 - infineon,ir36021 126 126 - # Infineon IR38060 Voltage Regulator 126 126 + # Infineon IR38060 Voltage Regulator 127 127 - infineon,ir38060 128 128 # Infineon IR38064 Voltage Regulator 129 129 - infineon,ir38064 130 130 - # Infineon IR38164 Voltage Regulator 130 130 + # Infineon IR38164 Voltage Regulator 131 131 - infineon,ir38164 132 132 - # Infineon IR38263 Voltage Regulator 132 132 + # Infineon IR38263 Voltage Regulator 133 133 - infineon,ir38263 134 134 # Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) 135 135 - infineon,slb9635tt

-32

Documentation/devicetree/bindings/ufs/cdns,ufshc.txt

reviewed

··· 1 1 - * Cadence Universal Flash Storage (UFS) Controller 2 2 - 3 3 - UFS nodes are defined to describe on-chip UFS host controllers. 4 4 - Each UFS controller instance should have its own node. 5 5 - Please see the ufshcd-pltfrm.txt for a list of all available properties. 6 6 - 7 7 - Required properties: 8 8 - - compatible : Compatible list, contains one of the following controllers: 9 9 - "cdns,ufshc" - Generic CDNS HCI, 10 10 - "cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY 11 11 - complemented with the JEDEC version: 12 12 - "jedec,ufs-2.0" 13 13 - 14 14 - - reg : Address and length of the UFS register set. 15 15 - - interrupts : One interrupt mapping. 16 16 - - freq-table-hz : Clock frequency table. 17 17 - See the ufshcd-pltfrm.txt for details. 18 18 - - clocks : List of phandle and clock specifier pairs. 19 19 - - clock-names : List of clock input name strings sorted in the same 20 20 - order as the clocks property. "core_clk" is mandatory. 21 21 - Depending on a type of a PHY, 22 22 - the "phy_clk" clock can also be added, if needed. 23 23 - 24 24 - Example: 25 25 - ufs@fd030000 { 26 26 - compatible = "cdns,ufshc", "jedec,ufs-2.0"; 27 27 - reg = <0xfd030000 0x10000>; 28 28 - interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; 29 29 - freq-table-hz = <0 0>, <0 0>; 30 30 - clocks = <&ufs_core_clk>, <&ufs_phy_clk>; 31 31 - clock-names = "core_clk", "phy_clk"; 32 32 - };

+68

Documentation/devicetree/bindings/ufs/cdns,ufshc.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Cadence Universal Flash Storage (UFS) Controller 8 8 + 9 9 + maintainers: 10 10 + - Jan Kotas <jank@cadence.com> 11 11 + 12 12 + # Select only our matches, not all jedec,ufs-2.0 13 13 + select: 14 14 + properties: 15 15 + compatible: 16 16 + contains: 17 17 + enum: 18 18 + - cdns,ufshc 19 19 + - cdns,ufshc-m31-16nm 20 20 + required: 21 21 + - compatible 22 22 + 23 23 + allOf: 24 24 + - $ref: ufs-common.yaml 25 25 + 26 26 + properties: 27 27 + compatible: 28 28 + items: 29 29 + - enum: 30 30 + - cdns,ufshc 31 31 + # CDNS UFS HC + M31 16nm PHY 32 32 + - cdns,ufshc-m31-16nm 33 33 + - const: jedec,ufs-2.0 34 34 + 35 35 + clocks: 36 36 + minItems: 1 37 37 + maxItems: 3 38 38 + 39 39 + clock-names: 40 40 + minItems: 1 41 41 + items: 42 42 + - const: core_clk 43 43 + - const: phy_clk 44 44 + - const: ref_clk 45 45 + 46 46 + reg: 47 47 + maxItems: 1 48 48 + 49 49 + required: 50 50 + - compatible 51 51 + - clocks 52 52 + - clock-names 53 53 + - reg 54 54 + 55 55 + unevaluatedProperties: false 56 56 + 57 57 + examples: 58 58 + - | 59 59 + #include <dt-bindings/interrupt-controller/arm-gic.h> 60 60 + 61 61 + ufs@fd030000 { 62 62 + compatible = "cdns,ufshc", "jedec,ufs-2.0"; 63 63 + reg = <0xfd030000 0x10000>; 64 64 + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 65 65 + freq-table-hz = <0 0>, <0 0>; 66 66 + clocks = <&ufs_core_clk>, <&ufs_phy_clk>; 67 67 + clock-names = "core_clk", "phy_clk"; 68 68 + };

+90

Documentation/devicetree/bindings/ufs/hisilicon,ufs.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/ufs/hisilicon,ufs.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: HiSilicon Universal Flash Storage (UFS) Controller 8 8 + 9 9 + maintainers: 10 10 + - Li Wei <liwei213@huawei.com> 11 11 + 12 12 + # Select only our matches, not all jedec,ufs 13 13 + select: 14 14 + properties: 15 15 + compatible: 16 16 + contains: 17 17 + enum: 18 18 + - hisilicon,hi3660-ufs 19 19 + - hisilicon,hi3670-ufs 20 20 + required: 21 21 + - compatible 22 22 + 23 23 + allOf: 24 24 + - $ref: ufs-common.yaml 25 25 + 26 26 + properties: 27 27 + compatible: 28 28 + oneOf: 29 29 + - items: 30 30 + - const: hisilicon,hi3660-ufs 31 31 + - const: jedec,ufs-1.1 32 32 + - items: 33 33 + - enum: 34 34 + - hisilicon,hi3670-ufs 35 35 + - const: jedec,ufs-2.1 36 36 + 37 37 + clocks: 38 38 + minItems: 2 39 39 + maxItems: 2 40 40 + 41 41 + clock-names: 42 42 + items: 43 43 + - const: ref_clk 44 44 + - const: phy_clk 45 45 + 46 46 + reg: 47 47 + items: 48 48 + - description: UFS register address space 49 49 + - description: UFS SYS CTRL register address space 50 50 + 51 51 + resets: 52 52 + maxItems: 1 53 53 + 54 54 + reset-names: 55 55 + items: 56 56 + - const: rst 57 57 + 58 58 + required: 59 59 + - compatible 60 60 + - reg 61 61 + - resets 62 62 + - reset-names 63 63 + 64 64 + unevaluatedProperties: false 65 65 + 66 66 + examples: 67 67 + - | 68 68 + #include <dt-bindings/clock/hi3670-clock.h> 69 69 + #include <dt-bindings/interrupt-controller/arm-gic.h> 70 70 + 71 71 + soc { 72 72 + #address-cells = <2>; 73 73 + #size-cells = <2>; 74 74 + 75 75 + ufs@ff3c0000 { 76 76 + compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; 77 77 + reg = <0x0 0xff3c0000 0x0 0x1000>, 78 78 + <0x0 0xff3e0000 0x0 0x1000>; 79 79 + interrupt-parent = <&gic>; 80 80 + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 81 81 + clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, 82 82 + <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; 83 83 + clock-names = "ref_clk", "phy_clk"; 84 84 + freq-table-hz = <0 0>, 85 85 + <0 0>; 86 86 + 87 87 + resets = <&crg_rst 0x84 12>; 88 88 + reset-names = "rst"; 89 89 + }; 90 90 + };

+67

Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/ufs/mediatek,ufs.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Mediatek Universal Flash Storage (UFS) Controller 8 8 + 9 9 + maintainers: 10 10 + - Stanley Chu <stanley.chu@mediatek.com> 11 11 + 12 12 + allOf: 13 13 + - $ref: ufs-common.yaml 14 14 + 15 15 + properties: 16 16 + compatible: 17 17 + enum: 18 18 + - mediatek,mt8183-ufshci 19 19 + - mediatek,mt8192-ufshci 20 20 + 21 21 + clocks: 22 22 + maxItems: 1 23 23 + 24 24 + clock-names: 25 25 + items: 26 26 + - const: ufs 27 27 + 28 28 + phys: 29 29 + maxItems: 1 30 30 + 31 31 + reg: 32 32 + maxItems: 1 33 33 + 34 34 + vcc-supply: true 35 35 + 36 36 + required: 37 37 + - compatible 38 38 + - clocks 39 39 + - clock-names 40 40 + - phys 41 41 + - reg 42 42 + - vcc-supply 43 43 + 44 44 + unevaluatedProperties: false 45 45 + 46 46 + examples: 47 47 + - | 48 48 + #include <dt-bindings/clock/mt8183-clk.h> 49 49 + #include <dt-bindings/interrupt-controller/arm-gic.h> 50 50 + 51 51 + soc { 52 52 + #address-cells = <2>; 53 53 + #size-cells = <2>; 54 54 + 55 55 + ufs@ff3c0000 { 56 56 + compatible = "mediatek,mt8183-ufshci"; 57 57 + reg = <0 0x11270000 0 0x2300>; 58 58 + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>; 59 59 + phys = <&ufsphy>; 60 60 + 61 61 + clocks = <&infracfg_ao CLK_INFRA_UFS>; 62 62 + clock-names = "ufs"; 63 63 + freq-table-hz = <0 0>; 64 64 + 65 65 + vcc-supply = <&mt_pmic_vemc_ldo_reg>; 66 66 + }; 67 67 + };

+244

Documentation/devicetree/bindings/ufs/qcom,ufs.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Qualcomm Universal Flash Storage (UFS) Controller 8 8 + 9 9 + maintainers: 10 10 + - Bjorn Andersson <bjorn.andersson@linaro.org> 11 11 + - Andy Gross <agross@kernel.org> 12 12 + 13 13 + # Select only our matches, not all jedec,ufs-2.0 14 14 + select: 15 15 + properties: 16 16 + compatible: 17 17 + contains: 18 18 + const: qcom,ufshc 19 19 + required: 20 20 + - compatible 21 21 + 22 22 + properties: 23 23 + compatible: 24 24 + items: 25 25 + - enum: 26 26 + - qcom,msm8994-ufshc 27 27 + - qcom,msm8996-ufshc 28 28 + - qcom,msm8998-ufshc 29 29 + - qcom,sdm845-ufshc 30 30 + - qcom,sm6350-ufshc 31 31 + - qcom,sm8150-ufshc 32 32 + - qcom,sm8250-ufshc 33 33 + - qcom,sm8350-ufshc 34 34 + - qcom,sm8450-ufshc 35 35 + - const: qcom,ufshc 36 36 + - const: jedec,ufs-2.0 37 37 + 38 38 + clocks: 39 39 + minItems: 8 40 40 + maxItems: 11 41 41 + 42 42 + clock-names: 43 43 + minItems: 8 44 44 + maxItems: 11 45 45 + 46 46 + interconnects: 47 47 + minItems: 2 48 48 + maxItems: 2 49 49 + 50 50 + interconnect-names: 51 51 + items: 52 52 + - const: ufs-ddr 53 53 + - const: cpu-ufs 54 54 + 55 55 + iommus: 56 56 + minItems: 1 57 57 + maxItems: 2 58 58 + 59 59 + phys: 60 60 + maxItems: 1 61 61 + 62 62 + phy-names: 63 63 + items: 64 64 + - const: ufsphy 65 65 + 66 66 + power-domains: 67 67 + maxItems: 1 68 68 + 69 69 + reg: 70 70 + minItems: 1 71 71 + maxItems: 2 72 72 + 73 73 + resets: 74 74 + maxItems: 1 75 75 + 76 76 + '#reset-cells': 77 77 + const: 1 78 78 + 79 79 + reset-names: 80 80 + items: 81 81 + - const: rst 82 82 + 83 83 + reset-gpios: 84 84 + maxItems: 1 85 85 + description: 86 86 + GPIO connected to the RESET pin of the UFS memory device. 87 87 + 88 88 + required: 89 89 + - compatible 90 90 + - reg 91 91 + 92 92 + allOf: 93 93 + - $ref: ufs-common.yaml 94 94 + 95 95 + - if: 96 96 + properties: 97 97 + compatible: 98 98 + contains: 99 99 + enum: 100 100 + - qcom,msm8998-ufshc 101 101 + - qcom,sm8250-ufshc 102 102 + - qcom,sm8350-ufshc 103 103 + - qcom,sm8450-ufshc 104 104 + then: 105 105 + properties: 106 106 + clocks: 107 107 + minItems: 8 108 108 + maxItems: 8 109 109 + clock-names: 110 110 + items: 111 111 + - const: core_clk 112 112 + - const: bus_aggr_clk 113 113 + - const: iface_clk 114 114 + - const: core_clk_unipro 115 115 + - const: ref_clk 116 116 + - const: tx_lane0_sync_clk 117 117 + - const: rx_lane0_sync_clk 118 118 + - const: rx_lane1_sync_clk 119 119 + reg: 120 120 + minItems: 1 121 121 + maxItems: 1 122 122 + 123 123 + - if: 124 124 + properties: 125 125 + compatible: 126 126 + contains: 127 127 + enum: 128 128 + - qcom,sdm845-ufshc 129 129 + - qcom,sm6350-ufshc 130 130 + - qcom,sm8150-ufshc 131 131 + then: 132 132 + properties: 133 133 + clocks: 134 134 + minItems: 9 135 135 + maxItems: 9 136 136 + clock-names: 137 137 + items: 138 138 + - const: core_clk 139 139 + - const: bus_aggr_clk 140 140 + - const: iface_clk 141 141 + - const: core_clk_unipro 142 142 + - const: ref_clk 143 143 + - const: tx_lane0_sync_clk 144 144 + - const: rx_lane0_sync_clk 145 145 + - const: rx_lane1_sync_clk 146 146 + - const: ice_core_clk 147 147 + reg: 148 148 + minItems: 2 149 149 + maxItems: 2 150 150 + 151 151 + - if: 152 152 + properties: 153 153 + compatible: 154 154 + contains: 155 155 + enum: 156 156 + - qcom,msm8996-ufshc 157 157 + then: 158 158 + properties: 159 159 + clocks: 160 160 + minItems: 11 161 161 + maxItems: 11 162 162 + clock-names: 163 163 + items: 164 164 + - const: core_clk_src 165 165 + - const: core_clk 166 166 + - const: bus_clk 167 167 + - const: bus_aggr_clk 168 168 + - const: iface_clk 169 169 + - const: core_clk_unipro_src 170 170 + - const: core_clk_unipro 171 171 + - const: core_clk_ice 172 172 + - const: ref_clk 173 173 + - const: tx_lane0_sync_clk 174 174 + - const: rx_lane0_sync_clk 175 175 + reg: 176 176 + minItems: 1 177 177 + maxItems: 1 178 178 + 179 179 + # TODO: define clock bindings for qcom,msm8994-ufshc 180 180 + 181 181 + unevaluatedProperties: false 182 182 + 183 183 + examples: 184 184 + - | 185 185 + #include <dt-bindings/clock/qcom,gcc-sm8450.h> 186 186 + #include <dt-bindings/clock/qcom,rpmh.h> 187 187 + #include <dt-bindings/gpio/gpio.h> 188 188 + #include <dt-bindings/interconnect/qcom,sm8450.h> 189 189 + #include <dt-bindings/interrupt-controller/arm-gic.h> 190 190 + 191 191 + soc { 192 192 + #address-cells = <2>; 193 193 + #size-cells = <2>; 194 194 + 195 195 + ufs@1d84000 { 196 196 + compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 197 197 + "jedec,ufs-2.0"; 198 198 + reg = <0 0x01d84000 0 0x3000>; 199 199 + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 200 200 + phys = <&ufs_mem_phy_lanes>; 201 201 + phy-names = "ufsphy"; 202 202 + lanes-per-direction = <2>; 203 203 + #reset-cells = <1>; 204 204 + resets = <&gcc GCC_UFS_PHY_BCR>; 205 205 + reset-names = "rst"; 206 206 + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; 207 207 + 208 208 + vcc-supply = <&vreg_l7b_2p5>; 209 209 + vcc-max-microamp = <1100000>; 210 210 + vccq-supply = <&vreg_l9b_1p2>; 211 211 + vccq-max-microamp = <1200000>; 212 212 + 213 213 + power-domains = <&gcc UFS_PHY_GDSC>; 214 214 + iommus = <&apps_smmu 0xe0 0x0>; 215 215 + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, 216 216 + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; 217 217 + interconnect-names = "ufs-ddr", "cpu-ufs"; 218 218 + 219 219 + clock-names = "core_clk", 220 220 + "bus_aggr_clk", 221 221 + "iface_clk", 222 222 + "core_clk_unipro", 223 223 + "ref_clk", 224 224 + "tx_lane0_sync_clk", 225 225 + "rx_lane0_sync_clk", 226 226 + "rx_lane1_sync_clk"; 227 227 + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 228 228 + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 229 229 + <&gcc GCC_UFS_PHY_AHB_CLK>, 230 230 + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 231 231 + <&rpmhcc RPMH_CXO_CLK>, 232 232 + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 233 233 + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 234 234 + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 235 235 + freq-table-hz = <75000000 300000000>, 236 236 + <0 0>, 237 237 + <0 0>, 238 238 + <75000000 300000000>, 239 239 + <75000000 300000000>, 240 240 + <0 0>, 241 241 + <0 0>, 242 242 + <0 0>; 243 243 + }; 244 244 + };

+4 -9

Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml

reviewed

··· 11 11 12 12 description: | 13 13 Each Samsung UFS host controller instance should have its own node. 14 14 - This binding define Samsung specific binding other then what is used 15 15 - in the common ufshcd bindings 16 16 - [1] Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt 14 14 + 15 15 + allOf: 16 16 + - $ref: ufs-common.yaml 17 17 18 18 properties: 19 19 - 20 19 compatible: 21 20 enum: 22 21 - samsung,exynos7-ufs ··· 46 47 - const: core_clk 47 48 - const: sclk_unipro_main 48 49 49 49 - interrupts: 50 50 - maxItems: 1 51 51 - 52 50 phys: 53 51 maxItems: 1 54 52 ··· 63 67 required: 64 68 - compatible 65 69 - reg 66 66 - - interrupts 67 70 - phys 68 71 - phy-names 69 72 - clocks 70 73 - clock-names 71 74 72 72 - additionalProperties: false 75 75 + unevaluatedProperties: false 73 76 74 77 examples: 75 78 - |

+51

Documentation/devicetree/bindings/ufs/snps,tc-dwc-g210.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/ufs/snps,tc-dwc-g210.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Synopsys DesignWare Universal Flash Storage (UFS) Controller 8 8 + 9 9 + maintainers: 10 10 + - Li Wei <liwei213@huawei.com> 11 11 + 12 12 + # Select only our matches, not all jedec,ufs 13 13 + select: 14 14 + properties: 15 15 + compatible: 16 16 + contains: 17 17 + enum: 18 18 + - snps,dwc-ufshcd-1.40a 19 19 + required: 20 20 + - compatible 21 21 + 22 22 + allOf: 23 23 + - $ref: ufs-common.yaml 24 24 + 25 25 + properties: 26 26 + compatible: 27 27 + items: 28 28 + - enum: 29 29 + - snps,g210-tc-6.00-20bit 30 30 + - snps,g210-tc-6.00-40bit 31 31 + - const: snps,dwc-ufshcd-1.40a 32 32 + - const: jedec,ufs-2.0 33 33 + 34 34 + reg: 35 35 + maxItems: 1 36 36 + 37 37 + required: 38 38 + - compatible 39 39 + - reg 40 40 + 41 41 + unevaluatedProperties: false 42 42 + 43 43 + examples: 44 44 + - | 45 45 + ufs@d0000000 { 46 46 + compatible = "snps,g210-tc-6.00-40bit", 47 47 + "snps,dwc-ufshcd-1.40a", 48 48 + "jedec,ufs-2.0"; 49 49 + reg = <0xd0000000 0x10000>; 50 50 + interrupts = <24>; 51 51 + };

-26

Documentation/devicetree/bindings/ufs/tc-dwc-g210-pltfrm.txt

reviewed

··· 1 1 - * Universal Flash Storage (UFS) DesignWare Host Controller 2 2 - 3 3 - DWC_UFS nodes are defined to describe on-chip UFS host controllers and MPHY. 4 4 - Each UFS controller instance should have its own node. 5 5 - 6 6 - Required properties: 7 7 - - compatible : compatible list must contain the PHY type & version: 8 8 - "snps,g210-tc-6.00-20bit" 9 9 - "snps,g210-tc-6.00-40bit" 10 10 - complemented with the Controller IP version: 11 11 - "snps,dwc-ufshcd-1.40a" 12 12 - complemented with the JEDEC version: 13 13 - "jedec,ufs-1.1" 14 14 - "jedec,ufs-2.0" 15 15 - 16 16 - - reg : <registers mapping> 17 17 - - interrupts : <interrupt mapping for UFS host controller IRQ> 18 18 - 19 19 - Example for a setup using a 1.40a DWC Controller with a 6.00 G210 40-bit TC: 20 20 - dwc-ufs@d0000000 { 21 21 - compatible = "snps,g210-tc-6.00-40bit", 22 22 - "snps,dwc-ufshcd-1.40a", 23 23 - "jedec,ufs-2.0"; 24 24 - reg = < 0xd0000000 0x10000 >; 25 25 - interrupts = < 24 >; 26 26 - };

+3 -4

Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml

reviewed

··· 47 47 48 48 patternProperties: 49 49 "^ufs@[0-9a-f]+$": 50 50 - type: object 50 50 + $ref: cdns,ufshc.yaml 51 51 description: | 52 52 - Cadence UFS controller node must be the child node. Refer 53 53 - Documentation/devicetree/bindings/ufs/cdns,ufshc.txt for binding 54 54 - documentation of child node 52 52 + Cadence UFS controller node must be the child node. 53 53 + unevaluatedProperties: false 55 54 56 55 additionalProperties: false 57 56

+82

Documentation/devicetree/bindings/ufs/ufs-common.yaml

reviewed

··· 1 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 2 + %YAML 1.2 3 3 + --- 4 4 + $id: http://devicetree.org/schemas/ufs/ufs-common.yaml# 5 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 + 7 7 + title: Common properties for Universal Flash Storage (UFS) Host Controllers 8 8 + 9 9 + maintainers: 10 10 + - Alim Akhtar <alim.akhtar@samsung.com> 11 11 + - Avri Altman <avri.altman@wdc.com> 12 12 + 13 13 + properties: 14 14 + clocks: true 15 15 + 16 16 + clock-names: true 17 17 + 18 18 + freq-table-hz: 19 19 + items: 20 20 + items: 21 21 + - description: Minimum frequency for given clock in Hz 22 22 + - description: Maximum frequency for given clock in Hz 23 23 + description: | 24 24 + Array of <min max> operating frequencies in Hz stored in the same order 25 25 + as the clocks property. If this property is not defined or a value in the 26 26 + array is "0" then it is assumed that the frequency is set by the parent 27 27 + clock or a fixed rate clock source. 28 28 + 29 29 + interrupts: 30 30 + maxItems: 1 31 31 + 32 32 + lanes-per-direction: 33 33 + $ref: /schemas/types.yaml#/definitions/uint32 34 34 + enum: [1, 2] 35 35 + default: 2 36 36 + description: 37 37 + Number of lanes available per direction. Note that it is assume same 38 38 + number of lanes is used both directions at once. 39 39 + 40 40 + vdd-hba-supply: 41 41 + description: 42 42 + Phandle to UFS host controller supply regulator node. 43 43 + 44 44 + vcc-supply: 45 45 + description: 46 46 + Phandle to VCC supply regulator node. 47 47 + 48 48 + vccq-supply: 49 49 + description: 50 50 + Phandle to VCCQ supply regulator node. 51 51 + 52 52 + vccq2-supply: 53 53 + description: 54 54 + Phandle to VCCQ2 supply regulator node. 55 55 + 56 56 + vcc-supply-1p8: 57 57 + type: boolean 58 58 + description: 59 59 + For embedded UFS devices, valid VCC range is 1.7-1.95V or 2.7-3.6V. This 60 60 + boolean property when set, specifies to use low voltage range of 61 61 + 1.7-1.95V. Note for external UFS cards this property is invalid and valid 62 62 + VCC range is always 2.7-3.6V. 63 63 + 64 64 + vcc-max-microamp: 65 65 + description: 66 66 + Specifies max. load that can be drawn from VCC supply. 67 67 + 68 68 + vccq-max-microamp: 69 69 + description: 70 70 + Specifies max. load that can be drawn from VCCQ supply. 71 71 + 72 72 + vccq2-max-microamp: 73 73 + description: 74 74 + Specifies max. load that can be drawn from VCCQ2 supply. 75 75 + 76 76 + dependencies: 77 77 + freq-table-hz: [ 'clocks' ] 78 78 + 79 79 + required: 80 80 + - interrupts 81 81 + 82 82 + additionalProperties: true

-42

Documentation/devicetree/bindings/ufs/ufs-hisi.txt

reviewed

··· 1 1 - * Hisilicon Universal Flash Storage (UFS) Host Controller 2 2 - 3 3 - UFS nodes are defined to describe on-chip UFS hardware macro. 4 4 - Each UFS Host Controller should have its own node. 5 5 - 6 6 - Required properties: 7 7 - - compatible : compatible list, contains one of the following - 8 8 - "hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs 9 9 - host controller present on Hi3660 chipset. 10 10 - "hisilicon,hi3670-ufs", "jedec,ufs-2.1" for hisi ufs 11 11 - host controller present on Hi3670 chipset. 12 12 - - reg : should contain UFS register address space & UFS SYS CTRL register address, 13 13 - - interrupts : interrupt number 14 14 - - clocks : List of phandle and clock specifier pairs 15 15 - - clock-names : List of clock input name strings sorted in the same 16 16 - order as the clocks property. "ref_clk", "phy_clk" is optional 17 17 - - freq-table-hz : Array of <min max> operating frequencies stored in the same 18 18 - order as the clocks property. If this property is not 19 19 - defined or a value in the array is "0" then it is assumed 20 20 - that the frequency is set by the parent clock or a 21 21 - fixed rate clock source. 22 22 - - resets : describe reset node register 23 23 - - reset-names : reset node register, the "rst" corresponds to reset the whole UFS IP. 24 24 - 25 25 - Example: 26 26 - 27 27 - ufs: ufs@ff3b0000 { 28 28 - compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; 29 29 - /* 0: HCI standard */ 30 30 - /* 1: UFS SYS CTRL */ 31 31 - reg = <0x0 0xff3b0000 0x0 0x1000>, 32 32 - <0x0 0xff3b1000 0x0 0x1000>; 33 33 - interrupt-parent = <&gic>; 34 34 - interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 35 35 - clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, 36 36 - <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; 37 37 - clock-names = "ref_clk", "phy_clk"; 38 38 - freq-table-hz = <0 0>, <0 0>; 39 39 - /* offset: 0x84; bit: 12 */ 40 40 - resets = <&crg_rst 0x84 12>; 41 41 - reset-names = "rst"; 42 42 - };

-45

Documentation/devicetree/bindings/ufs/ufs-mediatek.txt

reviewed

··· 1 1 - * Mediatek Universal Flash Storage (UFS) Host Controller 2 2 - 3 3 - UFS nodes are defined to describe on-chip UFS hardware macro. 4 4 - Each UFS Host Controller should have its own node. 5 5 - 6 6 - To bind UFS PHY with UFS host controller, the controller node should 7 7 - contain a phandle reference to UFS M-PHY node. 8 8 - 9 9 - Required properties for UFS nodes: 10 10 - - compatible : Compatible list, contains the following controller: 11 11 - "mediatek,mt8183-ufshci" for MediaTek UFS host controller 12 12 - present on MT8183 chipsets. 13 13 - "mediatek,mt8192-ufshci" for MediaTek UFS host controller 14 14 - present on MT8192 chipsets. 15 15 - - reg : Address and length of the UFS register set. 16 16 - - phys : phandle to m-phy. 17 17 - - clocks : List of phandle and clock specifier pairs. 18 18 - - clock-names : List of clock input name strings sorted in the same 19 19 - order as the clocks property. "ufs" is mandatory. 20 20 - "ufs": ufshci core control clock. 21 21 - - freq-table-hz : Array of <min max> operating frequencies stored in the same 22 22 - order as the clocks property. If this property is not 23 23 - defined or a value in the array is "0" then it is assumed 24 24 - that the frequency is set by the parent clock or a 25 25 - fixed rate clock source. 26 26 - - vcc-supply : phandle to VCC supply regulator node. 27 27 - 28 28 - Example: 29 29 - 30 30 - ufsphy: phy@11fa0000 { 31 31 - ... 32 32 - }; 33 33 - 34 34 - ufshci@11270000 { 35 35 - compatible = "mediatek,mt8183-ufshci"; 36 36 - reg = <0 0x11270000 0 0x2300>; 37 37 - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>; 38 38 - phys = <&ufsphy>; 39 39 - 40 40 - clocks = <&infracfg_ao INFRACFG_AO_UFS_CG>; 41 41 - clock-names = "ufs"; 42 42 - freq-table-hz = <0 0>; 43 43 - 44 44 - vcc-supply = <&mt_pmic_vemc_ldo_reg>; 45 45 - };

-63

Documentation/devicetree/bindings/ufs/ufs-qcom.txt

reviewed

··· 1 1 - * Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY 2 2 - 3 3 - UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro. 4 4 - Each UFS PHY node should have its own node. 5 5 - 6 6 - To bind UFS PHY with UFS host controller, the controller node should 7 7 - contain a phandle reference to UFS PHY node. 8 8 - 9 9 - Required properties: 10 10 - - compatible : compatible list, contains one of the following - 11 11 - "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy, 12 12 - "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy, 13 13 - "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy 14 14 - present on MSM8996 chipset. 15 15 - - reg : should contain PHY register address space (mandatory), 16 16 - - reg-names : indicates various resources passed to driver (via reg proptery) by name. 17 17 - Required "reg-names" is "phy_mem". 18 18 - - #phy-cells : This property shall be set to 0 19 19 - - vdda-phy-supply : phandle to main PHY supply for analog domain 20 20 - - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply 21 21 - - clocks : List of phandle and clock specifier pairs 22 22 - - clock-names : List of clock input name strings sorted in the same 23 23 - order as the clocks property. "ref_clk_src", "ref_clk", 24 24 - "tx_iface_clk" & "rx_iface_clk" are mandatory but 25 25 - "ref_clk_parent" is optional 26 26 - 27 27 - Optional properties: 28 28 - - vdda-phy-max-microamp : specifies max. load that can be drawn from phy supply 29 29 - - vdda-pll-max-microamp : specifies max. load that can be drawn from pll supply 30 30 - - vddp-ref-clk-supply : phandle to UFS device ref_clk pad power supply 31 31 - - vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply 32 32 - - resets : specifies the PHY reset in the UFS controller 33 33 - 34 34 - Example: 35 35 - 36 36 - ufsphy1: ufsphy@fc597000 { 37 37 - compatible = "qcom,ufs-phy-qmp-20nm"; 38 38 - reg = <0xfc597000 0x800>; 39 39 - reg-names = "phy_mem"; 40 40 - #phy-cells = <0>; 41 41 - vdda-phy-supply = <&pma8084_l4>; 42 42 - vdda-pll-supply = <&pma8084_l12>; 43 43 - vdda-phy-max-microamp = <50000>; 44 44 - vdda-pll-max-microamp = <1000>; 45 45 - clock-names = "ref_clk_src", 46 46 - "ref_clk_parent", 47 47 - "ref_clk", 48 48 - "tx_iface_clk", 49 49 - "rx_iface_clk"; 50 50 - clocks = <&clock_rpm clk_ln_bb_clk>, 51 51 - <&clock_gcc clk_pcie_1_phy_ldo >, 52 52 - <&clock_gcc clk_ufs_phy_ldo>, 53 53 - <&clock_gcc clk_gcc_ufs_tx_cfg_clk>, 54 54 - <&clock_gcc clk_gcc_ufs_rx_cfg_clk>; 55 55 - resets = <&ufshc 0>; 56 56 - }; 57 57 - 58 58 - ufshc: ufshc@fc598000 { 59 59 - #reset-cells = <1>; 60 60 - ... 61 61 - phys = <&ufsphy1>; 62 62 - phy-names = "ufsphy"; 63 63 - };

-90

Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt

reviewed

··· 1 1 - * Universal Flash Storage (UFS) Host Controller 2 2 - 3 3 - UFSHC nodes are defined to describe on-chip UFS host controllers. 4 4 - Each UFS controller instance should have its own node. 5 5 - 6 6 - Required properties: 7 7 - - compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0" 8 8 - 9 9 - For Qualcomm SoCs must contain, as below, an 10 10 - SoC-specific compatible along with "qcom,ufshc" and 11 11 - the appropriate jedec string: 12 12 - "qcom,msm8994-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 13 13 - "qcom,msm8996-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 14 14 - "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 15 15 - "qcom,sdm845-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 16 16 - "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 17 17 - "qcom,sm8250-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 18 18 - "qcom,sm8350-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 19 19 - "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0" 20 20 - - interrupts : <interrupt mapping for UFS host controller IRQ> 21 21 - - reg : <registers mapping> 22 22 - 23 23 - Optional properties: 24 24 - - phys : phandle to UFS PHY node 25 25 - - phy-names : the string "ufsphy" when is found in a node, along 26 26 - with "phys" attribute, provides phandle to UFS PHY node 27 27 - - vdd-hba-supply : phandle to UFS host controller supply regulator node 28 28 - - vcc-supply : phandle to VCC supply regulator node 29 29 - - vccq-supply : phandle to VCCQ supply regulator node 30 30 - - vccq2-supply : phandle to VCCQ2 supply regulator node 31 31 - - vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V 32 32 - or 2.7-3.6V. This boolean property when set, specifies 33 33 - to use low voltage range of 1.7-1.95V. Note for external 34 34 - UFS cards this property is invalid and valid VCC range is 35 35 - always 2.7-3.6V. 36 36 - - vcc-max-microamp : specifies max. load that can be drawn from vcc supply 37 37 - - vccq-max-microamp : specifies max. load that can be drawn from vccq supply 38 38 - - vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply 39 39 - 40 40 - - clocks : List of phandle and clock specifier pairs 41 41 - - clock-names : List of clock input name strings sorted in the same 42 42 - order as the clocks property. 43 43 - "ref_clk" indicates reference clock frequency. 44 44 - UFS host supplies reference clock to UFS device and UFS device 45 45 - specification allows host to provide one of the 4 frequencies (19.2 MHz, 46 46 - 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is 47 47 - parsed and used to update the reference clock setting in device. 48 48 - Defaults to 26 MHz(as per specification) if not specified by host. 49 49 - - freq-table-hz : Array of <min max> operating frequencies stored in the same 50 50 - order as the clocks property. If this property is not 51 51 - defined or a value in the array is "0" then it is assumed 52 52 - that the frequency is set by the parent clock or a 53 53 - fixed rate clock source. 54 54 - -lanes-per-direction : number of lanes available per direction - either 1 or 2. 55 55 - Note that it is assume same number of lanes is used both 56 56 - directions at once. If not specified, default is 2 lanes per direction. 57 57 - - #reset-cells : Must be <1> for Qualcomm UFS controllers that expose 58 58 - PHY reset from the UFS controller. 59 59 - - resets : reset node register 60 60 - - reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP. 61 61 - - reset-gpios : A phandle and gpio specifier denoting the GPIO connected 62 62 - to the RESET pin of the UFS memory device. 63 63 - 64 64 - Note: If above properties are not defined it can be assumed that the supply 65 65 - regulators or clocks are always on. 66 66 - 67 67 - Example: 68 68 - ufshc@fc598000 { 69 69 - compatible = "jedec,ufs-1.1"; 70 70 - reg = <0xfc598000 0x800>; 71 71 - interrupts = <0 28 0>; 72 72 - 73 73 - vdd-hba-supply = <&xxx_reg0>; 74 74 - vcc-supply = <&xxx_reg1>; 75 75 - vcc-supply-1p8; 76 76 - vccq-supply = <&xxx_reg2>; 77 77 - vccq2-supply = <&xxx_reg3>; 78 78 - vcc-max-microamp = 500000; 79 79 - vccq-max-microamp = 200000; 80 80 - vccq2-max-microamp = 200000; 81 81 - 82 82 - clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>; 83 83 - clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk"; 84 84 - freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>; 85 85 - resets = <&reset 0 1>; 86 86 - reset-names = "rst"; 87 87 - phys = <&ufsphy1>; 88 88 - phy-names = "ufsphy"; 89 89 - #reset-cells = <1>; 90 90 - };

+1 -1

Documentation/devicetree/bindings/usb/dwc3-cavium.txt

reviewed

··· 20 20 refclk-type-hs = "dlmc_ref_clk0"; 21 21 power = <0x00000002 0x00000002 0x00000001>; 22 22 xhci@1690000000000 { 23 23 - compatible = "cavium,octeon-7130-xhci", "synopsys,dwc3"; 23 23 + compatible = "cavium,octeon-7130-xhci", "snps,dwc3"; 24 24 reg = <0x00016900 0x00000000 0x00000010 0x00000000>; 25 25 interrupt-parent = <0x00000010>; 26 26 interrupts = <0x00000009 0x00000004>;

+1 -1

Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml

reviewed

··· 83 83 - const: ss 84 84 85 85 nvidia,xusb-padctl: 86 86 - $ref: /schemas/types.yaml#/definitions/phandle-array 86 86 + $ref: /schemas/types.yaml#/definitions/phandle 87 87 description: 88 88 phandle to the XUSB pad controller that is used to configure the USB pads 89 89 used by the XUDC controller.

+4 -1

Documentation/devicetree/bindings/usb/renesas,usbhs.yaml

reviewed

··· 20 20 - enum: 21 21 - renesas,usbhs-r7s9210 # RZ/A2 22 22 - renesas,usbhs-r9a07g044 # RZ/G2{L,LC} 23 23 + - renesas,usbhs-r9a07g054 # RZ/V2L 23 24 - const: renesas,rza2-usbhs 24 25 25 26 - items: ··· 117 116 properties: 118 117 compatible: 119 118 contains: 120 120 - const: renesas,usbhs-r9a07g044 119 119 + enum: 120 120 + - renesas,usbhs-r9a07g044 121 121 + - renesas,usbhs-r9a07g054 121 122 then: 122 123 properties: 123 124 interrupts:

+1 -3

Documentation/devicetree/bindings/usb/st,stusb160x.yaml

reviewed

··· 32 32 33 33 connector: 34 34 type: object 35 35 - 36 36 - allOf: 37 37 - - $ref: ../connector/usb-connector.yaml 35 35 + $ref: /schemas/connector/usb-connector.yaml# 38 36 39 37 properties: 40 38 compatible:

+1 -1

Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml

reviewed

··· 92 92 ranges; 93 93 94 94 usb@2690000 { 95 95 - compatible = "synopsys,dwc3"; 95 95 + compatible = "snps,dwc3"; 96 96 reg = <0x2690000 0x70000>; 97 97 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; 98 98 usb-phy = <&usb_phy>, <&usb_phy>;

+11 -1

Documentation/devicetree/bindings/vendor-prefixes.yaml

reviewed

··· 509 509 description: Himax Technologies, Inc. 510 510 "^hirschmann,.*": 511 511 description: Hirschmann Automation and Control GmbH 512 512 + "^hisi,.*": 513 513 + description: HiSilicon Limited (deprecated, use hisilicon) 514 514 + deprecated: true 512 515 "^hisilicon,.*": 513 516 description: HiSilicon Limited. 514 517 "^hit,.*": ··· 527 524 "^hoperun,.*": 528 525 description: Jiangsu HopeRun Software Co., Ltd. 529 526 "^hp,.*": 530 530 - description: Hewlett Packard 527 527 + description: Hewlett Packard Inc. 528 528 + "^hpe,.*": 529 529 + description: Hewlett Packard Enterprise 531 530 "^hsg,.*": 532 531 description: HannStar Display Co. 533 532 "^holtek,.*": ··· 1205 1200 description: Synaptics Inc. 1206 1201 "^synology,.*": 1207 1202 description: Synology, Inc. 1203 1203 + "^synopsys,.*": 1204 1204 + description: Synopsys, Inc. (deprecated, use snps) 1205 1205 + deprecated: true 1208 1206 "^tbs,.*": 1209 1207 description: TBS Technologies 1210 1208 "^tbs-biometrics,.*": ··· 1393 1385 description: Wanchanglong Electronics Technology（SHENZHEN）Co.，Ltd. 1394 1386 "^x-powers,.*": 1395 1387 description: X-Powers 1388 1388 + "^xen,.*": 1389 1389 + description: Xen Hypervisor 1396 1390 "^xes,.*": 1397 1391 description: Extreme Engineering Solutions (X-ES) 1398 1392 "^xiaomi,.*":

+2

Documentation/devicetree/bindings/virtio/mmio.yaml

reviewed

··· 20 20 reg: 21 21 maxItems: 1 22 22 23 23 + dma-coherent: true 24 24 + 23 25 interrupts: 24 26 maxItems: 1 25 27

+1 -7

Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml

reviewed

··· 29 29 clocks: 30 30 maxItems: 1 31 31 32 32 - assigned-clocks: 33 33 - maxItems: 1 34 34 - 35 35 - assigned-clocks-parents: 36 36 - maxItems: 1 37 37 - 38 32 timeout-sec: true 39 33 40 34 required: ··· 50 56 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 51 57 clocks = <&pcc2 IMX7ULP_CLK_WDG1>; 52 58 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>; 53 53 - assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; 59 59 + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; 54 60 timeout-sec = <40>; 55 61 }; 56 62

+11 -17

Documentation/devicetree/bindings/writing-schema.rst

reviewed

··· 118 118 binding documents and validate DTS files using the DT schema. The DT schema 119 119 project can be installed with pip:: 120 120 121 121 - pip3 install git+https://github.com/devicetree-org/dt-schema.git@master 121 121 + pip3 install dtschema 122 122 + 123 123 + Note that 'dtschema' installation requires 'swig' and Python development files 124 124 + installed first. On Debian/Ubuntu systems:: 125 125 + 126 126 + apt install swig python3-dev 122 127 123 128 Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be 124 129 installed. Ensure they are in your PATH (~/.local/bin by default). 125 125 - 126 126 - dtc must also be built with YAML output support enabled. This requires that 127 127 - libyaml and its headers be installed on the host system. For some distributions 128 128 - that involves installing the development package, such as: 129 129 - 130 130 - Debian:: 131 131 - 132 132 - apt-get install libyaml-dev 133 133 - 134 134 - Fedora:: 135 135 - 136 136 - dnf -y install libyaml-devel 137 130 138 131 Running checks 139 132 ~~~~~~~~~~~~~~ ··· 150 157 151 158 make dt_binding_check dtbs_check 152 159 153 153 - It is also possible to run checks with a single schema file by setting the 154 154 - ``DT_SCHEMA_FILES`` variable to a specific schema file. 160 160 + It is also possible to run checks with a subset of matching schema files by 161 161 + setting the ``DT_SCHEMA_FILES`` variable to a specific schema file or pattern. 155 162 156 163 :: 157 164 158 158 - make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/trivial-devices.yaml 159 159 - make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/trivial-devices.yaml 165 165 + make dt_binding_check DT_SCHEMA_FILES=trivial-devices.yaml 166 166 + make dt_binding_check DT_SCHEMA_FILES=/gpio/ 167 167 + make dtbs_check DT_SCHEMA_FILES=trivial-devices.yaml 160 168 161 169 162 170 json-schema Resources

+24 -3

Documentation/devicetree/of_unittest.rst

reviewed

··· 24 24 most of the device drivers in various use cases. 25 25 26 26 27 27 - 2. Test-data 27 27 + 2. Verbose Output (EXPECT) 28 28 + ========================== 29 29 + 30 30 + If unittest detects a problem it will print a warning or error message to 31 31 + the console. Unittest also triggers warning and error messages from other 32 32 + kernel code as a result of intentionally bad unittest data. This has led 33 33 + to confusion as to whether the triggered messages are an expected result 34 34 + of a test or whether there is a real problem that is independent of unittest. 35 35 + 36 36 + 'EXPECT \ : text' (begin) and 'EXPECT / : text' (end) messages have been 37 37 + added to unittest to report that a warning or error is expected. The 38 38 + begin is printed before triggering the warning or error, and the end is 39 39 + printed after triggering the warning or error. 40 40 + 41 41 + The EXPECT messages result in very noisy console messages that are difficult 42 42 + to read. The script scripts/dtc/of_unittest_expect was created to filter 43 43 + this verbosity and highlight mismatches between triggered warnings and 44 44 + errors vs expected warnings and errors. More information is available 45 45 + from 'scripts/dtc/of_unittest_expect --help'. 46 46 + 47 47 + 48 48 + 3. Test-data 28 49 ============ 29 50 30 51 The Device Tree Source file (drivers/of/unittest-data/testcases.dts) contains ··· 77 56 linked into the kernel image. 78 57 79 58 80 80 - 2.1. Adding the test data 59 59 + 3.1. Adding the test data 81 60 ------------------------- 82 61 83 62 Un-flattened device tree structure: ··· 212 191 update_node_properties(). 213 192 214 193 215 215 - 2.2. Removing the test data 194 194 + 3.2. Removing the test data 216 195 --------------------------- 217 196 218 197 Once the test case execution is complete, selftest_data_remove is called in

+9 -1

MAINTAINERS

reviewed

··· 2510 2510 F: Documentation/devicetree/bindings/arm/rda.yaml 2511 2511 F: Documentation/devicetree/bindings/gpio/gpio-rda.yaml 2512 2512 F: Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt 2513 2513 - F: Documentation/devicetree/bindings/serial/rda,8810pl-uart.txt 2513 2513 + F: Documentation/devicetree/bindings/serial/rda,8810pl-uart.yaml 2514 2514 F: Documentation/devicetree/bindings/timer/rda,8810pl-timer.txt 2515 2515 F: arch/arm/boot/dts/rda8810pl-* 2516 2516 F: drivers/clocksource/timer-rda.c ··· 6444 6444 S: Supported 6445 6445 T: git git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git 6446 6446 F: Documentation/devicetree/bindings/display/exynos/ 6447 6447 + F: Documentation/devicetree/bindings/display/samsung/ 6447 6448 F: drivers/gpu/drm/exynos/ 6448 6449 F: include/uapi/drm/exynos_drm.h 6449 6450 ··· 14557 14556 14558 14557 OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS 14559 14558 M: Rob Herring <robh+dt@kernel.org> 14559 14559 + M: Krzysztof Kozlowski <krzk+dt@kernel.org> 14560 14560 L: devicetree@vger.kernel.org 14561 14561 S: Maintained 14562 14562 C: irc://irc.libera.chat/devicetree ··· 19905 19903 T: git git://linuxtv.org/media_tree.git 19906 19904 F: drivers/media/pci/tw686x/ 19907 19905 19906 19906 + U-BOOT ENVIRONMENT VARIABLES 19907 19907 + M: Rafał Miłecki <rafal@milecki.pl> 19908 19908 + S: Maintained 19909 19909 + F: Documentation/devicetree/bindings/nvmem/u-boot,env.yaml 19910 19910 + 19908 19911 UACCE ACCELERATOR FRAMEWORK 19909 19912 M: Zhangfei Gao <zhangfei.gao@linaro.org> 19910 19913 M: Zhou Wang <wangzhou1@hisilicon.com> ··· 20012 20005 R: Avri Altman <avri.altman@wdc.com> 20013 20006 L: linux-scsi@vger.kernel.org 20014 20007 S: Supported 20008 20008 + F: Documentation/devicetree/bindings/ufs/ 20015 20009 F: Documentation/scsi/ufs.rst 20016 20010 F: drivers/scsi/ufs/ 20017 20011

-54

drivers/of/base.c

reviewed

··· 16 16 17 17 #define pr_fmt(fmt) "OF: " fmt 18 18 19 19 - #include <linux/bitmap.h> 20 19 #include <linux/console.h> 21 20 #include <linux/ctype.h> 22 21 #include <linux/cpu.h> ··· 1990 1991 return id; 1991 1992 } 1992 1993 EXPORT_SYMBOL_GPL(of_alias_get_id); 1993 1993 - 1994 1994 - /** 1995 1995 - * of_alias_get_alias_list - Get alias list for the given device driver 1996 1996 - * @matches: Array of OF device match structures to search in 1997 1997 - * @stem: Alias stem of the given device_node 1998 1998 - * @bitmap: Bitmap field pointer 1999 1999 - * @nbits: Maximum number of alias IDs which can be recorded in bitmap 2000 2000 - * 2001 2001 - * The function travels the lookup table to record alias ids for the given 2002 2002 - * device match structures and alias stem. 2003 2003 - * 2004 2004 - * Return: 0 or -ENOSYS when !CONFIG_OF or 2005 2005 - * -EOVERFLOW if alias ID is greater then allocated nbits 2006 2006 - */ 2007 2007 - int of_alias_get_alias_list(const struct of_device_id *matches, 2008 2008 - const char *stem, unsigned long *bitmap, 2009 2009 - unsigned int nbits) 2010 2010 - { 2011 2011 - struct alias_prop *app; 2012 2012 - int ret = 0; 2013 2013 - 2014 2014 - /* Zero bitmap field to make sure that all the time it is clean */ 2015 2015 - bitmap_zero(bitmap, nbits); 2016 2016 - 2017 2017 - mutex_lock(&of_mutex); 2018 2018 - pr_debug("%s: Looking for stem: %s\n", __func__, stem); 2019 2019 - list_for_each_entry(app, &aliases_lookup, link) { 2020 2020 - pr_debug("%s: stem: %s, id: %d\n", 2021 2021 - __func__, app->stem, app->id); 2022 2022 - 2023 2023 - if (strcmp(app->stem, stem) != 0) { 2024 2024 - pr_debug("%s: stem comparison didn't pass %s\n", 2025 2025 - __func__, app->stem); 2026 2026 - continue; 2027 2027 - } 2028 2028 - 2029 2029 - if (of_match_node(matches, app->np)) { 2030 2030 - pr_debug("%s: Allocated ID %d\n", __func__, app->id); 2031 2031 - 2032 2032 - if (app->id >= nbits) { 2033 2033 - pr_warn("%s: ID %d >= than bitmap field %d\n", 2034 2034 - __func__, app->id, nbits); 2035 2035 - ret = -EOVERFLOW; 2036 2036 - } else { 2037 2037 - set_bit(app->id, bitmap); 2038 2038 - } 2039 2039 - } 2040 2040 - } 2041 2041 - mutex_unlock(&of_mutex); 2042 2042 - 2043 2043 - return ret; 2044 2044 - } 2045 2045 - EXPORT_SYMBOL_GPL(of_alias_get_alias_list); 2046 1994 2047 1995 /** 2048 1996 * of_alias_get_highest_id - Get highest alias id for the given stem

+1 -1

drivers/of/unittest.c

reviewed

··· 44 44 pr_err("FAIL %s():%i " fmt, __func__, __LINE__, ##__VA_ARGS__); \ 45 45 } else { \ 46 46 unittest_results.passed++; \ 47 47 - pr_debug("pass %s():%i\n", __func__, __LINE__); \ 47 47 + pr_info("pass %s():%i\n", __func__, __LINE__); \ 48 48 } \ 49 49 failed; \ 50 50 })

+1 -1

include/dt-bindings/clock/alphascale,asm9260.h

reviewed

··· 55 55 #define CLKID_AHB_I2S1 45 56 56 #define CLKID_AHB_MAC1 46 57 57 58 58 - /* devider */ 58 58 + /* divider */ 59 59 #define CLKID_SYS_CPU 47 60 60 #define CLKID_SYS_AHB 48 61 61 #define CLKID_SYS_I2S0M 49

+1 -1

include/dt-bindings/clock/axis,artpec6-clkctrl.h

reviewed

··· 2 2 /* 3 3 * ARTPEC-6 clock controller indexes 4 4 * 5 5 - * Copyright 2016 Axis Comunications AB. 5 5 + * Copyright 2016 Axis Communications AB. 6 6 */ 7 7 8 8 #ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H

+1 -2

include/dt-bindings/clock/boston-clock.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 1 2 /* 2 3 * Copyright (C) 2016 Imagination Technologies 3 3 - * 4 4 - * SPDX-License-Identifier: GPL-2.0 5 4 */ 6 5 7 6 #ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__

+2 -2

include/dt-bindings/clock/marvell,mmp2.h

reviewed

··· 32 32 #define MMP2_CLK_I2S0 31 33 33 #define MMP2_CLK_I2S1 32 34 34 35 35 - /* apb periphrals */ 35 35 + /* apb peripherals */ 36 36 #define MMP2_CLK_TWSI0 60 37 37 #define MMP2_CLK_TWSI1 61 38 38 #define MMP2_CLK_TWSI2 62 ··· 60 60 #define MMP3_CLK_THERMAL2 84 61 61 #define MMP3_CLK_THERMAL3 85 62 62 63 63 - /* axi periphrals */ 63 63 + /* axi peripherals */ 64 64 #define MMP2_CLK_SDH0 101 65 65 #define MMP2_CLK_SDH1 102 66 66 #define MMP2_CLK_SDH2 103

+2 -2

include/dt-bindings/clock/marvell,pxa168.h

reviewed

··· 23 23 #define PXA168_CLK_UART_PLL 27 24 24 #define PXA168_CLK_USB_PLL 28 25 25 26 26 - /* apb periphrals */ 26 26 + /* apb peripherals */ 27 27 #define PXA168_CLK_TWSI0 60 28 28 #define PXA168_CLK_TWSI1 61 29 29 #define PXA168_CLK_TWSI2 62 ··· 45 45 #define PXA168_CLK_SSP4 78 46 46 #define PXA168_CLK_TIMER 79 47 47 48 48 - /* axi periphrals */ 48 48 + /* axi peripherals */ 49 49 #define PXA168_CLK_DFC 100 50 50 #define PXA168_CLK_SDH0 101 51 51 #define PXA168_CLK_SDH1 102

+2 -2

include/dt-bindings/clock/marvell,pxa910.h

reviewed

··· 23 23 #define PXA910_CLK_UART_PLL 27 24 24 #define PXA910_CLK_USB_PLL 28 25 25 26 26 - /* apb periphrals */ 26 26 + /* apb peripherals */ 27 27 #define PXA910_CLK_TWSI0 60 28 28 #define PXA910_CLK_TWSI1 61 29 29 #define PXA910_CLK_TWSI2 62 ··· 43 43 #define PXA910_CLK_TIMER0 76 44 44 #define PXA910_CLK_TIMER1 77 45 45 46 46 - /* axi periphrals */ 46 46 + /* axi peripherals */ 47 47 #define PXA910_CLK_DFC 100 48 48 #define PXA910_CLK_SDH0 101 49 49 #define PXA910_CLK_SDH1 102

+1 -1

include/dt-bindings/clock/nuvoton,npcm7xx-clock.h

reviewed

··· 1 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 2 /* 3 3 * Nuvoton NPCM7xx Clock Generator binding 4 4 - * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk 4 4 + * clock binding number for all clocks supported by nuvoton,npcm7xx-clk 5 5 * 6 6 * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com 7 7 *

+2 -2

include/dt-bindings/clock/stm32fx-clock.h

reviewed

··· 7 7 */ 8 8 9 9 /* 10 10 - * List of clocks wich are not derived from system clock (SYSCLOCK) 10 10 + * List of clocks which are not derived from system clock (SYSCLOCK) 11 11 * 12 12 * The index of these clocks is the secondary index of DT bindings 13 13 - * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt) 13 13 + * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt) 14 14 * 15 15 * e.g: 16 16 <assigned-clocks = <&rcc 1 CLK_LSE>;

+1 -1

include/dt-bindings/clock/stratix10-clock.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: GPL-2.0 */ 1 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 /* 3 3 * Copyright (C) 2017, Intel Corporation 4 4 */

-10

include/linux/of.h

reviewed

··· 388 388 extern void of_alias_scan(void * (*dt_alloc)(u64 size, u64 align)); 389 389 extern int of_alias_get_id(struct device_node *np, const char *stem); 390 390 extern int of_alias_get_highest_id(const char *stem); 391 391 - extern int of_alias_get_alias_list(const struct of_device_id *matches, 392 392 - const char *stem, unsigned long *bitmap, 393 393 - unsigned int nbits); 394 391 395 392 extern int of_machine_is_compatible(const char *compat); 396 393 ··· 759 762 } 760 763 761 764 static inline int of_alias_get_highest_id(const char *stem) 762 762 - { 763 763 - return -ENOSYS; 764 764 - } 765 765 - 766 766 - static inline int of_alias_get_alias_list(const struct of_device_id *matches, 767 767 - const char *stem, unsigned long *bitmap, 768 768 - unsigned int nbits) 769 765 { 770 766 return -ENOSYS; 771 767 }

+9 -16

scripts/Makefile.lib

reviewed

··· 87 87 88 88 always-y += $(dtb-y) 89 89 90 90 - ifneq ($(CHECK_DTBS),) 91 91 - always-y += $(patsubst %.dtb,%.dt.yaml, $(real-dtb-y)) 92 92 - always-y += $(patsubst %.dtbo,%.dt.yaml, $(real-dtb-y)) 93 93 - endif 94 94 - 95 90 # Add subdir path 96 91 97 92 extra-y := $(addprefix $(obj)/,$(extra-y)) ··· 342 347 -d $(depfile).dtc.tmp $(dtc-tmp) ; \ 343 348 cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) 344 349 345 345 - $(obj)/%.dtb: $(src)/%.dts $(DTC) FORCE 346 346 - $(call if_changed_dep,dtc) 347 347 - 348 348 - $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE 349 349 - $(call if_changed_dep,dtc) 350 350 - 351 350 quiet_cmd_fdtoverlay = DTOVL $@ 352 351 cmd_fdtoverlay = $(objtree)/scripts/dtc/fdtoverlay -o $@ -i $(real-prereqs) 353 352 ··· 349 360 $(call if_changed,fdtoverlay) 350 361 $(call multi_depend, $(multi-dtb-y), .dtb, -dtbs) 351 362 363 363 + ifneq ($(CHECK_DTBS)$(CHECK_DT_BINDING),) 352 364 DT_CHECKER ?= dt-validate 353 353 - DT_CHECKER_FLAGS ?= $(if $(DT_SCHEMA_FILES),,-m) 365 365 + DT_CHECKER_FLAGS ?= $(if $(DT_SCHEMA_FILES),-l $(DT_SCHEMA_FILES),-m) 354 366 DT_BINDING_DIR := Documentation/devicetree/bindings 355 355 - # DT_TMP_SCHEMA may be overridden from Documentation/devicetree/bindings/Makefile 356 356 - DT_TMP_SCHEMA ?= $(objtree)/$(DT_BINDING_DIR)/processed-schema.json 367 367 + DT_TMP_SCHEMA := $(objtree)/$(DT_BINDING_DIR)/processed-schema.json 357 368 358 369 quiet_cmd_dtb_check = CHECK $@ 359 359 - cmd_dtb_check = $(DT_CHECKER) $(DT_CHECKER_FLAGS) -u $(srctree)/$(DT_BINDING_DIR) -p $(DT_TMP_SCHEMA) $@ 370 370 + cmd_dtb_check = $(DT_CHECKER) $(DT_CHECKER_FLAGS) -u $(srctree)/$(DT_BINDING_DIR) -p $(DT_TMP_SCHEMA) $@ || true 371 371 + endif 360 372 361 373 define rule_dtc 362 374 $(call cmd_and_fixdep,dtc) 363 375 $(call cmd,dtb_check) 364 376 endef 365 377 366 366 - $(obj)/%.dt.yaml: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE 378 378 + $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE 367 379 $(call if_changed_rule,dtc) 380 380 + 381 381 + $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE 382 382 + $(call if_changed_dep,dtc) 368 383 369 384 dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) 370 385

-13

scripts/dtc/Makefile

reviewed

··· 17 17 18 18 # Source files need to get at the userspace version of libfdt_env.h to compile 19 19 HOST_EXTRACFLAGS += -I $(srctree)/$(src)/libfdt 20 20 - 21 21 - ifeq ($(shell pkg-config --exists yaml-0.1 2>/dev/null && echo yes),) 22 22 - ifneq ($(CHECK_DT_BINDING)$(CHECK_DTBS),) 23 23 - $(error dtc needs libyaml for DT schema validation support. \ 24 24 - Install the necessary libyaml development package.) 25 25 - endif 26 20 HOST_EXTRACFLAGS += -DNO_YAML 27 27 - else 28 28 - dtc-objs += yamltree.o 29 29 - # To include <yaml.h> installed in a non-default path 30 30 - HOSTCFLAGS_yamltree.o := $(shell pkg-config --cflags yaml-0.1) 31 31 - # To link libyaml installed in a non-default path 32 32 - HOSTLDLIBS_dtc := $(shell pkg-config yaml-0.1 --libs) 33 33 - endif 34 21 35 22 # Generated files need one more search path to include headers in source tree 36 23 HOSTCFLAGS_dtc-lexer.lex.o := -I $(srctree)/$(src)

+408

scripts/dtc/of_unittest_expect

reviewed

··· 1 1 + #!/usr/bin/perl 2 2 + # SPDX-License-Identifier: GPL-2.0 3 3 + # 4 4 + # Copyright 2020, 2022 Sony Corporation 5 5 + # 6 6 + # Author: Frank Rowand 7 7 + 8 8 + # This program is meant to be an aid to reading the verbose output of 9 9 + # on the console log that results from executing the Linux kernel 10 10 + # devicetree unittest (drivers/of/unitest.c). 11 11 + 12 12 + $VUFX = "220201a"; 13 13 + 14 14 + use strict 'refs'; 15 15 + use strict subs; 16 16 + 17 17 + use Getopt::Long; 18 18 + use Text::Wrap; 19 19 + 20 20 + # strip off everything before final "/" 21 21 + (undef, $script_name) = split(/^.*\//, $0); 22 22 + 23 23 + # following /usr/include/sysexits.h 24 24 + $EX_OK=0; 25 25 + $EX_USAGE=64; 26 26 + 27 27 + 28 28 + #______________________________________________________________________________ 29 29 + sub compare { 30 30 + my ($expect, $got) = @_; 31 31 + my $expect_next; 32 32 + my $expect_next_lit; 33 33 + my $got_next; 34 34 + my $type; 35 35 + 36 36 + while ($expect) { 37 37 + 38 38 + ($expect_next, $type) = split(/<</, $expect); 39 39 + ($type) = split(/>>/, $type); 40 40 + $expect =~ s/^.*?>>//; # '?' is non-greedy, minimal match 41 41 + 42 42 + # literal, ignore all metacharacters when used in a regex 43 43 + $expect_next_lit = quotemeta($expect_next); 44 44 + 45 45 + $got_next = $got; 46 46 + $got_next =~ s/^($expect_next_lit).*/\1/; 47 47 + $got =~ s/^$expect_next_lit//; 48 48 + 49 49 + if ($expect_next ne $got_next) { 50 50 + return 0; 51 51 + } 52 52 + 53 53 + if ($type eq "int") { 54 54 + if ($got =~ /^[+-]*[0-9]+/) { 55 55 + $got =~ s/^[+-]*[0-9]+//; 56 56 + } else { 57 57 + return 0; 58 58 + } 59 59 + } elsif ($type eq "hex") { 60 60 + if ($got =~ /^(0x)*[0-9a-f]+/) { 61 61 + $got =~ s/^(0x)*[0-9a-f]+//; 62 62 + } else { 63 63 + return 0; 64 64 + } 65 65 + } elsif ($type eq "") { 66 66 + if ($expect_next ne $got_next) { 67 67 + return 0; 68 68 + } else { 69 69 + return 1; 70 70 + } 71 71 + } else { 72 72 + $internal_err++; 73 73 + print "** ERROR: special pattern not recognized: <<$type>>, CONSOLE_LOG line: $.\n"; 74 74 + return 0; 75 75 + } 76 76 + 77 77 + } 78 78 + 79 79 + # should not get here 80 80 + $internal_err++; 81 81 + print "** ERROR: $script_name internal error, at end of compare(), CONSOLE_LOG line: $.\n"; 82 82 + 83 83 + return 0; 84 84 + } 85 85 + 86 86 + 87 87 + #______________________________________________________________________________ 88 88 + sub usage { 89 89 + 90 90 + # ***** when editing, be careful to not put tabs in the string printed: 91 91 + 92 92 + print STDERR 93 93 + " 94 94 + usage: 95 95 + 96 96 + $script_name CONSOLE_LOG 97 97 + 98 98 + -h print program usage 99 99 + --help print program usage 100 100 + --hide-expect suppress output of EXPECTed lines 101 101 + --line-num report line number of CONSOLE_LOG 102 102 + --no-expect-stats do not report EXPECT statistics 103 103 + --no-strip-ts do not strip leading console timestamps 104 104 + --verbose do not suppress EXPECT begin and end lines 105 105 + --version print program version and exit 106 106 + 107 107 + 108 108 + Process a console log for EXPECTed test related messages to either 109 109 + highlight expected devicetree unittest related messages or suppress 110 110 + the messages. Leading console timestamps will be stripped. 111 111 + 112 112 + Various unittests may trigger kernel messages from outside the 113 113 + unittest code. The unittest annotates that it expects the message 114 114 + to occur with an 'EXPECT \\ : text' (begin) before triggering the 115 115 + message, and an 'EXPECT / : text' (end) after triggering the message. 116 116 + 117 117 + If an expected message does not occur, that will be reported. 118 118 + 119 119 + For each expected message, the 'EXPECT \\ : text' (begin) and 120 120 + 'EXPECT / : text' (end), 'text' will contain the message text. 121 121 + 122 122 + If 'EXPECT \\' (begin) and 'EXPECT /' (end) lines do not contain 123 123 + matching 'text', that will be reported. 124 124 + 125 125 + If EXPECT lines are nested, 'EXPECT /' (end) lines must be in the 126 126 + reverse order of the corresponding 'EXPECT \\' (begin) lines. 127 127 + 128 128 + 'EXPECT \\ : text' (begin) and 'EXPECT / : text' (end) lines can 129 129 + contain special patterns in 'text': 130 130 + 131 131 + <<int>> matches: [+-]*[0-9]+ 132 132 + <<hex>> matches: (0x)*[0-9a-f]+ 133 133 + 134 134 + 'EXPECT \\' (begin) and 'EXPECT /' (end) lines are suppressed. 135 135 + 136 136 + A prefix is added to every line of output: 137 137 + 138 138 + 'ok ' Line matches an enclosing EXPECT begin/end pair 139 139 + 140 140 + '** ' Line reports $script_name warning or error 141 141 + 142 142 + '-> ' Line reports start or end of the unittests 143 143 + 144 144 + '>> ' Line reports a unittest test FAIL 145 145 + 146 146 + ' ' Lines that are not otherwise prefixed 147 147 + 148 148 + Issues detected in CONSOLE_LOG are reported to STDOUT, not to STDERR. 149 149 + 150 150 + Known Issues: 151 151 + 152 152 + --line-num causes the CONSOLE_LOG line number to be printed in 4 columns. 153 153 + If CONSOLE_LOG contains more than 9999 lines then more columns will be 154 154 + used to report the line number for lines greater than 9999 (eg for 155 155 + lines 10000 - 99999, 5 columns will be used). 156 156 + "; 157 157 + 158 158 + return {}; 159 159 + } 160 160 + 161 161 + #______________________________________________________________________________ 162 162 + #______________________________________________________________________________ 163 163 + 164 164 + if (!GetOptions( 165 165 + "h" => \$help, 166 166 + "help" => \$help, 167 167 + "hide-expect" => \$hide_expect, 168 168 + "line-num" => \$print_line_num, 169 169 + "no-expect-stats" => \$no_expect_stats, 170 170 + "no-strip-ts" => \$no_strip_ts, 171 171 + "verbose" => \$verbose, 172 172 + "version" => \$version, 173 173 + )) { 174 174 + print STDERR "\n"; 175 175 + print STDERR "ERROR processing command line options\n"; 176 176 + print STDERR "\n"; 177 177 + print STDERR "For help, type '$script_name --help'\n"; 178 178 + print STDERR "\n"; 179 179 + 180 180 + exit $EX_OK; 181 181 + } 182 182 + 183 183 + 184 184 + if ($no_strip_ts) { 185 185 + $strip_ts = 1; 186 186 + $no_strip_ts = 0; 187 187 + } else { 188 188 + $strip_ts = 0; 189 189 + $no_strip_ts = 1; 190 190 + } 191 191 + 192 192 + 193 193 + # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 194 194 + if ($help){ 195 195 + 196 196 + &usage; 197 197 + 198 198 + exit $EX_OK; 199 199 + } 200 200 + 201 201 + 202 202 + # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 203 203 + 204 204 + if ($version) { 205 205 + print STDERR "\n$script_name $VUFX\n\n"; 206 206 + print STDERR "\n"; 207 207 + 208 208 + exit $EX_OK; 209 209 + } 210 210 + 211 211 + 212 212 + # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 213 213 + if ($#ARGV != 0) { 214 214 + 215 215 + # Limit input files to exactly one. 216 216 + # 217 217 + # 'while ($line = <ARGV>) {' in the code below supports multiple file 218 218 + # names on the command line, but the EXPECT statistics are reported 219 219 + # once for all input - it is not an expected use case to generate one 220 220 + # set of statistics for multiple input files. 221 221 + 222 222 + print STDERR "\n"; 223 223 + print STDERR "Required arguments: CONSOLE_LOG\n"; 224 224 + print STDERR "\n"; 225 225 + 226 226 + exit $EX_USAGE; 227 227 + } 228 228 + 229 229 + 230 230 + #______________________________________________________________________________ 231 231 + 232 232 + # Patterns to match 'EXPECT \ : ' (begin) and 'EXPECT / : ' (end) 233 233 + # 234 234 + # $exp_* are used as regex match patterns, 235 235 + # so '\\\\' in $exp_begin matches a single '\' 236 236 + # quotemeta() does not do the right thing in this case 237 237 + # 238 238 + # $pr_fmt is the prefix that unittest prints for every message 239 239 + 240 240 + $pr_fmt = "### dt-test ### "; 241 241 + $exp_begin = "${pr_fmt}EXPECT \\\\ : "; 242 242 + $exp_end = "${pr_fmt}EXPECT / : "; 243 243 + 244 244 + 245 245 + $line_num = ""; 246 246 + $timestamp = ""; 247 247 + 248 248 + LINE: 249 249 + while ($line = <ARGV>) { 250 250 + 251 251 + chomp $line; 252 252 + 253 253 + $prefix = " "; ## 2 characters 254 254 + 255 255 + 256 256 + if ($strip_ts) { 257 257 + 258 258 + $timestamp = $line; 259 259 + 260 260 + if ($timestamp =~ /^\[\s*[0-9]+\.[0-9]*\] /) { 261 261 + ($timestamp, $null) = split(/]/, $line); 262 262 + $timestamp = $timestamp . "] "; 263 263 + 264 264 + } else { 265 265 + $timestamp = ""; 266 266 + } 267 267 + } 268 268 + 269 269 + $line =~ s/^\[\s*[0-9]+\.[0-9]*\] //; 270 270 + 271 271 + 272 272 + # ----- find EXPECT begin 273 273 + 274 274 + if ($line =~ /^\s*$exp_begin/) { 275 275 + $data = $line; 276 276 + $data =~ s/^\s*$exp_begin//; 277 277 + push @begin, $data; 278 278 + 279 279 + if ($verbose) { 280 280 + if ($print_line_num) { 281 281 + $line_num = sprintf("%4s ", $.); 282 282 + } 283 283 + printf "%s %s%s%s\n", $prefix, $line_num, $timestamp, $line; 284 284 + } 285 285 + 286 286 + next LINE; 287 287 + } 288 288 + 289 289 + 290 290 + # ----- find EXPECT end 291 291 + 292 292 + if ($line =~ /^\s*$exp_end/) { 293 293 + $data = $line; 294 294 + $data =~ s/^\s*$exp_end//; 295 295 + 296 296 + if ($verbose) { 297 297 + if ($print_line_num) { 298 298 + $line_num = sprintf("%4s ", $.); 299 299 + } 300 300 + printf "%s %s%s%s\n", $prefix, $line_num, $timestamp, $line; 301 301 + } 302 302 + 303 303 + $found = 0; 304 304 + $no_begin = 0; 305 305 + if (@found_or_begin > 0) { 306 306 + $begin = pop @found_or_begin; 307 307 + if (compare($data, $begin)) { 308 308 + $found = 1; 309 309 + } 310 310 + } elsif (@begin > 0) { 311 311 + $begin = pop @begin; 312 312 + } else { 313 313 + $no_begin = 1; 314 314 + } 315 315 + 316 316 + if ($no_begin) { 317 317 + 318 318 + $expect_missing_begin++; 319 319 + print "** ERROR: EXPECT end without any EXPECT begin:\n"; 320 320 + print " end ---> $line\n"; 321 321 + 322 322 + } elsif (! $found) { 323 323 + 324 324 + if ($print_line_num) { 325 325 + $line_num = sprintf("%4s ", $.); 326 326 + } 327 327 + 328 328 + $expect_not_found++; 329 329 + printf "** %s%s$script_name WARNING - not found ---> %s\n", 330 330 + $line_num, $timestamp, $data; 331 331 + 332 332 + } elsif (! compare($data, $begin)) { 333 333 + 334 334 + $expect_missing_end++; 335 335 + print "** ERROR: EXPECT end does not match EXPECT begin:\n"; 336 336 + print " begin -> $begin\n"; 337 337 + print " end ---> $line\n"; 338 338 + 339 339 + } else { 340 340 + 341 341 + $expect_found++; 342 342 + 343 343 + } 344 344 + 345 345 + next LINE; 346 346 + } 347 347 + 348 348 + 349 349 + # ----- not an EXPECT line 350 350 + 351 351 + if (($line =~ /^${pr_fmt}start of unittest - you will see error messages$/) || 352 352 + ($line =~ /^${pr_fmt}end of unittest - [0-9]+ passed, [0-9]+ failed$/ ) ) { 353 353 + $prefix = "->"; # 2 characters 354 354 + } elsif ($line =~ /^${pr_fmt}FAIL /) { 355 355 + $unittest_fail++; 356 356 + $prefix = ">>"; # 2 characters 357 357 + } 358 358 + 359 359 + $found = 0; 360 360 + foreach $begin (@begin) { 361 361 + if (compare($begin, $line)) { 362 362 + $found = 1; 363 363 + last; 364 364 + } 365 365 + } 366 366 + 367 367 + if ($found) { 368 368 + $begin = shift @begin; 369 369 + while (! compare($begin, $line)) { 370 370 + push @found_or_begin, $begin; 371 371 + $begin = shift @begin; 372 372 + } 373 373 + push @found_or_begin, $line; 374 374 + 375 375 + if ($hide_expect) { 376 376 + $suppress_line = 1; 377 377 + next LINE; 378 378 + } 379 379 + $prefix = "ok"; # 2 characters 380 380 + } 381 381 + 382 382 + 383 383 + if ($print_line_num) { 384 384 + $line_num = sprintf("%4s ", $.); 385 385 + } 386 386 + 387 387 + printf "%s %s%s%s\n", $prefix, $line_num, $timestamp, $line; 388 388 + } 389 389 + 390 390 + if (! $no_expect_stats) { 391 391 + print "\n"; 392 392 + print "** EXPECT statistics:\n"; 393 393 + print "**\n"; 394 394 + printf "** EXPECT found : %4i\n", $expect_found; 395 395 + printf "** EXPECT not found : %4i\n", $expect_not_found; 396 396 + printf "** missing EXPECT begin : %4i\n", $expect_missing_begin; 397 397 + printf "** missing EXPECT end : %4i\n", $expect_missing_end; 398 398 + printf "** unittest FAIL : %4i\n", $unittest_fail; 399 399 + printf "** internal error : %4i\n", $internal_err; 400 400 + } 401 401 + 402 402 + if (@begin) { 403 403 + print "** ERROR: EXPECT begin without any EXPECT end:\n"; 404 404 + print " This list may be misleading.\n"; 405 405 + foreach $begin (@begin) { 406 406 + print " begin ---> $begin\n"; 407 407 + } 408 408 + }

+1 -1

scripts/dtc/update-dtc-source.sh

reviewed

··· 32 32 DTC_LINUX_PATH=`pwd`/scripts/dtc 33 33 34 34 DTC_SOURCE="checks.c data.c dtc.c dtc.h flattree.c fstree.c livetree.c srcpos.c \ 35 35 - srcpos.h treesource.c util.c util.h version_gen.h yamltree.c \ 35 35 + srcpos.h treesource.c util.c util.h version_gen.h \ 36 36 dtc-lexer.l dtc-parser.y" 37 37 LIBFDT_SOURCE="fdt.c fdt.h fdt_addresses.c fdt_empty_tree.c \ 38 38 fdt_overlay.c fdt_ro.c fdt_rw.c fdt_strerror.c fdt_sw.c \