Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2025-01-17' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Final(?) set of fixes for 6.13, I think the holidays finally caught up
with everyone, the misc changes are 2 weeks worth, otherwise amdgpu
and xe are most of it. The largest pieces is a new test so I'm not too
worried about that.
kunit:
- Fix W=1 build for kunit tests
bridge:
- Handle YCbCr420 better in bridge code, with tests
- itee-it6263 error handling fix
amdgpu:
- SMU 13 fix
- DP MST fixes
- DCN 3.5 fix
- PSR fixes
- eDP fix
- VRR fix
- Enforce isolation fixes
- GFX 12 fix
- PSP 14.x fix
xe:
- Add steering info support for GuC register lists
- Add means to wait for reset and synchronous reset
- Make changing ccs_mode a synchronous action
- Add missing mux registers
- Mark ComputeCS read mode as UC on iGPU, unblocking ULLS on iGPU
i915:
- Relax clear color alignment to 64 bytes [fb]
v3d:
- Fix warn when unloading v3d
nouveau:
- Fix cross-device fence handling in nouveau
- Fix backlight regression for macbooks 5,1
vmwgfx:
- Fix BO reservation handling in vmwgfx"
* tag 'drm-fixes-2025-01-17' of https://gitlab.freedesktop.org/drm/kernel: (33 commits)
drm/xe: Mark ComputeCS read mode as UC on iGPU
drm/xe/oa: Add missing VISACTL mux registers
drm/xe: make change ccs_mode a synchronous action
drm/xe: introduce xe_gt_reset and xe_gt_wait_for_reset
drm/xe/guc: Adding steering info support for GuC register lists
drm/bridge: ite-it6263: Prevent error pointer dereference in probe()
drm/v3d: Ensure job pointer is set to NULL after job completion
drm/vmwgfx: Add new keep_resv BO param
drm/vmwgfx: Remove busy_places
drm/vmwgfx: Unreserve BO on error
drm/amdgpu: fix fw attestation for MP0_14_0_{2/3}
drm/amdgpu: always sync the GFX pipe on ctx switch
drm/amdgpu: disable gfxoff with the compute workload on gfx12
drm/amdgpu: Fix Circular Locking Dependency in AMDGPU GFX Isolation
drm/i915/fb: Relax clear color alignment to 64 bytes
drm/amd/display: Disable replay and psr while VRR is enabled
drm/amd/display: Fix PSR-SU not support but still call the amdgpu_dm_psr_enable
nouveau/fence: handle cross device fences properly
drm/tests: connector: Add ycbcr_420_allowed tests
drm/connector: hdmi: Validate supported_formats matches ycbcr_420_allowed
...
+324
-109
+3
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+3
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
···
715
715
void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
716
716
{
717
717
enum amd_powergating_state state = idle ? AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE;
718
-
if (IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 &&
719
-
((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) {
718
+
if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 11 &&
719
+
((adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK) <= 64)) ||
720
+
(IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 12)) {
720
721
pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");
721
722
amdgpu_gfx_off_ctrl(adev, idle);
722
723
} else if ((IP_VERSION_MAJ(amdgpu_ip_version(adev, GC_HWIP, 0)) == 9) &&
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c
···
122
122
if (adev->flags & AMD_IS_APU)
123
123
return 0;
124
124
125
+
if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(14, 0, 2) ||
126
+
amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(14, 0, 3))
127
+
return 0;
128
+
125
129
if (adev->asic_type >= CHIP_SIENNA_CICHLID)
126
130
return 1;
127
131
+10
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+10
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
···
1989
1989
{
1990
1990
struct amdgpu_device *adev = ring->adev;
1991
1991
u32 idx;
1992
+
bool sched_work = false;
1992
1993
1993
1994
if (!adev->gfx.enable_cleaner_shader)
1994
1995
return;
···
2008
2007
mutex_lock(&adev->enforce_isolation_mutex);
2009
2008
if (adev->enforce_isolation[idx]) {
2010
2009
if (adev->kfd.init_complete)
2011
-
amdgpu_gfx_kfd_sch_ctrl(adev, idx, false);
2010
+
sched_work = true;
2012
2011
}
2013
2012
mutex_unlock(&adev->enforce_isolation_mutex);
2013
+
2014
+
if (sched_work)
2015
+
amdgpu_gfx_kfd_sch_ctrl(adev, idx, false);
2014
2016
}
2015
2017
2016
2018
void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring)
2017
2019
{
2018
2020
struct amdgpu_device *adev = ring->adev;
2019
2021
u32 idx;
2022
+
bool sched_work = false;
2020
2023
2021
2024
if (!adev->gfx.enable_cleaner_shader)
2022
2025
return;
···
2036
2031
mutex_lock(&adev->enforce_isolation_mutex);
2037
2032
if (adev->enforce_isolation[idx]) {
2038
2033
if (adev->kfd.init_complete)
2039
-
amdgpu_gfx_kfd_sch_ctrl(adev, idx, true);
2034
+
sched_work = true;
2040
2035
}
2041
2036
mutex_unlock(&adev->enforce_isolation_mutex);
2037
+
2038
+
if (sched_work)
2039
+
amdgpu_gfx_kfd_sch_ctrl(adev, idx, true);
2042
2040
}
2043
2041
2044
2042
/*
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
···
193
193
need_ctx_switch = ring->current_ctx != fence_ctx;
194
194
if (ring->funcs->emit_pipeline_sync && job &&
195
195
((tmp = amdgpu_sync_get_fence(&job->explicit_sync)) ||
196
-
(amdgpu_sriov_vf(adev) && need_ctx_switch) ||
197
-
amdgpu_vm_need_pipeline_sync(ring, job))) {
196
+
need_ctx_switch || amdgpu_vm_need_pipeline_sync(ring, job))) {
197
+
198
198
need_pipe_sync = true;
199
199
200
200
if (tmp)
+30
-11
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+30
-11
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
8896
8896
struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
8897
8897
struct amdgpu_dm_connector *aconn =
8898
8898
(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
8899
+
bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
8899
8900
8900
8901
if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
8901
8902
if (pr->config.replay_supported && !pr->replay_feature_enabled)
···
8923
8922
* adequate number of fast atomic commits to notify KMD
8924
8923
* of update events. See `vblank_control_worker()`.
8925
8924
*/
8926
-
if (acrtc_attach->dm_irq_params.allow_sr_entry &&
8925
+
if (!vrr_active &&
8926
+
acrtc_attach->dm_irq_params.allow_sr_entry &&
8927
8927
#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
8928
8928
!amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
8929
8929
#endif
8930
8930
(current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
8931
8931
if (pr->replay_feature_enabled && !pr->replay_allow_active)
8932
8932
amdgpu_dm_replay_enable(acrtc_state->stream, true);
8933
-
if (psr->psr_version >= DC_PSR_VERSION_SU_1 &&
8933
+
if (psr->psr_version == DC_PSR_VERSION_SU_1 &&
8934
8934
!psr->psr_allow_active && !aconn->disallow_edp_enter_psr)
8935
8935
amdgpu_dm_psr_enable(acrtc_state->stream);
8936
8936
}
···
9102
9100
acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
9103
9101
timestamp_ns;
9104
9102
if (acrtc_state->stream->link->psr_settings.psr_allow_active)
9105
-
amdgpu_dm_psr_disable(acrtc_state->stream);
9103
+
amdgpu_dm_psr_disable(acrtc_state->stream, true);
9106
9104
mutex_unlock(&dm->dc_lock);
9107
9105
}
9108
9106
}
···
9268
9266
bundle->stream_update.abm_level = &acrtc_state->abm_level;
9269
9267
9270
9268
mutex_lock(&dm->dc_lock);
9271
-
if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
9269
+
if ((acrtc_state->update_type > UPDATE_TYPE_FAST) || vrr_active) {
9272
9270
if (acrtc_state->stream->link->replay_settings.replay_allow_active)
9273
9271
amdgpu_dm_replay_disable(acrtc_state->stream);
9274
9272
if (acrtc_state->stream->link->psr_settings.psr_allow_active)
9275
-
amdgpu_dm_psr_disable(acrtc_state->stream);
9273
+
amdgpu_dm_psr_disable(acrtc_state->stream, true);
9276
9274
}
9277
9275
mutex_unlock(&dm->dc_lock);
9278
9276
···
11381
11379
return 0;
11382
11380
}
11383
11381
11382
+
static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev,
11383
+
struct drm_atomic_state *state,
11384
+
struct drm_crtc_state *crtc_state)
11385
+
{
11386
+
struct drm_plane *plane;
11387
+
struct drm_plane_state *new_plane_state, *old_plane_state;
11388
+
11389
+
drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {
11390
+
new_plane_state = drm_atomic_get_plane_state(state, plane);
11391
+
old_plane_state = drm_atomic_get_plane_state(state, plane);
11392
+
11393
+
if (old_plane_state->fb && new_plane_state->fb &&
11394
+
get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb))
11395
+
return true;
11396
+
}
11397
+
11398
+
return false;
11399
+
}
11400
+
11384
11401
/**
11385
11402
* amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
11386
11403
*
···
11597
11576
11598
11577
/* Remove exiting planes if they are modified */
11599
11578
for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {
11600
-
if (old_plane_state->fb && new_plane_state->fb &&
11601
-
get_mem_type(old_plane_state->fb) !=
11602
-
get_mem_type(new_plane_state->fb))
11603
-
lock_and_validation_needed = true;
11604
11579
11605
11580
ret = dm_update_plane_state(dc, state, plane,
11606
11581
old_plane_state,
···
11891
11874
11892
11875
/*
11893
11876
* Only allow async flips for fast updates that don't change
11894
-
* the FB pitch, the DCC state, rotation, etc.
11877
+
* the FB pitch, the DCC state, rotation, mem_type, etc.
11895
11878
*/
11896
-
if (new_crtc_state->async_flip && lock_and_validation_needed) {
11879
+
if (new_crtc_state->async_flip &&
11880
+
(lock_and_validation_needed ||
11881
+
amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) {
11897
11882
drm_dbg_atomic(crtc->dev,
11898
11883
"[CRTC:%d:%s] async flips are only supported for fast updates\n",
11899
11884
crtc->base.id, crtc->name);
+2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
···
697
697
struct drm_dp_mst_port *mst_output_port;
698
698
struct amdgpu_dm_connector *mst_root;
699
699
struct drm_dp_aux *dsc_aux;
700
+
uint32_t mst_local_bw;
701
+
uint16_t vc_full_pbn;
700
702
struct mutex handle_mst_msg_ready;
701
703
702
704
/* TODO see if we can merge with ddc_bus or make a dm_connector */
+16
-9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+16
-9
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
···
30
30
#include "amdgpu_dm.h"
31
31
#include "dc.h"
32
32
#include "amdgpu_securedisplay.h"
33
+
#include "amdgpu_dm_psr.h"
33
34
34
35
static const char *const pipe_crc_sources[] = {
35
36
"none",
···
225
224
226
225
mutex_lock(&adev->dm.dc_lock);
227
226
227
+
/* For PSR1, check that the panel has exited PSR */
228
+
if (stream_state->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
229
+
amdgpu_dm_psr_wait_disable(stream_state);
230
+
228
231
/* Enable or disable CRTC CRC generation */
229
232
if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {
230
233
if (!dc_stream_configure_crc(stream_state->ctx->dc,
···
362
357
363
358
}
364
359
360
+
/*
361
+
* Reading the CRC requires the vblank interrupt handler to be
362
+
* enabled. Keep a reference until CRC capture stops.
363
+
*/
364
+
enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src);
365
+
if (!enabled && enable) {
366
+
ret = drm_crtc_vblank_get(crtc);
367
+
if (ret)
368
+
goto cleanup;
369
+
}
370
+
365
371
#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
366
372
/* Reset secure_display when we change crc source from debugfs */
367
373
amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream);
···
383
367
goto cleanup;
384
368
}
385
369
386
-
/*
387
-
* Reading the CRC requires the vblank interrupt handler to be
388
-
* enabled. Keep a reference until CRC capture stops.
389
-
*/
390
-
enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src);
391
370
if (!enabled && enable) {
392
-
ret = drm_crtc_vblank_get(crtc);
393
-
if (ret)
394
-
goto cleanup;
395
-
396
371
if (dm_is_crc_source_dprx(source)) {
397
372
if (drm_dp_start_crc(aux, crtc)) {
398
373
DRM_DEBUG_DRIVER("dp start crc failed\n");
+2
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+2
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
···
93
93
return rc;
94
94
}
95
95
96
-
bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state)
96
+
bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state)
97
97
{
98
98
return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
99
99
dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
···
142
142
amdgpu_dm_replay_enable(vblank_work->stream, true);
143
143
} else if (vblank_enabled) {
144
144
if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
145
-
amdgpu_dm_psr_disable(vblank_work->stream);
145
+
amdgpu_dm_psr_disable(vblank_work->stream, false);
146
146
} else if (link->psr_settings.psr_feature_enabled &&
147
147
allow_sr_entry && !is_sr_active && !is_crc_window_active) {
148
148
+1
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h
+1
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h
···
37
37
38
38
bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc);
39
39
40
-
bool amdgpu_dm_crtc_vrr_active(struct dm_crtc_state *dm_state);
40
+
bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state);
41
41
42
42
int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc);
43
43
+1
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+1
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
···
3606
3606
/* PSR may write to OTG CRC window control register,
3607
3607
* so close it before starting secure_display.
3608
3608
*/
3609
-
amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream);
3609
+
amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream, true);
3610
3610
3611
3611
spin_lock_irq(&adev_to_drm(adev)->event_lock);
3612
3612
+34
-14
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+34
-14
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
···
155
155
return 0;
156
156
}
157
157
158
+
159
+
static inline void
160
+
amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector)
161
+
{
162
+
aconnector->drm_edid = NULL;
163
+
aconnector->dsc_aux = NULL;
164
+
aconnector->mst_output_port->passthrough_aux = NULL;
165
+
aconnector->mst_local_bw = 0;
166
+
aconnector->vc_full_pbn = 0;
167
+
}
168
+
158
169
static void
159
170
amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
160
171
{
···
193
182
194
183
dc_sink_release(dc_sink);
195
184
aconnector->dc_sink = NULL;
196
-
aconnector->drm_edid = NULL;
197
-
aconnector->dsc_aux = NULL;
198
-
port->passthrough_aux = NULL;
185
+
amdgpu_dm_mst_reset_mst_connector_setting(aconnector);
199
186
}
200
187
201
188
aconnector->mst_status = MST_STATUS_DEFAULT;
···
513
504
514
505
dc_sink_release(aconnector->dc_sink);
515
506
aconnector->dc_sink = NULL;
516
-
aconnector->drm_edid = NULL;
517
-
aconnector->dsc_aux = NULL;
518
-
port->passthrough_aux = NULL;
507
+
amdgpu_dm_mst_reset_mst_connector_setting(aconnector);
519
508
520
509
amdgpu_dm_set_mst_status(&aconnector->mst_status,
521
510
MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
···
1826
1819
struct drm_dp_mst_port *immediate_upstream_port = NULL;
1827
1820
uint32_t end_link_bw = 0;
1828
1821
1829
-
/*Get last DP link BW capability*/
1830
-
if (dp_get_link_current_set_bw(&aconnector->mst_output_port->aux, &end_link_bw)) {
1831
-
if (stream_kbps > end_link_bw) {
1822
+
/*Get last DP link BW capability. Mode shall be supported by Legacy peer*/
1823
+
if (aconnector->mst_output_port->pdt != DP_PEER_DEVICE_DP_LEGACY_CONV &&
1824
+
aconnector->mst_output_port->pdt != DP_PEER_DEVICE_NONE) {
1825
+
if (aconnector->vc_full_pbn != aconnector->mst_output_port->full_pbn) {
1826
+
dp_get_link_current_set_bw(&aconnector->mst_output_port->aux, &end_link_bw);
1827
+
aconnector->vc_full_pbn = aconnector->mst_output_port->full_pbn;
1828
+
aconnector->mst_local_bw = end_link_bw;
1829
+
} else {
1830
+
end_link_bw = aconnector->mst_local_bw;
1831
+
}
1832
+
1833
+
if (end_link_bw > 0 && stream_kbps > end_link_bw) {
1832
1834
DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."
1833
1835
"Mode required bw can't fit into last link\n");
1834
1836
return DC_FAIL_BANDWIDTH_VALIDATE;
···
1851
1835
if (immediate_upstream_port) {
1852
1836
virtual_channel_bw_in_kbps = kbps_from_pbn(immediate_upstream_port->full_pbn);
1853
1837
virtual_channel_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);
1854
-
if (bw_range.min_kbps > virtual_channel_bw_in_kbps) {
1855
-
DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."
1856
-
"Max dsc compression can't fit into MST available bw\n");
1857
-
return DC_FAIL_BANDWIDTH_VALIDATE;
1858
-
}
1838
+
} else {
1839
+
/* For topology LCT 1 case - only one mstb*/
1840
+
virtual_channel_bw_in_kbps = root_link_bw_in_kbps;
1841
+
}
1842
+
1843
+
if (bw_range.min_kbps > virtual_channel_bw_in_kbps) {
1844
+
DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link."
1845
+
"Max dsc compression can't fit into MST available bw\n");
1846
+
return DC_FAIL_BANDWIDTH_VALIDATE;
1859
1847
}
1860
1848
}
1861
1849
+32
-3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+32
-3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
···
201
201
*
202
202
* Return: true if success
203
203
*/
204
-
bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)
204
+
bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait)
205
205
{
206
-
unsigned int power_opt = 0;
207
206
bool psr_enable = false;
208
207
209
208
DRM_DEBUG_DRIVER("Disabling psr...\n");
210
209
211
-
return dc_link_set_psr_allow_active(stream->link, &psr_enable, true, false, &power_opt);
210
+
return dc_link_set_psr_allow_active(stream->link, &psr_enable, wait, false, NULL);
212
211
}
213
212
214
213
/*
···
249
250
}
250
251
251
252
return allow_active;
253
+
}
254
+
255
+
/**
256
+
* amdgpu_dm_psr_wait_disable() - Wait for eDP panel to exit PSR
257
+
* @stream: stream state attached to the eDP link
258
+
*
259
+
* Waits for a max of 500ms for the eDP panel to exit PSR.
260
+
*
261
+
* Return: true if panel exited PSR, false otherwise.
262
+
*/
263
+
bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream)
264
+
{
265
+
enum dc_psr_state psr_state = PSR_STATE0;
266
+
struct dc_link *link = stream->link;
267
+
int retry_count;
268
+
269
+
if (link == NULL)
270
+
return false;
271
+
272
+
for (retry_count = 0; retry_count <= 1000; retry_count++) {
273
+
dc_link_get_psr_state(link, &psr_state);
274
+
if (psr_state == PSR_STATE0)
275
+
break;
276
+
udelay(500);
277
+
}
278
+
279
+
if (retry_count == 1000)
280
+
return false;
281
+
282
+
return true;
252
283
}
+2
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
+2
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
···
34
34
void amdgpu_dm_set_psr_caps(struct dc_link *link);
35
35
void amdgpu_dm_psr_enable(struct dc_stream_state *stream);
36
36
bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
37
-
bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);
37
+
bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait);
38
38
bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
39
39
bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm);
40
+
bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream);
40
41
41
42
#endif /* AMDGPU_DM_AMDGPU_DM_PSR_H_ */
+2
-1
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
+2
-1
drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c
···
63
63
64
64
bool should_use_dmub_lock(struct dc_link *link)
65
65
{
66
-
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
66
+
if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1 ||
67
+
link->psr_settings.psr_version == DC_PSR_VERSION_1)
67
68
return true;
68
69
69
70
if (link->replay_settings.replay_feature_enabled)
+2
-2
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+2
-2
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
···
195
195
.dcn_downspread_percent = 0.5,
196
196
.gpuvm_min_page_size_bytes = 4096,
197
197
.hostvm_min_page_size_bytes = 4096,
198
-
.do_urgent_latency_adjustment = 1,
198
+
.do_urgent_latency_adjustment = 0,
199
199
.urgent_latency_adjustment_fabric_clock_component_us = 0,
200
-
.urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,
200
+
.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
201
201
};
202
202
203
203
void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)
+2
-2
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
+2
-2
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
+6
-6
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+6
-6
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
···
1398
1398
1399
1399
link_hwss->disable_link_output(link, link_res, signal);
1400
1400
link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
1401
-
1402
-
if (signal == SIGNAL_TYPE_EDP &&
1403
-
link->dc->hwss.edp_power_control &&
1404
-
!link->skip_implict_edp_power_control)
1405
-
link->dc->hwss.edp_power_control(link, false);
1406
-
else if (dmcu != NULL && dmcu->funcs->unlock_phy)
1401
+
/*
1402
+
* Add the logic to extract BOTH power up and power down sequences
1403
+
* from enable/disable link output and only call edp panel control
1404
+
* in enable_link_dp and disable_link_dp once.
1405
+
*/
1406
+
if (dmcu != NULL && dmcu->funcs->unlock_phy)
1407
1407
dmcu->funcs->unlock_phy(dmcu);
1408
1408
1409
1409
dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
+6
-5
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+6
-5
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
···
2643
2643
&backend_workload_mask);
2644
2644
2645
2645
/* Add optimizations for SMU13.0.0/10. Reuse the power saving profile */
2646
-
if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) &&
2647
-
((smu->adev->pm.fw_version == 0x004e6601) ||
2648
-
(smu->adev->pm.fw_version >= 0x004e7300))) ||
2649
-
(amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
2650
-
smu->adev->pm.fw_version >= 0x00504500)) {
2646
+
if ((workload_mask & (1 << PP_SMC_POWER_PROFILE_COMPUTE)) &&
2647
+
((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) &&
2648
+
((smu->adev->pm.fw_version == 0x004e6601) ||
2649
+
(smu->adev->pm.fw_version >= 0x004e7300))) ||
2650
+
(amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) &&
2651
+
smu->adev->pm.fw_version >= 0x00504500))) {
2651
2652
workload_type = smu_cmn_to_asic_specific_index(smu,
2652
2653
CMN2ASIC_MAPPING_WORKLOAD,
2653
2654
PP_SMC_POWER_PROFILE_POWERSAVING);
+2
-2
drivers/gpu/drm/bridge/ite-it6263.c
+2
-2
drivers/gpu/drm/bridge/ite-it6263.c
···
845
845
it->lvds_i2c = devm_i2c_new_dummy_device(dev, client->adapter,
846
846
LVDS_INPUT_CTRL_I2C_ADDR);
847
847
if (IS_ERR(it->lvds_i2c))
848
-
dev_err_probe(it->dev, PTR_ERR(it->lvds_i2c),
849
-
"failed to allocate I2C device for LVDS\n");
848
+
return dev_err_probe(it->dev, PTR_ERR(it->lvds_i2c),
849
+
"failed to allocate I2C device for LVDS\n");
850
850
851
851
it->lvds_regmap = devm_regmap_init_i2c(it->lvds_i2c,
852
852
&it6263_lvds_regmap_config);
+6
-2
drivers/gpu/drm/display/drm_bridge_connector.c
+6
-2
drivers/gpu/drm/display/drm_bridge_connector.c
···
459
459
if (connector_type == DRM_MODE_CONNECTOR_Unknown)
460
460
return ERR_PTR(-EINVAL);
461
461
462
-
if (bridge_connector->bridge_hdmi)
462
+
if (bridge_connector->bridge_hdmi) {
463
+
if (!connector->ycbcr_420_allowed)
464
+
supported_formats &= ~BIT(HDMI_COLORSPACE_YUV420);
465
+
463
466
ret = drmm_connector_hdmi_init(drm, connector,
464
467
bridge_connector->bridge_hdmi->vendor,
465
468
bridge_connector->bridge_hdmi->product,
···
471
468
connector_type, ddc,
472
469
supported_formats,
473
470
max_bpc);
474
-
else
471
+
} else {
475
472
ret = drmm_connector_init(drm, connector,
476
473
&drm_bridge_connector_funcs,
477
474
connector_type, ddc);
475
+
}
478
476
if (ret)
479
477
return ERR_PTR(ret);
480
478
+4
drivers/gpu/drm/drm_bridge.c
+4
drivers/gpu/drm/drm_bridge.c
···
207
207
{
208
208
mutex_init(&bridge->hpd_mutex);
209
209
210
+
if (bridge->ops & DRM_BRIDGE_OP_HDMI)
211
+
bridge->ycbcr_420_allowed = !!(bridge->supported_formats &
212
+
BIT(HDMI_COLORSPACE_YUV420));
213
+
210
214
mutex_lock(&bridge_lock);
211
215
list_add_tail(&bridge->list, &bridge_list);
212
216
mutex_unlock(&bridge_lock);
+3
drivers/gpu/drm/drm_connector.c
+3
drivers/gpu/drm/drm_connector.c
···
507
507
if (!supported_formats || !(supported_formats & BIT(HDMI_COLORSPACE_RGB)))
508
508
return -EINVAL;
509
509
510
+
if (connector->ycbcr_420_allowed != !!(supported_formats & BIT(HDMI_COLORSPACE_YUV420)))
511
+
return -EINVAL;
512
+
510
513
if (!(max_bpc == 8 || max_bpc == 10 || max_bpc == 12))
511
514
return -EINVAL;
512
515
+1
-1
drivers/gpu/drm/i915/display/intel_fb.c
+1
-1
drivers/gpu/drm/i915/display/intel_fb.c
···
1694
1694
* arithmetic related to alignment and offset calculation.
1695
1695
*/
1696
1696
if (is_gen12_ccs_cc_plane(&fb->base, i)) {
1697
-
if (IS_ALIGNED(fb->base.offsets[i], PAGE_SIZE))
1697
+
if (IS_ALIGNED(fb->base.offsets[i], 64))
1698
1698
continue;
1699
1699
else
1700
1700
return -EINVAL;
+4
-2
drivers/gpu/drm/nouveau/nouveau_fence.c
+4
-2
drivers/gpu/drm/nouveau/nouveau_fence.c
···
387
387
if (f) {
388
388
struct nouveau_channel *prev;
389
389
bool must_wait = true;
390
+
bool local;
390
391
391
392
rcu_read_lock();
392
393
prev = rcu_dereference(f->channel);
393
-
if (prev && (prev == chan ||
394
-
fctx->sync(f, prev, chan) == 0))
394
+
local = prev && prev->cli->drm == chan->cli->drm;
395
+
if (local && (prev == chan ||
396
+
fctx->sync(f, prev, chan) == 0))
395
397
must_wait = false;
396
398
rcu_read_unlock();
397
399
if (!must_wait)
+1
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c
+1
drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c
+60
drivers/gpu/drm/tests/drm_connector_test.c
+60
drivers/gpu/drm/tests/drm_connector_test.c
···
635
635
KUNIT_EXPECT_LT(test, ret, 0);
636
636
}
637
637
638
+
struct drm_connector_hdmi_init_formats_yuv420_allowed_test {
639
+
unsigned long supported_formats;
640
+
bool yuv420_allowed;
641
+
int expected_result;
642
+
};
643
+
644
+
#define YUV420_ALLOWED_TEST(_formats, _allowed, _result) \
645
+
{ \
646
+
.supported_formats = BIT(HDMI_COLORSPACE_RGB) | (_formats), \
647
+
.yuv420_allowed = _allowed, \
648
+
.expected_result = _result, \
649
+
}
650
+
651
+
static const struct drm_connector_hdmi_init_formats_yuv420_allowed_test
652
+
drm_connector_hdmi_init_formats_yuv420_allowed_tests[] = {
653
+
YUV420_ALLOWED_TEST(BIT(HDMI_COLORSPACE_YUV420), true, 0),
654
+
YUV420_ALLOWED_TEST(BIT(HDMI_COLORSPACE_YUV420), false, -EINVAL),
655
+
YUV420_ALLOWED_TEST(BIT(HDMI_COLORSPACE_YUV422), true, -EINVAL),
656
+
YUV420_ALLOWED_TEST(BIT(HDMI_COLORSPACE_YUV422), false, 0),
657
+
};
658
+
659
+
static void
660
+
drm_connector_hdmi_init_formats_yuv420_allowed_desc(const struct drm_connector_hdmi_init_formats_yuv420_allowed_test *t,
661
+
char *desc)
662
+
{
663
+
sprintf(desc, "supported_formats=0x%lx yuv420_allowed=%d",
664
+
t->supported_formats, t->yuv420_allowed);
665
+
}
666
+
667
+
KUNIT_ARRAY_PARAM(drm_connector_hdmi_init_formats_yuv420_allowed,
668
+
drm_connector_hdmi_init_formats_yuv420_allowed_tests,
669
+
drm_connector_hdmi_init_formats_yuv420_allowed_desc);
670
+
671
+
/*
672
+
* Test that the registration of an HDMI connector succeeds only when
673
+
* the presence of YUV420 in the supported formats matches the value
674
+
* of the ycbcr_420_allowed flag.
675
+
*/
676
+
static void drm_test_connector_hdmi_init_formats_yuv420_allowed(struct kunit *test)
677
+
{
678
+
const struct drm_connector_hdmi_init_formats_yuv420_allowed_test *params;
679
+
struct drm_connector_init_priv *priv = test->priv;
680
+
int ret;
681
+
682
+
params = test->param_value;
683
+
priv->connector.ycbcr_420_allowed = params->yuv420_allowed;
684
+
685
+
ret = drmm_connector_hdmi_init(&priv->drm, &priv->connector,
686
+
"Vendor", "Product",
687
+
&dummy_funcs,
688
+
&dummy_hdmi_funcs,
689
+
DRM_MODE_CONNECTOR_HDMIA,
690
+
&priv->ddc,
691
+
params->supported_formats,
692
+
8);
693
+
KUNIT_EXPECT_EQ(test, ret, params->expected_result);
694
+
}
695
+
638
696
/*
639
697
* Test that the registration of an HDMI connector with an HDMI
640
698
* connector type succeeds.
···
784
726
KUNIT_CASE(drm_test_connector_hdmi_init_bpc_null),
785
727
KUNIT_CASE(drm_test_connector_hdmi_init_formats_empty),
786
728
KUNIT_CASE(drm_test_connector_hdmi_init_formats_no_rgb),
729
+
KUNIT_CASE_PARAM(drm_test_connector_hdmi_init_formats_yuv420_allowed,
730
+
drm_connector_hdmi_init_formats_yuv420_allowed_gen_params),
787
731
KUNIT_CASE(drm_test_connector_hdmi_init_null_ddc),
788
732
KUNIT_CASE(drm_test_connector_hdmi_init_null_product),
789
733
KUNIT_CASE(drm_test_connector_hdmi_init_null_vendor),
+1
-2
drivers/gpu/drm/tests/drm_kunit_helpers.c
+1
-2
drivers/gpu/drm/tests/drm_kunit_helpers.c
···
320
320
}
321
321
322
322
/**
323
-
* drm_kunit_display_mode_from_cea_vic() - return a mode for CEA VIC
324
-
for a KUnit test
323
+
* drm_kunit_display_mode_from_cea_vic() - return a mode for CEA VIC for a KUnit test
325
324
* @test: The test context object
326
325
* @dev: DRM device
327
326
* @video_code: CEA VIC of the mode
+4
drivers/gpu/drm/v3d/v3d_irq.c
+4
drivers/gpu/drm/v3d/v3d_irq.c
···
108
108
v3d_job_update_stats(&v3d->bin_job->base, V3D_BIN);
109
109
trace_v3d_bcl_irq(&v3d->drm, fence->seqno);
110
110
dma_fence_signal(&fence->base);
111
+
v3d->bin_job = NULL;
111
112
status = IRQ_HANDLED;
112
113
}
113
114
···
119
118
v3d_job_update_stats(&v3d->render_job->base, V3D_RENDER);
120
119
trace_v3d_rcl_irq(&v3d->drm, fence->seqno);
121
120
dma_fence_signal(&fence->base);
121
+
v3d->render_job = NULL;
122
122
status = IRQ_HANDLED;
123
123
}
124
124
···
130
128
v3d_job_update_stats(&v3d->csd_job->base, V3D_CSD);
131
129
trace_v3d_csd_irq(&v3d->drm, fence->seqno);
132
130
dma_fence_signal(&fence->base);
131
+
v3d->csd_job = NULL;
133
132
status = IRQ_HANDLED;
134
133
}
135
134
···
168
165
v3d_job_update_stats(&v3d->tfu_job->base, V3D_TFU);
169
166
trace_v3d_tfu_irq(&v3d->drm, fence->seqno);
170
167
dma_fence_signal(&fence->base);
168
+
v3d->tfu_job = NULL;
171
169
status = IRQ_HANDLED;
172
170
}
173
171
+2
-2
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
+2
-2
drivers/gpu/drm/vmwgfx/vmwgfx_bo.c
···
228
228
VMW_BO_DOMAIN_VRAM,
229
229
VMW_BO_DOMAIN_VRAM);
230
230
buf->places[0].lpfn = PFN_UP(bo->resource->size);
231
-
buf->busy_places[0].lpfn = PFN_UP(bo->resource->size);
232
231
ret = ttm_bo_validate(bo, &buf->placement, &ctx);
233
232
234
233
/* For some reason we didn't end up at the start of vram */
···
442
443
443
444
if (params->pin)
444
445
ttm_bo_pin(&vmw_bo->tbo);
445
-
ttm_bo_unreserve(&vmw_bo->tbo);
446
+
if (!params->keep_resv)
447
+
ttm_bo_unreserve(&vmw_bo->tbo);
446
448
447
449
return 0;
448
450
}
+2
-2
drivers/gpu/drm/vmwgfx/vmwgfx_bo.h
+2
-2
drivers/gpu/drm/vmwgfx/vmwgfx_bo.h
···
56
56
u32 domain;
57
57
u32 busy_domain;
58
58
enum ttm_bo_type bo_type;
59
-
size_t size;
60
59
bool pin;
60
+
bool keep_resv;
61
+
size_t size;
61
62
struct dma_resv *resv;
62
63
struct sg_table *sg;
63
64
};
···
84
83
85
84
struct ttm_placement placement;
86
85
struct ttm_place places[5];
87
-
struct ttm_place busy_places[5];
88
86
89
87
/* Protected by reservation */
90
88
struct ttm_bo_kmap_obj map;
+2
-5
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+2
-5
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
···
403
403
.busy_domain = VMW_BO_DOMAIN_SYS,
404
404
.bo_type = ttm_bo_type_kernel,
405
405
.size = PAGE_SIZE,
406
-
.pin = true
406
+
.pin = true,
407
+
.keep_resv = true,
407
408
};
408
409
409
410
/*
···
415
414
ret = vmw_bo_create(dev_priv, &bo_params, &vbo);
416
415
if (unlikely(ret != 0))
417
416
return ret;
418
-
419
-
ret = ttm_bo_reserve(&vbo->tbo, false, true, NULL);
420
-
BUG_ON(ret != 0);
421
-
vmw_bo_pin_reserved(vbo, true);
422
417
423
418
ret = ttm_bo_kmap(&vbo->tbo, 0, 1, &map);
424
419
if (likely(ret == 0)) {
+1
drivers/gpu/drm/vmwgfx/vmwgfx_gem.c
+1
drivers/gpu/drm/vmwgfx/vmwgfx_gem.c
+15
-5
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+15
-5
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
···
750
750
struct vmw_plane_state *old_vps = vmw_plane_state_to_vps(old_state);
751
751
struct vmw_bo *old_bo = NULL;
752
752
struct vmw_bo *new_bo = NULL;
753
+
struct ww_acquire_ctx ctx;
753
754
s32 hotspot_x, hotspot_y;
754
755
int ret;
755
756
···
770
769
if (du->cursor_surface)
771
770
du->cursor_age = du->cursor_surface->snooper.age;
772
771
772
+
ww_acquire_init(&ctx, &reservation_ww_class);
773
+
773
774
if (!vmw_user_object_is_null(&old_vps->uo)) {
774
775
old_bo = vmw_user_object_buffer(&old_vps->uo);
775
-
ret = ttm_bo_reserve(&old_bo->tbo, false, false, NULL);
776
+
ret = ttm_bo_reserve(&old_bo->tbo, false, false, &ctx);
776
777
if (ret != 0)
777
778
return;
778
779
}
···
782
779
if (!vmw_user_object_is_null(&vps->uo)) {
783
780
new_bo = vmw_user_object_buffer(&vps->uo);
784
781
if (old_bo != new_bo) {
785
-
ret = ttm_bo_reserve(&new_bo->tbo, false, false, NULL);
786
-
if (ret != 0)
782
+
ret = ttm_bo_reserve(&new_bo->tbo, false, false, &ctx);
783
+
if (ret != 0) {
784
+
if (old_bo) {
785
+
ttm_bo_unreserve(&old_bo->tbo);
786
+
ww_acquire_fini(&ctx);
787
+
}
787
788
return;
789
+
}
788
790
} else {
789
791
new_bo = NULL;
790
792
}
···
811
803
hotspot_x, hotspot_y);
812
804
}
813
805
814
-
if (old_bo)
815
-
ttm_bo_unreserve(&old_bo->tbo);
816
806
if (new_bo)
817
807
ttm_bo_unreserve(&new_bo->tbo);
808
+
if (old_bo)
809
+
ttm_bo_unreserve(&old_bo->tbo);
810
+
811
+
ww_acquire_fini(&ctx);
818
812
819
813
du->cursor_x = new_state->crtc_x + du->set_gui_x;
820
814
du->cursor_y = new_state->crtc_y + du->set_gui_y;
+2
-5
drivers/gpu/drm/vmwgfx/vmwgfx_shader.c
+2
-5
drivers/gpu/drm/vmwgfx/vmwgfx_shader.c
···
896
896
.busy_domain = VMW_BO_DOMAIN_SYS,
897
897
.bo_type = ttm_bo_type_device,
898
898
.size = size,
899
-
.pin = true
899
+
.pin = true,
900
+
.keep_resv = true,
900
901
};
901
902
902
903
if (!vmw_shader_id_ok(user_key, shader_type))
···
906
905
ret = vmw_bo_create(dev_priv, &bo_params, &buf);
907
906
if (unlikely(ret != 0))
908
907
goto out;
909
-
910
-
ret = ttm_bo_reserve(&buf->tbo, false, true, NULL);
911
-
if (unlikely(ret != 0))
912
-
goto no_reserve;
913
908
914
909
/* Map and copy shader bytecode. */
915
910
ret = ttm_bo_kmap(&buf->tbo, 0, PFN_UP(size), &map);
+2
-3
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
+2
-3
drivers/gpu/drm/vmwgfx/vmwgfx_ttm_buffer.c
···
572
572
.busy_domain = domain,
573
573
.bo_type = ttm_bo_type_kernel,
574
574
.size = bo_size,
575
-
.pin = true
575
+
.pin = true,
576
+
.keep_resv = true,
576
577
};
577
578
578
579
ret = vmw_bo_create(dev_priv, &bo_params, &vbo);
579
580
if (unlikely(ret != 0))
580
581
return ret;
581
582
582
-
ret = ttm_bo_reserve(&vbo->tbo, false, true, NULL);
583
-
BUG_ON(ret != 0);
584
583
ret = vmw_ttm_populate(vbo->tbo.bdev, vbo->tbo.ttm, &ctx);
585
584
if (likely(ret == 0)) {
586
585
struct vmw_ttm_tt *vmw_tt =
+3
-4
drivers/gpu/drm/xe/tests/xe_bo.c
+3
-4
drivers/gpu/drm/xe/tests/xe_bo.c
···
257
257
* however seems quite fragile not to also restart the GT. Try
258
258
* to do that here by triggering a GT reset.
259
259
*/
260
-
for_each_gt(__gt, xe, id) {
261
-
xe_gt_reset_async(__gt);
262
-
flush_work(&__gt->reset.worker);
263
-
}
260
+
for_each_gt(__gt, xe, id)
261
+
xe_gt_reset(__gt);
262
+
264
263
if (err) {
265
264
KUNIT_FAIL(test, "restore kernel err=%pe\n",
266
265
ERR_PTR(err));
+1
-2
drivers/gpu/drm/xe/tests/xe_mocs.c
+1
-2
drivers/gpu/drm/xe/tests/xe_mocs.c
+25
drivers/gpu/drm/xe/xe_gt.h
+25
drivers/gpu/drm/xe/xe_gt.h
···
57
57
void xe_gt_remove(struct xe_gt *gt);
58
58
59
59
/**
60
+
* xe_gt_wait_for_reset - wait for gt's async reset to finalize.
61
+
* @gt: GT structure
62
+
* Return:
63
+
* %true if it waited for the work to finish execution,
64
+
* %false if there was no scheduled reset or it was done.
65
+
*/
66
+
static inline bool xe_gt_wait_for_reset(struct xe_gt *gt)
67
+
{
68
+
return flush_work(>->reset.worker);
69
+
}
70
+
71
+
/**
72
+
* xe_gt_reset - perform synchronous reset
73
+
* @gt: GT structure
74
+
* Return:
75
+
* %true if it waited for the reset to finish,
76
+
* %false if there was no scheduled reset.
77
+
*/
78
+
static inline bool xe_gt_reset(struct xe_gt *gt)
79
+
{
80
+
xe_gt_reset_async(gt);
81
+
return xe_gt_wait_for_reset(gt);
82
+
}
83
+
84
+
/**
60
85
* xe_gt_any_hw_engine_by_reset_domain - scan the list of engines and return the
61
86
* first that matches the same reset domain as @class
62
87
* @gt: GT structure
+1
-1
drivers/gpu/drm/xe/xe_gt_ccs_mode.c
+1
-1
drivers/gpu/drm/xe/xe_gt_ccs_mode.c
+1
-3
drivers/gpu/drm/xe/xe_gt_debugfs.c
+1
-3
drivers/gpu/drm/xe/xe_gt_debugfs.c
···
132
132
static int force_reset_sync(struct xe_gt *gt, struct drm_printer *p)
133
133
{
134
134
xe_pm_runtime_get(gt_to_xe(gt));
135
-
xe_gt_reset_async(gt);
135
+
xe_gt_reset(gt);
136
136
xe_pm_runtime_put(gt_to_xe(gt));
137
-
138
-
flush_work(>->reset.worker);
139
137
140
138
return 0;
141
139
}
+3
-3
drivers/gpu/drm/xe/xe_gt_mcr.c
+3
-3
drivers/gpu/drm/xe/xe_gt_mcr.c
···
550
550
* Returns true if the caller should steer to the @group/@instance values
551
551
* returned. Returns false if the caller need not perform any steering
552
552
*/
553
-
static bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
554
-
struct xe_reg_mcr reg_mcr,
555
-
u8 *group, u8 *instance)
553
+
bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
554
+
struct xe_reg_mcr reg_mcr,
555
+
u8 *group, u8 *instance)
556
556
{
557
557
const struct xe_reg reg = to_xe_reg(reg_mcr);
558
558
const struct xe_mmio_range *implicit_ranges;
+4
drivers/gpu/drm/xe/xe_gt_mcr.h
+4
drivers/gpu/drm/xe/xe_gt_mcr.h
···
26
26
void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr mcr_reg,
27
27
u32 value);
28
28
29
+
bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt,
30
+
struct xe_reg_mcr reg_mcr,
31
+
u8 *group, u8 *instance);
32
+
29
33
void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p);
30
34
void xe_gt_mcr_get_dss_steering(struct xe_gt *gt, unsigned int dss, u16 *group, u16 *instance);
31
35
u32 xe_gt_mcr_steering_info_to_dss_id(struct xe_gt *gt, u16 group, u16 instance);
+15
drivers/gpu/drm/xe/xe_guc_ads.c
+15
drivers/gpu/drm/xe/xe_guc_ads.c
···
29
29
#include "xe_platform_types.h"
30
30
#include "xe_uc_fw.h"
31
31
#include "xe_wa.h"
32
+
#include "xe_gt_mcr.h"
32
33
33
34
/* Slack of a few additional entries per engine */
34
35
#define ADS_REGSET_EXTRA_MAX 8
···
701
700
.offset = reg.addr,
702
701
.flags = reg.masked ? GUC_REGSET_MASKED : 0,
703
702
};
703
+
704
+
if (reg.mcr) {
705
+
struct xe_reg_mcr mcr_reg = XE_REG_MCR(reg.addr);
706
+
u8 group, instance;
707
+
708
+
bool steer = xe_gt_mcr_get_nonterminated_steering(ads_to_gt(ads), mcr_reg,
709
+
&group, &instance);
710
+
711
+
if (steer) {
712
+
entry.flags |= FIELD_PREP(GUC_REGSET_STEERING_GROUP, group);
713
+
entry.flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, instance);
714
+
entry.flags |= GUC_REGSET_STEERING_NEEDED;
715
+
}
716
+
}
704
717
705
718
xe_map_memcpy_to(ads_to_xe(ads), regset_map, n_entry * sizeof(entry),
706
719
&entry, sizeof(entry));
+1
-1
drivers/gpu/drm/xe/xe_hw_engine.c
+1
-1
drivers/gpu/drm/xe/xe_hw_engine.c
···
419
419
* Bspec: 72161
420
420
*/
421
421
const u8 mocs_write_idx = gt->mocs.uc_index;
422
-
const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE &&
422
+
const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&
423
423
(GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ?
424
424
gt->mocs.wb_index : gt->mocs.uc_index;
425
425
u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
+1
drivers/gpu/drm/xe/xe_oa.c
+1
drivers/gpu/drm/xe/xe_oa.c
···
2198
2198
{ .start = 0x5194, .end = 0x5194 }, /* SYS_MEM_LAT_MEASURE_MERTF_GRP_3D */
2199
2199
{ .start = 0x8704, .end = 0x8704 }, /* LMEM_LAT_MEASURE_MCFG_GRP */
2200
2200
{ .start = 0xB1BC, .end = 0xB1BC }, /* L3_BANK_LAT_MEASURE_LBCF_GFX */
2201
+
{ .start = 0xD0E0, .end = 0xD0F4 }, /* VISACTL */
2201
2202
{ .start = 0xE18C, .end = 0xE18C }, /* SAMPLER_MODE */
2202
2203
{ .start = 0xE590, .end = 0xE590 }, /* TDL_LSC_LAT_MEASURE_TDL_GFX */
2203
2204
{ .start = 0x13000, .end = 0x137FC }, /* PES_0_PESL0 - PES_63_UPPER_PESL3 */