tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

Merge tag 'drm-fixes-2024-02-03' of git://anongit.freedesktop.org/drm/drm

Pul drm fixes from Dave Airlie:
"Regular weekly fixes, mostly amdgpu and xe. One nouveau fix is a
better fix for the deadlock and also helps with a sync race we were
seeing.

dma-buf:
- heaps CMA page accounting fix

virtio-gpu:
- fix segment size

xe:
- A crash fix
- A fix for an assert due to missing mem_acces ref
- Only allow a single user-fence per exec / bind.
- Some sparse warning fixes
- Two fixes for compilation failures on various odd combinations of
gcc / arch pointed out on LKML.
- Fix a fragile partial allocation pointed out on LKML.
- A sysfs ABI documentation warning fix

amdgpu:
- Fix reboot issue seen on some 7000 series dGPUs
- Fix client init order for KFD
- Misc display fixes
- USB-C fix
- DCN 3.5 fixes
- Fix issues with GPU scheduler and GPU reset
- GPU firmware loading fix
- Misc fixes
- GC 11.5 fix
- VCN 4.0.5 fix
- IH overflow fix

amdkfd:
- SVM fixes
- Trap handler fix
- Fix device permission lookup
- Properly reserve BO before validating it

nouveau:
- fence/irq lock deadlock fix (second attempt)
- gsp command size fix

* tag 'drm-fixes-2024-02-03' of git://anongit.freedesktop.org/drm/drm: (35 commits)
nouveau: offload fence uevents work to workqueue
nouveau/gsp: use correct size for registry rpc.
drm/amdgpu/pm: Use inline function for IP version check
drm/hwmon: Fix abi doc warnings
drm/xe: Make all GuC ABI shift values unsigned
drm/xe/vm: Subclass userptr vmas
drm/xe: Use LRC prefix rather than CTX prefix in lrc desc defines
drm/xe: Don't use __user error pointers
drm/xe: Annotate mcr_[un]lock()
drm/xe: Only allow 1 ufence per exec / bind IOCTL
drm/xe: Grab mem_access when disabling C6 on skip_guc_pc platforms
drm/xe: Fix crash in trace_dma_fence_init()
drm/amdgpu: Reset IH OVERFLOW_CLEAR bit
drm/amdgpu: remove asymmetrical irq disabling in vcn 4.0.5 suspend
drm/amdgpu: drm/amdgpu: remove golden setting for gfx 11.5.0
drm/amdkfd: reserve the BO before validating it
drm/amdgpu: Fix missing error code in 'gmc_v6/7/8/9_0_hw_init()'
drm/amd/display: Fix buffer overflow in 'get_host_router_total_dp_tunnel_bw()'
drm/amd/display: Add NULL check for kzalloc in 'amdgpu_dm_atomic_commit_tail()'
drm/amd: Don't init MEC2 firmware when it fails to load
...

Linus Torvalds 9c2f0338 eab5c86d

+475 -403
+7 -7
Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon
··· 1 - What: /sys/devices/.../hwmon/hwmon<i>/in0_input 1 + What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/in0_input 2 2 Date: February 2023 3 3 KernelVersion: 6.2 4 4 Contact: intel-gfx@lists.freedesktop.org ··· 6 6 7 7 Only supported for particular Intel i915 graphics platforms. 8 8 9 - What: /sys/devices/.../hwmon/hwmon<i>/power1_max 9 + What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_max 10 10 Date: February 2023 11 11 KernelVersion: 6.2 12 12 Contact: intel-gfx@lists.freedesktop.org ··· 20 20 21 21 Only supported for particular Intel i915 graphics platforms. 22 22 23 - What: /sys/devices/.../hwmon/hwmon<i>/power1_rated_max 23 + What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_rated_max 24 24 Date: February 2023 25 25 KernelVersion: 6.2 26 26 Contact: intel-gfx@lists.freedesktop.org ··· 28 28 29 29 Only supported for particular Intel i915 graphics platforms. 30 30 31 - What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval 31 + What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_max_interval 32 32 Date: February 2023 33 33 KernelVersion: 6.2 34 34 Contact: intel-gfx@lists.freedesktop.org ··· 37 37 38 38 Only supported for particular Intel i915 graphics platforms. 39 39 40 - What: /sys/devices/.../hwmon/hwmon<i>/power1_crit 40 + What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_crit 41 41 Date: February 2023 42 42 KernelVersion: 6.2 43 43 Contact: intel-gfx@lists.freedesktop.org ··· 50 50 51 51 Only supported for particular Intel i915 graphics platforms. 52 52 53 - What: /sys/devices/.../hwmon/hwmon<i>/curr1_crit 53 + What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/curr1_crit 54 54 Date: February 2023 55 55 KernelVersion: 6.2 56 56 Contact: intel-gfx@lists.freedesktop.org ··· 63 63 64 64 Only supported for particular Intel i915 graphics platforms. 65 65 66 - What: /sys/devices/.../hwmon/hwmon<i>/energy1_input 66 + What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/energy1_input 67 67 Date: February 2023 68 68 KernelVersion: 6.2 69 69 Contact: intel-gfx@lists.freedesktop.org
+7 -7
Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
··· 1 - What: /sys/devices/.../hwmon/hwmon<i>/power1_max 1 + What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_max 2 2 Date: September 2023 3 3 KernelVersion: 6.5 4 4 Contact: intel-xe@lists.freedesktop.org ··· 12 12 13 13 Only supported for particular Intel xe graphics platforms. 14 14 15 - What: /sys/devices/.../hwmon/hwmon<i>/power1_rated_max 15 + What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_rated_max 16 16 Date: September 2023 17 17 KernelVersion: 6.5 18 18 Contact: intel-xe@lists.freedesktop.org ··· 20 20 21 21 Only supported for particular Intel xe graphics platforms. 22 22 23 - What: /sys/devices/.../hwmon/hwmon<i>/power1_crit 23 + What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_crit 24 24 Date: September 2023 25 25 KernelVersion: 6.5 26 26 Contact: intel-xe@lists.freedesktop.org ··· 33 33 34 34 Only supported for particular Intel xe graphics platforms. 35 35 36 - What: /sys/devices/.../hwmon/hwmon<i>/curr1_crit 36 + What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/curr1_crit 37 37 Date: September 2023 38 38 KernelVersion: 6.5 39 39 Contact: intel-xe@lists.freedesktop.org ··· 44 44 the operating frequency if the power averaged over a window 45 45 exceeds this limit. 46 46 47 - What: /sys/devices/.../hwmon/hwmon<i>/in0_input 47 + What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/in0_input 48 48 Date: September 2023 49 49 KernelVersion: 6.5 50 50 Contact: intel-xe@lists.freedesktop.org ··· 52 52 53 53 Only supported for particular Intel xe graphics platforms. 54 54 55 - What: /sys/devices/.../hwmon/hwmon<i>/energy1_input 55 + What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/energy1_input 56 56 Date: September 2023 57 57 KernelVersion: 6.5 58 58 Contact: intel-xe@lists.freedesktop.org ··· 60 60 61 61 Only supported for particular Intel xe graphics platforms. 62 62 63 - What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval 63 + What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_max_interval 64 64 Date: October 2023 65 65 KernelVersion: 6.6 66 66 Contact: intel-xe@lists.freedesktop.org
+3 -4
drivers/dma-buf/heaps/cma_heap.c
··· 168 168 if (vmf->pgoff > buffer->pagecount) 169 169 return VM_FAULT_SIGBUS; 170 170 171 - vmf->page = buffer->pages[vmf->pgoff]; 172 - get_page(vmf->page); 173 - 174 - return 0; 171 + return vmf_insert_pfn(vma, vmf->address, page_to_pfn(buffer->pages[vmf->pgoff])); 175 172 } 176 173 177 174 static const struct vm_operations_struct dma_heap_vm_ops = { ··· 181 184 182 185 if ((vma->vm_flags & (VM_SHARED | VM_MAYSHARE)) == 0) 183 186 return -EINVAL; 187 + 188 + vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP); 184 189 185 190 vma->vm_ops = &dma_heap_vm_ops; 186 191 vma->vm_private_data = buffer;
+21 -11
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
··· 141 141 static const struct drm_client_funcs kfd_client_funcs = { 142 142 .unregister = drm_client_release, 143 143 }; 144 + 145 + int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev) 146 + { 147 + int ret; 148 + 149 + if (!adev->kfd.init_complete) 150 + return 0; 151 + 152 + ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd", 153 + &kfd_client_funcs); 154 + if (ret) { 155 + dev_err(adev->dev, "Failed to init DRM client: %d\n", 156 + ret); 157 + return ret; 158 + } 159 + 160 + drm_client_register(&adev->kfd.client); 161 + 162 + return 0; 163 + } 164 + 144 165 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 145 166 { 146 167 int i; 147 168 int last_valid_bit; 148 - int ret; 149 169 150 170 amdgpu_amdkfd_gpuvm_init_mem_limits(); 151 171 ··· 183 163 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 184 164 .enable_mes = adev->enable_mes, 185 165 }; 186 - 187 - ret = drm_client_init(&adev->ddev, &adev->kfd.client, "kfd", &kfd_client_funcs); 188 - if (ret) { 189 - dev_err(adev->dev, "Failed to init DRM client: %d\n", ret); 190 - return; 191 - } 192 166 193 167 /* this is going to have a few of the MSBs set that we need to 194 168 * clear ··· 222 208 223 209 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 224 210 &gpu_resources); 225 - if (adev->kfd.init_complete) 226 - drm_client_register(&adev->kfd.client); 227 - else 228 - drm_client_release(&adev->kfd.client); 229 211 230 212 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 231 213
+3 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
··· 182 182 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, 183 183 struct mm_struct *mm, 184 184 struct svm_range_bo *svm_bo); 185 + 186 + int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev); 185 187 #if defined(CONFIG_DEBUG_FS) 186 188 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data); 187 189 #endif ··· 303 301 struct kgd_mem *mem, void *drm_priv); 304 302 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 305 303 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv); 306 - void amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv); 304 + int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv); 307 305 int amdgpu_amdkfd_gpuvm_sync_memory( 308 306 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr); 309 307 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c
··· 290 290 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 291 291 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 292 292 293 - if (!(ring && drm_sched_wqueue_ready(&ring->sched))) 293 + if (!amdgpu_ring_sched_ready(ring)) 294 294 continue; 295 295 296 296 /* stop secheduler and drain ring. */
+17 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
··· 2085 2085 return ret; 2086 2086 } 2087 2087 2088 - void amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv) 2088 + int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv) 2089 2089 { 2090 2090 struct kfd_mem_attachment *entry; 2091 2091 struct amdgpu_vm *vm; 2092 + int ret; 2092 2093 2093 2094 vm = drm_priv_to_vm(drm_priv); 2094 2095 2095 2096 mutex_lock(&mem->lock); 2096 2097 2098 + ret = amdgpu_bo_reserve(mem->bo, true); 2099 + if (ret) 2100 + goto out; 2101 + 2097 2102 list_for_each_entry(entry, &mem->attachments, list) { 2098 - if (entry->bo_va->base.vm == vm) 2099 - kfd_mem_dmaunmap_attachment(mem, entry); 2103 + if (entry->bo_va->base.vm != vm) 2104 + continue; 2105 + if (entry->bo_va->base.bo->tbo.ttm && 2106 + !entry->bo_va->base.bo->tbo.ttm->sg) 2107 + continue; 2108 + 2109 + kfd_mem_dmaunmap_attachment(mem, entry); 2100 2110 } 2101 2111 2112 + amdgpu_bo_unreserve(mem->bo); 2113 + out: 2102 2114 mutex_unlock(&mem->lock); 2115 + 2116 + return ret; 2103 2117 } 2104 2118 2105 2119 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
+4 -4
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
··· 1678 1678 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1679 1679 struct amdgpu_ring *ring = adev->rings[i]; 1680 1680 1681 - if (!ring || !drm_sched_wqueue_ready(&ring->sched)) 1681 + if (!amdgpu_ring_sched_ready(ring)) 1682 1682 continue; 1683 1683 drm_sched_wqueue_stop(&ring->sched); 1684 1684 } ··· 1694 1694 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1695 1695 struct amdgpu_ring *ring = adev->rings[i]; 1696 1696 1697 - if (!ring || !drm_sched_wqueue_ready(&ring->sched)) 1697 + if (!amdgpu_ring_sched_ready(ring)) 1698 1698 continue; 1699 1699 drm_sched_wqueue_start(&ring->sched); 1700 1700 } ··· 1916 1916 1917 1917 ring = adev->rings[val]; 1918 1918 1919 - if (!ring || !ring->funcs->preempt_ib || 1920 - !drm_sched_wqueue_ready(&ring->sched)) 1919 + if (!amdgpu_ring_sched_ready(ring) || 1920 + !ring->funcs->preempt_ib) 1921 1921 return -EINVAL; 1922 1922 1923 1923 /* the last preemption failed */
+13 -23
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 4121 4121 } 4122 4122 } 4123 4123 } else { 4124 - switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 4125 - case IP_VERSION(13, 0, 0): 4126 - case IP_VERSION(13, 0, 7): 4127 - case IP_VERSION(13, 0, 10): 4128 - r = psp_gpu_reset(adev); 4129 - break; 4130 - default: 4131 - tmp = amdgpu_reset_method; 4132 - /* It should do a default reset when loading or reloading the driver, 4133 - * regardless of the module parameter reset_method. 4134 - */ 4135 - amdgpu_reset_method = AMD_RESET_METHOD_NONE; 4136 - r = amdgpu_asic_reset(adev); 4137 - amdgpu_reset_method = tmp; 4138 - break; 4139 - } 4140 - 4124 + tmp = amdgpu_reset_method; 4125 + /* It should do a default reset when loading or reloading the driver, 4126 + * regardless of the module parameter reset_method. 4127 + */ 4128 + amdgpu_reset_method = AMD_RESET_METHOD_NONE; 4129 + r = amdgpu_asic_reset(adev); 4130 + amdgpu_reset_method = tmp; 4141 4131 if (r) { 4142 4132 dev_err(adev->dev, "asic reset on init failed\n"); 4143 4133 goto failed; ··· 5021 5031 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 5022 5032 struct amdgpu_ring *ring = adev->rings[i]; 5023 5033 5024 - if (!ring || !drm_sched_wqueue_ready(&ring->sched)) 5034 + if (!amdgpu_ring_sched_ready(ring)) 5025 5035 continue; 5026 5036 5027 5037 spin_lock(&ring->sched.job_list_lock); ··· 5160 5170 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 5161 5171 struct amdgpu_ring *ring = adev->rings[i]; 5162 5172 5163 - if (!ring || !drm_sched_wqueue_ready(&ring->sched)) 5173 + if (!amdgpu_ring_sched_ready(ring)) 5164 5174 continue; 5165 5175 5166 5176 /* Clear job fence from fence drv to avoid force_completion ··· 5627 5637 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 5628 5638 struct amdgpu_ring *ring = tmp_adev->rings[i]; 5629 5639 5630 - if (!ring || !drm_sched_wqueue_ready(&ring->sched)) 5640 + if (!amdgpu_ring_sched_ready(ring)) 5631 5641 continue; 5632 5642 5633 5643 drm_sched_stop(&ring->sched, job ? &job->base : NULL); ··· 5696 5706 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 5697 5707 struct amdgpu_ring *ring = tmp_adev->rings[i]; 5698 5708 5699 - if (!ring || !drm_sched_wqueue_ready(&ring->sched)) 5709 + if (!amdgpu_ring_sched_ready(ring)) 5700 5710 continue; 5701 5711 5702 5712 drm_sched_start(&ring->sched, true); ··· 6051 6061 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 6052 6062 struct amdgpu_ring *ring = adev->rings[i]; 6053 6063 6054 - if (!ring || !drm_sched_wqueue_ready(&ring->sched)) 6064 + if (!amdgpu_ring_sched_ready(ring)) 6055 6065 continue; 6056 6066 6057 6067 drm_sched_stop(&ring->sched, NULL); ··· 6179 6189 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { 6180 6190 struct amdgpu_ring *ring = adev->rings[i]; 6181 6191 6182 - if (!ring || !drm_sched_wqueue_ready(&ring->sched)) 6192 + if (!amdgpu_ring_sched_ready(ring)) 6183 6193 continue; 6184 6194 6185 6195 drm_sched_start(&ring->sched, true);
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
··· 2255 2255 if (ret) 2256 2256 goto err_pci; 2257 2257 2258 + ret = amdgpu_amdkfd_drm_client_create(adev); 2259 + if (ret) 2260 + goto err_pci; 2261 + 2258 2262 /* 2259 2263 * 1. don't init fbdev on hw without DCE 2260 2264 * 2. don't init fbdev if there are no connectors
+12
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
··· 635 635 ring->name); 636 636 637 637 ring->sched.ready = !r; 638 + 638 639 return r; 639 640 } 640 641 ··· 717 716 { 718 717 if (ring->is_sw_ring) 719 718 amdgpu_sw_ring_ib_mark_offset(ring, AMDGPU_MUX_OFFSET_TYPE_DE); 719 + } 720 + 721 + bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring) 722 + { 723 + if (!ring) 724 + return false; 725 + 726 + if (ring->no_scheduler || !drm_sched_wqueue_ready(&ring->sched)) 727 + return false; 728 + 729 + return true; 720 730 }
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
··· 450 450 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 451 451 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 452 452 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 453 - 453 + bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring); 454 454 #endif
+6
drivers/gpu/drm/amd/amdgpu/cik_ih.c
··· 204 204 tmp = RREG32(mmIH_RB_CNTL); 205 205 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; 206 206 WREG32(mmIH_RB_CNTL, tmp); 207 + 208 + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 209 + * can be detected. 210 + */ 211 + tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; 212 + WREG32(mmIH_RB_CNTL, tmp); 207 213 } 208 214 return (wptr & ih->ptr_mask); 209 215 }
+5
drivers/gpu/drm/amd/amdgpu/cz_ih.c
··· 216 216 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 217 217 WREG32(mmIH_RB_CNTL, tmp); 218 218 219 + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 220 + * can be detected. 221 + */ 222 + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 223 + WREG32(mmIH_RB_CNTL, tmp); 219 224 220 225 out: 221 226 return (wptr & ih->ptr_mask);
-2
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
··· 4027 4027 err = 0; 4028 4028 adev->gfx.mec2_fw = NULL; 4029 4029 } 4030 - amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4031 - amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4032 4030 4033 4031 gfx_v10_0_check_fw_write_wait(adev); 4034 4032 out:
-22
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
··· 107 107 SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a) 108 108 }; 109 109 110 - static const struct soc15_reg_golden golden_settings_gc_11_5_0[] = { 111 - SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_DEBUG5, 0xffffffff, 0x00000800), 112 - SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 113 - SOC15_REG_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500), 114 - SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 115 - SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 116 - SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL, 0xffffffff, 0xf37fff3f), 117 - SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xfffffffb, 0x00f40188), 118 - SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ffffff, 0x80009007), 119 - SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf1ffffff, 0x00880007), 120 - SOC15_REG_GOLDEN_VALUE(GC, 0, regPC_CONFIG_CNTL_1, 0xffffffff, 0x00010000), 121 - SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000), 122 - SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL2, 0x007f0000, 0x00000000), 123 - SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xffcfffff, 0x0000200a), 124 - SOC15_REG_GOLDEN_VALUE(GC, 0, regUTCL1_CTRL_2, 0xffffffff, 0x0000048f) 125 - }; 126 - 127 110 #define DEFAULT_SH_MEM_CONFIG \ 128 111 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 129 112 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ ··· 286 303 soc15_program_register_sequence(adev, 287 304 golden_settings_gc_11_0_1, 288 305 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1)); 289 - break; 290 - case IP_VERSION(11, 5, 0): 291 - soc15_program_register_sequence(adev, 292 - golden_settings_gc_11_5_0, 293 - (const u32)ARRAY_SIZE(golden_settings_gc_11_5_0)); 294 306 break; 295 307 default: 296 308 break;
+2 -2
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
··· 915 915 916 916 if (amdgpu_emu_mode == 1) 917 917 return amdgpu_gmc_vram_checking(adev); 918 - else 919 - return r; 918 + 919 + return 0; 920 920 } 921 921 922 922 static int gmc_v6_0_hw_fini(void *handle)
+2 -2
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
··· 1099 1099 1100 1100 if (amdgpu_emu_mode == 1) 1101 1101 return amdgpu_gmc_vram_checking(adev); 1102 - else 1103 - return r; 1102 + 1103 + return 0; 1104 1104 } 1105 1105 1106 1106 static int gmc_v7_0_hw_fini(void *handle)
+2 -2
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
··· 1219 1219 1220 1220 if (amdgpu_emu_mode == 1) 1221 1221 return amdgpu_gmc_vram_checking(adev); 1222 - else 1223 - return r; 1222 + 1223 + return 0; 1224 1224 } 1225 1225 1226 1226 static int gmc_v8_0_hw_fini(void *handle)
+2 -2
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
··· 2341 2341 2342 2342 if (amdgpu_emu_mode == 1) 2343 2343 return amdgpu_gmc_vram_checking(adev); 2344 - else 2345 - return r; 2344 + 2345 + return 0; 2346 2346 } 2347 2347 2348 2348 /**
+5
drivers/gpu/drm/amd/amdgpu/iceland_ih.c
··· 215 215 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 216 216 WREG32(mmIH_RB_CNTL, tmp); 217 217 218 + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 219 + * can be detected. 220 + */ 221 + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 222 + WREG32(mmIH_RB_CNTL, tmp); 218 223 219 224 out: 220 225 return (wptr & ih->ptr_mask);
+6
drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
··· 418 418 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 419 419 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 420 420 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 421 + 422 + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 423 + * can be detected. 424 + */ 425 + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 426 + WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 421 427 out: 422 428 return (wptr & ih->ptr_mask); 423 429 }
+7
drivers/gpu/drm/amd/amdgpu/ih_v6_1.c
··· 418 418 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 419 419 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 420 420 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 421 + 422 + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 423 + * can be detected. 424 + */ 425 + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 426 + WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 427 + 421 428 out: 422 429 return (wptr & ih->ptr_mask); 423 430 }
+6
drivers/gpu/drm/amd/amdgpu/navi10_ih.c
··· 442 442 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); 443 443 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 444 444 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 445 + 446 + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 447 + * can be detected. 448 + */ 449 + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 450 + WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 445 451 out: 446 452 return (wptr & ih->ptr_mask); 447 453 }
+6
drivers/gpu/drm/amd/amdgpu/si_ih.c
··· 119 119 tmp = RREG32(IH_RB_CNTL); 120 120 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; 121 121 WREG32(IH_RB_CNTL, tmp); 122 + 123 + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 124 + * can be detected. 125 + */ 126 + tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; 127 + WREG32(IH_RB_CNTL, tmp); 122 128 } 123 129 return (wptr & ih->ptr_mask); 124 130 }
+6
drivers/gpu/drm/amd/amdgpu/tonga_ih.c
··· 219 219 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 220 220 WREG32(mmIH_RB_CNTL, tmp); 221 221 222 + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 223 + * can be detected. 224 + */ 225 + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 226 + WREG32(mmIH_RB_CNTL, tmp); 227 + 222 228 out: 223 229 return (wptr & ih->ptr_mask); 224 230 }
-17
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
··· 2018 2018 } 2019 2019 2020 2020 /** 2021 - * vcn_v4_0_set_interrupt_state - set VCN block interrupt state 2022 - * 2023 - * @adev: amdgpu_device pointer 2024 - * @source: interrupt sources 2025 - * @type: interrupt types 2026 - * @state: interrupt states 2027 - * 2028 - * Set VCN block interrupt state 2029 - */ 2030 - static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 2031 - unsigned type, enum amdgpu_interrupt_state state) 2032 - { 2033 - return 0; 2034 - } 2035 - 2036 - /** 2037 2021 * vcn_v4_0_set_ras_interrupt_state - set VCN block RAS interrupt state 2038 2022 * 2039 2023 * @adev: amdgpu_device pointer ··· 2081 2097 } 2082 2098 2083 2099 static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = { 2084 - .set = vcn_v4_0_set_interrupt_state, 2085 2100 .process = vcn_v4_0_process_interrupt, 2086 2101 }; 2087 2102
-19
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
··· 269 269 vcn_v4_0_5_set_powergating_state(adev, AMD_PG_STATE_GATE); 270 270 } 271 271 } 272 - 273 - amdgpu_irq_put(adev, &adev->vcn.inst[i].irq, 0); 274 272 } 275 273 276 274 return 0; ··· 1667 1669 } 1668 1670 1669 1671 /** 1670 - * vcn_v4_0_5_set_interrupt_state - set VCN block interrupt state 1671 - * 1672 - * @adev: amdgpu_device pointer 1673 - * @source: interrupt sources 1674 - * @type: interrupt types 1675 - * @state: interrupt states 1676 - * 1677 - * Set VCN block interrupt state 1678 - */ 1679 - static int vcn_v4_0_5_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 1680 - unsigned type, enum amdgpu_interrupt_state state) 1681 - { 1682 - return 0; 1683 - } 1684 - 1685 - /** 1686 1672 * vcn_v4_0_5_process_interrupt - process VCN block interrupt 1687 1673 * 1688 1674 * @adev: amdgpu_device pointer ··· 1708 1726 } 1709 1727 1710 1728 static const struct amdgpu_irq_src_funcs vcn_v4_0_5_irq_funcs = { 1711 - .set = vcn_v4_0_5_set_interrupt_state, 1712 1729 .process = vcn_v4_0_5_process_interrupt, 1713 1730 }; 1714 1731
+6
drivers/gpu/drm/amd/amdgpu/vega10_ih.c
··· 373 373 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 374 374 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 375 375 376 + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 377 + * can be detected. 378 + */ 379 + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 380 + WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 381 + 376 382 out: 377 383 return (wptr & ih->ptr_mask); 378 384 }
+6
drivers/gpu/drm/amd/amdgpu/vega20_ih.c
··· 421 421 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 422 422 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 423 423 424 + /* Unset the CLEAR_OVERFLOW bit immediately so new overflows 425 + * can be detected. 426 + */ 427 + tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0); 428 + WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); 429 + 424 430 out: 425 431 return (wptr & ih->ptr_mask); 426 432 }
+7 -7
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
··· 674 674 0x86ea6a6a, 0x8f6e837a, 675 675 0xb96ee0c2, 0xbf800002, 676 676 0xb97a0002, 0xbf8a0000, 677 - 0xbe801f6c, 0xbf810000, 677 + 0xbe801f6c, 0xbf9b0000, 678 678 }; 679 679 680 680 static const uint32_t cwsr_trap_nv1x_hex[] = { ··· 1091 1091 0xb9eef807, 0x876dff6d, 1092 1092 0x0000ffff, 0x87fe7e7e, 1093 1093 0x87ea6a6a, 0xb9faf802, 1094 - 0xbe80226c, 0xbf810000, 1094 + 0xbe80226c, 0xbf9b0000, 1095 1095 0xbf9f0000, 0xbf9f0000, 1096 1096 0xbf9f0000, 0xbf9f0000, 1097 1097 0xbf9f0000, 0x00000000, ··· 1574 1574 0x86ea6a6a, 0x8f6e837a, 1575 1575 0xb96ee0c2, 0xbf800002, 1576 1576 0xb97a0002, 0xbf8a0000, 1577 - 0xbe801f6c, 0xbf810000, 1577 + 0xbe801f6c, 0xbf9b0000, 1578 1578 }; 1579 1579 1580 1580 static const uint32_t cwsr_trap_aldebaran_hex[] = { ··· 2065 2065 0x86ea6a6a, 0x8f6e837a, 2066 2066 0xb96ee0c2, 0xbf800002, 2067 2067 0xb97a0002, 0xbf8a0000, 2068 - 0xbe801f6c, 0xbf810000, 2068 + 0xbe801f6c, 0xbf9b0000, 2069 2069 }; 2070 2070 2071 2071 static const uint32_t cwsr_trap_gfx10_hex[] = { ··· 2500 2500 0x876dff6d, 0x0000ffff, 2501 2501 0x87fe7e7e, 0x87ea6a6a, 2502 2502 0xb9faf802, 0xbe80226c, 2503 - 0xbf810000, 0xbf9f0000, 2503 + 0xbf9b0000, 0xbf9f0000, 2504 2504 0xbf9f0000, 0xbf9f0000, 2505 2505 0xbf9f0000, 0xbf9f0000, 2506 2506 }; ··· 2944 2944 0xb8eef802, 0xbf0d866e, 2945 2945 0xbfa20002, 0xb97af802, 2946 2946 0xbe80486c, 0xb97af802, 2947 - 0xbe804a6c, 0xbfb00000, 2947 + 0xbe804a6c, 0xbfb10000, 2948 2948 0xbf9f0000, 0xbf9f0000, 2949 2949 0xbf9f0000, 0xbf9f0000, 2950 2950 0xbf9f0000, 0x00000000, ··· 3436 3436 0x86ea6a6a, 0x8f6e837a, 3437 3437 0xb96ee0c2, 0xbf800002, 3438 3438 0xb97a0002, 0xbf8a0000, 3439 - 0xbe801f6c, 0xbf810000, 3439 + 0xbe801f6c, 0xbf9b0000, 3440 3440 };
+1 -1
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx10.asm
··· 1104 1104 s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution 1105 1105 1106 1106 L_END_PGM: 1107 - s_endpgm 1107 + s_endpgm_saved 1108 1108 end 1109 1109 1110 1110 function write_hwreg_to_mem(s, s_rsrc, s_mem_offset)
+1 -1
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm
··· 921 921 /* the END */ 922 922 /**************************************************************************/ 923 923 L_END_PGM: 924 - s_endpgm 924 + s_endpgm_saved 925 925 926 926 end 927 927
+3 -1
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
··· 1442 1442 kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT); 1443 1443 1444 1444 /* Remove dma mapping after tlb flush to avoid IO_PAGE_FAULT */ 1445 - amdgpu_amdkfd_gpuvm_dmaunmap_mem(mem, peer_pdd->drm_priv); 1445 + err = amdgpu_amdkfd_gpuvm_dmaunmap_mem(mem, peer_pdd->drm_priv); 1446 + if (err) 1447 + goto sync_memory_failed; 1446 1448 } 1447 1449 1448 1450 mutex_unlock(&p->mutex);
+1 -1
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
··· 574 574 pr_debug("svms 0x%p [0x%lx 0x%lx]\n", prange->svms, prange->start, 575 575 prange->last); 576 576 577 - addr = prange->start << PAGE_SHIFT; 577 + addr = migrate->start; 578 578 579 579 src = (uint64_t *)(scratch + npages); 580 580 dst = scratch;
+7 -2
drivers/gpu/drm/amd/amdkfd/kfd_priv.h
··· 1488 1488 1489 1489 /* Cgroup Support */ 1490 1490 /* Check with device cgroup if @kfd device is accessible */ 1491 - static inline int kfd_devcgroup_check_permission(struct kfd_node *kfd) 1491 + static inline int kfd_devcgroup_check_permission(struct kfd_node *node) 1492 1492 { 1493 1493 #if defined(CONFIG_CGROUP_DEVICE) || defined(CONFIG_CGROUP_BPF) 1494 - struct drm_device *ddev = adev_to_drm(kfd->adev); 1494 + struct drm_device *ddev; 1495 + 1496 + if (node->xcp) 1497 + ddev = node->xcp->ddev; 1498 + else 1499 + ddev = adev_to_drm(node->adev); 1495 1500 1496 1501 return devcgroup_check_permission(DEVCG_DEV_CHAR, DRM_MAJOR, 1497 1502 ddev->render->index,
+4
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
··· 9187 9187 * To fix this, DC should permit updating only stream properties. 9188 9188 */ 9189 9189 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC); 9190 + if (!dummy_updates) { 9191 + DRM_ERROR("Failed to allocate memory for dummy_updates.\n"); 9192 + continue; 9193 + } 9190 9194 for (j = 0; j < status->plane_count; j++) 9191 9195 dummy_updates[j].surface = status->plane_states[0]; 9192 9196
+16 -16
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
··· 437 437 .wm_inst = WM_A, 438 438 .wm_type = WM_TYPE_PSTATE_CHG, 439 439 .pstate_latency_us = 11.72, 440 - .sr_exit_time_us = 14.0, 441 - .sr_enter_plus_exit_time_us = 16.0, 440 + .sr_exit_time_us = 28.0, 441 + .sr_enter_plus_exit_time_us = 30.0, 442 442 .valid = true, 443 443 }, 444 444 { 445 445 .wm_inst = WM_B, 446 446 .wm_type = WM_TYPE_PSTATE_CHG, 447 447 .pstate_latency_us = 11.72, 448 - .sr_exit_time_us = 14.0, 449 - .sr_enter_plus_exit_time_us = 16.0, 448 + .sr_exit_time_us = 28.0, 449 + .sr_enter_plus_exit_time_us = 30.0, 450 450 .valid = true, 451 451 }, 452 452 { 453 453 .wm_inst = WM_C, 454 454 .wm_type = WM_TYPE_PSTATE_CHG, 455 455 .pstate_latency_us = 11.72, 456 - .sr_exit_time_us = 14.0, 457 - .sr_enter_plus_exit_time_us = 16.0, 456 + .sr_exit_time_us = 28.0, 457 + .sr_enter_plus_exit_time_us = 30.0, 458 458 .valid = true, 459 459 }, 460 460 { 461 461 .wm_inst = WM_D, 462 462 .wm_type = WM_TYPE_PSTATE_CHG, 463 463 .pstate_latency_us = 11.72, 464 - .sr_exit_time_us = 14.0, 465 - .sr_enter_plus_exit_time_us = 16.0, 464 + .sr_exit_time_us = 28.0, 465 + .sr_enter_plus_exit_time_us = 30.0, 466 466 .valid = true, 467 467 }, 468 468 } ··· 474 474 .wm_inst = WM_A, 475 475 .wm_type = WM_TYPE_PSTATE_CHG, 476 476 .pstate_latency_us = 11.65333, 477 - .sr_exit_time_us = 14.0, 478 - .sr_enter_plus_exit_time_us = 16.0, 477 + .sr_exit_time_us = 28.0, 478 + .sr_enter_plus_exit_time_us = 30.0, 479 479 .valid = true, 480 480 }, 481 481 { 482 482 .wm_inst = WM_B, 483 483 .wm_type = WM_TYPE_PSTATE_CHG, 484 484 .pstate_latency_us = 11.65333, 485 - .sr_exit_time_us = 14.0, 486 - .sr_enter_plus_exit_time_us = 16.0, 485 + .sr_exit_time_us = 28.0, 486 + .sr_enter_plus_exit_time_us = 30.0, 487 487 .valid = true, 488 488 }, 489 489 { 490 490 .wm_inst = WM_C, 491 491 .wm_type = WM_TYPE_PSTATE_CHG, 492 492 .pstate_latency_us = 11.65333, 493 - .sr_exit_time_us = 14.0, 494 - .sr_enter_plus_exit_time_us = 16.0, 493 + .sr_exit_time_us = 28.0, 494 + .sr_enter_plus_exit_time_us = 30.0, 495 495 .valid = true, 496 496 }, 497 497 { 498 498 .wm_inst = WM_D, 499 499 .wm_type = WM_TYPE_PSTATE_CHG, 500 500 .pstate_latency_us = 11.65333, 501 - .sr_exit_time_us = 14.0, 502 - .sr_enter_plus_exit_time_us = 16.0, 501 + .sr_exit_time_us = 28.0, 502 + .sr_enter_plus_exit_time_us = 30.0, 503 503 .valid = true, 504 504 }, 505 505 }
+2 -2
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
··· 1112 1112 struct pipe_ctx *pri_pipe; 1113 1113 struct dc_plane_state *plane; 1114 1114 int slice_count; 1115 - } mpc_combines[MAX_SURFACES]; 1115 + } mpc_combines[MAX_PLANES]; 1116 1116 int mpc_combine_count; 1117 1117 }; 1118 1118 ··· 2753 2753 struct _vcs_dpi_voltage_scaling_st entry = {0}; 2754 2754 struct clk_limit_table_entry max_clk_data = {0}; 2755 2755 2756 - unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299; 2756 + unsigned int min_dcfclk_mhz = 399, min_fclk_mhz = 599; 2757 2757 2758 2758 static const unsigned int num_dcfclk_stas = 5; 2759 2759 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
+2 -2
drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
··· 164 164 }, 165 165 }, 166 166 .num_states = 5, 167 - .sr_exit_time_us = 14.0, 168 - .sr_enter_plus_exit_time_us = 16.0, 167 + .sr_exit_time_us = 28.0, 168 + .sr_enter_plus_exit_time_us = 30.0, 169 169 .sr_exit_z8_time_us = 210.0, 170 170 .sr_enter_plus_exit_z8_time_us = 320.0, 171 171 .fclk_change_latency_us = 24.0,
+11 -20
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
··· 341 341 break; 342 342 } 343 343 344 - if (dml2->config.bbox_overrides.clks_table.num_states) 345 - p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states; 346 - 347 344 /* Override from passed values, if available */ 348 345 for (i = 0; i < p->in_states->num_states; i++) { 349 346 if (dml2->config.bbox_overrides.sr_exit_latency_us) { ··· 397 400 } 398 401 /* Copy clocks tables entries, if available */ 399 402 if (dml2->config.bbox_overrides.clks_table.num_states) { 403 + p->in_states->num_states = dml2->config.bbox_overrides.clks_table.num_states; 400 404 401 405 for (i = 0; i < dml2->config.bbox_overrides.clks_table.num_entries_per_clk.num_dcfclk_levels; i++) { 402 406 p->in_states->state_array[i].dcfclk_mhz = dml2->config.bbox_overrides.clks_table.clk_entries[i].dcfclk_mhz; ··· 791 793 } 792 794 } 793 795 794 - /*TODO no support for mpc combine, need rework - should calculate scaling params based on plane+stream*/ 795 - static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_state *in, const struct dc_state *context) 796 + static struct scaler_data get_scaler_data_for_plane(const struct dc_plane_state *in, struct dc_state *context) 796 797 { 797 798 int i; 798 - struct scaler_data data = { 0 }; 799 + struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe; 800 + 801 + memset(temp_pipe, 0, sizeof(struct pipe_ctx)); 799 802 800 803 for (i = 0; i < MAX_PIPES; i++) { 801 804 const struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 802 805 803 806 if (pipe->plane_state == in && !pipe->prev_odm_pipe) { 804 - const struct pipe_ctx *next_pipe = pipe->next_odm_pipe; 807 + temp_pipe->stream = pipe->stream; 808 + temp_pipe->plane_state = pipe->plane_state; 809 + temp_pipe->plane_res.scl_data.taps = pipe->plane_res.scl_data.taps; 805 810 806 - data = context->res_ctx.pipe_ctx[i].plane_res.scl_data; 807 - while (next_pipe) { 808 - data.h_active += next_pipe->plane_res.scl_data.h_active; 809 - data.recout.width += next_pipe->plane_res.scl_data.recout.width; 810 - if (in->rotation == ROTATION_ANGLE_0 || in->rotation == ROTATION_ANGLE_180) { 811 - data.viewport.width += next_pipe->plane_res.scl_data.viewport.width; 812 - } else { 813 - data.viewport.height += next_pipe->plane_res.scl_data.viewport.height; 814 - } 815 - next_pipe = next_pipe->next_odm_pipe; 816 - } 811 + resource_build_scaling_params(temp_pipe); 817 812 break; 818 813 } 819 814 } 820 815 821 816 ASSERT(i < MAX_PIPES); 822 - return data; 817 + return temp_pipe->plane_res.scl_data; 823 818 } 824 819 825 820 static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_stream_state *in) ··· 857 866 out->ScalerEnabled[location] = false; 858 867 } 859 868 860 - static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_plane_state *in, const struct dc_state *context) 869 + static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out, unsigned int location, const struct dc_plane_state *in, struct dc_state *context) 861 870 { 862 871 const struct scaler_data scaler_data = get_scaler_data_for_plane(in, context); 863 872
+1 -1
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
··· 1183 1183 dto_params.timing = &pipe_ctx->stream->timing; 1184 1184 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 1185 1185 if (dccg) { 1186 - dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 1187 1186 dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); 1188 1187 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); 1188 + dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 1189 1189 } 1190 1190 } else if (dccg && dccg->funcs->disable_symclk_se) { 1191 1191 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,
+5 -6
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
··· 2790 2790 } 2791 2791 2792 2792 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2793 - dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 2794 - dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); 2795 - 2796 - phyd32clk = get_phyd32clk_src(link); 2797 - dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 2798 - 2799 2793 dto_params.otg_inst = tg->inst; 2800 2794 dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10; 2801 2795 dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx); 2802 2796 dto_params.timing = &pipe_ctx->stream->timing; 2803 2797 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); 2804 2798 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 2799 + dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 2800 + dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst); 2801 + 2802 + phyd32clk = get_phyd32clk_src(link); 2803 + dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); 2805 2804 } else { 2806 2805 if (dccg->funcs->enable_symclk_se) 2807 2806 dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,
+2
drivers/gpu/drm/amd/display/dc/inc/core_types.h
··· 469 469 unsigned int hpo_dp_link_enc_to_link_idx[MAX_HPO_DP2_LINK_ENCODERS]; 470 470 int hpo_dp_link_enc_ref_cnts[MAX_HPO_DP2_LINK_ENCODERS]; 471 471 bool is_mpc_3dlut_acquired[MAX_PIPES]; 472 + /* solely used for build scalar data in dml2 */ 473 + struct pipe_ctx temp_pipe; 472 474 }; 473 475 474 476 struct dce_bw_output {
+2 -31
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
··· 734 734 smu->adev = adev; 735 735 smu->pm_enabled = !!amdgpu_dpm; 736 736 smu->is_apu = false; 737 - smu->smu_baco.state = SMU_BACO_STATE_NONE; 737 + smu->smu_baco.state = SMU_BACO_STATE_EXIT; 738 738 smu->smu_baco.platform_support = false; 739 739 smu->user_dpm_profile.fan_mode = -1; 740 740 ··· 1954 1954 return 0; 1955 1955 } 1956 1956 1957 - static int smu_reset_mp1_state(struct smu_context *smu) 1958 - { 1959 - struct amdgpu_device *adev = smu->adev; 1960 - int ret = 0; 1961 - 1962 - if ((!adev->in_runpm) && (!adev->in_suspend) && 1963 - (!amdgpu_in_reset(adev))) 1964 - switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 1965 - case IP_VERSION(13, 0, 0): 1966 - case IP_VERSION(13, 0, 7): 1967 - case IP_VERSION(13, 0, 10): 1968 - ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); 1969 - break; 1970 - default: 1971 - break; 1972 - } 1973 - 1974 - return ret; 1975 - } 1976 - 1977 1957 static int smu_hw_fini(void *handle) 1978 1958 { 1979 1959 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1980 1960 struct smu_context *smu = adev->powerplay.pp_handle; 1981 - int ret; 1982 1961 1983 1962 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) 1984 1963 return 0; ··· 1975 1996 1976 1997 adev->pm.dpm_enabled = false; 1977 1998 1978 - ret = smu_smc_hw_cleanup(smu); 1979 - if (ret) 1980 - return ret; 1981 - 1982 - ret = smu_reset_mp1_state(smu); 1983 - if (ret) 1984 - return ret; 1985 - 1986 - return 0; 1999 + return smu_smc_hw_cleanup(smu); 1987 2000 } 1988 2001 1989 2002 static void smu_late_fini(void *handle)
-1
drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
··· 424 424 enum smu_baco_state { 425 425 SMU_BACO_STATE_ENTER = 0, 426 426 SMU_BACO_STATE_EXIT, 427 - SMU_BACO_STATE_NONE, 428 427 }; 429 428 430 429 struct smu_baco_context {
+2 -8
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
··· 2748 2748 2749 2749 switch (mp1_state) { 2750 2750 case PP_MP1_STATE_UNLOAD: 2751 - ret = smu_cmn_send_smc_msg_with_param(smu, 2752 - SMU_MSG_PrepareMp1ForUnload, 2753 - 0x55, NULL); 2754 - 2755 - if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT) 2756 - ret = smu_v13_0_disable_pmfw_state(smu); 2757 - 2751 + ret = smu_cmn_set_mp1_state(smu, mp1_state); 2758 2752 break; 2759 2753 default: 2760 2754 /* Ignore others */ ··· 2944 2950 { 2945 2951 struct amdgpu_device *adev = smu->adev; 2946 2952 2947 - switch (adev->ip_versions[MP1_HWIP][0]) { 2953 + switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2948 2954 case IP_VERSION(13, 0, 0): 2949 2955 return smu->smc_fw_version >= 0x004e6300; 2950 2956 case IP_VERSION(13, 0, 10):
+1 -7
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
··· 2505 2505 2506 2506 switch (mp1_state) { 2507 2507 case PP_MP1_STATE_UNLOAD: 2508 - ret = smu_cmn_send_smc_msg_with_param(smu, 2509 - SMU_MSG_PrepareMp1ForUnload, 2510 - 0x55, NULL); 2511 - 2512 - if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT) 2513 - ret = smu_v13_0_disable_pmfw_state(smu); 2514 - 2508 + ret = smu_cmn_set_mp1_state(smu, mp1_state); 2515 2509 break; 2516 2510 default: 2517 2511 /* Ignore others */
+19 -7
drivers/gpu/drm/nouveau/nouveau_fence.c
··· 103 103 void 104 104 nouveau_fence_context_del(struct nouveau_fence_chan *fctx) 105 105 { 106 + cancel_work_sync(&fctx->uevent_work); 106 107 nouveau_fence_context_kill(fctx, 0); 107 108 nvif_event_dtor(&fctx->event); 108 109 fctx->dead = 1; ··· 146 145 return drop; 147 146 } 148 147 149 - static int 150 - nouveau_fence_wait_uevent_handler(struct nvif_event *event, void *repv, u32 repc) 148 + static void 149 + nouveau_fence_uevent_work(struct work_struct *work) 151 150 { 152 - struct nouveau_fence_chan *fctx = container_of(event, typeof(*fctx), event); 151 + struct nouveau_fence_chan *fctx = container_of(work, struct nouveau_fence_chan, 152 + uevent_work); 153 153 unsigned long flags; 154 - int ret = NVIF_EVENT_KEEP; 154 + int drop = 0; 155 155 156 156 spin_lock_irqsave(&fctx->lock, flags); 157 157 if (!list_empty(&fctx->pending)) { ··· 162 160 fence = list_entry(fctx->pending.next, typeof(*fence), head); 163 161 chan = rcu_dereference_protected(fence->channel, lockdep_is_held(&fctx->lock)); 164 162 if (nouveau_fence_update(chan, fctx)) 165 - ret = NVIF_EVENT_DROP; 163 + drop = 1; 166 164 } 167 - spin_unlock_irqrestore(&fctx->lock, flags); 165 + if (drop) 166 + nvif_event_block(&fctx->event); 168 167 169 - return ret; 168 + spin_unlock_irqrestore(&fctx->lock, flags); 169 + } 170 + 171 + static int 172 + nouveau_fence_wait_uevent_handler(struct nvif_event *event, void *repv, u32 repc) 173 + { 174 + struct nouveau_fence_chan *fctx = container_of(event, typeof(*fctx), event); 175 + schedule_work(&fctx->uevent_work); 176 + return NVIF_EVENT_KEEP; 170 177 } 171 178 172 179 void ··· 189 178 } args; 190 179 int ret; 191 180 181 + INIT_WORK(&fctx->uevent_work, nouveau_fence_uevent_work); 192 182 INIT_LIST_HEAD(&fctx->flip); 193 183 INIT_LIST_HEAD(&fctx->pending); 194 184 spin_lock_init(&fctx->lock);
+1
drivers/gpu/drm/nouveau/nouveau_fence.h
··· 44 44 u32 context; 45 45 char name[32]; 46 46 47 + struct work_struct uevent_work; 47 48 struct nvif_event event; 48 49 int notify_ref, dead, killed; 49 50 };
+1 -1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
··· 1078 1078 if (IS_ERR(rpc)) 1079 1079 return PTR_ERR(rpc); 1080 1080 1081 - rpc->size = sizeof(*rpc); 1082 1081 rpc->numEntries = NV_GSP_REG_NUM_ENTRIES; 1083 1082 1084 1083 str_offset = offsetof(typeof(*rpc), entries[NV_GSP_REG_NUM_ENTRIES]); ··· 1093 1094 strings += name_len; 1094 1095 str_offset += name_len; 1095 1096 } 1097 + rpc->size = str_offset; 1096 1098 1097 1099 return nvkm_gsp_rpc_wr(gsp, rpc, false); 1098 1100 }
+1
drivers/gpu/drm/virtio/virtgpu_drv.c
··· 94 94 goto err_free; 95 95 } 96 96 97 + dma_set_max_seg_size(dev->dev, dma_max_mapping_size(dev->dev) ?: UINT_MAX); 97 98 ret = virtio_gpu_init(vdev, dev); 98 99 if (ret) 99 100 goto err_free;
+2 -2
drivers/gpu/drm/xe/abi/guc_actions_abi.h
··· 50 50 51 51 #define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN (GUC_HXG_REQUEST_MSG_MIN_LEN + 3u) 52 52 #define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0 53 - #define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffff << 16) 54 - #define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN (0xffff << 0) 53 + #define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffffu << 16) 54 + #define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN (0xffffu << 0) 55 55 #define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32 GUC_HXG_REQUEST_MSG_n_DATAn 56 56 #define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64 GUC_HXG_REQUEST_MSG_n_DATAn 57 57
+2 -2
drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
··· 242 242 (HOST2GUC_PC_SLPC_REQUEST_REQUEST_MSG_MIN_LEN + \ 243 243 HOST2GUC_PC_SLPC_EVENT_MAX_INPUT_ARGS) 244 244 #define HOST2GUC_PC_SLPC_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0 245 - #define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID (0xff << 8) 246 - #define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC (0xff << 0) 245 + #define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID (0xffu << 8) 246 + #define HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC (0xffu << 0) 247 247 #define HOST2GUC_PC_SLPC_REQUEST_MSG_N_EVENT_DATA_N GUC_HXG_REQUEST_MSG_n_DATAn 248 248 249 249 #endif
+4 -4
drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h
··· 82 82 #define GUC_CTB_HDR_LEN 1u 83 83 #define GUC_CTB_MSG_MIN_LEN GUC_CTB_HDR_LEN 84 84 #define GUC_CTB_MSG_MAX_LEN 256u 85 - #define GUC_CTB_MSG_0_FENCE (0xffff << 16) 86 - #define GUC_CTB_MSG_0_FORMAT (0xf << 12) 85 + #define GUC_CTB_MSG_0_FENCE (0xffffu << 16) 86 + #define GUC_CTB_MSG_0_FORMAT (0xfu << 12) 87 87 #define GUC_CTB_FORMAT_HXG 0u 88 - #define GUC_CTB_MSG_0_RESERVED (0xf << 8) 89 - #define GUC_CTB_MSG_0_NUM_DWORDS (0xff << 0) 88 + #define GUC_CTB_MSG_0_RESERVED (0xfu << 8) 89 + #define GUC_CTB_MSG_0_NUM_DWORDS (0xffu << 0) 90 90 91 91 /** 92 92 * DOC: CTB HXG Message
+3 -3
drivers/gpu/drm/xe/abi/guc_klvs_abi.h
··· 31 31 */ 32 32 33 33 #define GUC_KLV_LEN_MIN 1u 34 - #define GUC_KLV_0_KEY (0xffff << 16) 35 - #define GUC_KLV_0_LEN (0xffff << 0) 36 - #define GUC_KLV_n_VALUE (0xffffffff << 0) 34 + #define GUC_KLV_0_KEY (0xffffu << 16) 35 + #define GUC_KLV_0_LEN (0xffffu << 0) 36 + #define GUC_KLV_n_VALUE (0xffffffffu << 0) 37 37 38 38 /** 39 39 * DOC: GuC Self Config KLVs
+10 -10
drivers/gpu/drm/xe/abi/guc_messages_abi.h
··· 40 40 */ 41 41 42 42 #define GUC_HXG_MSG_MIN_LEN 1u 43 - #define GUC_HXG_MSG_0_ORIGIN (0x1 << 31) 43 + #define GUC_HXG_MSG_0_ORIGIN (0x1u << 31) 44 44 #define GUC_HXG_ORIGIN_HOST 0u 45 45 #define GUC_HXG_ORIGIN_GUC 1u 46 - #define GUC_HXG_MSG_0_TYPE (0x7 << 28) 46 + #define GUC_HXG_MSG_0_TYPE (0x7u << 28) 47 47 #define GUC_HXG_TYPE_REQUEST 0u 48 48 #define GUC_HXG_TYPE_EVENT 1u 49 49 #define GUC_HXG_TYPE_NO_RESPONSE_BUSY 3u 50 50 #define GUC_HXG_TYPE_NO_RESPONSE_RETRY 5u 51 51 #define GUC_HXG_TYPE_RESPONSE_FAILURE 6u 52 52 #define GUC_HXG_TYPE_RESPONSE_SUCCESS 7u 53 - #define GUC_HXG_MSG_0_AUX (0xfffffff << 0) 54 - #define GUC_HXG_MSG_n_PAYLOAD (0xffffffff << 0) 53 + #define GUC_HXG_MSG_0_AUX (0xfffffffu << 0) 54 + #define GUC_HXG_MSG_n_PAYLOAD (0xffffffffu << 0) 55 55 56 56 /** 57 57 * DOC: HXG Request ··· 85 85 */ 86 86 87 87 #define GUC_HXG_REQUEST_MSG_MIN_LEN GUC_HXG_MSG_MIN_LEN 88 - #define GUC_HXG_REQUEST_MSG_0_DATA0 (0xfff << 16) 89 - #define GUC_HXG_REQUEST_MSG_0_ACTION (0xffff << 0) 88 + #define GUC_HXG_REQUEST_MSG_0_DATA0 (0xfffu << 16) 89 + #define GUC_HXG_REQUEST_MSG_0_ACTION (0xffffu << 0) 90 90 #define GUC_HXG_REQUEST_MSG_n_DATAn GUC_HXG_MSG_n_PAYLOAD 91 91 92 92 /** ··· 117 117 */ 118 118 119 119 #define GUC_HXG_EVENT_MSG_MIN_LEN GUC_HXG_MSG_MIN_LEN 120 - #define GUC_HXG_EVENT_MSG_0_DATA0 (0xfff << 16) 121 - #define GUC_HXG_EVENT_MSG_0_ACTION (0xffff << 0) 120 + #define GUC_HXG_EVENT_MSG_0_DATA0 (0xfffu << 16) 121 + #define GUC_HXG_EVENT_MSG_0_ACTION (0xffffu << 0) 122 122 #define GUC_HXG_EVENT_MSG_n_DATAn GUC_HXG_MSG_n_PAYLOAD 123 123 124 124 /** ··· 188 188 */ 189 189 190 190 #define GUC_HXG_FAILURE_MSG_LEN GUC_HXG_MSG_MIN_LEN 191 - #define GUC_HXG_FAILURE_MSG_0_HINT (0xfff << 16) 192 - #define GUC_HXG_FAILURE_MSG_0_ERROR (0xffff << 0) 191 + #define GUC_HXG_FAILURE_MSG_0_HINT (0xfffu << 16) 192 + #define GUC_HXG_FAILURE_MSG_0_ERROR (0xffffu << 0) 193 193 194 194 /** 195 195 * DOC: HXG Response
+9 -1
drivers/gpu/drm/xe/xe_exec.c
··· 111 111 u64 addresses[XE_HW_ENGINE_MAX_INSTANCE]; 112 112 struct drm_gpuvm_exec vm_exec = {.extra.fn = xe_exec_fn}; 113 113 struct drm_exec *exec = &vm_exec.exec; 114 - u32 i, num_syncs = 0; 114 + u32 i, num_syncs = 0, num_ufence = 0; 115 115 struct xe_sched_job *job; 116 116 struct dma_fence *rebind_fence; 117 117 struct xe_vm *vm; ··· 157 157 SYNC_PARSE_FLAG_LR_MODE : 0)); 158 158 if (err) 159 159 goto err_syncs; 160 + 161 + if (xe_sync_is_ufence(&syncs[i])) 162 + num_ufence++; 163 + } 164 + 165 + if (XE_IOCTL_DBG(xe, num_ufence > 1)) { 166 + err = -EINVAL; 167 + goto err_syncs; 160 168 } 161 169 162 170 if (xe_exec_queue_is_parallel(q)) {
+2 -2
drivers/gpu/drm/xe/xe_gt_mcr.c
··· 480 480 * to synchronize with external clients (e.g., firmware), so a semaphore 481 481 * register will also need to be taken. 482 482 */ 483 - static void mcr_lock(struct xe_gt *gt) 483 + static void mcr_lock(struct xe_gt *gt) __acquires(&gt->mcr_lock) 484 484 { 485 485 struct xe_device *xe = gt_to_xe(gt); 486 486 int ret = 0; ··· 500 500 drm_WARN_ON_ONCE(&xe->drm, ret == -ETIMEDOUT); 501 501 } 502 502 503 - static void mcr_unlock(struct xe_gt *gt) 503 + static void mcr_unlock(struct xe_gt *gt) __releases(&gt->mcr_lock) 504 504 { 505 505 /* Release hardware semaphore - this is done by writing 1 to the register */ 506 506 if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270)
+7 -4
drivers/gpu/drm/xe/xe_gt_pagefault.c
··· 165 165 goto unlock_vm; 166 166 } 167 167 168 - if (!xe_vma_is_userptr(vma) || !xe_vma_userptr_check_repin(vma)) { 168 + if (!xe_vma_is_userptr(vma) || 169 + !xe_vma_userptr_check_repin(to_userptr_vma(vma))) { 169 170 downgrade_write(&vm->lock); 170 171 write_locked = false; 171 172 } ··· 182 181 /* TODO: Validate fault */ 183 182 184 183 if (xe_vma_is_userptr(vma) && write_locked) { 184 + struct xe_userptr_vma *uvma = to_userptr_vma(vma); 185 + 185 186 spin_lock(&vm->userptr.invalidated_lock); 186 - list_del_init(&vma->userptr.invalidate_link); 187 + list_del_init(&uvma->userptr.invalidate_link); 187 188 spin_unlock(&vm->userptr.invalidated_lock); 188 189 189 - ret = xe_vma_userptr_pin_pages(vma); 190 + ret = xe_vma_userptr_pin_pages(uvma); 190 191 if (ret) 191 192 goto unlock_vm; 192 193 ··· 223 220 dma_fence_put(fence); 224 221 225 222 if (xe_vma_is_userptr(vma)) 226 - ret = xe_vma_userptr_check_repin(vma); 223 + ret = xe_vma_userptr_check_repin(to_userptr_vma(vma)); 227 224 vma->usm.tile_invalidated &= ~BIT(tile->id); 228 225 229 226 unlock_dma_resv:
+2
drivers/gpu/drm/xe/xe_guc_pc.c
··· 963 963 struct xe_device *xe = pc_to_xe(pc); 964 964 965 965 if (xe->info.skip_guc_pc) { 966 + xe_device_mem_access_get(xe); 966 967 xe_gt_idle_disable_c6(pc_to_gt(pc)); 968 + xe_device_mem_access_put(xe); 967 969 return; 968 970 } 969 971
+3 -3
drivers/gpu/drm/xe/xe_hw_fence.c
··· 217 217 if (!fence) 218 218 return ERR_PTR(-ENOMEM); 219 219 220 - dma_fence_init(&fence->dma, &xe_hw_fence_ops, &ctx->irq->lock, 221 - ctx->dma_fence_ctx, ctx->next_seqno++); 222 - 223 220 fence->ctx = ctx; 224 221 fence->seqno_map = seqno_map; 225 222 INIT_LIST_HEAD(&fence->irq_link); 223 + 224 + dma_fence_init(&fence->dma, &xe_hw_fence_ops, &ctx->irq->lock, 225 + ctx->dma_fence_ctx, ctx->next_seqno++); 226 226 227 227 trace_xe_hw_fence_create(fence); 228 228
+7 -7
drivers/gpu/drm/xe/xe_lrc.c
··· 21 21 #include "xe_map.h" 22 22 #include "xe_vm.h" 23 23 24 - #define CTX_VALID (1 << 0) 25 - #define CTX_PRIVILEGE (1 << 8) 26 - #define CTX_ADDRESSING_MODE_SHIFT 3 27 - #define LEGACY_64B_CONTEXT 3 24 + #define LRC_VALID (1 << 0) 25 + #define LRC_PRIVILEGE (1 << 8) 26 + #define LRC_ADDRESSING_MODE_SHIFT 3 27 + #define LRC_LEGACY_64B_CONTEXT 3 28 28 29 29 #define ENGINE_CLASS_SHIFT 61 30 30 #define ENGINE_INSTANCE_SHIFT 48 ··· 762 762 (q->usm.acc_notify << ACC_NOTIFY_S) | 763 763 q->usm.acc_trigger); 764 764 765 - lrc->desc = CTX_VALID; 766 - lrc->desc |= LEGACY_64B_CONTEXT << CTX_ADDRESSING_MODE_SHIFT; 765 + lrc->desc = LRC_VALID; 766 + lrc->desc |= LRC_LEGACY_64B_CONTEXT << LRC_ADDRESSING_MODE_SHIFT; 767 767 /* TODO: Priority */ 768 768 769 769 /* While this appears to have something about privileged batches or 770 770 * some such, it really just means PPGTT mode. 771 771 */ 772 772 if (vm) 773 - lrc->desc |= CTX_PRIVILEGE; 773 + lrc->desc |= LRC_PRIVILEGE; 774 774 775 775 if (GRAPHICS_VERx100(xe) < 1250) { 776 776 lrc->desc |= (u64)hwe->instance << ENGINE_INSTANCE_SHIFT;
+16 -16
drivers/gpu/drm/xe/xe_pt.c
··· 618 618 619 619 if (!xe_vma_is_null(vma)) { 620 620 if (xe_vma_is_userptr(vma)) 621 - xe_res_first_sg(vma->userptr.sg, 0, xe_vma_size(vma), 622 - &curs); 621 + xe_res_first_sg(to_userptr_vma(vma)->userptr.sg, 0, 622 + xe_vma_size(vma), &curs); 623 623 else if (xe_bo_is_vram(bo) || xe_bo_is_stolen(bo)) 624 624 xe_res_first(bo->ttm.resource, xe_vma_bo_offset(vma), 625 625 xe_vma_size(vma), &curs); ··· 906 906 907 907 #ifdef CONFIG_DRM_XE_USERPTR_INVAL_INJECT 908 908 909 - static int xe_pt_userptr_inject_eagain(struct xe_vma *vma) 909 + static int xe_pt_userptr_inject_eagain(struct xe_userptr_vma *uvma) 910 910 { 911 - u32 divisor = vma->userptr.divisor ? vma->userptr.divisor : 2; 911 + u32 divisor = uvma->userptr.divisor ? uvma->userptr.divisor : 2; 912 912 static u32 count; 913 913 914 914 if (count++ % divisor == divisor - 1) { 915 - struct xe_vm *vm = xe_vma_vm(vma); 915 + struct xe_vm *vm = xe_vma_vm(&uvma->vma); 916 916 917 - vma->userptr.divisor = divisor << 1; 917 + uvma->userptr.divisor = divisor << 1; 918 918 spin_lock(&vm->userptr.invalidated_lock); 919 - list_move_tail(&vma->userptr.invalidate_link, 919 + list_move_tail(&uvma->userptr.invalidate_link, 920 920 &vm->userptr.invalidated); 921 921 spin_unlock(&vm->userptr.invalidated_lock); 922 922 return true; ··· 927 927 928 928 #else 929 929 930 - static bool xe_pt_userptr_inject_eagain(struct xe_vma *vma) 930 + static bool xe_pt_userptr_inject_eagain(struct xe_userptr_vma *uvma) 931 931 { 932 932 return false; 933 933 } ··· 1000 1000 { 1001 1001 struct xe_pt_migrate_pt_update *userptr_update = 1002 1002 container_of(pt_update, typeof(*userptr_update), base); 1003 - struct xe_vma *vma = pt_update->vma; 1004 - unsigned long notifier_seq = vma->userptr.notifier_seq; 1005 - struct xe_vm *vm = xe_vma_vm(vma); 1003 + struct xe_userptr_vma *uvma = to_userptr_vma(pt_update->vma); 1004 + unsigned long notifier_seq = uvma->userptr.notifier_seq; 1005 + struct xe_vm *vm = xe_vma_vm(&uvma->vma); 1006 1006 int err = xe_pt_vm_dependencies(pt_update->job, 1007 1007 &vm->rftree[pt_update->tile_id], 1008 1008 pt_update->start, ··· 1023 1023 */ 1024 1024 do { 1025 1025 down_read(&vm->userptr.notifier_lock); 1026 - if (!mmu_interval_read_retry(&vma->userptr.notifier, 1026 + if (!mmu_interval_read_retry(&uvma->userptr.notifier, 1027 1027 notifier_seq)) 1028 1028 break; 1029 1029 ··· 1032 1032 if (userptr_update->bind) 1033 1033 return -EAGAIN; 1034 1034 1035 - notifier_seq = mmu_interval_read_begin(&vma->userptr.notifier); 1035 + notifier_seq = mmu_interval_read_begin(&uvma->userptr.notifier); 1036 1036 } while (true); 1037 1037 1038 1038 /* Inject errors to test_whether they are handled correctly */ 1039 - if (userptr_update->bind && xe_pt_userptr_inject_eagain(vma)) { 1039 + if (userptr_update->bind && xe_pt_userptr_inject_eagain(uvma)) { 1040 1040 up_read(&vm->userptr.notifier_lock); 1041 1041 return -EAGAIN; 1042 1042 } ··· 1297 1297 vma->tile_present |= BIT(tile->id); 1298 1298 1299 1299 if (bind_pt_update.locked) { 1300 - vma->userptr.initial_bind = true; 1300 + to_userptr_vma(vma)->userptr.initial_bind = true; 1301 1301 up_read(&vm->userptr.notifier_lock); 1302 1302 xe_bo_put_commit(&deferred); 1303 1303 } ··· 1642 1642 1643 1643 if (!vma->tile_present) { 1644 1644 spin_lock(&vm->userptr.invalidated_lock); 1645 - list_del_init(&vma->userptr.invalidate_link); 1645 + list_del_init(&to_userptr_vma(vma)->userptr.invalidate_link); 1646 1646 spin_unlock(&vm->userptr.invalidated_lock); 1647 1647 } 1648 1648 up_read(&vm->userptr.notifier_lock);
+25 -25
drivers/gpu/drm/xe/xe_query.c
··· 459 459 sizeof_field(struct xe_gt, fuse_topo.eu_mask_per_dss)); 460 460 } 461 461 462 - static void __user *copy_mask(void __user *ptr, 463 - struct drm_xe_query_topology_mask *topo, 464 - void *mask, size_t mask_size) 462 + static int copy_mask(void __user **ptr, 463 + struct drm_xe_query_topology_mask *topo, 464 + void *mask, size_t mask_size) 465 465 { 466 466 topo->num_bytes = mask_size; 467 467 468 - if (copy_to_user(ptr, topo, sizeof(*topo))) 469 - return ERR_PTR(-EFAULT); 470 - ptr += sizeof(topo); 468 + if (copy_to_user(*ptr, topo, sizeof(*topo))) 469 + return -EFAULT; 470 + *ptr += sizeof(topo); 471 471 472 - if (copy_to_user(ptr, mask, mask_size)) 473 - return ERR_PTR(-EFAULT); 474 - ptr += mask_size; 472 + if (copy_to_user(*ptr, mask, mask_size)) 473 + return -EFAULT; 474 + *ptr += mask_size; 475 475 476 - return ptr; 476 + return 0; 477 477 } 478 478 479 479 static int query_gt_topology(struct xe_device *xe, ··· 493 493 } 494 494 495 495 for_each_gt(gt, xe, id) { 496 + int err; 497 + 496 498 topo.gt_id = id; 497 499 498 500 topo.type = DRM_XE_TOPO_DSS_GEOMETRY; 499 - query_ptr = copy_mask(query_ptr, &topo, 500 - gt->fuse_topo.g_dss_mask, 501 - sizeof(gt->fuse_topo.g_dss_mask)); 502 - if (IS_ERR(query_ptr)) 503 - return PTR_ERR(query_ptr); 501 + err = copy_mask(&query_ptr, &topo, gt->fuse_topo.g_dss_mask, 502 + sizeof(gt->fuse_topo.g_dss_mask)); 503 + if (err) 504 + return err; 504 505 505 506 topo.type = DRM_XE_TOPO_DSS_COMPUTE; 506 - query_ptr = copy_mask(query_ptr, &topo, 507 - gt->fuse_topo.c_dss_mask, 508 - sizeof(gt->fuse_topo.c_dss_mask)); 509 - if (IS_ERR(query_ptr)) 510 - return PTR_ERR(query_ptr); 507 + err = copy_mask(&query_ptr, &topo, gt->fuse_topo.c_dss_mask, 508 + sizeof(gt->fuse_topo.c_dss_mask)); 509 + if (err) 510 + return err; 511 511 512 512 topo.type = DRM_XE_TOPO_EU_PER_DSS; 513 - query_ptr = copy_mask(query_ptr, &topo, 514 - gt->fuse_topo.eu_mask_per_dss, 515 - sizeof(gt->fuse_topo.eu_mask_per_dss)); 516 - if (IS_ERR(query_ptr)) 517 - return PTR_ERR(query_ptr); 513 + err = copy_mask(&query_ptr, &topo, 514 + gt->fuse_topo.eu_mask_per_dss, 515 + sizeof(gt->fuse_topo.eu_mask_per_dss)); 516 + if (err) 517 + return err; 518 518 } 519 519 520 520 return 0;
+5
drivers/gpu/drm/xe/xe_sync.h
··· 33 33 xe_sync_in_fence_get(struct xe_sync_entry *sync, int num_sync, 34 34 struct xe_exec_queue *q, struct xe_vm *vm); 35 35 36 + static inline bool xe_sync_is_ufence(struct xe_sync_entry *sync) 37 + { 38 + return !!sync->ufence; 39 + } 40 + 36 41 #endif
+99 -66
drivers/gpu/drm/xe/xe_vm.c
··· 46 46 47 47 /** 48 48 * xe_vma_userptr_check_repin() - Advisory check for repin needed 49 - * @vma: The userptr vma 49 + * @uvma: The userptr vma 50 50 * 51 51 * Check if the userptr vma has been invalidated since last successful 52 52 * repin. The check is advisory only and can the function can be called ··· 56 56 * 57 57 * Return: 0 if userptr vma is valid, -EAGAIN otherwise; repin recommended. 58 58 */ 59 - int xe_vma_userptr_check_repin(struct xe_vma *vma) 59 + int xe_vma_userptr_check_repin(struct xe_userptr_vma *uvma) 60 60 { 61 - return mmu_interval_check_retry(&vma->userptr.notifier, 62 - vma->userptr.notifier_seq) ? 61 + return mmu_interval_check_retry(&uvma->userptr.notifier, 62 + uvma->userptr.notifier_seq) ? 63 63 -EAGAIN : 0; 64 64 } 65 65 66 - int xe_vma_userptr_pin_pages(struct xe_vma *vma) 66 + int xe_vma_userptr_pin_pages(struct xe_userptr_vma *uvma) 67 67 { 68 + struct xe_userptr *userptr = &uvma->userptr; 69 + struct xe_vma *vma = &uvma->vma; 68 70 struct xe_vm *vm = xe_vma_vm(vma); 69 71 struct xe_device *xe = vm->xe; 70 72 const unsigned long num_pages = xe_vma_size(vma) >> PAGE_SHIFT; ··· 82 80 if (vma->gpuva.flags & XE_VMA_DESTROYED) 83 81 return 0; 84 82 85 - notifier_seq = mmu_interval_read_begin(&vma->userptr.notifier); 86 - if (notifier_seq == vma->userptr.notifier_seq) 83 + notifier_seq = mmu_interval_read_begin(&userptr->notifier); 84 + if (notifier_seq == userptr->notifier_seq) 87 85 return 0; 88 86 89 87 pages = kvmalloc_array(num_pages, sizeof(*pages), GFP_KERNEL); 90 88 if (!pages) 91 89 return -ENOMEM; 92 90 93 - if (vma->userptr.sg) { 91 + if (userptr->sg) { 94 92 dma_unmap_sgtable(xe->drm.dev, 95 - vma->userptr.sg, 93 + userptr->sg, 96 94 read_only ? DMA_TO_DEVICE : 97 95 DMA_BIDIRECTIONAL, 0); 98 - sg_free_table(vma->userptr.sg); 99 - vma->userptr.sg = NULL; 96 + sg_free_table(userptr->sg); 97 + userptr->sg = NULL; 100 98 } 101 99 102 100 pinned = ret = 0; 103 101 if (in_kthread) { 104 - if (!mmget_not_zero(vma->userptr.notifier.mm)) { 102 + if (!mmget_not_zero(userptr->notifier.mm)) { 105 103 ret = -EFAULT; 106 104 goto mm_closed; 107 105 } 108 - kthread_use_mm(vma->userptr.notifier.mm); 106 + kthread_use_mm(userptr->notifier.mm); 109 107 } 110 108 111 109 while (pinned < num_pages) { ··· 125 123 } 126 124 127 125 if (in_kthread) { 128 - kthread_unuse_mm(vma->userptr.notifier.mm); 129 - mmput(vma->userptr.notifier.mm); 126 + kthread_unuse_mm(userptr->notifier.mm); 127 + mmput(userptr->notifier.mm); 130 128 } 131 129 mm_closed: 132 130 if (ret) 133 131 goto out; 134 132 135 - ret = sg_alloc_table_from_pages_segment(&vma->userptr.sgt, pages, 133 + ret = sg_alloc_table_from_pages_segment(&userptr->sgt, pages, 136 134 pinned, 0, 137 135 (u64)pinned << PAGE_SHIFT, 138 136 xe_sg_segment_size(xe->drm.dev), 139 137 GFP_KERNEL); 140 138 if (ret) { 141 - vma->userptr.sg = NULL; 139 + userptr->sg = NULL; 142 140 goto out; 143 141 } 144 - vma->userptr.sg = &vma->userptr.sgt; 142 + userptr->sg = &userptr->sgt; 145 143 146 - ret = dma_map_sgtable(xe->drm.dev, vma->userptr.sg, 144 + ret = dma_map_sgtable(xe->drm.dev, userptr->sg, 147 145 read_only ? DMA_TO_DEVICE : 148 146 DMA_BIDIRECTIONAL, 149 147 DMA_ATTR_SKIP_CPU_SYNC | 150 148 DMA_ATTR_NO_KERNEL_MAPPING); 151 149 if (ret) { 152 - sg_free_table(vma->userptr.sg); 153 - vma->userptr.sg = NULL; 150 + sg_free_table(userptr->sg); 151 + userptr->sg = NULL; 154 152 goto out; 155 153 } 156 154 ··· 169 167 kvfree(pages); 170 168 171 169 if (!(ret < 0)) { 172 - vma->userptr.notifier_seq = notifier_seq; 173 - if (xe_vma_userptr_check_repin(vma) == -EAGAIN) 170 + userptr->notifier_seq = notifier_seq; 171 + if (xe_vma_userptr_check_repin(uvma) == -EAGAIN) 174 172 goto retry; 175 173 } 176 174 ··· 637 635 const struct mmu_notifier_range *range, 638 636 unsigned long cur_seq) 639 637 { 640 - struct xe_vma *vma = container_of(mni, struct xe_vma, userptr.notifier); 638 + struct xe_userptr *userptr = container_of(mni, typeof(*userptr), notifier); 639 + struct xe_userptr_vma *uvma = container_of(userptr, typeof(*uvma), userptr); 640 + struct xe_vma *vma = &uvma->vma; 641 641 struct xe_vm *vm = xe_vma_vm(vma); 642 642 struct dma_resv_iter cursor; 643 643 struct dma_fence *fence; ··· 655 651 mmu_interval_set_seq(mni, cur_seq); 656 652 657 653 /* No need to stop gpu access if the userptr is not yet bound. */ 658 - if (!vma->userptr.initial_bind) { 654 + if (!userptr->initial_bind) { 659 655 up_write(&vm->userptr.notifier_lock); 660 656 return true; 661 657 } ··· 667 663 if (!xe_vm_in_fault_mode(vm) && 668 664 !(vma->gpuva.flags & XE_VMA_DESTROYED) && vma->tile_present) { 669 665 spin_lock(&vm->userptr.invalidated_lock); 670 - list_move_tail(&vma->userptr.invalidate_link, 666 + list_move_tail(&userptr->invalidate_link, 671 667 &vm->userptr.invalidated); 672 668 spin_unlock(&vm->userptr.invalidated_lock); 673 669 } ··· 707 703 708 704 int xe_vm_userptr_pin(struct xe_vm *vm) 709 705 { 710 - struct xe_vma *vma, *next; 706 + struct xe_userptr_vma *uvma, *next; 711 707 int err = 0; 712 708 LIST_HEAD(tmp_evict); 713 709 ··· 715 711 716 712 /* Collect invalidated userptrs */ 717 713 spin_lock(&vm->userptr.invalidated_lock); 718 - list_for_each_entry_safe(vma, next, &vm->userptr.invalidated, 714 + list_for_each_entry_safe(uvma, next, &vm->userptr.invalidated, 719 715 userptr.invalidate_link) { 720 - list_del_init(&vma->userptr.invalidate_link); 721 - list_move_tail(&vma->combined_links.userptr, 716 + list_del_init(&uvma->userptr.invalidate_link); 717 + list_move_tail(&uvma->userptr.repin_link, 722 718 &vm->userptr.repin_list); 723 719 } 724 720 spin_unlock(&vm->userptr.invalidated_lock); 725 721 726 722 /* Pin and move to temporary list */ 727 - list_for_each_entry_safe(vma, next, &vm->userptr.repin_list, 728 - combined_links.userptr) { 729 - err = xe_vma_userptr_pin_pages(vma); 723 + list_for_each_entry_safe(uvma, next, &vm->userptr.repin_list, 724 + userptr.repin_link) { 725 + err = xe_vma_userptr_pin_pages(uvma); 730 726 if (err < 0) 731 727 return err; 732 728 733 - list_move_tail(&vma->combined_links.userptr, &vm->rebind_list); 729 + list_del_init(&uvma->userptr.repin_link); 730 + list_move_tail(&uvma->vma.combined_links.rebind, &vm->rebind_list); 734 731 } 735 732 736 733 return 0; ··· 787 782 return fence; 788 783 } 789 784 785 + static void xe_vma_free(struct xe_vma *vma) 786 + { 787 + if (xe_vma_is_userptr(vma)) 788 + kfree(to_userptr_vma(vma)); 789 + else 790 + kfree(vma); 791 + } 792 + 790 793 #define VMA_CREATE_FLAG_READ_ONLY BIT(0) 791 794 #define VMA_CREATE_FLAG_IS_NULL BIT(1) 792 795 ··· 813 800 xe_assert(vm->xe, start < end); 814 801 xe_assert(vm->xe, end < vm->size); 815 802 816 - if (!bo && !is_null) /* userptr */ 803 + /* 804 + * Allocate and ensure that the xe_vma_is_userptr() return 805 + * matches what was allocated. 806 + */ 807 + if (!bo && !is_null) { 808 + struct xe_userptr_vma *uvma = kzalloc(sizeof(*uvma), GFP_KERNEL); 809 + 810 + if (!uvma) 811 + return ERR_PTR(-ENOMEM); 812 + 813 + vma = &uvma->vma; 814 + } else { 817 815 vma = kzalloc(sizeof(*vma), GFP_KERNEL); 818 - else 819 - vma = kzalloc(sizeof(*vma) - sizeof(struct xe_userptr), 820 - GFP_KERNEL); 821 - if (!vma) { 822 - vma = ERR_PTR(-ENOMEM); 823 - return vma; 816 + if (!vma) 817 + return ERR_PTR(-ENOMEM); 818 + 819 + if (is_null) 820 + vma->gpuva.flags |= DRM_GPUVA_SPARSE; 821 + if (bo) 822 + vma->gpuva.gem.obj = &bo->ttm.base; 824 823 } 825 824 826 825 INIT_LIST_HEAD(&vma->combined_links.rebind); ··· 843 818 vma->gpuva.va.range = end - start + 1; 844 819 if (read_only) 845 820 vma->gpuva.flags |= XE_VMA_READ_ONLY; 846 - if (is_null) 847 - vma->gpuva.flags |= DRM_GPUVA_SPARSE; 848 821 849 822 for_each_tile(tile, vm->xe, id) 850 823 vma->tile_mask |= 0x1 << id; ··· 859 836 860 837 vm_bo = drm_gpuvm_bo_obtain(vma->gpuva.vm, &bo->ttm.base); 861 838 if (IS_ERR(vm_bo)) { 862 - kfree(vma); 839 + xe_vma_free(vma); 863 840 return ERR_CAST(vm_bo); 864 841 } 865 842 866 843 drm_gpuvm_bo_extobj_add(vm_bo); 867 844 drm_gem_object_get(&bo->ttm.base); 868 - vma->gpuva.gem.obj = &bo->ttm.base; 869 845 vma->gpuva.gem.offset = bo_offset_or_userptr; 870 846 drm_gpuva_link(&vma->gpuva, vm_bo); 871 847 drm_gpuvm_bo_put(vm_bo); 872 848 } else /* userptr or null */ { 873 849 if (!is_null) { 850 + struct xe_userptr *userptr = &to_userptr_vma(vma)->userptr; 874 851 u64 size = end - start + 1; 875 852 int err; 876 853 877 - INIT_LIST_HEAD(&vma->userptr.invalidate_link); 854 + INIT_LIST_HEAD(&userptr->invalidate_link); 855 + INIT_LIST_HEAD(&userptr->repin_link); 878 856 vma->gpuva.gem.offset = bo_offset_or_userptr; 879 857 880 - err = mmu_interval_notifier_insert(&vma->userptr.notifier, 858 + err = mmu_interval_notifier_insert(&userptr->notifier, 881 859 current->mm, 882 860 xe_vma_userptr(vma), size, 883 861 &vma_userptr_notifier_ops); 884 862 if (err) { 885 - kfree(vma); 886 - vma = ERR_PTR(err); 887 - return vma; 863 + xe_vma_free(vma); 864 + return ERR_PTR(err); 888 865 } 889 866 890 - vma->userptr.notifier_seq = LONG_MAX; 867 + userptr->notifier_seq = LONG_MAX; 891 868 } 892 869 893 870 xe_vm_get(vm); ··· 903 880 bool read_only = xe_vma_read_only(vma); 904 881 905 882 if (xe_vma_is_userptr(vma)) { 906 - if (vma->userptr.sg) { 883 + struct xe_userptr *userptr = &to_userptr_vma(vma)->userptr; 884 + 885 + if (userptr->sg) { 907 886 dma_unmap_sgtable(xe->drm.dev, 908 - vma->userptr.sg, 887 + userptr->sg, 909 888 read_only ? DMA_TO_DEVICE : 910 889 DMA_BIDIRECTIONAL, 0); 911 - sg_free_table(vma->userptr.sg); 912 - vma->userptr.sg = NULL; 890 + sg_free_table(userptr->sg); 891 + userptr->sg = NULL; 913 892 } 914 893 915 894 /* ··· 919 894 * the notifer until we're sure the GPU is not accessing 920 895 * them anymore 921 896 */ 922 - mmu_interval_notifier_remove(&vma->userptr.notifier); 897 + mmu_interval_notifier_remove(&userptr->notifier); 923 898 xe_vm_put(vm); 924 899 } else if (xe_vma_is_null(vma)) { 925 900 xe_vm_put(vm); ··· 927 902 xe_bo_put(xe_vma_bo(vma)); 928 903 } 929 904 930 - kfree(vma); 905 + xe_vma_free(vma); 931 906 } 932 907 933 908 static void vma_destroy_work_func(struct work_struct *w) ··· 958 933 xe_assert(vm->xe, vma->gpuva.flags & XE_VMA_DESTROYED); 959 934 960 935 spin_lock(&vm->userptr.invalidated_lock); 961 - list_del(&vma->userptr.invalidate_link); 936 + list_del(&to_userptr_vma(vma)->userptr.invalidate_link); 962 937 spin_unlock(&vm->userptr.invalidated_lock); 963 938 } else if (!xe_vma_is_null(vma)) { 964 939 xe_bo_assert_held(xe_vma_bo(vma)); ··· 2175 2150 drm_exec_fini(&exec); 2176 2151 2177 2152 if (xe_vma_is_userptr(vma)) { 2178 - err = xe_vma_userptr_pin_pages(vma); 2153 + err = xe_vma_userptr_pin_pages(to_userptr_vma(vma)); 2179 2154 if (err) { 2180 2155 prep_vma_destroy(vm, vma, false); 2181 2156 xe_vma_destroy_unlocked(vma); ··· 2532 2507 2533 2508 if (err == -EAGAIN && xe_vma_is_userptr(vma)) { 2534 2509 lockdep_assert_held_write(&vm->lock); 2535 - err = xe_vma_userptr_pin_pages(vma); 2510 + err = xe_vma_userptr_pin_pages(to_userptr_vma(vma)); 2536 2511 if (!err) 2537 2512 goto retry_userptr; 2538 2513 ··· 2876 2851 struct drm_gpuva_ops **ops = NULL; 2877 2852 struct xe_vm *vm; 2878 2853 struct xe_exec_queue *q = NULL; 2879 - u32 num_syncs; 2854 + u32 num_syncs, num_ufence = 0; 2880 2855 struct xe_sync_entry *syncs = NULL; 2881 2856 struct drm_xe_vm_bind_op *bind_ops; 2882 2857 LIST_HEAD(ops_list); ··· 3013 2988 SYNC_PARSE_FLAG_DISALLOW_USER_FENCE : 0)); 3014 2989 if (err) 3015 2990 goto free_syncs; 2991 + 2992 + if (xe_sync_is_ufence(&syncs[num_syncs])) 2993 + num_ufence++; 2994 + } 2995 + 2996 + if (XE_IOCTL_DBG(xe, num_ufence > 1)) { 2997 + err = -EINVAL; 2998 + goto free_syncs; 3016 2999 } 3017 3000 3018 3001 if (!args->num_binds) { ··· 3163 3130 if (IS_ENABLED(CONFIG_PROVE_LOCKING)) { 3164 3131 if (xe_vma_is_userptr(vma)) { 3165 3132 WARN_ON_ONCE(!mmu_interval_check_retry 3166 - (&vma->userptr.notifier, 3167 - vma->userptr.notifier_seq)); 3133 + (&to_userptr_vma(vma)->userptr.notifier, 3134 + to_userptr_vma(vma)->userptr.notifier_seq)); 3168 3135 WARN_ON_ONCE(!dma_resv_test_signaled(xe_vm_resv(xe_vma_vm(vma)), 3169 3136 DMA_RESV_USAGE_BOOKKEEP)); 3170 3137 ··· 3225 3192 if (is_null) { 3226 3193 addr = 0; 3227 3194 } else if (is_userptr) { 3195 + struct sg_table *sg = to_userptr_vma(vma)->userptr.sg; 3228 3196 struct xe_res_cursor cur; 3229 3197 3230 - if (vma->userptr.sg) { 3231 - xe_res_first_sg(vma->userptr.sg, 0, XE_PAGE_SIZE, 3232 - &cur); 3198 + if (sg) { 3199 + xe_res_first_sg(sg, 0, XE_PAGE_SIZE, &cur); 3233 3200 addr = xe_res_dma(&cur); 3234 3201 } else { 3235 3202 addr = 0;
+14 -2
drivers/gpu/drm/xe/xe_vm.h
··· 160 160 return xe_vma_has_no_bo(vma) && !xe_vma_is_null(vma); 161 161 } 162 162 163 + /** 164 + * to_userptr_vma() - Return a pointer to an embedding userptr vma 165 + * @vma: Pointer to the embedded struct xe_vma 166 + * 167 + * Return: Pointer to the embedding userptr vma 168 + */ 169 + static inline struct xe_userptr_vma *to_userptr_vma(struct xe_vma *vma) 170 + { 171 + xe_assert(xe_vma_vm(vma)->xe, xe_vma_is_userptr(vma)); 172 + return container_of(vma, struct xe_userptr_vma, vma); 173 + } 174 + 163 175 u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile); 164 176 165 177 int xe_vm_create_ioctl(struct drm_device *dev, void *data, ··· 236 224 } 237 225 } 238 226 239 - int xe_vma_userptr_pin_pages(struct xe_vma *vma); 227 + int xe_vma_userptr_pin_pages(struct xe_userptr_vma *uvma); 240 228 241 - int xe_vma_userptr_check_repin(struct xe_vma *vma); 229 + int xe_vma_userptr_check_repin(struct xe_userptr_vma *uvma); 242 230 243 231 bool xe_vm_validate_should_retry(struct drm_exec *exec, int err, ktime_t *end); 244 232
+10 -6
drivers/gpu/drm/xe/xe_vm_types.h
··· 37 37 struct xe_userptr { 38 38 /** @invalidate_link: Link for the vm::userptr.invalidated list */ 39 39 struct list_head invalidate_link; 40 + /** @userptr: link into VM repin list if userptr. */ 41 + struct list_head repin_link; 40 42 /** 41 43 * @notifier: MMU notifier for user pointer (invalidation call back) 42 44 */ ··· 70 68 * resv. 71 69 */ 72 70 union { 73 - /** @userptr: link into VM repin list if userptr. */ 74 - struct list_head userptr; 75 71 /** @rebind: link into VM if this VMA needs rebinding. */ 76 72 struct list_head rebind; 77 73 /** @destroy: link to contested list when VM is being closed. */ ··· 105 105 * @pat_index: The pat index to use when encoding the PTEs for this vma. 106 106 */ 107 107 u16 pat_index; 108 + }; 108 109 109 - /** 110 - * @userptr: user pointer state, only allocated for VMAs that are 111 - * user pointers 112 - */ 110 + /** 111 + * struct xe_userptr_vma - A userptr vma subclass 112 + * @vma: The vma. 113 + * @userptr: Additional userptr information. 114 + */ 115 + struct xe_userptr_vma { 116 + struct xe_vma vma; 113 117 struct xe_userptr userptr; 114 118 }; 115 119