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spi: spi-qpic-snand: handle 'use_ecc' parameter of qcom_spi_config_cw_read()

During raw read, neither the status of the ECC correction nor the erased
state of the codeword gets checked by the qcom_spi_read_cw_raw() function,
so in case of raw access reading the corresponding registers via DMA is
superfluous.

Extend the qcom_spi_config_cw_read() function to evaluate the existing
(but actually unused) 'use_ecc' parameter, and configure reading only
the flash status register when ECC is not used.

With the change, the code gets in line with the corresponding part of
the config_nand_cw_read() function in the qcom_nandc driver.

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20250808-qpic-snand-handle-use_ecc-v1-1-67289fbb5e2f@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Gabor Juhos and committed by
Mark Brown 9c45f952 274f3264

+8 -3
+8 -3
drivers/spi/spi-qpic-snand.c
··· 491 491 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); 492 492 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 493 493 494 - qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); 495 - qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, 496 - NAND_BAM_NEXT_SGL); 494 + if (use_ecc) { 495 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); 496 + qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, 497 + NAND_BAM_NEXT_SGL); 498 + } else { 499 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 500 + NAND_BAM_NEXT_SGL); 501 + } 497 502 } 498 503 499 504 static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)