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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
dt-bindings: clock: Add Qualcomm QCS615 Video clock controller
Add DT bindings for the Video clock on QCS615 platforms. Add the
relevant DT include definitions as well.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-8-9c216e1615ab@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Taniya Das
and committed by
Bjorn Andersson
9c51c66c
f4b5b408
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Documentation/devicetree/bindings/clock/qcom,qcs615-videocc.yaml
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Documentation/devicetree/bindings/clock/qcom,qcs615-videocc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,qcs615-videocc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Video Clock & Reset Controller on QCS615
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maintainers:
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- Taniya Das <quic_tdas@quicinc.com>
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description: |
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Qualcomm video clock control module provides clocks, resets and power
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domains on QCS615 Qualcomm SoCs.
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See also: include/dt-bindings/clock/qcom,qcs615-videocc.h
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properties:
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compatible:
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const: qcom,qcs615-videocc
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clocks:
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items:
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- description: Board XO source
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- description: Sleep clock source
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,qcs615-gcc.h>
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clock-controller@ab00000 {
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compatible = "qcom,qcs615-videocc";
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reg = <0xab00000 0x10000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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include/dt-bindings/clock/qcom,qcs615-videocc.h
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include/dt-bindings/clock/qcom,qcs615-videocc.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_QCS615_H
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#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_QCS615_H
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/* VIDEO_CC clocks */
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#define VIDEO_CC_SLEEP_CLK 0
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#define VIDEO_CC_SLEEP_CLK_SRC 1
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#define VIDEO_CC_VCODEC0_AXI_CLK 2
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#define VIDEO_CC_VCODEC0_CORE_CLK 3
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#define VIDEO_CC_VENUS_AHB_CLK 4
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#define VIDEO_CC_VENUS_CLK_SRC 5
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#define VIDEO_CC_VENUS_CTL_AXI_CLK 6
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#define VIDEO_CC_VENUS_CTL_CORE_CLK 7
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#define VIDEO_CC_XO_CLK 8
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#define VIDEO_PLL0 9
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/* VIDEO_CC power domains */
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#define VCODEC0_GDSC 0
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#define VENUS_GDSC 1
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/* VIDEO_CC resets */
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#define VIDEO_CC_INTERFACE_BCR 0
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#define VIDEO_CC_VCODEC0_BCR 1
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#define VIDEO_CC_VENUS_BCR 2
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#endif