clk: qcom: gcc-msm8998: Control MMSS and GPUSS GPLL0 outputs properly

Up until now, we've been relying on some non-descript hardware magic
to pinkypromise turn the clocks on for us. While new SoCs shine with
that feature, MSM8998 can not always be fully trusted.

Register the MMSS and GPUSS GPLL0 legs with the CCF to allow for manual
enable voting.

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Tested-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-3-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Konrad Dybcio and committed by

Bjorn Andersson 2 years ago 9c76c5cf 9127b377

+58

1 changed file

expand all

drivers

clk

qcom

gcc-msm8998.c

+58

drivers/clk/qcom/gcc-msm8998.c

··· 25 25 #include "reset.h" 26 26 #include "gdsc.h" 27 27 28 + #define GCC_MMSS_MISC 0x0902C 29 + #define GCC_GPU_MISC 0x71028 30 + 28 31 static struct pll_vco fabia_vco[] = { 29 32 { 250000000, 2000000000, 0 }, 30 33 { 125000000, 1000000000, 1 }, ··· 1370 1367 }, 1371 1368 }; 1372 1369 1370 + static struct clk_branch gcc_mmss_gpll0_div_clk = { 1371 + .halt_check = BRANCH_HALT_DELAY, 1372 + .clkr = { 1373 + .enable_reg = 0x5200c, 1374 + .enable_mask = BIT(0), 1375 + .hw.init = &(struct clk_init_data){ 1376 + .name = "gcc_mmss_gpll0_div_clk", 1377 + .parent_hws = (const struct clk_hw *[]) { 1378 + &gpll0_out_main.clkr.hw, 1379 + }, 1380 + .num_parents = 1, 1381 + .ops = &clk_branch2_ops, 1382 + }, 1383 + }, 1384 + }; 1385 + 1373 1386 static struct clk_branch gcc_mmss_gpll0_clk = { 1374 1387 .halt_check = BRANCH_HALT_DELAY, 1375 1388 .clkr = { ··· 1409 1390 .enable_mask = BIT(2), 1410 1391 .hw.init = &(struct clk_init_data){ 1411 1392 .name = "gcc_mss_gpll0_div_clk_src", 1393 + .ops = &clk_branch2_ops, 1394 + }, 1395 + }, 1396 + }; 1397 + 1398 + static struct clk_branch gcc_gpu_gpll0_div_clk = { 1399 + .halt_check = BRANCH_HALT_DELAY, 1400 + .clkr = { 1401 + .enable_reg = 0x5200c, 1402 + .enable_mask = BIT(3), 1403 + .hw.init = &(struct clk_init_data){ 1404 + .name = "gcc_gpu_gpll0_div_clk", 1405 + .parent_hws = (const struct clk_hw *[]) { 1406 + &gpll0_out_main.clkr.hw, 1407 + }, 1408 + .num_parents = 1, 1409 + .ops = &clk_branch2_ops, 1410 + }, 1411 + }, 1412 + }; 1413 + 1414 + static struct clk_branch gcc_gpu_gpll0_clk = { 1415 + .halt_check = BRANCH_HALT_DELAY, 1416 + .clkr = { 1417 + .enable_reg = 0x5200c, 1418 + .enable_mask = BIT(4), 1419 + .hw.init = &(struct clk_init_data){ 1420 + .name = "gcc_gpu_gpll0_clk", 1421 + .parent_hws = (const struct clk_hw *[]) { 1422 + &gpll0_out_main.clkr.hw, 1423 + }, 1424 + .num_parents = 1, 1412 1425 .ops = &clk_branch2_ops, 1413 1426 }, 1414 1427 }, ··· 3131 3080 [AGGRE2_SNOC_NORTH_AXI] = &aggre2_snoc_north_axi_clk.clkr, 3132 3081 [SSC_XO] = &ssc_xo_clk.clkr, 3133 3082 [SSC_CNOC_AHBS_CLK] = &ssc_cnoc_ahbs_clk.clkr, 3083 + [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr, 3084 + [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr, 3085 + [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr, 3134 3086 }; 3135 3087 3136 3088 static struct gdsc *gcc_msm8998_gdscs[] = { ··· 3288 3234 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); 3289 3235 if (ret) 3290 3236 return ret; 3237 + 3238 + /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */ 3239 + regmap_write(regmap, GCC_MMSS_MISC, 0x10003); 3240 + regmap_write(regmap, GCC_GPU_MISC, 0x10003); 3291 3241 3292 3242 return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap); 3293 3243 }

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