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dt-bindings: iio: Correct indentation and style in DTS example
DTS example in the bindings should be indented with 2- or 4-spaces and
aligned with opening '- |', so correct any differences like 3-spaces or
mixtures 2- and 4-spaces in one binding.
No functional changes here, but saves some comments during reviews of
new patches built on existing code.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250324125313.82226-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Krzysztof Kozlowski
and committed by
Jonathan Cameron
9ca04c5e
bb8d952a
+51
-51
+51
-51
Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
+51
-51
Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
···
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examples:
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- |
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// Example 1: with stm32f429, ADC1, single-ended channel 8
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-
adc123: adc@40012000 {
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+
adc123: adc@40012000 {
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compatible = "st,stm32f4-adc-core";
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reg = <0x40012000 0x400>;
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interrupts = <18>;
···
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#address-cells = <1>;
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#size-cells = <0>;
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adc@0 {
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-
compatible = "st,stm32f4-adc";
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-
#io-channel-cells = <1>;
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-
reg = <0x0>;
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-
clocks = <&rcc 0 168>;
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-
interrupt-parent = <&adc123>;
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-
interrupts = <0>;
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-
st,adc-channels = <8>;
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-
dmas = <&dma2 0 0 0x400 0x0>;
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-
dma-names = "rx";
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-
assigned-resolution-bits = <8>;
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+
compatible = "st,stm32f4-adc";
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+
#io-channel-cells = <1>;
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+
reg = <0x0>;
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+
clocks = <&rcc 0 168>;
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+
interrupt-parent = <&adc123>;
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interrupts = <0>;
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st,adc-channels = <8>;
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dmas = <&dma2 0 0 0x400 0x0>;
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dma-names = "rx";
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+
assigned-resolution-bits = <8>;
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};
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// ...
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// other adc child nodes follow...
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-
};
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+
};
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- |
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// Example 2: with stm32mp157c to setup ADC1 with:
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// - channels 0 & 1 as single-ended
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// - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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adc12: adc@48003000 {
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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+
#include <dt-bindings/clock/stm32mp1-clks.h>
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+
adc12: adc@48003000 {
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compatible = "st,stm32mp1-adc-core";
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reg = <0x48003000 0x400>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
···
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#address-cells = <1>;
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#size-cells = <0>;
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adc@0 {
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-
compatible = "st,stm32mp1-adc";
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-
#io-channel-cells = <1>;
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reg = <0x0>;
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interrupt-parent = <&adc12>;
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interrupts = <0>;
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-
st,adc-channels = <0 1>;
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-
st,adc-diff-channels = <2 6>, <3 7>;
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-
st,min-sample-time-nsecs = <5000>;
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-
dmas = <&dmamux1 9 0x400 0x05>;
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-
dma-names = "rx";
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+
compatible = "st,stm32mp1-adc";
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+
#io-channel-cells = <1>;
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+
reg = <0x0>;
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+
interrupt-parent = <&adc12>;
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interrupts = <0>;
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+
st,adc-channels = <0 1>;
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+
st,adc-diff-channels = <2 6>, <3 7>;
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+
st,min-sample-time-nsecs = <5000>;
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+
dmas = <&dmamux1 9 0x400 0x05>;
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+
dma-names = "rx";
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};
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// ...
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// other adc child node follow...
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-
};
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+
};
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- |
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// Example 3: with stm32mp157c to setup ADC2 with:
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// - internal channels 13, 14, 15.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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adc122: adc@48003000 {
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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adc122: adc@48003000 {
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compatible = "st,stm32mp1-adc-core";
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reg = <0x48003000 0x400>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
···
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#address-cells = <1>;
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#size-cells = <0>;
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adc@100 {
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-
compatible = "st,stm32mp1-adc";
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#io-channel-cells = <1>;
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reg = <0x100>;
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interrupts = <1>;
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#address-cells = <1>;
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-
#size-cells = <0>;
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-
channel@13 {
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reg = <13>;
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label = "vrefint";
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st,min-sample-time-ns = <9000>;
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-
};
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-
channel@14 {
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reg = <14>;
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label = "vddcore";
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-
st,min-sample-time-ns = <9000>;
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-
};
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-
channel@15 {
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reg = <15>;
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label = "vbat";
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-
st,min-sample-time-ns = <9000>;
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-
};
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+
compatible = "st,stm32mp1-adc";
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+
#io-channel-cells = <1>;
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+
reg = <0x100>;
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+
interrupts = <1>;
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+
#address-cells = <1>;
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+
#size-cells = <0>;
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+
channel@13 {
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reg = <13>;
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label = "vrefint";
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+
st,min-sample-time-ns = <9000>;
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+
};
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+
channel@14 {
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reg = <14>;
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label = "vddcore";
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+
st,min-sample-time-ns = <9000>;
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+
};
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+
channel@15 {
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reg = <15>;
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label = "vbat";
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+
st,min-sample-time-ns = <9000>;
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+
};
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};
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-
};
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+
};
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...