tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
"A bunch of fixes for radeon, intel, omap and one amdkfd fix.

Radeon fixes are all over, but it does fix some cursor corruption
across suspend/resume. i915 should fix the second warn you were
seeing, so let us know if not. omap is a bunch of small fixes"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (28 commits)
drm/radeon: disable vce init on cayman (v2)
drm/amdgpu: fix timeout calculation
drm/radeon: check if BO_VA is set before adding it to the invalidation list
drm/radeon: allways add the VM clear duplicate
Revert "Revert "drm/radeon: dont switch vt on suspend""
drm/radeon: Fold radeon_set_cursor() into radeon_show_cursor()
drm/radeon: unpin cursor BOs on suspend and pin them again on resume (v2)
drm/radeon: Clean up reference counting and pinning of the cursor BOs
drm/amdkfd: validate pdd where it acquired first
Revert "drm/i915: Allocate context objects from stolen"
drm/i915: Declare the swizzling unknown for L-shaped configurations
drm/radeon: fix underflow in r600_cp_dispatch_texture()
drm/radeon: default to 2048 MB GART size on SI+
drm/radeon: fix HDP flushing
drm/radeon: use RCU query for GEM_BUSY syscall
drm/amdgpu: Handle irqs only based on irq ring, not irq status regs.
drm/radeon: Handle irqs only based on irq ring, not irq status regs.
drm/i915: Use crtc_state->active in primary check_plane func
drm/i915: Check crtc->active in intel_crtc_disable_planes
drm/i915: Restore all GGTT VMAs on resume
...

Linus Torvalds 9cb1680c 2278cb0b

+964 -717
+1 -1
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
··· 352 352 if (((int64_t)timeout_ns) < 0) 353 353 return MAX_SCHEDULE_TIMEOUT; 354 354 355 - timeout = ktime_sub_ns(ktime_get(), timeout_ns); 355 + timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 356 356 if (ktime_to_ns(timeout) < 0) 357 357 return 0; 358 358
+14 -8
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
··· 3403 3403 3404 3404 switch (entry->src_data) { 3405 3405 case 0: /* vblank */ 3406 - if (disp_int & interrupt_status_offsets[crtc].vblank) { 3406 + if (disp_int & interrupt_status_offsets[crtc].vblank) 3407 3407 dce_v10_0_crtc_vblank_int_ack(adev, crtc); 3408 - if (amdgpu_irq_enabled(adev, source, irq_type)) { 3409 - drm_handle_vblank(adev->ddev, crtc); 3410 - } 3411 - DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3408 + else 3409 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3410 + 3411 + if (amdgpu_irq_enabled(adev, source, irq_type)) { 3412 + drm_handle_vblank(adev->ddev, crtc); 3412 3413 } 3414 + DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3415 + 3413 3416 break; 3414 3417 case 1: /* vline */ 3415 - if (disp_int & interrupt_status_offsets[crtc].vline) { 3418 + if (disp_int & interrupt_status_offsets[crtc].vline) 3416 3419 dce_v10_0_crtc_vline_int_ack(adev, crtc); 3417 - DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3418 - } 3420 + else 3421 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3422 + 3423 + DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3424 + 3419 3425 break; 3420 3426 default: 3421 3427 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+14 -8
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
··· 3402 3402 3403 3403 switch (entry->src_data) { 3404 3404 case 0: /* vblank */ 3405 - if (disp_int & interrupt_status_offsets[crtc].vblank) { 3405 + if (disp_int & interrupt_status_offsets[crtc].vblank) 3406 3406 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3407 - if (amdgpu_irq_enabled(adev, source, irq_type)) { 3408 - drm_handle_vblank(adev->ddev, crtc); 3409 - } 3410 - DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3407 + else 3408 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3409 + 3410 + if (amdgpu_irq_enabled(adev, source, irq_type)) { 3411 + drm_handle_vblank(adev->ddev, crtc); 3411 3412 } 3413 + DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3414 + 3412 3415 break; 3413 3416 case 1: /* vline */ 3414 - if (disp_int & interrupt_status_offsets[crtc].vline) { 3417 + if (disp_int & interrupt_status_offsets[crtc].vline) 3415 3418 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3416 - DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3417 - } 3419 + else 3420 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3421 + 3422 + DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3423 + 3418 3424 break; 3419 3425 default: 3420 3426 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+14 -8
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
··· 3237 3237 3238 3238 switch (entry->src_data) { 3239 3239 case 0: /* vblank */ 3240 - if (disp_int & interrupt_status_offsets[crtc].vblank) { 3240 + if (disp_int & interrupt_status_offsets[crtc].vblank) 3241 3241 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); 3242 - if (amdgpu_irq_enabled(adev, source, irq_type)) { 3243 - drm_handle_vblank(adev->ddev, crtc); 3244 - } 3245 - DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3242 + else 3243 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3244 + 3245 + if (amdgpu_irq_enabled(adev, source, irq_type)) { 3246 + drm_handle_vblank(adev->ddev, crtc); 3246 3247 } 3248 + DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3249 + 3247 3250 break; 3248 3251 case 1: /* vline */ 3249 - if (disp_int & interrupt_status_offsets[crtc].vline) { 3252 + if (disp_int & interrupt_status_offsets[crtc].vline) 3250 3253 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK); 3251 - DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3252 - } 3254 + else 3255 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3256 + 3257 + DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3258 + 3253 3259 break; 3254 3260 default: 3255 3261 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
+7 -2
drivers/gpu/drm/amd/amdkfd/kfd_process.c
··· 420 420 pqm_uninit(&p->pqm); 421 421 422 422 pdd = kfd_get_process_device_data(dev, p); 423 + 424 + if (!pdd) { 425 + mutex_unlock(&p->mutex); 426 + return; 427 + } 428 + 423 429 if (pdd->reset_wavefronts) { 424 430 dbgdev_wave_reset_wavefronts(pdd->dev, p); 425 431 pdd->reset_wavefronts = false; ··· 437 431 * We don't call amd_iommu_unbind_pasid() here 438 432 * because the IOMMU called us. 439 433 */ 440 - if (pdd) 441 - pdd->bound = false; 434 + pdd->bound = false; 442 435 443 436 mutex_unlock(&p->mutex); 444 437 }
+1 -3
drivers/gpu/drm/i915/i915_gem_context.c
··· 157 157 struct drm_i915_gem_object *obj; 158 158 int ret; 159 159 160 - obj = i915_gem_object_create_stolen(dev, size); 161 - if (obj == NULL) 162 - obj = i915_gem_alloc_object(dev, size); 160 + obj = i915_gem_alloc_object(dev, size); 163 161 if (obj == NULL) 164 162 return ERR_PTR(-ENOMEM); 165 163
+16 -7
drivers/gpu/drm/i915/i915_gem_gtt.c
··· 2546 2546 struct drm_i915_private *dev_priv = dev->dev_private; 2547 2547 struct drm_i915_gem_object *obj; 2548 2548 struct i915_address_space *vm; 2549 + struct i915_vma *vma; 2550 + bool flush; 2549 2551 2550 2552 i915_check_and_clear_faults(dev); 2551 2553 ··· 2557 2555 dev_priv->gtt.base.total, 2558 2556 true); 2559 2557 2558 + /* Cache flush objects bound into GGTT and rebind them. */ 2559 + vm = &dev_priv->gtt.base; 2560 2560 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 2561 - struct i915_vma *vma = i915_gem_obj_to_vma(obj, 2562 - &dev_priv->gtt.base); 2563 - if (!vma) 2564 - continue; 2561 + flush = false; 2562 + list_for_each_entry(vma, &obj->vma_list, vma_link) { 2563 + if (vma->vm != vm) 2564 + continue; 2565 2565 2566 - i915_gem_clflush_object(obj, obj->pin_display); 2567 - WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE)); 2566 + WARN_ON(i915_vma_bind(vma, obj->cache_level, 2567 + PIN_UPDATE)); 2568 + 2569 + flush = true; 2570 + } 2571 + 2572 + if (flush) 2573 + i915_gem_clflush_object(obj, obj->pin_display); 2568 2574 } 2569 - 2570 2575 2571 2576 if (INTEL_INFO(dev)->gen >= 8) { 2572 2577 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
+11 -1
drivers/gpu/drm/i915/i915_gem_tiling.c
··· 183 183 if (IS_GEN4(dev)) { 184 184 uint32_t ddc2 = I915_READ(DCC2); 185 185 186 - if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE)) 186 + if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE)) { 187 + /* Since the swizzling may vary within an 188 + * object, we have no idea what the swizzling 189 + * is for any page in particular. Thus we 190 + * cannot migrate tiled pages using the GPU, 191 + * nor can we tell userspace what the exact 192 + * swizzling is for any object. 193 + */ 187 194 dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES; 195 + swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 196 + swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 197 + } 188 198 } 189 199 190 200 if (dcc == 0xffffffff) {
+9 -3
drivers/gpu/drm/i915/intel_display.c
··· 4854 4854 struct intel_plane *intel_plane; 4855 4855 int pipe = intel_crtc->pipe; 4856 4856 4857 + if (!intel_crtc->active) 4858 + return; 4859 + 4857 4860 intel_crtc_wait_for_pending_flips(crtc); 4858 4861 4859 4862 intel_pre_disable_primary(crtc); ··· 7890 7887 int pipe = pipe_config->cpu_transcoder; 7891 7888 enum dpio_channel port = vlv_pipe_to_channel(pipe); 7892 7889 intel_clock_t clock; 7893 - u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; 7890 + u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; 7894 7891 int refclk = 100000; 7895 7892 7896 7893 mutex_lock(&dev_priv->sb_lock); ··· 7898 7895 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); 7899 7896 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); 7900 7897 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); 7898 + pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 7901 7899 mutex_unlock(&dev_priv->sb_lock); 7902 7900 7903 7901 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; 7904 - clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); 7902 + clock.m2 = (pll_dw0 & 0xff) << 22; 7903 + if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) 7904 + clock.m2 |= pll_dw2 & 0x3fffff; 7905 7905 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; 7906 7906 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; 7907 7907 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; ··· 13276 13270 if (ret) 13277 13271 return ret; 13278 13272 13279 - if (intel_crtc->active) { 13273 + if (crtc_state->base.active) { 13280 13274 struct intel_plane_state *old_state = 13281 13275 to_intel_plane_state(plane->state); 13282 13276
+1 -1
drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
··· 285 285 286 286 if (wait) { 287 287 if (!wait_for_completion_timeout(&engine->compl, 288 - msecs_to_jiffies(1))) { 288 + msecs_to_jiffies(100))) { 289 289 dev_err(dmm->dev, "timed out waiting for done\n"); 290 290 ret = -ETIMEDOUT; 291 291 }
+3 -3
drivers/gpu/drm/omapdrm/omap_drv.h
··· 177 177 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); 178 178 struct drm_gem_object *omap_framebuffer_bo(struct drm_framebuffer *fb, int p); 179 179 int omap_framebuffer_pin(struct drm_framebuffer *fb); 180 - int omap_framebuffer_unpin(struct drm_framebuffer *fb); 180 + void omap_framebuffer_unpin(struct drm_framebuffer *fb); 181 181 void omap_framebuffer_update_scanout(struct drm_framebuffer *fb, 182 182 struct omap_drm_window *win, struct omap_overlay_info *info); 183 183 struct drm_connector *omap_framebuffer_get_next_connector( ··· 211 211 enum dma_data_direction dir); 212 212 int omap_gem_get_paddr(struct drm_gem_object *obj, 213 213 dma_addr_t *paddr, bool remap); 214 - int omap_gem_put_paddr(struct drm_gem_object *obj); 214 + void omap_gem_put_paddr(struct drm_gem_object *obj); 215 215 int omap_gem_get_pages(struct drm_gem_object *obj, struct page ***pages, 216 216 bool remap); 217 217 int omap_gem_put_pages(struct drm_gem_object *obj); ··· 236 236 /* PVR needs alignment to 8 pixels.. right now that is the most 237 237 * restrictive stride requirement.. 238 238 */ 239 - return ALIGN(pitch, 8 * bytespp); 239 + return roundup(pitch, 8 * bytespp); 240 240 } 241 241 242 242 /* map crtc to vblank mask */
+4 -12
drivers/gpu/drm/omapdrm/omap_fb.c
··· 287 287 } 288 288 289 289 /* unpin, no longer being scanned out: */ 290 - int omap_framebuffer_unpin(struct drm_framebuffer *fb) 290 + void omap_framebuffer_unpin(struct drm_framebuffer *fb) 291 291 { 292 292 struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb); 293 - int ret, i, n = drm_format_num_planes(fb->pixel_format); 293 + int i, n = drm_format_num_planes(fb->pixel_format); 294 294 295 295 mutex_lock(&omap_fb->lock); 296 296 ··· 298 298 299 299 if (omap_fb->pin_count > 0) { 300 300 mutex_unlock(&omap_fb->lock); 301 - return 0; 301 + return; 302 302 } 303 303 304 304 for (i = 0; i < n; i++) { 305 305 struct plane *plane = &omap_fb->planes[i]; 306 - ret = omap_gem_put_paddr(plane->bo); 307 - if (ret) 308 - goto fail; 306 + omap_gem_put_paddr(plane->bo); 309 307 plane->paddr = 0; 310 308 } 311 309 312 310 mutex_unlock(&omap_fb->lock); 313 - 314 - return 0; 315 - 316 - fail: 317 - mutex_unlock(&omap_fb->lock); 318 - return ret; 319 311 } 320 312 321 313 struct drm_gem_object *omap_framebuffer_bo(struct drm_framebuffer *fb, int p)
+1 -1
drivers/gpu/drm/omapdrm/omap_fbdev.c
··· 135 135 fbdev->ywrap_enabled = priv->has_dmm && ywrap_enabled; 136 136 if (fbdev->ywrap_enabled) { 137 137 /* need to align pitch to page size if using DMM scrolling */ 138 - mode_cmd.pitches[0] = ALIGN(mode_cmd.pitches[0], PAGE_SIZE); 138 + mode_cmd.pitches[0] = PAGE_ALIGN(mode_cmd.pitches[0]); 139 139 } 140 140 141 141 /* allocate backing bo */
+14 -12
drivers/gpu/drm/omapdrm/omap_gem.c
··· 808 808 /* Release physical address, when DMA is no longer being performed.. this 809 809 * could potentially unpin and unmap buffers from TILER 810 810 */ 811 - int omap_gem_put_paddr(struct drm_gem_object *obj) 811 + void omap_gem_put_paddr(struct drm_gem_object *obj) 812 812 { 813 813 struct omap_gem_object *omap_obj = to_omap_bo(obj); 814 - int ret = 0; 814 + int ret; 815 815 816 816 mutex_lock(&obj->dev->struct_mutex); 817 817 if (omap_obj->paddr_cnt > 0) { ··· 821 821 if (ret) { 822 822 dev_err(obj->dev->dev, 823 823 "could not unpin pages: %d\n", ret); 824 - goto fail; 825 824 } 826 825 ret = tiler_release(omap_obj->block); 827 826 if (ret) { ··· 831 832 omap_obj->block = NULL; 832 833 } 833 834 } 834 - fail: 835 + 835 836 mutex_unlock(&obj->dev->struct_mutex); 836 - return ret; 837 837 } 838 838 839 839 /* Get rotated scanout address (only valid if already pinned), at the ··· 1376 1378 1377 1379 omap_obj = kzalloc(sizeof(*omap_obj), GFP_KERNEL); 1378 1380 if (!omap_obj) 1379 - goto fail; 1380 - 1381 - spin_lock(&priv->list_lock); 1382 - list_add(&omap_obj->mm_list, &priv->obj_list); 1383 - spin_unlock(&priv->list_lock); 1381 + return NULL; 1384 1382 1385 1383 obj = &omap_obj->base; 1386 1384 ··· 1386 1392 */ 1387 1393 omap_obj->vaddr = dma_alloc_writecombine(dev->dev, size, 1388 1394 &omap_obj->paddr, GFP_KERNEL); 1389 - if (omap_obj->vaddr) 1390 - flags |= OMAP_BO_DMA; 1395 + if (!omap_obj->vaddr) { 1396 + kfree(omap_obj); 1391 1397 1398 + return NULL; 1399 + } 1400 + 1401 + flags |= OMAP_BO_DMA; 1392 1402 } 1403 + 1404 + spin_lock(&priv->list_lock); 1405 + list_add(&omap_obj->mm_list, &priv->obj_list); 1406 + spin_unlock(&priv->list_lock); 1393 1407 1394 1408 omap_obj->flags = flags; 1395 1409
+26
drivers/gpu/drm/omapdrm/omap_plane.c
··· 17 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 18 */ 19 19 20 + #include <drm/drm_atomic.h> 20 21 #include <drm/drm_atomic_helper.h> 21 22 #include <drm/drm_plane_helper.h> 22 23 ··· 154 153 dispc_ovl_enable(omap_plane->id, false); 155 154 } 156 155 156 + static int omap_plane_atomic_check(struct drm_plane *plane, 157 + struct drm_plane_state *state) 158 + { 159 + struct drm_crtc_state *crtc_state; 160 + 161 + if (!state->crtc) 162 + return 0; 163 + 164 + crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 165 + if (IS_ERR(crtc_state)) 166 + return PTR_ERR(crtc_state); 167 + 168 + if (state->crtc_x < 0 || state->crtc_y < 0) 169 + return -EINVAL; 170 + 171 + if (state->crtc_x + state->crtc_w > crtc_state->adjusted_mode.hdisplay) 172 + return -EINVAL; 173 + 174 + if (state->crtc_y + state->crtc_h > crtc_state->adjusted_mode.vdisplay) 175 + return -EINVAL; 176 + 177 + return 0; 178 + } 179 + 157 180 static const struct drm_plane_helper_funcs omap_plane_helper_funcs = { 158 181 .prepare_fb = omap_plane_prepare_fb, 159 182 .cleanup_fb = omap_plane_cleanup_fb, 183 + .atomic_check = omap_plane_atomic_check, 160 184 .atomic_update = omap_plane_atomic_update, 161 185 .atomic_disable = omap_plane_atomic_disable, 162 186 };
+192 -144
drivers/gpu/drm/radeon/cik.c
··· 7964 7964 case 1: /* D1 vblank/vline */ 7965 7965 switch (src_data) { 7966 7966 case 0: /* D1 vblank */ 7967 - if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) { 7968 - if (rdev->irq.crtc_vblank_int[0]) { 7969 - drm_handle_vblank(rdev->ddev, 0); 7970 - rdev->pm.vblank_sync = true; 7971 - wake_up(&rdev->irq.vblank_queue); 7972 - } 7973 - if (atomic_read(&rdev->irq.pflip[0])) 7974 - radeon_crtc_handle_vblank(rdev, 0); 7975 - rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 7976 - DRM_DEBUG("IH: D1 vblank\n"); 7967 + if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)) 7968 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 7969 + 7970 + if (rdev->irq.crtc_vblank_int[0]) { 7971 + drm_handle_vblank(rdev->ddev, 0); 7972 + rdev->pm.vblank_sync = true; 7973 + wake_up(&rdev->irq.vblank_queue); 7977 7974 } 7975 + if (atomic_read(&rdev->irq.pflip[0])) 7976 + radeon_crtc_handle_vblank(rdev, 0); 7977 + rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 7978 + DRM_DEBUG("IH: D1 vblank\n"); 7979 + 7978 7980 break; 7979 7981 case 1: /* D1 vline */ 7980 - if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) { 7981 - rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT; 7982 - DRM_DEBUG("IH: D1 vline\n"); 7983 - } 7982 + if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)) 7983 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 7984 + 7985 + rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT; 7986 + DRM_DEBUG("IH: D1 vline\n"); 7987 + 7984 7988 break; 7985 7989 default: 7986 7990 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 7994 7990 case 2: /* D2 vblank/vline */ 7995 7991 switch (src_data) { 7996 7992 case 0: /* D2 vblank */ 7997 - if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 7998 - if (rdev->irq.crtc_vblank_int[1]) { 7999 - drm_handle_vblank(rdev->ddev, 1); 8000 - rdev->pm.vblank_sync = true; 8001 - wake_up(&rdev->irq.vblank_queue); 8002 - } 8003 - if (atomic_read(&rdev->irq.pflip[1])) 8004 - radeon_crtc_handle_vblank(rdev, 1); 8005 - rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 8006 - DRM_DEBUG("IH: D2 vblank\n"); 7993 + if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT)) 7994 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 7995 + 7996 + if (rdev->irq.crtc_vblank_int[1]) { 7997 + drm_handle_vblank(rdev->ddev, 1); 7998 + rdev->pm.vblank_sync = true; 7999 + wake_up(&rdev->irq.vblank_queue); 8007 8000 } 8001 + if (atomic_read(&rdev->irq.pflip[1])) 8002 + radeon_crtc_handle_vblank(rdev, 1); 8003 + rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 8004 + DRM_DEBUG("IH: D2 vblank\n"); 8005 + 8008 8006 break; 8009 8007 case 1: /* D2 vline */ 8010 - if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT) { 8011 - rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 8012 - DRM_DEBUG("IH: D2 vline\n"); 8013 - } 8008 + if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT)) 8009 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8010 + 8011 + rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 8012 + DRM_DEBUG("IH: D2 vline\n"); 8013 + 8014 8014 break; 8015 8015 default: 8016 8016 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 8024 8016 case 3: /* D3 vblank/vline */ 8025 8017 switch (src_data) { 8026 8018 case 0: /* D3 vblank */ 8027 - if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 8028 - if (rdev->irq.crtc_vblank_int[2]) { 8029 - drm_handle_vblank(rdev->ddev, 2); 8030 - rdev->pm.vblank_sync = true; 8031 - wake_up(&rdev->irq.vblank_queue); 8032 - } 8033 - if (atomic_read(&rdev->irq.pflip[2])) 8034 - radeon_crtc_handle_vblank(rdev, 2); 8035 - rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 8036 - DRM_DEBUG("IH: D3 vblank\n"); 8019 + if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)) 8020 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8021 + 8022 + if (rdev->irq.crtc_vblank_int[2]) { 8023 + drm_handle_vblank(rdev->ddev, 2); 8024 + rdev->pm.vblank_sync = true; 8025 + wake_up(&rdev->irq.vblank_queue); 8037 8026 } 8027 + if (atomic_read(&rdev->irq.pflip[2])) 8028 + radeon_crtc_handle_vblank(rdev, 2); 8029 + rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 8030 + DRM_DEBUG("IH: D3 vblank\n"); 8031 + 8038 8032 break; 8039 8033 case 1: /* D3 vline */ 8040 - if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 8041 - rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 8042 - DRM_DEBUG("IH: D3 vline\n"); 8043 - } 8034 + if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)) 8035 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8036 + 8037 + rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 8038 + DRM_DEBUG("IH: D3 vline\n"); 8039 + 8044 8040 break; 8045 8041 default: 8046 8042 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 8054 8042 case 4: /* D4 vblank/vline */ 8055 8043 switch (src_data) { 8056 8044 case 0: /* D4 vblank */ 8057 - if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 8058 - if (rdev->irq.crtc_vblank_int[3]) { 8059 - drm_handle_vblank(rdev->ddev, 3); 8060 - rdev->pm.vblank_sync = true; 8061 - wake_up(&rdev->irq.vblank_queue); 8062 - } 8063 - if (atomic_read(&rdev->irq.pflip[3])) 8064 - radeon_crtc_handle_vblank(rdev, 3); 8065 - rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 8066 - DRM_DEBUG("IH: D4 vblank\n"); 8045 + if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)) 8046 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8047 + 8048 + if (rdev->irq.crtc_vblank_int[3]) { 8049 + drm_handle_vblank(rdev->ddev, 3); 8050 + rdev->pm.vblank_sync = true; 8051 + wake_up(&rdev->irq.vblank_queue); 8067 8052 } 8053 + if (atomic_read(&rdev->irq.pflip[3])) 8054 + radeon_crtc_handle_vblank(rdev, 3); 8055 + rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 8056 + DRM_DEBUG("IH: D4 vblank\n"); 8057 + 8068 8058 break; 8069 8059 case 1: /* D4 vline */ 8070 - if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 8071 - rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 8072 - DRM_DEBUG("IH: D4 vline\n"); 8073 - } 8060 + if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)) 8061 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8062 + 8063 + rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 8064 + DRM_DEBUG("IH: D4 vline\n"); 8065 + 8074 8066 break; 8075 8067 default: 8076 8068 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 8084 8068 case 5: /* D5 vblank/vline */ 8085 8069 switch (src_data) { 8086 8070 case 0: /* D5 vblank */ 8087 - if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 8088 - if (rdev->irq.crtc_vblank_int[4]) { 8089 - drm_handle_vblank(rdev->ddev, 4); 8090 - rdev->pm.vblank_sync = true; 8091 - wake_up(&rdev->irq.vblank_queue); 8092 - } 8093 - if (atomic_read(&rdev->irq.pflip[4])) 8094 - radeon_crtc_handle_vblank(rdev, 4); 8095 - rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 8096 - DRM_DEBUG("IH: D5 vblank\n"); 8071 + if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)) 8072 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8073 + 8074 + if (rdev->irq.crtc_vblank_int[4]) { 8075 + drm_handle_vblank(rdev->ddev, 4); 8076 + rdev->pm.vblank_sync = true; 8077 + wake_up(&rdev->irq.vblank_queue); 8097 8078 } 8079 + if (atomic_read(&rdev->irq.pflip[4])) 8080 + radeon_crtc_handle_vblank(rdev, 4); 8081 + rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 8082 + DRM_DEBUG("IH: D5 vblank\n"); 8083 + 8098 8084 break; 8099 8085 case 1: /* D5 vline */ 8100 - if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 8101 - rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 8102 - DRM_DEBUG("IH: D5 vline\n"); 8103 - } 8086 + if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)) 8087 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8088 + 8089 + rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 8090 + DRM_DEBUG("IH: D5 vline\n"); 8091 + 8104 8092 break; 8105 8093 default: 8106 8094 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 8114 8094 case 6: /* D6 vblank/vline */ 8115 8095 switch (src_data) { 8116 8096 case 0: /* D6 vblank */ 8117 - if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 8118 - if (rdev->irq.crtc_vblank_int[5]) { 8119 - drm_handle_vblank(rdev->ddev, 5); 8120 - rdev->pm.vblank_sync = true; 8121 - wake_up(&rdev->irq.vblank_queue); 8122 - } 8123 - if (atomic_read(&rdev->irq.pflip[5])) 8124 - radeon_crtc_handle_vblank(rdev, 5); 8125 - rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 8126 - DRM_DEBUG("IH: D6 vblank\n"); 8097 + if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)) 8098 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8099 + 8100 + if (rdev->irq.crtc_vblank_int[5]) { 8101 + drm_handle_vblank(rdev->ddev, 5); 8102 + rdev->pm.vblank_sync = true; 8103 + wake_up(&rdev->irq.vblank_queue); 8127 8104 } 8105 + if (atomic_read(&rdev->irq.pflip[5])) 8106 + radeon_crtc_handle_vblank(rdev, 5); 8107 + rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 8108 + DRM_DEBUG("IH: D6 vblank\n"); 8109 + 8128 8110 break; 8129 8111 case 1: /* D6 vline */ 8130 - if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 8131 - rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 8132 - DRM_DEBUG("IH: D6 vline\n"); 8133 - } 8112 + if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)) 8113 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8114 + 8115 + rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 8116 + DRM_DEBUG("IH: D6 vline\n"); 8117 + 8134 8118 break; 8135 8119 default: 8136 8120 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 8154 8130 case 42: /* HPD hotplug */ 8155 8131 switch (src_data) { 8156 8132 case 0: 8157 - if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) { 8158 - rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT; 8159 - queue_hotplug = true; 8160 - DRM_DEBUG("IH: HPD1\n"); 8161 - } 8133 + if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT)) 8134 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8135 + 8136 + rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT; 8137 + queue_hotplug = true; 8138 + DRM_DEBUG("IH: HPD1\n"); 8139 + 8162 8140 break; 8163 8141 case 1: 8164 - if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) { 8165 - rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT; 8166 - queue_hotplug = true; 8167 - DRM_DEBUG("IH: HPD2\n"); 8168 - } 8142 + if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT)) 8143 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8144 + 8145 + rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT; 8146 + queue_hotplug = true; 8147 + DRM_DEBUG("IH: HPD2\n"); 8148 + 8169 8149 break; 8170 8150 case 2: 8171 - if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) { 8172 - rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 8173 - queue_hotplug = true; 8174 - DRM_DEBUG("IH: HPD3\n"); 8175 - } 8151 + if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT)) 8152 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8153 + 8154 + rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 8155 + queue_hotplug = true; 8156 + DRM_DEBUG("IH: HPD3\n"); 8157 + 8176 8158 break; 8177 8159 case 3: 8178 - if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) { 8179 - rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 8180 - queue_hotplug = true; 8181 - DRM_DEBUG("IH: HPD4\n"); 8182 - } 8160 + if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT)) 8161 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8162 + 8163 + rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 8164 + queue_hotplug = true; 8165 + DRM_DEBUG("IH: HPD4\n"); 8166 + 8183 8167 break; 8184 8168 case 4: 8185 - if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) { 8186 - rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 8187 - queue_hotplug = true; 8188 - DRM_DEBUG("IH: HPD5\n"); 8189 - } 8169 + if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT)) 8170 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8171 + 8172 + rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 8173 + queue_hotplug = true; 8174 + DRM_DEBUG("IH: HPD5\n"); 8175 + 8190 8176 break; 8191 8177 case 5: 8192 - if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) { 8193 - rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 8194 - queue_hotplug = true; 8195 - DRM_DEBUG("IH: HPD6\n"); 8196 - } 8178 + if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT)) 8179 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8180 + 8181 + rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 8182 + queue_hotplug = true; 8183 + DRM_DEBUG("IH: HPD6\n"); 8184 + 8197 8185 break; 8198 8186 case 6: 8199 - if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) { 8200 - rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT; 8201 - queue_dp = true; 8202 - DRM_DEBUG("IH: HPD_RX 1\n"); 8203 - } 8187 + if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT)) 8188 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8189 + 8190 + rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT; 8191 + queue_dp = true; 8192 + DRM_DEBUG("IH: HPD_RX 1\n"); 8193 + 8204 8194 break; 8205 8195 case 7: 8206 - if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT) { 8207 - rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; 8208 - queue_dp = true; 8209 - DRM_DEBUG("IH: HPD_RX 2\n"); 8210 - } 8196 + if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT)) 8197 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8198 + 8199 + rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; 8200 + queue_dp = true; 8201 + DRM_DEBUG("IH: HPD_RX 2\n"); 8202 + 8211 8203 break; 8212 8204 case 8: 8213 - if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { 8214 - rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; 8215 - queue_dp = true; 8216 - DRM_DEBUG("IH: HPD_RX 3\n"); 8217 - } 8205 + if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT)) 8206 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8207 + 8208 + rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; 8209 + queue_dp = true; 8210 + DRM_DEBUG("IH: HPD_RX 3\n"); 8211 + 8218 8212 break; 8219 8213 case 9: 8220 - if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { 8221 - rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; 8222 - queue_dp = true; 8223 - DRM_DEBUG("IH: HPD_RX 4\n"); 8224 - } 8214 + if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT)) 8215 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8216 + 8217 + rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; 8218 + queue_dp = true; 8219 + DRM_DEBUG("IH: HPD_RX 4\n"); 8220 + 8225 8221 break; 8226 8222 case 10: 8227 - if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { 8228 - rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; 8229 - queue_dp = true; 8230 - DRM_DEBUG("IH: HPD_RX 5\n"); 8231 - } 8223 + if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT)) 8224 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8225 + 8226 + rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; 8227 + queue_dp = true; 8228 + DRM_DEBUG("IH: HPD_RX 5\n"); 8229 + 8232 8230 break; 8233 8231 case 11: 8234 - if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { 8235 - rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; 8236 - queue_dp = true; 8237 - DRM_DEBUG("IH: HPD_RX 6\n"); 8238 - } 8232 + if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT)) 8233 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 8234 + 8235 + rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; 8236 + queue_dp = true; 8237 + DRM_DEBUG("IH: HPD_RX 6\n"); 8238 + 8239 8239 break; 8240 8240 default: 8241 8241 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
+217 -175
drivers/gpu/drm/radeon/evergreen.c
··· 4924 4924 return IRQ_NONE; 4925 4925 4926 4926 rptr = rdev->ih.rptr; 4927 - DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4927 + DRM_DEBUG("evergreen_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 4928 4928 4929 4929 /* Order reading of wptr vs. reading of IH ring data */ 4930 4930 rmb(); ··· 4942 4942 case 1: /* D1 vblank/vline */ 4943 4943 switch (src_data) { 4944 4944 case 0: /* D1 vblank */ 4945 - if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { 4946 - if (rdev->irq.crtc_vblank_int[0]) { 4947 - drm_handle_vblank(rdev->ddev, 0); 4948 - rdev->pm.vblank_sync = true; 4949 - wake_up(&rdev->irq.vblank_queue); 4950 - } 4951 - if (atomic_read(&rdev->irq.pflip[0])) 4952 - radeon_crtc_handle_vblank(rdev, 0); 4953 - rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4954 - DRM_DEBUG("IH: D1 vblank\n"); 4945 + if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)) 4946 + DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n"); 4947 + 4948 + if (rdev->irq.crtc_vblank_int[0]) { 4949 + drm_handle_vblank(rdev->ddev, 0); 4950 + rdev->pm.vblank_sync = true; 4951 + wake_up(&rdev->irq.vblank_queue); 4955 4952 } 4953 + if (atomic_read(&rdev->irq.pflip[0])) 4954 + radeon_crtc_handle_vblank(rdev, 0); 4955 + rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4956 + DRM_DEBUG("IH: D1 vblank\n"); 4957 + 4956 4958 break; 4957 4959 case 1: /* D1 vline */ 4958 - if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { 4959 - rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4960 - DRM_DEBUG("IH: D1 vline\n"); 4961 - } 4960 + if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)) 4961 + DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n"); 4962 + 4963 + rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4964 + DRM_DEBUG("IH: D1 vline\n"); 4965 + 4962 4966 break; 4963 4967 default: 4964 4968 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 4972 4968 case 2: /* D2 vblank/vline */ 4973 4969 switch (src_data) { 4974 4970 case 0: /* D2 vblank */ 4975 - if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 4976 - if (rdev->irq.crtc_vblank_int[1]) { 4977 - drm_handle_vblank(rdev->ddev, 1); 4978 - rdev->pm.vblank_sync = true; 4979 - wake_up(&rdev->irq.vblank_queue); 4980 - } 4981 - if (atomic_read(&rdev->irq.pflip[1])) 4982 - radeon_crtc_handle_vblank(rdev, 1); 4983 - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 4984 - DRM_DEBUG("IH: D2 vblank\n"); 4971 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)) 4972 + DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n"); 4973 + 4974 + if (rdev->irq.crtc_vblank_int[1]) { 4975 + drm_handle_vblank(rdev->ddev, 1); 4976 + rdev->pm.vblank_sync = true; 4977 + wake_up(&rdev->irq.vblank_queue); 4985 4978 } 4979 + if (atomic_read(&rdev->irq.pflip[1])) 4980 + radeon_crtc_handle_vblank(rdev, 1); 4981 + rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 4982 + DRM_DEBUG("IH: D2 vblank\n"); 4983 + 4986 4984 break; 4987 4985 case 1: /* D2 vline */ 4988 - if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { 4989 - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 4990 - DRM_DEBUG("IH: D2 vline\n"); 4991 - } 4986 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)) 4987 + DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n"); 4988 + 4989 + rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 4990 + DRM_DEBUG("IH: D2 vline\n"); 4991 + 4992 4992 break; 4993 4993 default: 4994 4994 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 5002 4994 case 3: /* D3 vblank/vline */ 5003 4995 switch (src_data) { 5004 4996 case 0: /* D3 vblank */ 5005 - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 5006 - if (rdev->irq.crtc_vblank_int[2]) { 5007 - drm_handle_vblank(rdev->ddev, 2); 5008 - rdev->pm.vblank_sync = true; 5009 - wake_up(&rdev->irq.vblank_queue); 5010 - } 5011 - if (atomic_read(&rdev->irq.pflip[2])) 5012 - radeon_crtc_handle_vblank(rdev, 2); 5013 - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 5014 - DRM_DEBUG("IH: D3 vblank\n"); 4997 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)) 4998 + DRM_DEBUG("IH: D3 vblank - IH event w/o asserted irq bit?\n"); 4999 + 5000 + if (rdev->irq.crtc_vblank_int[2]) { 5001 + drm_handle_vblank(rdev->ddev, 2); 5002 + rdev->pm.vblank_sync = true; 5003 + wake_up(&rdev->irq.vblank_queue); 5015 5004 } 5005 + if (atomic_read(&rdev->irq.pflip[2])) 5006 + radeon_crtc_handle_vblank(rdev, 2); 5007 + rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 5008 + DRM_DEBUG("IH: D3 vblank\n"); 5009 + 5016 5010 break; 5017 5011 case 1: /* D3 vline */ 5018 - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 5019 - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 5020 - DRM_DEBUG("IH: D3 vline\n"); 5021 - } 5012 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)) 5013 + DRM_DEBUG("IH: D3 vline - IH event w/o asserted irq bit?\n"); 5014 + 5015 + rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 5016 + DRM_DEBUG("IH: D3 vline\n"); 5017 + 5022 5018 break; 5023 5019 default: 5024 5020 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 5032 5020 case 4: /* D4 vblank/vline */ 5033 5021 switch (src_data) { 5034 5022 case 0: /* D4 vblank */ 5035 - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 5036 - if (rdev->irq.crtc_vblank_int[3]) { 5037 - drm_handle_vblank(rdev->ddev, 3); 5038 - rdev->pm.vblank_sync = true; 5039 - wake_up(&rdev->irq.vblank_queue); 5040 - } 5041 - if (atomic_read(&rdev->irq.pflip[3])) 5042 - radeon_crtc_handle_vblank(rdev, 3); 5043 - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 5044 - DRM_DEBUG("IH: D4 vblank\n"); 5023 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)) 5024 + DRM_DEBUG("IH: D4 vblank - IH event w/o asserted irq bit?\n"); 5025 + 5026 + if (rdev->irq.crtc_vblank_int[3]) { 5027 + drm_handle_vblank(rdev->ddev, 3); 5028 + rdev->pm.vblank_sync = true; 5029 + wake_up(&rdev->irq.vblank_queue); 5045 5030 } 5031 + if (atomic_read(&rdev->irq.pflip[3])) 5032 + radeon_crtc_handle_vblank(rdev, 3); 5033 + rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 5034 + DRM_DEBUG("IH: D4 vblank\n"); 5035 + 5046 5036 break; 5047 5037 case 1: /* D4 vline */ 5048 - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 5049 - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 5050 - DRM_DEBUG("IH: D4 vline\n"); 5051 - } 5038 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)) 5039 + DRM_DEBUG("IH: D4 vline - IH event w/o asserted irq bit?\n"); 5040 + 5041 + rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 5042 + DRM_DEBUG("IH: D4 vline\n"); 5043 + 5052 5044 break; 5053 5045 default: 5054 5046 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 5062 5046 case 5: /* D5 vblank/vline */ 5063 5047 switch (src_data) { 5064 5048 case 0: /* D5 vblank */ 5065 - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 5066 - if (rdev->irq.crtc_vblank_int[4]) { 5067 - drm_handle_vblank(rdev->ddev, 4); 5068 - rdev->pm.vblank_sync = true; 5069 - wake_up(&rdev->irq.vblank_queue); 5070 - } 5071 - if (atomic_read(&rdev->irq.pflip[4])) 5072 - radeon_crtc_handle_vblank(rdev, 4); 5073 - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 5074 - DRM_DEBUG("IH: D5 vblank\n"); 5049 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)) 5050 + DRM_DEBUG("IH: D5 vblank - IH event w/o asserted irq bit?\n"); 5051 + 5052 + if (rdev->irq.crtc_vblank_int[4]) { 5053 + drm_handle_vblank(rdev->ddev, 4); 5054 + rdev->pm.vblank_sync = true; 5055 + wake_up(&rdev->irq.vblank_queue); 5075 5056 } 5057 + if (atomic_read(&rdev->irq.pflip[4])) 5058 + radeon_crtc_handle_vblank(rdev, 4); 5059 + rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 5060 + DRM_DEBUG("IH: D5 vblank\n"); 5061 + 5076 5062 break; 5077 5063 case 1: /* D5 vline */ 5078 - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 5079 - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 5080 - DRM_DEBUG("IH: D5 vline\n"); 5081 - } 5064 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)) 5065 + DRM_DEBUG("IH: D5 vline - IH event w/o asserted irq bit?\n"); 5066 + 5067 + rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 5068 + DRM_DEBUG("IH: D5 vline\n"); 5069 + 5082 5070 break; 5083 5071 default: 5084 5072 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 5092 5072 case 6: /* D6 vblank/vline */ 5093 5073 switch (src_data) { 5094 5074 case 0: /* D6 vblank */ 5095 - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 5096 - if (rdev->irq.crtc_vblank_int[5]) { 5097 - drm_handle_vblank(rdev->ddev, 5); 5098 - rdev->pm.vblank_sync = true; 5099 - wake_up(&rdev->irq.vblank_queue); 5100 - } 5101 - if (atomic_read(&rdev->irq.pflip[5])) 5102 - radeon_crtc_handle_vblank(rdev, 5); 5103 - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 5104 - DRM_DEBUG("IH: D6 vblank\n"); 5075 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)) 5076 + DRM_DEBUG("IH: D6 vblank - IH event w/o asserted irq bit?\n"); 5077 + 5078 + if (rdev->irq.crtc_vblank_int[5]) { 5079 + drm_handle_vblank(rdev->ddev, 5); 5080 + rdev->pm.vblank_sync = true; 5081 + wake_up(&rdev->irq.vblank_queue); 5105 5082 } 5083 + if (atomic_read(&rdev->irq.pflip[5])) 5084 + radeon_crtc_handle_vblank(rdev, 5); 5085 + rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 5086 + DRM_DEBUG("IH: D6 vblank\n"); 5087 + 5106 5088 break; 5107 5089 case 1: /* D6 vline */ 5108 - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 5109 - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 5110 - DRM_DEBUG("IH: D6 vline\n"); 5111 - } 5090 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)) 5091 + DRM_DEBUG("IH: D6 vline - IH event w/o asserted irq bit?\n"); 5092 + 5093 + rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 5094 + DRM_DEBUG("IH: D6 vline\n"); 5095 + 5112 5096 break; 5113 5097 default: 5114 5098 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 5132 5108 case 42: /* HPD hotplug */ 5133 5109 switch (src_data) { 5134 5110 case 0: 5135 - if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 5136 - rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 5137 - queue_hotplug = true; 5138 - DRM_DEBUG("IH: HPD1\n"); 5139 - } 5111 + if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT)) 5112 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5113 + 5114 + rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 5115 + queue_hotplug = true; 5116 + DRM_DEBUG("IH: HPD1\n"); 5140 5117 break; 5141 5118 case 1: 5142 - if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 5143 - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 5144 - queue_hotplug = true; 5145 - DRM_DEBUG("IH: HPD2\n"); 5146 - } 5119 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT)) 5120 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5121 + 5122 + rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 5123 + queue_hotplug = true; 5124 + DRM_DEBUG("IH: HPD2\n"); 5147 5125 break; 5148 5126 case 2: 5149 - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 5150 - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 5151 - queue_hotplug = true; 5152 - DRM_DEBUG("IH: HPD3\n"); 5153 - } 5127 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT)) 5128 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5129 + 5130 + rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 5131 + queue_hotplug = true; 5132 + DRM_DEBUG("IH: HPD3\n"); 5154 5133 break; 5155 5134 case 3: 5156 - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 5157 - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 5158 - queue_hotplug = true; 5159 - DRM_DEBUG("IH: HPD4\n"); 5160 - } 5135 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT)) 5136 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5137 + 5138 + rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 5139 + queue_hotplug = true; 5140 + DRM_DEBUG("IH: HPD4\n"); 5161 5141 break; 5162 5142 case 4: 5163 - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 5164 - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 5165 - queue_hotplug = true; 5166 - DRM_DEBUG("IH: HPD5\n"); 5167 - } 5143 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT)) 5144 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5145 + 5146 + rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 5147 + queue_hotplug = true; 5148 + DRM_DEBUG("IH: HPD5\n"); 5168 5149 break; 5169 5150 case 5: 5170 - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 5171 - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 5172 - queue_hotplug = true; 5173 - DRM_DEBUG("IH: HPD6\n"); 5174 - } 5151 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT)) 5152 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5153 + 5154 + rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 5155 + queue_hotplug = true; 5156 + DRM_DEBUG("IH: HPD6\n"); 5175 5157 break; 5176 5158 case 6: 5177 - if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) { 5178 - rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; 5179 - queue_dp = true; 5180 - DRM_DEBUG("IH: HPD_RX 1\n"); 5181 - } 5159 + if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT)) 5160 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5161 + 5162 + rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; 5163 + queue_dp = true; 5164 + DRM_DEBUG("IH: HPD_RX 1\n"); 5182 5165 break; 5183 5166 case 7: 5184 - if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) { 5185 - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; 5186 - queue_dp = true; 5187 - DRM_DEBUG("IH: HPD_RX 2\n"); 5188 - } 5167 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT)) 5168 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5169 + 5170 + rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; 5171 + queue_dp = true; 5172 + DRM_DEBUG("IH: HPD_RX 2\n"); 5189 5173 break; 5190 5174 case 8: 5191 - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { 5192 - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; 5193 - queue_dp = true; 5194 - DRM_DEBUG("IH: HPD_RX 3\n"); 5195 - } 5175 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT)) 5176 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5177 + 5178 + rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; 5179 + queue_dp = true; 5180 + DRM_DEBUG("IH: HPD_RX 3\n"); 5196 5181 break; 5197 5182 case 9: 5198 - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { 5199 - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; 5200 - queue_dp = true; 5201 - DRM_DEBUG("IH: HPD_RX 4\n"); 5202 - } 5183 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT)) 5184 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5185 + 5186 + rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; 5187 + queue_dp = true; 5188 + DRM_DEBUG("IH: HPD_RX 4\n"); 5203 5189 break; 5204 5190 case 10: 5205 - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { 5206 - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; 5207 - queue_dp = true; 5208 - DRM_DEBUG("IH: HPD_RX 5\n"); 5209 - } 5191 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT)) 5192 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5193 + 5194 + rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; 5195 + queue_dp = true; 5196 + DRM_DEBUG("IH: HPD_RX 5\n"); 5210 5197 break; 5211 5198 case 11: 5212 - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { 5213 - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; 5214 - queue_dp = true; 5215 - DRM_DEBUG("IH: HPD_RX 6\n"); 5216 - } 5199 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT)) 5200 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5201 + 5202 + rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; 5203 + queue_dp = true; 5204 + DRM_DEBUG("IH: HPD_RX 6\n"); 5217 5205 break; 5218 5206 default: 5219 5207 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 5235 5199 case 44: /* hdmi */ 5236 5200 switch (src_data) { 5237 5201 case 0: 5238 - if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { 5239 - rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG; 5240 - queue_hdmi = true; 5241 - DRM_DEBUG("IH: HDMI0\n"); 5242 - } 5202 + if (!(rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG)) 5203 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5204 + 5205 + rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG; 5206 + queue_hdmi = true; 5207 + DRM_DEBUG("IH: HDMI0\n"); 5243 5208 break; 5244 5209 case 1: 5245 - if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { 5246 - rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG; 5247 - queue_hdmi = true; 5248 - DRM_DEBUG("IH: HDMI1\n"); 5249 - } 5210 + if (!(rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG)) 5211 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5212 + 5213 + rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG; 5214 + queue_hdmi = true; 5215 + DRM_DEBUG("IH: HDMI1\n"); 5250 5216 break; 5251 5217 case 2: 5252 - if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { 5253 - rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG; 5254 - queue_hdmi = true; 5255 - DRM_DEBUG("IH: HDMI2\n"); 5256 - } 5218 + if (!(rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG)) 5219 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5220 + 5221 + rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG; 5222 + queue_hdmi = true; 5223 + DRM_DEBUG("IH: HDMI2\n"); 5257 5224 break; 5258 5225 case 3: 5259 - if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { 5260 - rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG; 5261 - queue_hdmi = true; 5262 - DRM_DEBUG("IH: HDMI3\n"); 5263 - } 5226 + if (!(rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG)) 5227 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5228 + 5229 + rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG; 5230 + queue_hdmi = true; 5231 + DRM_DEBUG("IH: HDMI3\n"); 5264 5232 break; 5265 5233 case 4: 5266 - if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { 5267 - rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG; 5268 - queue_hdmi = true; 5269 - DRM_DEBUG("IH: HDMI4\n"); 5270 - } 5234 + if (!(rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG)) 5235 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5236 + 5237 + rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG; 5238 + queue_hdmi = true; 5239 + DRM_DEBUG("IH: HDMI4\n"); 5271 5240 break; 5272 5241 case 5: 5273 - if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { 5274 - rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG; 5275 - queue_hdmi = true; 5276 - DRM_DEBUG("IH: HDMI5\n"); 5277 - } 5242 + if (!(rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG)) 5243 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 5244 + 5245 + rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG; 5246 + queue_hdmi = true; 5247 + DRM_DEBUG("IH: HDMI5\n"); 5278 5248 break; 5279 5249 default: 5280 5250 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
+14 -11
drivers/gpu/drm/radeon/ni.c
··· 2162 2162 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); 2163 2163 } 2164 2164 2165 - ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; 2166 - if (ring->ring_size) 2167 - r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); 2165 + if (rdev->family == CHIP_ARUBA) { 2166 + ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; 2167 + if (ring->ring_size) 2168 + r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); 2168 2169 2169 - ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; 2170 - if (ring->ring_size) 2171 - r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); 2170 + ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; 2171 + if (ring->ring_size) 2172 + r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); 2172 2173 2173 - if (!r) 2174 - r = vce_v1_0_init(rdev); 2175 - else if (r != -ENOENT) 2176 - DRM_ERROR("radeon: failed initializing VCE (%d).\n", r); 2174 + if (!r) 2175 + r = vce_v1_0_init(rdev); 2176 + if (r) 2177 + DRM_ERROR("radeon: failed initializing VCE (%d).\n", r); 2178 + } 2177 2179 2178 2180 r = radeon_ib_pool_init(rdev); 2179 2181 if (r) { ··· 2398 2396 radeon_irq_kms_fini(rdev); 2399 2397 uvd_v1_0_fini(rdev); 2400 2398 radeon_uvd_fini(rdev); 2401 - radeon_vce_fini(rdev); 2399 + if (rdev->family == CHIP_ARUBA) 2400 + radeon_vce_fini(rdev); 2402 2401 cayman_pcie_gart_fini(rdev); 2403 2402 r600_vram_scratch_fini(rdev); 2404 2403 radeon_gem_fini(rdev);
+87 -68
drivers/gpu/drm/radeon/r600.c
··· 4086 4086 case 1: /* D1 vblank/vline */ 4087 4087 switch (src_data) { 4088 4088 case 0: /* D1 vblank */ 4089 - if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 4090 - if (rdev->irq.crtc_vblank_int[0]) { 4091 - drm_handle_vblank(rdev->ddev, 0); 4092 - rdev->pm.vblank_sync = true; 4093 - wake_up(&rdev->irq.vblank_queue); 4094 - } 4095 - if (atomic_read(&rdev->irq.pflip[0])) 4096 - radeon_crtc_handle_vblank(rdev, 0); 4097 - rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4098 - DRM_DEBUG("IH: D1 vblank\n"); 4089 + if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) 4090 + DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n"); 4091 + 4092 + if (rdev->irq.crtc_vblank_int[0]) { 4093 + drm_handle_vblank(rdev->ddev, 0); 4094 + rdev->pm.vblank_sync = true; 4095 + wake_up(&rdev->irq.vblank_queue); 4099 4096 } 4097 + if (atomic_read(&rdev->irq.pflip[0])) 4098 + radeon_crtc_handle_vblank(rdev, 0); 4099 + rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 4100 + DRM_DEBUG("IH: D1 vblank\n"); 4101 + 4100 4102 break; 4101 4103 case 1: /* D1 vline */ 4102 - if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 4103 - rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4104 - DRM_DEBUG("IH: D1 vline\n"); 4105 - } 4104 + if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) 4105 + DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n"); 4106 + 4107 + rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 4108 + DRM_DEBUG("IH: D1 vline\n"); 4109 + 4106 4110 break; 4107 4111 default: 4108 4112 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 4116 4112 case 5: /* D2 vblank/vline */ 4117 4113 switch (src_data) { 4118 4114 case 0: /* D2 vblank */ 4119 - if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 4120 - if (rdev->irq.crtc_vblank_int[1]) { 4121 - drm_handle_vblank(rdev->ddev, 1); 4122 - rdev->pm.vblank_sync = true; 4123 - wake_up(&rdev->irq.vblank_queue); 4124 - } 4125 - if (atomic_read(&rdev->irq.pflip[1])) 4126 - radeon_crtc_handle_vblank(rdev, 1); 4127 - rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4128 - DRM_DEBUG("IH: D2 vblank\n"); 4115 + if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) 4116 + DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n"); 4117 + 4118 + if (rdev->irq.crtc_vblank_int[1]) { 4119 + drm_handle_vblank(rdev->ddev, 1); 4120 + rdev->pm.vblank_sync = true; 4121 + wake_up(&rdev->irq.vblank_queue); 4129 4122 } 4123 + if (atomic_read(&rdev->irq.pflip[1])) 4124 + radeon_crtc_handle_vblank(rdev, 1); 4125 + rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 4126 + DRM_DEBUG("IH: D2 vblank\n"); 4127 + 4130 4128 break; 4131 4129 case 1: /* D1 vline */ 4132 - if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 4133 - rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4134 - DRM_DEBUG("IH: D2 vline\n"); 4135 - } 4130 + if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) 4131 + DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n"); 4132 + 4133 + rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 4134 + DRM_DEBUG("IH: D2 vline\n"); 4135 + 4136 4136 break; 4137 4137 default: 4138 4138 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 4156 4148 case 19: /* HPD/DAC hotplug */ 4157 4149 switch (src_data) { 4158 4150 case 0: 4159 - if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 4160 - rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4161 - queue_hotplug = true; 4162 - DRM_DEBUG("IH: HPD1\n"); 4163 - } 4151 + if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) 4152 + DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n"); 4153 + 4154 + rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 4155 + queue_hotplug = true; 4156 + DRM_DEBUG("IH: HPD1\n"); 4164 4157 break; 4165 4158 case 1: 4166 - if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 4167 - rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4168 - queue_hotplug = true; 4169 - DRM_DEBUG("IH: HPD2\n"); 4170 - } 4159 + if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) 4160 + DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n"); 4161 + 4162 + rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 4163 + queue_hotplug = true; 4164 + DRM_DEBUG("IH: HPD2\n"); 4171 4165 break; 4172 4166 case 4: 4173 - if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 4174 - rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4175 - queue_hotplug = true; 4176 - DRM_DEBUG("IH: HPD3\n"); 4177 - } 4167 + if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) 4168 + DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n"); 4169 + 4170 + rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 4171 + queue_hotplug = true; 4172 + DRM_DEBUG("IH: HPD3\n"); 4178 4173 break; 4179 4174 case 5: 4180 - if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 4181 - rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4182 - queue_hotplug = true; 4183 - DRM_DEBUG("IH: HPD4\n"); 4184 - } 4175 + if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) 4176 + DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n"); 4177 + 4178 + rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 4179 + queue_hotplug = true; 4180 + DRM_DEBUG("IH: HPD4\n"); 4185 4181 break; 4186 4182 case 10: 4187 - if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 4188 - rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4189 - queue_hotplug = true; 4190 - DRM_DEBUG("IH: HPD5\n"); 4191 - } 4183 + if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) 4184 + DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n"); 4185 + 4186 + rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 4187 + queue_hotplug = true; 4188 + DRM_DEBUG("IH: HPD5\n"); 4192 4189 break; 4193 4190 case 12: 4194 - if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 4195 - rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4196 - queue_hotplug = true; 4197 - DRM_DEBUG("IH: HPD6\n"); 4198 - } 4191 + if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) 4192 + DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n"); 4193 + 4194 + rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 4195 + queue_hotplug = true; 4196 + DRM_DEBUG("IH: HPD6\n"); 4197 + 4199 4198 break; 4200 4199 default: 4201 4200 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 4212 4197 case 21: /* hdmi */ 4213 4198 switch (src_data) { 4214 4199 case 4: 4215 - if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4216 - rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4217 - queue_hdmi = true; 4218 - DRM_DEBUG("IH: HDMI0\n"); 4219 - } 4200 + if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) 4201 + DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n"); 4202 + 4203 + rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4204 + queue_hdmi = true; 4205 + DRM_DEBUG("IH: HDMI0\n"); 4206 + 4220 4207 break; 4221 4208 case 5: 4222 - if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4223 - rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4224 - queue_hdmi = true; 4225 - DRM_DEBUG("IH: HDMI1\n"); 4226 - } 4209 + if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) 4210 + DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n"); 4211 + 4212 + rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4213 + queue_hdmi = true; 4214 + DRM_DEBUG("IH: HDMI1\n"); 4215 + 4227 4216 break; 4228 4217 default: 4229 4218 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
+1 -1
drivers/gpu/drm/radeon/r600_cp.c
··· 2483 2483 struct drm_buf *buf; 2484 2484 u32 *buffer; 2485 2485 const u8 __user *data; 2486 - int size, pass_size; 2486 + unsigned int size, pass_size; 2487 2487 u64 src_offset, dst_offset; 2488 2488 2489 2489 if (!radeon_check_offset(dev_priv, tex->offset)) {
+44 -65
drivers/gpu/drm/radeon/radeon_cursor.c
··· 91 91 struct radeon_device *rdev = crtc->dev->dev_private; 92 92 93 93 if (ASIC_IS_DCE4(rdev)) { 94 + WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 95 + upper_32_bits(radeon_crtc->cursor_addr)); 96 + WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 97 + lower_32_bits(radeon_crtc->cursor_addr)); 94 98 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset); 95 99 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN | 96 100 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) | 97 101 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2)); 98 102 } else if (ASIC_IS_AVIVO(rdev)) { 103 + if (rdev->family >= CHIP_RV770) { 104 + if (radeon_crtc->crtc_id) 105 + WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 106 + upper_32_bits(radeon_crtc->cursor_addr)); 107 + else 108 + WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 109 + upper_32_bits(radeon_crtc->cursor_addr)); 110 + } 111 + 112 + WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 113 + lower_32_bits(radeon_crtc->cursor_addr)); 99 114 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); 100 115 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | 101 116 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); 102 117 } else { 118 + /* offset is from DISP(2)_BASE_ADDRESS */ 119 + WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, 120 + radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr); 121 + 103 122 switch (radeon_crtc->crtc_id) { 104 123 case 0: 105 124 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); ··· 224 205 | (x << 16) 225 206 | y)); 226 207 /* offset is from DISP(2)_BASE_ADDRESS */ 227 - WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset + 228 - (yorigin * 256))); 208 + WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, 209 + radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr + 210 + yorigin * 256); 229 211 } 230 212 231 213 radeon_crtc->cursor_x = x; ··· 247 227 return ret; 248 228 } 249 229 250 - static int radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj) 251 - { 252 - struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 253 - struct radeon_device *rdev = crtc->dev->dev_private; 254 - struct radeon_bo *robj = gem_to_radeon_bo(obj); 255 - uint64_t gpu_addr; 256 - int ret; 257 - 258 - ret = radeon_bo_reserve(robj, false); 259 - if (unlikely(ret != 0)) 260 - goto fail; 261 - /* Only 27 bit offset for legacy cursor */ 262 - ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM, 263 - ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, 264 - &gpu_addr); 265 - radeon_bo_unreserve(robj); 266 - if (ret) 267 - goto fail; 268 - 269 - if (ASIC_IS_DCE4(rdev)) { 270 - WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 271 - upper_32_bits(gpu_addr)); 272 - WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 273 - gpu_addr & 0xffffffff); 274 - } else if (ASIC_IS_AVIVO(rdev)) { 275 - if (rdev->family >= CHIP_RV770) { 276 - if (radeon_crtc->crtc_id) 277 - WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); 278 - else 279 - WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr)); 280 - } 281 - WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 282 - gpu_addr & 0xffffffff); 283 - } else { 284 - radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; 285 - /* offset is from DISP(2)_BASE_ADDRESS */ 286 - WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); 287 - } 288 - 289 - return 0; 290 - 291 - fail: 292 - drm_gem_object_unreference_unlocked(obj); 293 - 294 - return ret; 295 - } 296 - 297 230 int radeon_crtc_cursor_set2(struct drm_crtc *crtc, 298 231 struct drm_file *file_priv, 299 232 uint32_t handle, ··· 256 283 int32_t hot_y) 257 284 { 258 285 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 286 + struct radeon_device *rdev = crtc->dev->dev_private; 259 287 struct drm_gem_object *obj; 288 + struct radeon_bo *robj; 260 289 int ret; 261 290 262 291 if (!handle) { ··· 280 305 return -ENOENT; 281 306 } 282 307 308 + robj = gem_to_radeon_bo(obj); 309 + ret = radeon_bo_reserve(robj, false); 310 + if (ret != 0) { 311 + drm_gem_object_unreference_unlocked(obj); 312 + return ret; 313 + } 314 + /* Only 27 bit offset for legacy cursor */ 315 + ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM, 316 + ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, 317 + &radeon_crtc->cursor_addr); 318 + radeon_bo_unreserve(robj); 319 + if (ret) { 320 + DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 321 + drm_gem_object_unreference_unlocked(obj); 322 + return ret; 323 + } 324 + 283 325 radeon_crtc->cursor_width = width; 284 326 radeon_crtc->cursor_height = height; 285 327 ··· 315 323 radeon_crtc->cursor_hot_y = hot_y; 316 324 } 317 325 318 - ret = radeon_set_cursor(crtc, obj); 319 - 320 - if (ret) 321 - DRM_ERROR("radeon_set_cursor returned %d, not changing cursor\n", 322 - ret); 323 - else 324 - radeon_show_cursor(crtc); 326 + radeon_show_cursor(crtc); 325 327 326 328 radeon_lock_cursor(crtc, false); 327 329 ··· 327 341 radeon_bo_unpin(robj); 328 342 radeon_bo_unreserve(robj); 329 343 } 330 - if (radeon_crtc->cursor_bo != obj) 331 - drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo); 344 + drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo); 332 345 } 333 346 334 347 radeon_crtc->cursor_bo = obj; ··· 345 360 void radeon_cursor_reset(struct drm_crtc *crtc) 346 361 { 347 362 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 348 - int ret; 349 363 350 364 if (radeon_crtc->cursor_bo) { 351 365 radeon_lock_cursor(crtc, true); ··· 352 368 radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x, 353 369 radeon_crtc->cursor_y); 354 370 355 - ret = radeon_set_cursor(crtc, radeon_crtc->cursor_bo); 356 - if (ret) 357 - DRM_ERROR("radeon_set_cursor returned %d, not showing " 358 - "cursor\n", ret); 359 - else 360 - radeon_show_cursor(crtc); 371 + radeon_show_cursor(crtc); 361 372 362 373 radeon_lock_cursor(crtc, false); 363 374 }
+52 -14
drivers/gpu/drm/radeon/radeon_device.c
··· 1080 1080 } 1081 1081 1082 1082 /** 1083 + * Determine a sensible default GART size according to ASIC family. 1084 + * 1085 + * @family ASIC family name 1086 + */ 1087 + static int radeon_gart_size_auto(enum radeon_family family) 1088 + { 1089 + /* default to a larger gart size on newer asics */ 1090 + if (family >= CHIP_TAHITI) 1091 + return 2048; 1092 + else if (family >= CHIP_RV770) 1093 + return 1024; 1094 + else 1095 + return 512; 1096 + } 1097 + 1098 + /** 1083 1099 * radeon_check_arguments - validate module params 1084 1100 * 1085 1101 * @rdev: radeon_device pointer ··· 1113 1097 } 1114 1098 1115 1099 if (radeon_gart_size == -1) { 1116 - /* default to a larger gart size on newer asics */ 1117 - if (rdev->family >= CHIP_RV770) 1118 - radeon_gart_size = 1024; 1119 - else 1120 - radeon_gart_size = 512; 1100 + radeon_gart_size = radeon_gart_size_auto(rdev->family); 1121 1101 } 1122 1102 /* gtt size must be power of two and greater or equal to 32M */ 1123 1103 if (radeon_gart_size < 32) { 1124 1104 dev_warn(rdev->dev, "gart size (%d) too small\n", 1125 1105 radeon_gart_size); 1126 - if (rdev->family >= CHIP_RV770) 1127 - radeon_gart_size = 1024; 1128 - else 1129 - radeon_gart_size = 512; 1106 + radeon_gart_size = radeon_gart_size_auto(rdev->family); 1130 1107 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 1131 1108 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 1132 1109 radeon_gart_size); 1133 - if (rdev->family >= CHIP_RV770) 1134 - radeon_gart_size = 1024; 1135 - else 1136 - radeon_gart_size = 512; 1110 + radeon_gart_size = radeon_gart_size_auto(rdev->family); 1137 1111 } 1138 1112 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 1139 1113 ··· 1578 1572 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1579 1573 } 1580 1574 1581 - /* unpin the front buffers */ 1575 + /* unpin the front buffers and cursors */ 1582 1576 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1577 + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1583 1578 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb); 1584 1579 struct radeon_bo *robj; 1580 + 1581 + if (radeon_crtc->cursor_bo) { 1582 + struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1583 + r = radeon_bo_reserve(robj, false); 1584 + if (r == 0) { 1585 + radeon_bo_unpin(robj); 1586 + radeon_bo_unreserve(robj); 1587 + } 1588 + } 1585 1589 1586 1590 if (rfb == NULL || rfb->obj == NULL) { 1587 1591 continue; ··· 1655 1639 { 1656 1640 struct drm_connector *connector; 1657 1641 struct radeon_device *rdev = dev->dev_private; 1642 + struct drm_crtc *crtc; 1658 1643 int r; 1659 1644 1660 1645 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) ··· 1694 1677 } 1695 1678 1696 1679 radeon_restore_bios_scratch_regs(rdev); 1680 + 1681 + /* pin cursors */ 1682 + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1683 + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1684 + 1685 + if (radeon_crtc->cursor_bo) { 1686 + struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1687 + r = radeon_bo_reserve(robj, false); 1688 + if (r == 0) { 1689 + /* Only 27 bit offset for legacy cursor */ 1690 + r = radeon_bo_pin_restricted(robj, 1691 + RADEON_GEM_DOMAIN_VRAM, 1692 + ASIC_IS_AVIVO(rdev) ? 1693 + 0 : 1 << 27, 1694 + &radeon_crtc->cursor_addr); 1695 + if (r != 0) 1696 + DRM_ERROR("Failed to pin cursor BO (%d)\n", r); 1697 + radeon_bo_unreserve(robj); 1698 + } 1699 + } 1700 + } 1697 1701 1698 1702 /* init dig PHYs, disp eng pll */ 1699 1703 if (rdev->is_atom_bios) {
+1
drivers/gpu/drm/radeon/radeon_fb.c
··· 257 257 } 258 258 259 259 info->par = rfbdev; 260 + info->skip_vt_switch = true; 260 261 261 262 ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj); 262 263 if (ret) {
+9 -3
drivers/gpu/drm/radeon/radeon_gem.c
··· 428 428 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 429 429 struct drm_file *filp) 430 430 { 431 - struct radeon_device *rdev = dev->dev_private; 432 431 struct drm_radeon_gem_busy *args = data; 433 432 struct drm_gem_object *gobj; 434 433 struct radeon_bo *robj; ··· 439 440 return -ENOENT; 440 441 } 441 442 robj = gem_to_radeon_bo(gobj); 442 - r = radeon_bo_wait(robj, &cur_placement, true); 443 + 444 + r = reservation_object_test_signaled_rcu(robj->tbo.resv, true); 445 + if (r == 0) 446 + r = -EBUSY; 447 + else 448 + r = 0; 449 + 450 + cur_placement = ACCESS_ONCE(robj->tbo.mem.mem_type); 443 451 args->domain = radeon_mem_type_to_domain(cur_placement); 444 452 drm_gem_object_unreference_unlocked(gobj); 445 - r = radeon_gem_handle_lockup(rdev, r); 446 453 return r; 447 454 } 448 455 ··· 476 471 r = ret; 477 472 478 473 /* Flush HDP cache via MMIO if necessary */ 474 + cur_placement = ACCESS_ONCE(robj->tbo.mem.mem_type); 479 475 if (rdev->asic->mmio_hdp_flush && 480 476 radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM) 481 477 robj->rdev->asic->mmio_hdp_flush(rdev);
-1
drivers/gpu/drm/radeon/radeon_mode.h
··· 343 343 int max_cursor_width; 344 344 int max_cursor_height; 345 345 uint32_t legacy_display_base_addr; 346 - uint32_t legacy_cursor_offset; 347 346 enum radeon_rmx_type rmx_type; 348 347 u8 h_border; 349 348 u8 v_border;
+19 -21
drivers/gpu/drm/radeon/radeon_vm.c
··· 493 493 } 494 494 495 495 if (bo_va->it.start || bo_va->it.last) { 496 - spin_lock(&vm->status_lock); 497 - if (list_empty(&bo_va->vm_status)) { 498 - /* add a clone of the bo_va to clear the old address */ 499 - struct radeon_bo_va *tmp; 500 - spin_unlock(&vm->status_lock); 501 - tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); 502 - if (!tmp) { 503 - mutex_unlock(&vm->mutex); 504 - r = -ENOMEM; 505 - goto error_unreserve; 506 - } 507 - tmp->it.start = bo_va->it.start; 508 - tmp->it.last = bo_va->it.last; 509 - tmp->vm = vm; 510 - tmp->bo = radeon_bo_ref(bo_va->bo); 511 - spin_lock(&vm->status_lock); 512 - list_add(&tmp->vm_status, &vm->freed); 496 + /* add a clone of the bo_va to clear the old address */ 497 + struct radeon_bo_va *tmp; 498 + tmp = kzalloc(sizeof(struct radeon_bo_va), GFP_KERNEL); 499 + if (!tmp) { 500 + mutex_unlock(&vm->mutex); 501 + r = -ENOMEM; 502 + goto error_unreserve; 513 503 } 514 - spin_unlock(&vm->status_lock); 504 + tmp->it.start = bo_va->it.start; 505 + tmp->it.last = bo_va->it.last; 506 + tmp->vm = vm; 507 + tmp->bo = radeon_bo_ref(bo_va->bo); 515 508 516 509 interval_tree_remove(&bo_va->it, &vm->va); 510 + spin_lock(&vm->status_lock); 517 511 bo_va->it.start = 0; 518 512 bo_va->it.last = 0; 513 + list_del_init(&bo_va->vm_status); 514 + list_add(&tmp->vm_status, &vm->freed); 515 + spin_unlock(&vm->status_lock); 519 516 } 520 517 521 518 if (soffset || eoffset) { 519 + spin_lock(&vm->status_lock); 522 520 bo_va->it.start = soffset; 523 521 bo_va->it.last = eoffset - 1; 524 - interval_tree_insert(&bo_va->it, &vm->va); 525 - spin_lock(&vm->status_lock); 526 522 list_add(&bo_va->vm_status, &vm->cleared); 527 523 spin_unlock(&vm->status_lock); 524 + interval_tree_insert(&bo_va->it, &vm->va); 528 525 } 529 526 530 527 bo_va->flags = flags; ··· 1155 1158 1156 1159 list_for_each_entry(bo_va, &bo->va, bo_list) { 1157 1160 spin_lock(&bo_va->vm->status_lock); 1158 - if (list_empty(&bo_va->vm_status)) 1161 + if (list_empty(&bo_va->vm_status) && 1162 + (bo_va->it.start || bo_va->it.last)) 1159 1163 list_add(&bo_va->vm_status, &bo_va->vm->invalidated); 1160 1164 spin_unlock(&bo_va->vm->status_lock); 1161 1165 }
+192 -144
drivers/gpu/drm/radeon/si.c
··· 6466 6466 case 1: /* D1 vblank/vline */ 6467 6467 switch (src_data) { 6468 6468 case 0: /* D1 vblank */ 6469 - if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { 6470 - if (rdev->irq.crtc_vblank_int[0]) { 6471 - drm_handle_vblank(rdev->ddev, 0); 6472 - rdev->pm.vblank_sync = true; 6473 - wake_up(&rdev->irq.vblank_queue); 6474 - } 6475 - if (atomic_read(&rdev->irq.pflip[0])) 6476 - radeon_crtc_handle_vblank(rdev, 0); 6477 - rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 6478 - DRM_DEBUG("IH: D1 vblank\n"); 6469 + if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)) 6470 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6471 + 6472 + if (rdev->irq.crtc_vblank_int[0]) { 6473 + drm_handle_vblank(rdev->ddev, 0); 6474 + rdev->pm.vblank_sync = true; 6475 + wake_up(&rdev->irq.vblank_queue); 6479 6476 } 6477 + if (atomic_read(&rdev->irq.pflip[0])) 6478 + radeon_crtc_handle_vblank(rdev, 0); 6479 + rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 6480 + DRM_DEBUG("IH: D1 vblank\n"); 6481 + 6480 6482 break; 6481 6483 case 1: /* D1 vline */ 6482 - if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { 6483 - rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 6484 - DRM_DEBUG("IH: D1 vline\n"); 6485 - } 6484 + if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)) 6485 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6486 + 6487 + rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 6488 + DRM_DEBUG("IH: D1 vline\n"); 6489 + 6486 6490 break; 6487 6491 default: 6488 6492 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 6496 6492 case 2: /* D2 vblank/vline */ 6497 6493 switch (src_data) { 6498 6494 case 0: /* D2 vblank */ 6499 - if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 6500 - if (rdev->irq.crtc_vblank_int[1]) { 6501 - drm_handle_vblank(rdev->ddev, 1); 6502 - rdev->pm.vblank_sync = true; 6503 - wake_up(&rdev->irq.vblank_queue); 6504 - } 6505 - if (atomic_read(&rdev->irq.pflip[1])) 6506 - radeon_crtc_handle_vblank(rdev, 1); 6507 - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 6508 - DRM_DEBUG("IH: D2 vblank\n"); 6495 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)) 6496 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6497 + 6498 + if (rdev->irq.crtc_vblank_int[1]) { 6499 + drm_handle_vblank(rdev->ddev, 1); 6500 + rdev->pm.vblank_sync = true; 6501 + wake_up(&rdev->irq.vblank_queue); 6509 6502 } 6503 + if (atomic_read(&rdev->irq.pflip[1])) 6504 + radeon_crtc_handle_vblank(rdev, 1); 6505 + rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 6506 + DRM_DEBUG("IH: D2 vblank\n"); 6507 + 6510 6508 break; 6511 6509 case 1: /* D2 vline */ 6512 - if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { 6513 - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 6514 - DRM_DEBUG("IH: D2 vline\n"); 6515 - } 6510 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)) 6511 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6512 + 6513 + rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 6514 + DRM_DEBUG("IH: D2 vline\n"); 6515 + 6516 6516 break; 6517 6517 default: 6518 6518 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 6526 6518 case 3: /* D3 vblank/vline */ 6527 6519 switch (src_data) { 6528 6520 case 0: /* D3 vblank */ 6529 - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 6530 - if (rdev->irq.crtc_vblank_int[2]) { 6531 - drm_handle_vblank(rdev->ddev, 2); 6532 - rdev->pm.vblank_sync = true; 6533 - wake_up(&rdev->irq.vblank_queue); 6534 - } 6535 - if (atomic_read(&rdev->irq.pflip[2])) 6536 - radeon_crtc_handle_vblank(rdev, 2); 6537 - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 6538 - DRM_DEBUG("IH: D3 vblank\n"); 6521 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)) 6522 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6523 + 6524 + if (rdev->irq.crtc_vblank_int[2]) { 6525 + drm_handle_vblank(rdev->ddev, 2); 6526 + rdev->pm.vblank_sync = true; 6527 + wake_up(&rdev->irq.vblank_queue); 6539 6528 } 6529 + if (atomic_read(&rdev->irq.pflip[2])) 6530 + radeon_crtc_handle_vblank(rdev, 2); 6531 + rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 6532 + DRM_DEBUG("IH: D3 vblank\n"); 6533 + 6540 6534 break; 6541 6535 case 1: /* D3 vline */ 6542 - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 6543 - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 6544 - DRM_DEBUG("IH: D3 vline\n"); 6545 - } 6536 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)) 6537 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6538 + 6539 + rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 6540 + DRM_DEBUG("IH: D3 vline\n"); 6541 + 6546 6542 break; 6547 6543 default: 6548 6544 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 6556 6544 case 4: /* D4 vblank/vline */ 6557 6545 switch (src_data) { 6558 6546 case 0: /* D4 vblank */ 6559 - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 6560 - if (rdev->irq.crtc_vblank_int[3]) { 6561 - drm_handle_vblank(rdev->ddev, 3); 6562 - rdev->pm.vblank_sync = true; 6563 - wake_up(&rdev->irq.vblank_queue); 6564 - } 6565 - if (atomic_read(&rdev->irq.pflip[3])) 6566 - radeon_crtc_handle_vblank(rdev, 3); 6567 - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 6568 - DRM_DEBUG("IH: D4 vblank\n"); 6547 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)) 6548 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6549 + 6550 + if (rdev->irq.crtc_vblank_int[3]) { 6551 + drm_handle_vblank(rdev->ddev, 3); 6552 + rdev->pm.vblank_sync = true; 6553 + wake_up(&rdev->irq.vblank_queue); 6569 6554 } 6555 + if (atomic_read(&rdev->irq.pflip[3])) 6556 + radeon_crtc_handle_vblank(rdev, 3); 6557 + rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 6558 + DRM_DEBUG("IH: D4 vblank\n"); 6559 + 6570 6560 break; 6571 6561 case 1: /* D4 vline */ 6572 - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 6573 - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 6574 - DRM_DEBUG("IH: D4 vline\n"); 6575 - } 6562 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)) 6563 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6564 + 6565 + rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 6566 + DRM_DEBUG("IH: D4 vline\n"); 6567 + 6576 6568 break; 6577 6569 default: 6578 6570 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 6586 6570 case 5: /* D5 vblank/vline */ 6587 6571 switch (src_data) { 6588 6572 case 0: /* D5 vblank */ 6589 - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 6590 - if (rdev->irq.crtc_vblank_int[4]) { 6591 - drm_handle_vblank(rdev->ddev, 4); 6592 - rdev->pm.vblank_sync = true; 6593 - wake_up(&rdev->irq.vblank_queue); 6594 - } 6595 - if (atomic_read(&rdev->irq.pflip[4])) 6596 - radeon_crtc_handle_vblank(rdev, 4); 6597 - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 6598 - DRM_DEBUG("IH: D5 vblank\n"); 6573 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)) 6574 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6575 + 6576 + if (rdev->irq.crtc_vblank_int[4]) { 6577 + drm_handle_vblank(rdev->ddev, 4); 6578 + rdev->pm.vblank_sync = true; 6579 + wake_up(&rdev->irq.vblank_queue); 6599 6580 } 6581 + if (atomic_read(&rdev->irq.pflip[4])) 6582 + radeon_crtc_handle_vblank(rdev, 4); 6583 + rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 6584 + DRM_DEBUG("IH: D5 vblank\n"); 6585 + 6600 6586 break; 6601 6587 case 1: /* D5 vline */ 6602 - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 6603 - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 6604 - DRM_DEBUG("IH: D5 vline\n"); 6605 - } 6588 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)) 6589 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6590 + 6591 + rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 6592 + DRM_DEBUG("IH: D5 vline\n"); 6593 + 6606 6594 break; 6607 6595 default: 6608 6596 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 6616 6596 case 6: /* D6 vblank/vline */ 6617 6597 switch (src_data) { 6618 6598 case 0: /* D6 vblank */ 6619 - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 6620 - if (rdev->irq.crtc_vblank_int[5]) { 6621 - drm_handle_vblank(rdev->ddev, 5); 6622 - rdev->pm.vblank_sync = true; 6623 - wake_up(&rdev->irq.vblank_queue); 6624 - } 6625 - if (atomic_read(&rdev->irq.pflip[5])) 6626 - radeon_crtc_handle_vblank(rdev, 5); 6627 - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 6628 - DRM_DEBUG("IH: D6 vblank\n"); 6599 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)) 6600 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6601 + 6602 + if (rdev->irq.crtc_vblank_int[5]) { 6603 + drm_handle_vblank(rdev->ddev, 5); 6604 + rdev->pm.vblank_sync = true; 6605 + wake_up(&rdev->irq.vblank_queue); 6629 6606 } 6607 + if (atomic_read(&rdev->irq.pflip[5])) 6608 + radeon_crtc_handle_vblank(rdev, 5); 6609 + rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 6610 + DRM_DEBUG("IH: D6 vblank\n"); 6611 + 6630 6612 break; 6631 6613 case 1: /* D6 vline */ 6632 - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 6633 - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 6634 - DRM_DEBUG("IH: D6 vline\n"); 6635 - } 6614 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)) 6615 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6616 + 6617 + rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 6618 + DRM_DEBUG("IH: D6 vline\n"); 6619 + 6636 6620 break; 6637 6621 default: 6638 6622 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); ··· 6656 6632 case 42: /* HPD hotplug */ 6657 6633 switch (src_data) { 6658 6634 case 0: 6659 - if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 6660 - rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 6661 - queue_hotplug = true; 6662 - DRM_DEBUG("IH: HPD1\n"); 6663 - } 6635 + if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT)) 6636 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6637 + 6638 + rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 6639 + queue_hotplug = true; 6640 + DRM_DEBUG("IH: HPD1\n"); 6641 + 6664 6642 break; 6665 6643 case 1: 6666 - if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 6667 - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 6668 - queue_hotplug = true; 6669 - DRM_DEBUG("IH: HPD2\n"); 6670 - } 6644 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT)) 6645 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6646 + 6647 + rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 6648 + queue_hotplug = true; 6649 + DRM_DEBUG("IH: HPD2\n"); 6650 + 6671 6651 break; 6672 6652 case 2: 6673 - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 6674 - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 6675 - queue_hotplug = true; 6676 - DRM_DEBUG("IH: HPD3\n"); 6677 - } 6653 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT)) 6654 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6655 + 6656 + rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 6657 + queue_hotplug = true; 6658 + DRM_DEBUG("IH: HPD3\n"); 6659 + 6678 6660 break; 6679 6661 case 3: 6680 - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 6681 - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 6682 - queue_hotplug = true; 6683 - DRM_DEBUG("IH: HPD4\n"); 6684 - } 6662 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT)) 6663 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6664 + 6665 + rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 6666 + queue_hotplug = true; 6667 + DRM_DEBUG("IH: HPD4\n"); 6668 + 6685 6669 break; 6686 6670 case 4: 6687 - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 6688 - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 6689 - queue_hotplug = true; 6690 - DRM_DEBUG("IH: HPD5\n"); 6691 - } 6671 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT)) 6672 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6673 + 6674 + rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 6675 + queue_hotplug = true; 6676 + DRM_DEBUG("IH: HPD5\n"); 6677 + 6692 6678 break; 6693 6679 case 5: 6694 - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 6695 - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 6696 - queue_hotplug = true; 6697 - DRM_DEBUG("IH: HPD6\n"); 6698 - } 6680 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT)) 6681 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6682 + 6683 + rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 6684 + queue_hotplug = true; 6685 + DRM_DEBUG("IH: HPD6\n"); 6686 + 6699 6687 break; 6700 6688 case 6: 6701 - if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) { 6702 - rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; 6703 - queue_dp = true; 6704 - DRM_DEBUG("IH: HPD_RX 1\n"); 6705 - } 6689 + if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT)) 6690 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6691 + 6692 + rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; 6693 + queue_dp = true; 6694 + DRM_DEBUG("IH: HPD_RX 1\n"); 6695 + 6706 6696 break; 6707 6697 case 7: 6708 - if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) { 6709 - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; 6710 - queue_dp = true; 6711 - DRM_DEBUG("IH: HPD_RX 2\n"); 6712 - } 6698 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT)) 6699 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6700 + 6701 + rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; 6702 + queue_dp = true; 6703 + DRM_DEBUG("IH: HPD_RX 2\n"); 6704 + 6713 6705 break; 6714 6706 case 8: 6715 - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { 6716 - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; 6717 - queue_dp = true; 6718 - DRM_DEBUG("IH: HPD_RX 3\n"); 6719 - } 6707 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT)) 6708 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6709 + 6710 + rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; 6711 + queue_dp = true; 6712 + DRM_DEBUG("IH: HPD_RX 3\n"); 6713 + 6720 6714 break; 6721 6715 case 9: 6722 - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { 6723 - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; 6724 - queue_dp = true; 6725 - DRM_DEBUG("IH: HPD_RX 4\n"); 6726 - } 6716 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT)) 6717 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6718 + 6719 + rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; 6720 + queue_dp = true; 6721 + DRM_DEBUG("IH: HPD_RX 4\n"); 6722 + 6727 6723 break; 6728 6724 case 10: 6729 - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { 6730 - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; 6731 - queue_dp = true; 6732 - DRM_DEBUG("IH: HPD_RX 5\n"); 6733 - } 6725 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT)) 6726 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6727 + 6728 + rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; 6729 + queue_dp = true; 6730 + DRM_DEBUG("IH: HPD_RX 5\n"); 6731 + 6734 6732 break; 6735 6733 case 11: 6736 - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { 6737 - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; 6738 - queue_dp = true; 6739 - DRM_DEBUG("IH: HPD_RX 6\n"); 6740 - } 6734 + if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT)) 6735 + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 6736 + 6737 + rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; 6738 + queue_dp = true; 6739 + DRM_DEBUG("IH: HPD_RX 6\n"); 6740 + 6741 6741 break; 6742 6742 default: 6743 6743 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);