+23

drivers/gpu/drm/drm_print.c

reviewed

··· 390 390 } 391 391 } 392 392 EXPORT_SYMBOL(drm_print_regset32); 393 393 + 394 394 + /** 395 395 + * drm_print_hex_dump - print a hex dump to a &drm_printer stream 396 396 + * @p: The &drm_printer 397 397 + * @prefix: Prefix for each line, may be NULL for no prefix 398 398 + * @buf: Buffer to dump 399 399 + * @len: Length of buffer 400 400 + * 401 401 + * Print hex dump to &drm_printer, with 16 space-separated hex bytes per line, 402 402 + * optionally with a prefix on each line. No separator is added after prefix. 403 403 + */ 404 404 + void drm_print_hex_dump(struct drm_printer *p, const char *prefix, 405 405 + const u8 *buf, size_t len) 406 406 + { 407 407 + int i; 408 408 + 409 409 + for (i = 0; i < len; i += 16) { 410 410 + int bytes_per_line = min(16, len - i); 411 411 + 412 412 + drm_printf(p, "%s%*ph\n", prefix ?: "", bytes_per_line, buf + i); 413 413 + } 414 414 + } 415 415 + EXPORT_SYMBOL(drm_print_hex_dump);

+1 -1

drivers/gpu/drm/i915/Makefile

reviewed

··· 30 30 i915_params.o \ 31 31 i915_pci.o \ 32 32 i915_scatterlist.o \ 33 33 - i915_suspend.o \ 34 33 i915_switcheroo.o \ 35 34 i915_sysfs.o \ 36 35 i915_utils.o \ ··· 219 220 i915-y += \ 220 221 display/hsw_ips.o \ 221 222 display/i9xx_plane.o \ 223 223 + display/i9xx_display_sr.o \ 222 224 display/i9xx_wm.o \ 223 225 display/intel_alpm.o \ 224 226 display/intel_atomic.o \

+22 -3

drivers/gpu/drm/i915/display/g4x_dp.c

reviewed

··· 55 55 return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0]; 56 56 } 57 57 58 58 - void g4x_dp_set_clock(struct intel_encoder *encoder, 59 59 - struct intel_crtc_state *pipe_config) 58 58 + static void g4x_dp_set_clock(struct intel_encoder *encoder, 59 59 + struct intel_crtc_state *pipe_config) 60 60 { 61 61 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 62 62 const struct dpll *divisor = NULL; ··· 1223 1223 return intel_de_read(display, DEISR) & bit; 1224 1224 } 1225 1225 1226 1226 + static int g4x_dp_compute_config(struct intel_encoder *encoder, 1227 1227 + struct intel_crtc_state *crtc_state, 1228 1228 + struct drm_connector_state *conn_state) 1229 1229 + { 1230 1230 + struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1231 1231 + int ret; 1232 1232 + 1233 1233 + if (HAS_PCH_SPLIT(i915) && encoder->port != PORT_A) 1234 1234 + crtc_state->has_pch_encoder = true; 1235 1235 + 1236 1236 + ret = intel_dp_compute_config(encoder, crtc_state, conn_state); 1237 1237 + if (ret) 1238 1238 + return ret; 1239 1239 + 1240 1240 + g4x_dp_set_clock(encoder, crtc_state); 1241 1241 + 1242 1242 + return 0; 1243 1243 + } 1244 1244 + 1226 1245 static void g4x_dp_suspend_complete(struct intel_encoder *encoder) 1227 1246 { 1228 1247 /* ··· 1326 1307 intel_encoder_link_check_init(intel_encoder, intel_dp_link_check); 1327 1308 1328 1309 intel_encoder->hotplug = intel_dp_hotplug; 1329 1329 - intel_encoder->compute_config = intel_dp_compute_config; 1310 1310 + intel_encoder->compute_config = g4x_dp_compute_config; 1330 1311 intel_encoder->get_hw_state = intel_dp_get_hw_state; 1331 1312 intel_encoder->get_config = intel_dp_get_config; 1332 1313 intel_encoder->sync_state = intel_dp_sync_state;

-6

drivers/gpu/drm/i915/display/g4x_dp.h

reviewed

··· 19 19 20 20 #ifdef I915 21 21 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915); 22 22 - void g4x_dp_set_clock(struct intel_encoder *encoder, 23 23 - struct intel_crtc_state *pipe_config); 24 22 bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, 25 23 i915_reg_t dp_reg, enum port port, 26 24 enum pipe *pipe); ··· 28 30 static inline const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) 29 31 { 30 32 return NULL; 31 31 - } 32 32 - static inline void g4x_dp_set_clock(struct intel_encoder *encoder, 33 33 - struct intel_crtc_state *pipe_config) 34 34 - { 35 33 } 36 34 static inline bool g4x_dp_port_enabled(struct drm_i915_private *dev_priv, 37 35 i915_reg_t dp_reg, int port,

+18 -2

drivers/gpu/drm/i915/display/hsw_ips.c

reviewed

··· 185 185 /* IPS only exists on ULT machines and is tied to pipe A. */ 186 186 bool hsw_crtc_supports_ips(struct intel_crtc *crtc) 187 187 { 188 188 - return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; 188 188 + struct intel_display *display = to_intel_display(crtc); 189 189 + 190 190 + return HAS_IPS(display) && crtc->pipe == PIPE_A; 189 191 } 190 192 191 191 - bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) 193 193 + static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) 192 194 { 193 195 struct intel_display *display = to_intel_display(crtc_state); 194 196 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); ··· 218 216 return false; 219 217 220 218 return true; 219 219 + } 220 220 + 221 221 + int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state) 222 222 + { 223 223 + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 224 224 + 225 225 + if (!IS_BROADWELL(i915)) 226 226 + return 0; 227 227 + 228 228 + if (!hsw_crtc_state_ips_capable(crtc_state)) 229 229 + return 0; 230 230 + 231 231 + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 232 232 + return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95); 221 233 } 222 234 223 235 int hsw_ips_compute_config(struct intel_atomic_state *state,

+3 -3

drivers/gpu/drm/i915/display/hsw_ips.h

reviewed

··· 19 19 void hsw_ips_post_update(struct intel_atomic_state *state, 20 20 struct intel_crtc *crtc); 21 21 bool hsw_crtc_supports_ips(struct intel_crtc *crtc); 22 22 - bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state); 22 22 + int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state); 23 23 int hsw_ips_compute_config(struct intel_atomic_state *state, 24 24 struct intel_crtc *crtc); 25 25 void hsw_ips_get_config(struct intel_crtc_state *crtc_state); ··· 42 42 { 43 43 return false; 44 44 } 45 45 - static inline bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) 45 45 + static inline int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state) 46 46 { 47 47 - return false; 47 47 + return 0; 48 48 } 49 49 static inline int hsw_ips_compute_config(struct intel_atomic_state *state, 50 50 struct intel_crtc *crtc)

+95

drivers/gpu/drm/i915/display/i9xx_display_sr.c

reviewed

··· 1 1 + // SPDX-License-Identifier: MIT 2 2 + /* 3 3 + * Copyright © 2024 Intel Corporation 4 4 + */ 5 5 + 6 6 + #include "i915_drv.h" 7 7 + #include "i915_reg.h" 8 8 + #include "i9xx_display_sr.h" 9 9 + #include "intel_de.h" 10 10 + #include "intel_gmbus.h" 11 11 + #include "intel_pci_config.h" 12 12 + 13 13 + static void i9xx_display_save_swf(struct intel_display *display) 14 14 + { 15 15 + int i; 16 16 + 17 17 + /* Scratch space */ 18 18 + if (DISPLAY_VER(display) == 2 && display->platform.mobile) { 19 19 + for (i = 0; i < 7; i++) { 20 20 + display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); 21 21 + display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); 22 22 + } 23 23 + for (i = 0; i < 3; i++) 24 24 + display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); 25 25 + } else if (DISPLAY_VER(display) == 2) { 26 26 + for (i = 0; i < 7; i++) 27 27 + display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); 28 28 + } else if (HAS_GMCH(display)) { 29 29 + for (i = 0; i < 16; i++) { 30 30 + display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); 31 31 + display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); 32 32 + } 33 33 + for (i = 0; i < 3; i++) 34 34 + display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); 35 35 + } 36 36 + } 37 37 + 38 38 + static void i9xx_display_restore_swf(struct intel_display *display) 39 39 + { 40 40 + int i; 41 41 + 42 42 + /* Scratch space */ 43 43 + if (DISPLAY_VER(display) == 2 && display->platform.mobile) { 44 44 + for (i = 0; i < 7; i++) { 45 45 + intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]); 46 46 + intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); 47 47 + } 48 48 + for (i = 0; i < 3; i++) 49 49 + intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]); 50 50 + } else if (DISPLAY_VER(display) == 2) { 51 51 + for (i = 0; i < 7; i++) 52 52 + intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); 53 53 + } else if (HAS_GMCH(display)) { 54 54 + for (i = 0; i < 16; i++) { 55 55 + intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]); 56 56 + intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); 57 57 + } 58 58 + for (i = 0; i < 3; i++) 59 59 + intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]); 60 60 + } 61 61 + } 62 62 + 63 63 + void i9xx_display_sr_save(struct intel_display *display) 64 64 + { 65 65 + struct pci_dev *pdev = to_pci_dev(display->drm->dev); 66 66 + 67 67 + if (!HAS_DISPLAY(display)) 68 68 + return; 69 69 + 70 70 + /* Display arbitration control */ 71 71 + if (DISPLAY_VER(display) <= 4) 72 72 + display->restore.saveDSPARB = intel_de_read(display, DSPARB(display)); 73 73 + 74 74 + if (DISPLAY_VER(display) == 4) 75 75 + pci_read_config_word(pdev, GCDGMBUS, &display->restore.saveGCDGMBUS); 76 76 + 77 77 + i9xx_display_save_swf(display); 78 78 + } 79 79 + 80 80 + void i9xx_display_sr_restore(struct intel_display *display) 81 81 + { 82 82 + struct pci_dev *pdev = to_pci_dev(display->drm->dev); 83 83 + 84 84 + if (!HAS_DISPLAY(display)) 85 85 + return; 86 86 + 87 87 + i9xx_display_restore_swf(display); 88 88 + 89 89 + if (DISPLAY_VER(display) == 4) 90 90 + pci_write_config_word(pdev, GCDGMBUS, display->restore.saveGCDGMBUS); 91 91 + 92 92 + /* Display arbitration */ 93 93 + if (DISPLAY_VER(display) <= 4) 94 94 + intel_de_write(display, DSPARB(display), display->restore.saveDSPARB); 95 95 + }

+14

drivers/gpu/drm/i915/display/i9xx_display_sr.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* 3 3 + * Copyright © 2024 Intel Corporation 4 4 + */ 5 5 + 6 6 + #ifndef __I9XX_DISPLAY_SR_H__ 7 7 + #define __I9XX_DISPLAY_SR_H__ 8 8 + 9 9 + struct intel_display; 10 10 + 11 11 + void i9xx_display_sr_save(struct intel_display *display); 12 12 + void i9xx_display_sr_restore(struct intel_display *display); 13 13 + 14 14 + #endif

+3 -1

drivers/gpu/drm/i915/display/icl_dsi.c

reviewed

··· 1602 1602 1603 1603 /* FIXME: split only when necessary */ 1604 1604 if (crtc_state->dsc.slice_count > 1) 1605 1605 - crtc_state->dsc.dsc_split = true; 1605 1605 + crtc_state->dsc.num_streams = 2; 1606 1606 + else 1607 1607 + crtc_state->dsc.num_streams = 1; 1606 1608 1607 1609 /* FIXME: initialize from VBT */ 1608 1610 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;

+50 -4

drivers/gpu/drm/i915/display/intel_audio.c

reviewed

··· 681 681 682 682 void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state) 683 683 { 684 684 - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 685 685 - struct drm_i915_private *i915 = to_i915(crtc->base.dev); 684 684 + struct intel_display *display = to_intel_display(crtc_state); 686 685 enum transcoder trans = crtc_state->cpu_transcoder; 687 686 688 688 - if (HAS_DP20(i915)) 689 689 - intel_de_rmw(i915, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, 687 687 + if (HAS_DP20(display)) 688 688 + intel_de_rmw(display, AUD_DP_2DOT0_CTRL(trans), AUD_ENABLE_SDP_SPLIT, 690 689 crtc_state->sdp_split_enable ? AUD_ENABLE_SDP_SPLIT : 0); 691 690 } 692 691 ··· 978 979 979 980 drm_modeset_drop_locks(&ctx); 980 981 drm_modeset_acquire_fini(&ctx); 982 982 + } 983 983 + 984 984 + int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state) 985 985 + { 986 986 + struct intel_display *display = to_intel_display(crtc_state); 987 987 + struct drm_i915_private *dev_priv = to_i915(display->drm); 988 988 + int min_cdclk = 0; 989 989 + 990 990 + if (!crtc_state->has_audio) 991 991 + return 0; 992 992 + 993 993 + /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 994 994 + * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 995 995 + * there may be audio corruption or screen corruption." This cdclk 996 996 + * restriction for GLK is 316.8 MHz. 997 997 + */ 998 998 + if (intel_crtc_has_dp_encoder(crtc_state) && 999 999 + crtc_state->port_clock >= 540000 && 1000 1000 + crtc_state->lane_count == 4) { 1001 1001 + if (DISPLAY_VER(display) == 10) { 1002 1002 + /* Display WA #1145: glk */ 1003 1003 + min_cdclk = max(min_cdclk, 316800); 1004 1004 + } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) { 1005 1005 + /* Display WA #1144: skl,bxt */ 1006 1006 + min_cdclk = max(min_cdclk, 432000); 1007 1007 + } 1008 1008 + } 1009 1009 + 1010 1010 + /* 1011 1011 + * According to BSpec, "The CD clock frequency must be at least twice 1012 1012 + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 1013 1013 + */ 1014 1014 + if (DISPLAY_VER(display) >= 9) 1015 1015 + min_cdclk = max(min_cdclk, 2 * 96000); 1016 1016 + 1017 1017 + /* 1018 1018 + * "For DP audio configuration, cdclk frequency shall be set to 1019 1019 + * meet the following requirements: 1020 1020 + * DP Link Frequency(MHz) | Cdclk frequency(MHz) 1021 1021 + * 270 | 320 or higher 1022 1022 + * 162 | 200 or higher" 1023 1023 + */ 1024 1024 + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1025 1025 + intel_crtc_has_dp_encoder(crtc_state)) 1026 1026 + min_cdclk = max(min_cdclk, crtc_state->port_clock); 1027 1027 + 1028 1028 + return min_cdclk; 981 1029 } 982 1030 983 1031 static unsigned long i915_audio_component_get_power(struct device *kdev)

+1

drivers/gpu/drm/i915/display/intel_audio.h

reviewed

··· 27 27 struct intel_crtc_state *crtc_state); 28 28 void intel_audio_cdclk_change_pre(struct drm_i915_private *dev_priv); 29 29 void intel_audio_cdclk_change_post(struct drm_i915_private *dev_priv); 30 30 + int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state); 30 31 void intel_audio_init(struct drm_i915_private *dev_priv); 31 32 void intel_audio_register(struct drm_i915_private *i915); 32 33 void intel_audio_deinit(struct drm_i915_private *dev_priv);

+12 -3

drivers/gpu/drm/i915/display/intel_bios.c

reviewed

··· 1402 1402 panel_type); 1403 1403 } 1404 1404 1405 1405 + static void vbt_edp_to_pps_delays(struct intel_pps_delays *pps, 1406 1406 + const struct edp_power_seq *edp_pps) 1407 1407 + { 1408 1408 + pps->power_up = edp_pps->t1_t3; 1409 1409 + pps->backlight_on = edp_pps->t8; 1410 1410 + pps->backlight_off = edp_pps->t9; 1411 1411 + pps->power_down = edp_pps->t10; 1412 1412 + pps->power_cycle = edp_pps->t11_t12; 1413 1413 + } 1414 1414 + 1405 1415 static void 1406 1416 parse_edp(struct intel_display *display, 1407 1417 struct intel_panel *panel) 1408 1418 { 1409 1419 const struct bdb_edp *edp; 1410 1410 - const struct edp_power_seq *edp_pps; 1411 1420 const struct edp_fast_link_params *edp_link_params; 1412 1421 int panel_type = panel->vbt.panel_type; 1413 1422 ··· 1437 1428 } 1438 1429 1439 1430 /* Get the eDP sequencing and link info */ 1440 1440 - edp_pps = &edp->power_seqs[panel_type]; 1441 1431 edp_link_params = &edp->fast_link_params[panel_type]; 1442 1432 1443 1443 - panel->vbt.edp.pps = *edp_pps; 1433 1433 + vbt_edp_to_pps_delays(&panel->vbt.edp.pps, 1434 1434 + &edp->power_seqs[panel_type]); 1444 1435 1445 1436 if (display->vbt.version >= 224) { 1446 1437 panel->vbt.edp.rate =

-8

drivers/gpu/drm/i915/display/intel_bios.h

reviewed

··· 50 50 INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE, 51 51 }; 52 52 53 53 - struct edp_power_seq { 54 54 - u16 t1_t3; 55 55 - u16 t8; 56 56 - u16 t9; 57 57 - u16 t10; 58 58 - u16 t11_t12; 59 59 - } __packed; 60 60 - 61 53 /* 62 54 * MIPI Sequence Block definitions 63 55 *

+1 -1

drivers/gpu/drm/i915/display/intel_bw.c

reviewed

··· 1256 1256 min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state); 1257 1257 1258 1258 for_each_pipe(i915, pipe) 1259 1259 - min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk); 1259 1259 + min_cdclk = max(min_cdclk, bw_state->min_cdclk[pipe]); 1260 1260 1261 1261 return min_cdclk; 1262 1262 }

+37 -138

drivers/gpu/drm/i915/display/intel_cdclk.c

reviewed

··· 37 37 #include "intel_cdclk.h" 38 38 #include "intel_crtc.h" 39 39 #include "intel_de.h" 40 40 - #include "intel_dp.h" 41 40 #include "intel_display_types.h" 42 41 #include "intel_mchbar_regs.h" 43 42 #include "intel_pci_config.h" ··· 45 46 #include "intel_vdsc.h" 46 47 #include "skl_watermark.h" 47 48 #include "skl_watermark_regs.h" 49 49 + #include "vlv_dsi.h" 48 50 #include "vlv_sideband.h" 49 51 50 52 /** ··· 2761 2761 "Post changing CDCLK to"); 2762 2762 } 2763 2763 2764 2764 + /* pixels per CDCLK */ 2765 2765 + static int intel_cdclk_ppc(struct intel_display *display, bool double_wide) 2766 2766 + { 2767 2767 + return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1; 2768 2768 + } 2769 2769 + 2770 2770 + /* max pixel rate as % of CDCLK (not accounting for PPC) */ 2771 2771 + static int intel_cdclk_guardband(struct intel_display *display) 2772 2772 + { 2773 2773 + struct drm_i915_private *dev_priv = to_i915(display->drm); 2774 2774 + 2775 2775 + if (DISPLAY_VER(display) >= 9 || 2776 2776 + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2777 2777 + return 100; 2778 2778 + else if (IS_CHERRYVIEW(dev_priv)) 2779 2779 + return 95; 2780 2780 + else 2781 2781 + return 90; 2782 2782 + } 2783 2783 + 2764 2784 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) 2765 2785 { 2766 2786 struct intel_display *display = to_intel_display(crtc_state); 2767 2767 - struct drm_i915_private *dev_priv = to_i915(display->drm); 2787 2787 + int ppc = intel_cdclk_ppc(display, crtc_state->double_wide); 2788 2788 + int guardband = intel_cdclk_guardband(display); 2768 2789 int pixel_rate = crtc_state->pixel_rate; 2769 2790 2770 2770 - if (DISPLAY_VER(display) >= 10) 2771 2771 - return DIV_ROUND_UP(pixel_rate, 2); 2772 2772 - else if (DISPLAY_VER(display) == 9 || 2773 2773 - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 2774 2774 - return pixel_rate; 2775 2775 - else if (IS_CHERRYVIEW(dev_priv)) 2776 2776 - return DIV_ROUND_UP(pixel_rate * 100, 95); 2777 2777 - else if (crtc_state->double_wide) 2778 2778 - return DIV_ROUND_UP(pixel_rate * 100, 90 * 2); 2779 2779 - else 2780 2780 - return DIV_ROUND_UP(pixel_rate * 100, 90); 2791 2791 + return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc); 2781 2792 } 2782 2793 2783 2794 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) ··· 2799 2788 int min_cdclk = 0; 2800 2789 2801 2790 for_each_intel_plane_on_crtc(display->drm, crtc, plane) 2802 2802 - min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); 2803 2803 - 2804 2804 - return min_cdclk; 2805 2805 - } 2806 2806 - 2807 2807 - static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) 2808 2808 - { 2809 2809 - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2810 2810 - struct intel_display *display = to_intel_display(crtc); 2811 2811 - int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); 2812 2812 - int min_cdclk = 0; 2813 2813 - 2814 2814 - /* 2815 2815 - * When we decide to use only one VDSC engine, since 2816 2816 - * each VDSC operates with 1 ppc throughput, pixel clock 2817 2817 - * cannot be higher than the VDSC clock (cdclk) 2818 2818 - * If there 2 VDSC engines, then pixel clock can't be higher than 2819 2819 - * VDSC clock(cdclk) * 2 and so on. 2820 2820 - */ 2821 2821 - min_cdclk = max_t(int, min_cdclk, 2822 2822 - DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances)); 2823 2823 - 2824 2824 - if (crtc_state->joiner_pipes) { 2825 2825 - int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); 2826 2826 - 2827 2827 - /* 2828 2828 - * According to Bigjoiner bw check: 2829 2829 - * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock 2830 2830 - * 2831 2831 - * We have already computed compressed_bpp, so now compute the min CDCLK that 2832 2832 - * is required to support this compressed_bpp. 2833 2833 - * 2834 2834 - * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits) 2835 2835 - * 2836 2836 - * Since PPC = 2 with bigjoiner 2837 2837 - * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits 2838 2838 - */ 2839 2839 - int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24; 2840 2840 - int min_cdclk_bj = 2841 2841 - (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * 2842 2842 - pixel_clock) / (2 * bigjoiner_interface_bits); 2843 2843 - 2844 2844 - min_cdclk = max(min_cdclk, min_cdclk_bj); 2845 2845 - } 2791 2791 + min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]); 2846 2792 2847 2793 return min_cdclk; 2848 2794 } 2849 2795 2850 2796 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 2851 2797 { 2852 2852 - struct intel_display *display = to_intel_display(crtc_state); 2853 2853 - struct drm_i915_private *dev_priv = to_i915(display->drm); 2854 2798 int min_cdclk; 2855 2799 2856 2800 if (!crtc_state->hw.enable) 2857 2801 return 0; 2858 2802 2859 2803 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state); 2860 2860 - 2861 2861 - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ 2862 2862 - if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) 2863 2863 - min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95); 2864 2864 - 2865 2865 - /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz, 2866 2866 - * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else 2867 2867 - * there may be audio corruption or screen corruption." This cdclk 2868 2868 - * restriction for GLK is 316.8 MHz. 2869 2869 - */ 2870 2870 - if (intel_crtc_has_dp_encoder(crtc_state) && 2871 2871 - crtc_state->has_audio && 2872 2872 - crtc_state->port_clock >= 540000 && 2873 2873 - crtc_state->lane_count == 4) { 2874 2874 - if (DISPLAY_VER(display) == 10) { 2875 2875 - /* Display WA #1145: glk */ 2876 2876 - min_cdclk = max(316800, min_cdclk); 2877 2877 - } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) { 2878 2878 - /* Display WA #1144: skl,bxt */ 2879 2879 - min_cdclk = max(432000, min_cdclk); 2880 2880 - } 2881 2881 - } 2882 2882 - 2883 2883 - /* 2884 2884 - * According to BSpec, "The CD clock frequency must be at least twice 2885 2885 - * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. 2886 2886 - */ 2887 2887 - if (crtc_state->has_audio && DISPLAY_VER(display) >= 9) 2888 2888 - min_cdclk = max(2 * 96000, min_cdclk); 2889 2889 - 2890 2890 - /* 2891 2891 - * "For DP audio configuration, cdclk frequency shall be set to 2892 2892 - * meet the following requirements: 2893 2893 - * DP Link Frequency(MHz) | Cdclk frequency(MHz) 2894 2894 - * 270 | 320 or higher 2895 2895 - * 162 | 200 or higher" 2896 2896 - */ 2897 2897 - if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2898 2898 - intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) 2899 2899 - min_cdclk = max(crtc_state->port_clock, min_cdclk); 2900 2900 - 2901 2901 - /* 2902 2902 - * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 2903 2903 - * than 320000KHz. 2904 2904 - */ 2905 2905 - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2906 2906 - IS_VALLEYVIEW(dev_priv)) 2907 2907 - min_cdclk = max(320000, min_cdclk); 2908 2908 - 2909 2909 - /* 2910 2910 - * On Geminilake once the CDCLK gets as low as 79200 2911 2911 - * picture gets unstable, despite that values are 2912 2912 - * correct for DSI PLL and DE PLL. 2913 2913 - */ 2914 2914 - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) && 2915 2915 - IS_GEMINILAKE(dev_priv)) 2916 2916 - min_cdclk = max(158400, min_cdclk); 2917 2917 - 2918 2918 - /* Account for additional needs from the planes */ 2919 2919 - min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk); 2920 2920 - 2921 2921 - if (crtc_state->dsc.compression_enable) 2922 2922 - min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2804 2804 + min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state)); 2805 2805 + min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state)); 2806 2806 + min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state)); 2807 2807 + min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state)); 2808 2808 + min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state)); 2923 2809 2924 2810 return min_cdclk; 2925 2811 } ··· 2868 2960 min_cdclk = max(cdclk_state->force_min_cdclk, 2869 2961 cdclk_state->bw_min_cdclk); 2870 2962 for_each_pipe(display, pipe) 2871 2871 - min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); 2963 2963 + min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]); 2872 2964 2873 2965 /* 2874 2966 * Avoid glk_force_audio_cdclk() causing excessive screen ··· 2880 2972 */ 2881 2973 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && 2882 2974 !is_power_of_2(cdclk_state->active_pipes)) 2883 2883 - min_cdclk = max(2 * 96000, min_cdclk); 2975 2975 + min_cdclk = max(min_cdclk, 2 * 96000); 2884 2976 2885 2977 if (min_cdclk > display->cdclk.max_cdclk_freq) { 2886 2978 drm_dbg_kms(display->drm, ··· 2936 3028 2937 3029 min_voltage_level = 0; 2938 3030 for_each_pipe(display, pipe) 2939 2939 - min_voltage_level = max(cdclk_state->min_voltage_level[pipe], 2940 2940 - min_voltage_level); 3031 3031 + min_voltage_level = max(min_voltage_level, 3032 3032 + cdclk_state->min_voltage_level[pipe]); 2941 3033 2942 3034 return min_voltage_level; 2943 3035 } ··· 3360 3452 3361 3453 static int intel_compute_max_dotclk(struct intel_display *display) 3362 3454 { 3363 3363 - struct drm_i915_private *dev_priv = to_i915(display->drm); 3455 3455 + int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display)); 3456 3456 + int guardband = intel_cdclk_guardband(display); 3364 3457 int max_cdclk_freq = display->cdclk.max_cdclk_freq; 3365 3458 3366 3366 - if (DISPLAY_VER(display) >= 10) 3367 3367 - return 2 * max_cdclk_freq; 3368 3368 - else if (DISPLAY_VER(display) == 9 || 3369 3369 - IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3370 3370 - return max_cdclk_freq; 3371 3371 - else if (IS_CHERRYVIEW(dev_priv)) 3372 3372 - return max_cdclk_freq*95/100; 3373 3373 - else if (DISPLAY_VER(display) < 4) 3374 3374 - return 2*max_cdclk_freq*90/100; 3375 3375 - else 3376 3376 - return max_cdclk_freq*90/100; 3459 3459 + return ppc * max_cdclk_freq * guardband / 100; 3377 3460 } 3378 3461 3379 3462 /**

+80 -83

drivers/gpu/drm/i915/display/intel_crt.c

reviewed

··· 38 38 #include "i915_reg.h" 39 39 #include "intel_connector.h" 40 40 #include "intel_crt.h" 41 41 + #include "intel_crt_regs.h" 41 42 #include "intel_crtc.h" 42 43 #include "intel_ddi.h" 43 44 #include "intel_ddi_buf_trans.h" ··· 56 55 #include "intel_pch_refclk.h" 57 56 58 57 /* Here's the desired hotplug mode */ 59 59 - #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 58 58 + #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_ENABLE | \ 59 59 + ADPA_CRT_HOTPLUG_PERIOD_128 | \ 60 60 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 61 61 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 62 62 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 63 63 - ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 64 64 - ADPA_CRT_HOTPLUG_ENABLE) 63 63 + ADPA_CRT_HOTPLUG_VOLREF_325MV) 64 64 + #define ADPA_HOTPLUG_MASK (ADPA_CRT_HOTPLUG_MONITOR_MASK | \ 65 65 + ADPA_CRT_HOTPLUG_ENABLE | \ 66 66 + ADPA_CRT_HOTPLUG_PERIOD_MASK | \ 67 67 + ADPA_CRT_HOTPLUG_WARMUP_MASK | \ 68 68 + ADPA_CRT_HOTPLUG_SAMPLE_MASK | \ 69 69 + ADPA_CRT_HOTPLUG_VOLTAGE_MASK | \ 70 70 + ADPA_CRT_HOTPLUG_VOLREF_MASK | \ 71 71 + ADPA_CRT_HOTPLUG_FORCE_TRIGGER) 65 72 66 73 struct intel_crt { 67 74 struct intel_encoder base; 68 68 - /* DPMS state is stored in the connector, which we need in the 69 69 - * encoder's enable/disable callbacks */ 70 70 - struct intel_connector *connector; 71 75 bool force_hotplug_required; 72 76 i915_reg_t adpa_reg; 73 77 }; ··· 97 91 98 92 /* asserts want to know the pipe even if the port is disabled */ 99 93 if (HAS_PCH_CPT(dev_priv)) 100 100 - *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT; 94 94 + *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val); 101 95 else 102 102 - *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT; 96 96 + *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val); 103 97 104 98 return val & ADPA_DAC_ENABLE; 105 99 } ··· 147 141 } 148 142 149 143 static void intel_crt_get_config(struct intel_encoder *encoder, 150 150 - struct intel_crtc_state *pipe_config) 144 144 + struct intel_crtc_state *crtc_state) 151 145 { 152 152 - pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 146 146 + crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 153 147 154 154 - pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 148 148 + crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 155 149 156 156 - pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 150 150 + crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; 157 151 } 158 152 159 153 static void hsw_crt_get_config(struct intel_encoder *encoder, 160 160 - struct intel_crtc_state *pipe_config) 154 154 + struct intel_crtc_state *crtc_state) 161 155 { 162 162 - lpt_pch_get_config(pipe_config); 156 156 + lpt_pch_get_config(crtc_state); 163 157 164 164 - hsw_ddi_get_config(encoder, pipe_config); 158 158 + hsw_ddi_get_config(encoder, crtc_state); 165 159 166 166 - pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 167 167 - DRM_MODE_FLAG_NHSYNC | 168 168 - DRM_MODE_FLAG_PVSYNC | 169 169 - DRM_MODE_FLAG_NVSYNC); 170 170 - pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 160 160 + crtc_state->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 161 161 + DRM_MODE_FLAG_NHSYNC | 162 162 + DRM_MODE_FLAG_PVSYNC | 163 163 + DRM_MODE_FLAG_NVSYNC); 164 164 + crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 171 165 } 172 166 173 167 /* Note: The caller is required to filter out dpms modes not supported by the ··· 250 244 const struct intel_crtc_state *old_crtc_state, 251 245 const struct drm_connector_state *old_conn_state) 252 246 { 253 253 - struct intel_display *display = to_intel_display(state); 247 247 + struct intel_display *display = to_intel_display(encoder); 254 248 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 255 249 256 250 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder); ··· 263 257 const struct intel_crtc_state *old_crtc_state, 264 258 const struct drm_connector_state *old_conn_state) 265 259 { 266 266 - struct intel_display *display = to_intel_display(state); 260 260 + struct intel_display *display = to_intel_display(encoder); 267 261 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 268 262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 269 263 ··· 293 287 const struct intel_crtc_state *crtc_state, 294 288 const struct drm_connector_state *conn_state) 295 289 { 296 296 - struct intel_display *display = to_intel_display(state); 290 290 + struct intel_display *display = to_intel_display(encoder); 297 291 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 298 292 299 293 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder); ··· 306 300 const struct intel_crtc_state *crtc_state, 307 301 const struct drm_connector_state *conn_state) 308 302 { 309 309 - struct intel_display *display = to_intel_display(state); 303 303 + struct intel_display *display = to_intel_display(encoder); 310 304 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 311 305 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 312 306 enum pipe pipe = crtc->pipe; ··· 325 319 const struct intel_crtc_state *crtc_state, 326 320 const struct drm_connector_state *conn_state) 327 321 { 328 328 - struct intel_display *display = to_intel_display(state); 322 322 + struct intel_display *display = to_intel_display(encoder); 329 323 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 330 324 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 331 325 enum pipe pipe = crtc->pipe; ··· 361 355 struct drm_display_mode *mode) 362 356 { 363 357 struct intel_display *display = to_intel_display(connector->dev); 364 364 - struct drm_device *dev = connector->dev; 365 365 - struct drm_i915_private *dev_priv = to_i915(dev); 358 358 + struct drm_i915_private *dev_priv = to_i915(connector->dev); 366 359 int max_dotclk = display->cdclk.max_dotclk_freq; 367 360 enum drm_mode_status status; 368 361 int max_clock; ··· 404 399 } 405 400 406 401 static int intel_crt_compute_config(struct intel_encoder *encoder, 407 407 - struct intel_crtc_state *pipe_config, 402 402 + struct intel_crtc_state *crtc_state, 408 403 struct drm_connector_state *conn_state) 409 404 { 410 405 struct drm_display_mode *adjusted_mode = 411 411 - &pipe_config->hw.adjusted_mode; 406 406 + &crtc_state->hw.adjusted_mode; 412 407 413 408 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 414 409 return -EINVAL; 415 410 416 416 - pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 417 417 - pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 411 411 + crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 412 412 + crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 418 413 419 414 return 0; 420 415 } 421 416 422 417 static int pch_crt_compute_config(struct intel_encoder *encoder, 423 423 - struct intel_crtc_state *pipe_config, 418 418 + struct intel_crtc_state *crtc_state, 424 419 struct drm_connector_state *conn_state) 425 420 { 426 421 struct drm_display_mode *adjusted_mode = 427 427 - &pipe_config->hw.adjusted_mode; 422 422 + &crtc_state->hw.adjusted_mode; 428 423 429 424 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 430 425 return -EINVAL; 431 426 432 432 - pipe_config->has_pch_encoder = true; 433 433 - if (!intel_fdi_compute_pipe_bpp(pipe_config)) 427 427 + crtc_state->has_pch_encoder = true; 428 428 + if (!intel_fdi_compute_pipe_bpp(crtc_state)) 434 429 return -EINVAL; 435 430 436 436 - pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 431 431 + crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 437 432 438 433 return 0; 439 434 } 440 435 441 436 static int hsw_crt_compute_config(struct intel_encoder *encoder, 442 442 - struct intel_crtc_state *pipe_config, 437 437 + struct intel_crtc_state *crtc_state, 443 438 struct drm_connector_state *conn_state) 444 439 { 445 440 struct intel_display *display = to_intel_display(encoder); 446 441 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 447 442 struct drm_display_mode *adjusted_mode = 448 448 - &pipe_config->hw.adjusted_mode; 443 443 + &crtc_state->hw.adjusted_mode; 449 444 450 445 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 451 446 return -EINVAL; ··· 455 450 adjusted_mode->crtc_hblank_start > 4096) 456 451 return -EINVAL; 457 452 458 458 - pipe_config->has_pch_encoder = true; 459 459 - if (!intel_fdi_compute_pipe_bpp(pipe_config)) 453 453 + crtc_state->has_pch_encoder = true; 454 454 + if (!intel_fdi_compute_pipe_bpp(crtc_state)) 460 455 return -EINVAL; 461 456 462 462 - pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 457 457 + crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 463 458 464 459 /* LPT FDI RX only supports 8bpc. */ 465 460 if (HAS_PCH_LPT(dev_priv)) { 466 461 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ 467 467 - if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 462 462 + if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) { 468 463 drm_dbg_kms(display->drm, 469 464 "LPT only supports 24bpp\n"); 470 465 return -EINVAL; 471 466 } 472 467 473 473 - pipe_config->pipe_bpp = 24; 468 468 + crtc_state->pipe_bpp = 24; 474 469 } 475 470 476 471 /* FDI must always be 2.7 GHz */ 477 477 - pipe_config->port_clock = 135000 * 2; 472 472 + crtc_state->port_clock = 135000 * 2; 478 473 479 479 - pipe_config->enhanced_framing = true; 474 474 + crtc_state->enhanced_framing = true; 480 475 481 481 - adjusted_mode->crtc_clock = lpt_iclkip(pipe_config); 476 476 + adjusted_mode->crtc_clock = lpt_iclkip(crtc_state); 482 477 483 478 return 0; 484 479 } ··· 486 481 static bool ilk_crt_detect_hotplug(struct drm_connector *connector) 487 482 { 488 483 struct intel_display *display = to_intel_display(connector->dev); 489 489 - struct drm_device *dev = connector->dev; 490 484 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 491 491 - struct drm_i915_private *dev_priv = to_i915(dev); 485 485 + struct drm_i915_private *dev_priv = to_i915(connector->dev); 492 486 u32 adpa; 493 487 bool ret; 494 488 ··· 536 532 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 537 533 { 538 534 struct intel_display *display = to_intel_display(connector->dev); 539 539 - struct drm_device *dev = connector->dev; 540 535 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 541 541 - struct drm_i915_private *dev_priv = to_i915(dev); 536 536 + struct drm_i915_private *dev_priv = to_i915(connector->dev); 542 537 bool reenable_hpd; 543 538 u32 adpa; 544 539 bool ret; ··· 591 588 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 592 589 { 593 590 struct intel_display *display = to_intel_display(connector->dev); 594 594 - struct drm_device *dev = connector->dev; 595 595 - struct drm_i915_private *dev_priv = to_i915(dev); 591 591 + struct drm_i915_private *dev_priv = to_i915(connector->dev); 596 592 u32 stat; 597 593 bool ret = false; 598 594 int i, tries = 0; ··· 858 856 struct intel_display *display = to_intel_display(connector->dev); 859 857 struct drm_i915_private *dev_priv = to_i915(connector->dev); 860 858 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 861 861 - struct intel_encoder *intel_encoder = &crt->base; 859 859 + struct intel_encoder *encoder = &crt->base; 862 860 struct drm_atomic_state *state; 863 861 intel_wakeref_t wakeref; 864 862 int status; ··· 867 865 connector->base.id, connector->name, 868 866 force); 869 867 870 870 - if (!intel_display_device_enabled(dev_priv)) 868 868 + if (!intel_display_device_enabled(display)) 871 869 return connector_status_disconnected; 872 870 873 873 - if (!intel_display_driver_check_access(dev_priv)) 871 871 + if (!intel_display_driver_check_access(display)) 874 872 return connector->status; 875 873 876 874 if (display->params.load_detect_test) { 877 877 - wakeref = intel_display_power_get(dev_priv, 878 878 - intel_encoder->power_domain); 875 875 + wakeref = intel_display_power_get(dev_priv, encoder->power_domain); 879 876 goto load_detect; 880 877 } 881 878 ··· 882 881 if (dmi_check_system(intel_spurious_crt_detect)) 883 882 return connector_status_disconnected; 884 883 885 885 - wakeref = intel_display_power_get(dev_priv, 886 886 - intel_encoder->power_domain); 884 884 + wakeref = intel_display_power_get(dev_priv, encoder->power_domain); 887 885 888 886 if (I915_HAS_HOTPLUG(display)) { 889 887 /* We can not rely on the HPD pin always being correctly wired ··· 939 939 } 940 940 941 941 out: 942 942 - intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 942 942 + intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 943 943 944 944 return status; 945 945 } ··· 947 947 static int intel_crt_get_modes(struct drm_connector *connector) 948 948 { 949 949 struct intel_display *display = to_intel_display(connector->dev); 950 950 - struct drm_device *dev = connector->dev; 951 951 - struct drm_i915_private *dev_priv = to_i915(dev); 950 950 + struct drm_i915_private *dev_priv = to_i915(connector->dev); 952 951 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 953 953 - struct intel_encoder *intel_encoder = &crt->base; 952 952 + struct intel_encoder *encoder = &crt->base; 954 953 intel_wakeref_t wakeref; 955 954 struct i2c_adapter *ddc; 956 955 int ret; 957 956 958 958 - if (!intel_display_driver_check_access(dev_priv)) 957 957 + if (!intel_display_driver_check_access(display)) 959 958 return drm_edid_connector_add_modes(connector); 960 959 961 961 - wakeref = intel_display_power_get(dev_priv, 962 962 - intel_encoder->power_domain); 960 960 + wakeref = intel_display_power_get(dev_priv, encoder->power_domain); 963 961 964 962 ret = intel_crt_ddc_get_modes(connector, connector->ddc); 965 963 if (ret || !IS_G4X(dev_priv)) ··· 968 970 ret = intel_crt_ddc_get_modes(connector, ddc); 969 971 970 972 out: 971 971 - intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 973 973 + intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 972 974 973 975 return ret; 974 976 } ··· 982 984 u32 adpa; 983 985 984 986 adpa = intel_de_read(display, crt->adpa_reg); 985 985 - adpa &= ~ADPA_CRT_HOTPLUG_MASK; 987 987 + adpa &= ~ADPA_HOTPLUG_MASK; 986 988 adpa |= ADPA_HOTPLUG_BITS; 987 989 intel_de_write(display, crt->adpa_reg, adpa); 988 990 intel_de_posting_read(display, crt->adpa_reg); ··· 1020 1022 void intel_crt_init(struct intel_display *display) 1021 1023 { 1022 1024 struct drm_i915_private *dev_priv = to_i915(display->drm); 1023 1023 - struct drm_connector *connector; 1025 1025 + struct intel_connector *connector; 1024 1026 struct intel_crt *crt; 1025 1025 - struct intel_connector *intel_connector; 1026 1027 i915_reg_t adpa_reg; 1027 1028 u8 ddc_pin; 1028 1029 u32 adpa; ··· 1044 1047 * it and see what happens. 1045 1048 */ 1046 1049 intel_de_write(display, adpa_reg, 1047 1047 - adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 1050 1050 + adpa | ADPA_DAC_ENABLE | 1051 1051 + ADPA_HSYNC_CNTL_DISABLE | 1052 1052 + ADPA_VSYNC_CNTL_DISABLE); 1048 1053 if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0) 1049 1054 return; 1050 1055 intel_de_write(display, adpa_reg, adpa); ··· 1056 1057 if (!crt) 1057 1058 return; 1058 1059 1059 1059 - intel_connector = intel_connector_alloc(); 1060 1060 - if (!intel_connector) { 1060 1060 + connector = intel_connector_alloc(); 1061 1061 + if (!connector) { 1061 1062 kfree(crt); 1062 1063 return; 1063 1064 } 1064 1065 1065 1066 ddc_pin = display->vbt.crt_ddc_pin; 1066 1067 1067 1067 - connector = &intel_connector->base; 1068 1068 - crt->connector = intel_connector; 1069 1069 - drm_connector_init_with_ddc(display->drm, connector, 1068 1068 + drm_connector_init_with_ddc(display->drm, &connector->base, 1070 1069 &intel_crt_connector_funcs, 1071 1070 DRM_MODE_CONNECTOR_VGA, 1072 1071 intel_gmbus_get_adapter(display, ddc_pin)); ··· 1072 1075 drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs, 1073 1076 DRM_MODE_ENCODER_DAC, "CRT"); 1074 1077 1075 1075 - intel_connector_attach_encoder(intel_connector, &crt->base); 1078 1078 + intel_connector_attach_encoder(connector, &crt->base); 1076 1079 1077 1080 crt->base.type = INTEL_OUTPUT_ANALOG; 1078 1081 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI); ··· 1082 1085 crt->base.pipe_mask = ~0; 1083 1086 1084 1087 if (DISPLAY_VER(display) != 2) 1085 1085 - connector->interlace_allowed = true; 1088 1088 + connector->base.interlace_allowed = true; 1086 1089 1087 1090 crt->adpa_reg = adpa_reg; 1088 1091 ··· 1092 1095 !dmi_check_system(intel_spurious_crt_detect)) { 1093 1096 crt->base.hpd_pin = HPD_CRT; 1094 1097 crt->base.hotplug = intel_encoder_hotplug; 1095 1095 - intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 1098 1098 + connector->polled = DRM_CONNECTOR_POLL_HPD; 1096 1099 } else { 1097 1097 - intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1100 1100 + connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1098 1101 } 1099 1099 - intel_connector->base.polled = intel_connector->polled; 1102 1102 + connector->base.polled = connector->polled; 1100 1103 1101 1104 if (HAS_DDI(display)) { 1102 1105 assert_port_valid(dev_priv, PORT_E); ··· 1129 1132 crt->base.get_hw_state = intel_crt_get_hw_state; 1130 1133 crt->base.enable = intel_enable_crt; 1131 1134 } 1132 1132 - intel_connector->get_hw_state = intel_connector_get_hw_state; 1135 1135 + connector->get_hw_state = intel_connector_get_hw_state; 1133 1136 1134 1134 - drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 1137 1137 + drm_connector_helper_add(&connector->base, &intel_crt_connector_helper_funcs); 1135 1138 1136 1139 /* 1137 1140 * TODO: find a proper way to discover whether we need to set the the

+48

drivers/gpu/drm/i915/display/intel_crt_regs.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: MIT */ 2 2 + /* 3 3 + * Copyright © 2024 Intel Corporation 4 4 + */ 5 5 + 6 6 + #ifndef __INTEL_CRT_REGS_H__ 7 7 + #define __INTEL_CRT_REGS_H__ 8 8 + 9 9 + #include "intel_display_reg_defs.h" 10 10 + 11 11 + #define ADPA _MMIO(0x61100) 12 12 + #define PCH_ADPA _MMIO(0xe1100) 13 13 + #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 14 14 + #define ADPA_DAC_ENABLE REG_BIT(31) 15 15 + #define ADPA_PIPE_SEL_MASK REG_BIT(30) 16 16 + #define ADPA_PIPE_SEL(pipe) REG_FIELD_PREP(ADPA_PIPE_SEL_MASK, (pipe)) 17 17 + #define ADPA_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29) 18 18 + #define ADPA_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(ADPA_PIPE_SEL_MASK_CPT, (pipe)) 19 19 + #define ADPA_CRT_HOTPLUG_MONITOR_MASK REG_GENMASK(25, 24) 20 20 + #define ADPA_CRT_HOTPLUG_MONITOR_NONE REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 0) 21 21 + #define ADPA_CRT_HOTPLUG_MONITOR_COLOR REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 3) 22 22 + #define ADPA_CRT_HOTPLUG_MONITOR_MONO REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 2) 23 23 + #define ADPA_CRT_HOTPLUG_ENABLE REG_BIT(23) 24 24 + #define ADPA_CRT_HOTPLUG_PERIOD_MASK REG_BIT(22) 25 25 + #define ADPA_CRT_HOTPLUG_PERIOD_64 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 0) 26 26 + #define ADPA_CRT_HOTPLUG_PERIOD_128 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 1) 27 27 + #define ADPA_CRT_HOTPLUG_WARMUP_MASK REG_BIT(21) 28 28 + #define ADPA_CRT_HOTPLUG_WARMUP_5MS REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 0) 29 29 + #define ADPA_CRT_HOTPLUG_WARMUP_10MS REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 1) 30 30 + #define ADPA_CRT_HOTPLUG_SAMPLE_MASK REG_BIT(20) 31 31 + #define ADPA_CRT_HOTPLUG_SAMPLE_2S REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 0) 32 32 + #define ADPA_CRT_HOTPLUG_SAMPLE_4S REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 1) 33 33 + #define ADPA_CRT_HOTPLUG_VOLTAGE_MASK REG_GENMASK(19, 18) 34 34 + #define ADPA_CRT_HOTPLUG_VOLTAGE_40 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 0) 35 35 + #define ADPA_CRT_HOTPLUG_VOLTAGE_50 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 1) 36 36 + #define ADPA_CRT_HOTPLUG_VOLTAGE_60 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 2) 37 37 + #define ADPA_CRT_HOTPLUG_VOLTAGE_70 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 3) 38 38 + #define ADPA_CRT_HOTPLUG_VOLREF_MASK REG_BIT(17) 39 39 + #define ADPA_CRT_HOTPLUG_VOLREF_325MV REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 0) 40 40 + #define ADPA_CRT_HOTPLUG_VOLREF_475MV REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 1) 41 41 + #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER REG_BIT(16) 42 42 + #define ADPA_USE_VGA_HVPOLARITY REG_BIT(15) 43 43 + #define ADPA_HSYNC_CNTL_DISABLE REG_BIT(11) 44 44 + #define ADPA_VSYNC_CNTL_DISABLE REG_BIT(10) 45 45 + #define ADPA_VSYNC_ACTIVE_HIGH REG_BIT(4) 46 46 + #define ADPA_HSYNC_ACTIVE_HIGH REG_BIT(3) 47 47 + 48 48 + #endif /* __INTEL_CRT_REGS_H__ */

+2 -12

drivers/gpu/drm/i915/display/intel_crtc_state_dump.c

reviewed

··· 50 50 hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame); 51 51 } 52 52 53 53 - static void 54 54 - intel_dump_buffer(const char *prefix, const u8 *buf, size_t len) 55 55 - { 56 56 - if (!drm_debug_enabled(DRM_UT_KMS)) 57 57 - return; 58 58 - 59 59 - print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_NONE, 60 60 - 16, 0, buf, len, false); 61 61 - } 62 62 - 63 53 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x 64 54 65 55 static const char * const output_type_str[] = { ··· 283 293 drm_dp_as_sdp_log(&p, &pipe_config->infoframes.as_sdp); 284 294 285 295 if (pipe_config->has_audio) 286 286 - intel_dump_buffer("ELD: ", pipe_config->eld, 287 287 - drm_eld_size(pipe_config->eld)); 296 296 + drm_print_hex_dump(&p, "ELD: ", pipe_config->eld, 297 297 + drm_eld_size(pipe_config->eld)); 288 298 289 299 drm_printf(&p, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n", 290 300 str_yes_no(pipe_config->vrr.enable),

+2 -3

drivers/gpu/drm/i915/display/intel_cursor.c

reviewed

··· 619 619 const struct intel_crtc_state *crtc_state) 620 620 { 621 621 struct intel_display *display = to_intel_display(plane->base.dev); 622 622 - struct drm_i915_private *i915 = to_i915(plane->base.dev); 623 622 enum plane_id plane_id = plane->id; 624 623 enum pipe pipe = plane->pipe; 625 624 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; ··· 626 627 &crtc_state->wm.skl.plane_ddb[plane_id]; 627 628 int level; 628 629 629 629 - for (level = 0; level < i915->display.wm.num_levels; level++) 630 630 + for (level = 0; level < display->wm.num_levels; level++) 630 631 intel_de_write_dsb(display, dsb, CUR_WM(pipe, level), 631 632 skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); 632 633 633 634 intel_de_write_dsb(display, dsb, CUR_WM_TRANS(pipe), 634 635 skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); 635 636 636 636 - if (HAS_HW_SAGV_WM(i915)) { 637 637 + if (HAS_HW_SAGV_WM(display)) { 637 638 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 638 639 639 640 intel_de_write_dsb(display, dsb, CUR_WM_SAGV(pipe),

+1 -1

drivers/gpu/drm/i915/display/intel_cx0_phy.c

reviewed

··· 2987 2987 struct intel_display *display = to_intel_display(encoder); 2988 2988 enum phy phy = intel_encoder_to_phy(encoder); 2989 2989 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2990 2990 - bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2990 2990 + bool lane_reversal = dig_port->lane_reversal; 2991 2991 u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 : 2992 2992 INTEL_CX0_LANE0; 2993 2993 intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);

+284 -207

drivers/gpu/drm/i915/display/intel_ddi.c

reviewed

··· 335 335 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 336 336 337 337 /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ 338 338 - intel_dp->DP = dig_port->saved_port_bits | 339 339 - DDI_PORT_WIDTH(crtc_state->lane_count) | 338 338 + intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) | 340 339 DDI_BUF_TRANS_SELECT(0); 340 340 + 341 341 + if (dig_port->lane_reversal) 342 342 + intel_dp->DP |= DDI_BUF_PORT_REVERSAL; 343 343 + if (dig_port->ddi_a_4_lanes) 344 344 + intel_dp->DP |= DDI_A_4_LANES; 341 345 342 346 if (DISPLAY_VER(i915) >= 14) { 343 347 if (intel_dp_is_uhbr(crtc_state)) ··· 459 455 } 460 456 461 457 static void 462 462 - intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, 463 463 - const struct intel_crtc_state *crtc_state) 458 458 + intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state, 459 459 + bool enable) 464 460 { 465 465 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 461 461 + struct intel_display *display = to_intel_display(crtc_state); 466 462 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 467 463 u32 val = 0; 468 464 469 469 - if (intel_dp_is_uhbr(crtc_state)) 465 465 + if (!HAS_DP20(display)) 466 466 + return; 467 467 + 468 468 + if (enable && intel_dp_is_uhbr(crtc_state)) 470 469 val = TRANS_DP2_128B132B_CHANNEL_CODING; 471 470 472 472 - intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val); 471 471 + intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val); 473 472 } 474 473 475 474 /* ··· 624 617 625 618 /* 626 619 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable 627 627 - * bit. 620 620 + * bit for the DDI function and enables the DP2 configuration. Called for all 621 621 + * transcoder types. 628 622 */ 629 629 - static void 623 623 + void 630 624 intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 631 625 const struct intel_crtc_state *crtc_state) 632 626 { ··· 636 628 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 637 629 u32 ctl; 638 630 631 631 + intel_ddi_config_transcoder_dp2(crtc_state, true); 632 632 + 639 633 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); 640 634 ctl &= ~TRANS_DDI_FUNC_ENABLE; 641 635 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 642 636 ctl); 643 637 } 644 638 639 639 + /* 640 640 + * Disable the DDI function and port syncing. 641 641 + * For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port, 642 642 + * SST/MST mode and disable the DP2 configuration. For TGL+ MST-master 643 643 + * transcoders these are done later in intel_ddi_post_disable_dp(). 644 644 + */ 645 645 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) 646 646 { 647 647 struct intel_display *display = to_intel_display(crtc_state); ··· 686 670 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), 687 671 ctl); 688 672 673 673 + if (intel_dp_mst_is_slave_trans(crtc_state)) 674 674 + intel_ddi_config_transcoder_dp2(crtc_state, false); 675 675 + 689 676 if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && 690 677 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 691 678 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); ··· 719 700 720 701 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 721 702 { 722 722 - struct drm_device *dev = intel_connector->base.dev; 723 723 - struct drm_i915_private *dev_priv = to_i915(dev); 703 703 + struct intel_display *display = to_intel_display(intel_connector); 704 704 + struct drm_i915_private *dev_priv = to_i915(display->drm); 724 705 struct intel_encoder *encoder = intel_attached_encoder(intel_connector); 725 706 int type = intel_connector->base.connector_type; 726 707 enum port port = encoder->port; 727 708 enum transcoder cpu_transcoder; 728 709 intel_wakeref_t wakeref; 729 710 enum pipe pipe = 0; 730 730 - u32 tmp; 711 711 + u32 ddi_mode; 731 712 bool ret; 732 713 733 714 wakeref = intel_display_power_get_if_enabled(dev_priv, ··· 735 716 if (!wakeref) 736 717 return false; 737 718 719 719 + /* Note: This returns false for DP MST primary encoders. */ 738 720 if (!encoder->get_hw_state(encoder, &pipe)) { 739 721 ret = false; 740 722 goto out; ··· 746 726 else 747 727 cpu_transcoder = (enum transcoder) pipe; 748 728 749 749 - tmp = intel_de_read(dev_priv, 750 750 - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 729 729 + ddi_mode = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & 730 730 + TRANS_DDI_MODE_SELECT_MASK; 751 731 752 752 - switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 753 753 - case TRANS_DDI_MODE_SELECT_HDMI: 754 754 - case TRANS_DDI_MODE_SELECT_DVI: 732 732 + if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI || 733 733 + ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 755 734 ret = type == DRM_MODE_CONNECTOR_HDMIA; 756 756 - break; 757 757 - 758 758 - case TRANS_DDI_MODE_SELECT_DP_SST: 735 735 + } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 736 736 + ret = type == DRM_MODE_CONNECTOR_VGA; 737 737 + } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 759 738 ret = type == DRM_MODE_CONNECTOR_eDP || 760 760 - type == DRM_MODE_CONNECTOR_DisplayPort; 761 761 - break; 762 762 - 763 763 - case TRANS_DDI_MODE_SELECT_DP_MST: 764 764 - /* if the transcoder is in MST state then 765 765 - * connector isn't connected */ 739 739 + type == DRM_MODE_CONNECTOR_DisplayPort; 740 740 + } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) { 741 741 + /* 742 742 + * encoder->get_hw_state() should have bailed out on MST. This 743 743 + * must be SST and non-eDP. 744 744 + */ 745 745 + ret = type == DRM_MODE_CONNECTOR_DisplayPort; 746 746 + } else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) { 747 747 + /* encoder->get_hw_state() should have bailed out on MST. */ 766 748 ret = false; 767 767 - break; 768 768 - 769 769 - case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 770 770 - if (HAS_DP20(dev_priv)) 771 771 - /* 128b/132b */ 772 772 - ret = false; 773 773 - else 774 774 - /* FDI */ 775 775 - ret = type == DRM_MODE_CONNECTOR_VGA; 776 776 - break; 777 777 - 778 778 - default: 749 749 + } else { 779 750 ret = false; 780 780 - break; 781 751 } 782 752 783 753 out: ··· 779 769 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, 780 770 u8 *pipe_mask, bool *is_dp_mst) 781 771 { 782 782 - struct drm_device *dev = encoder->base.dev; 783 783 - struct drm_i915_private *dev_priv = to_i915(dev); 772 772 + struct intel_display *display = to_intel_display(encoder); 773 773 + struct drm_i915_private *dev_priv = to_i915(display->drm); 784 774 enum port port = encoder->port; 785 775 intel_wakeref_t wakeref; 786 776 enum pipe p; ··· 825 815 mst_pipe_mask = 0; 826 816 for_each_pipe(dev_priv, p) { 827 817 enum transcoder cpu_transcoder = (enum transcoder)p; 828 828 - unsigned int port_mask, ddi_select; 818 818 + u32 port_mask, ddi_select, ddi_mode; 829 819 intel_wakeref_t trans_wakeref; 830 820 831 821 trans_wakeref = intel_display_power_get_if_enabled(dev_priv, ··· 849 839 if ((tmp & port_mask) != ddi_select) 850 840 continue; 851 841 852 852 - if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST || 853 853 - (HAS_DP20(dev_priv) && 854 854 - (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)) 842 842 + ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK; 843 843 + 844 844 + if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST || 845 845 + (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))) 855 846 mst_pipe_mask |= BIT(p); 856 847 857 848 *pipe_mask |= BIT(p); ··· 2207 2196 return DP_TP_CTL(encoder->port); 2208 2197 } 2209 2198 2210 2210 - i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2211 2211 - const struct intel_crtc_state *crtc_state) 2199 2199 + static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 2200 2200 + const struct intel_crtc_state *crtc_state) 2212 2201 { 2213 2202 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2214 2203 ··· 2217 2206 tgl_dp_tp_transcoder(crtc_state)); 2218 2207 else 2219 2208 return DP_TP_STATUS(encoder->port); 2209 2209 + } 2210 2210 + 2211 2211 + void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 2212 2212 + const struct intel_crtc_state *crtc_state) 2213 2213 + { 2214 2214 + struct intel_display *display = to_intel_display(encoder); 2215 2215 + 2216 2216 + intel_de_write(display, dp_tp_status_reg(encoder, crtc_state), 2217 2217 + DP_TP_STATUS_ACT_SENT); 2218 2218 + } 2219 2219 + 2220 2220 + void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 2221 2221 + const struct intel_crtc_state *crtc_state) 2222 2222 + { 2223 2223 + struct intel_display *display = to_intel_display(encoder); 2224 2224 + 2225 2225 + if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), 2226 2226 + DP_TP_STATUS_ACT_SENT, 1)) 2227 2227 + drm_err(display->drm, "Timed out waiting for ACT sent\n"); 2220 2228 } 2221 2229 2222 2230 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, ··· 2406 2376 2407 2377 if (intel_encoder_is_combo(encoder)) { 2408 2378 enum phy phy = intel_encoder_to_phy(encoder); 2409 2409 - bool lane_reversal = 2410 2410 - dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 2411 2379 2412 2380 intel_combo_phy_power_up_lanes(i915, phy, false, 2413 2381 crtc_state->lane_count, 2414 2414 - lane_reversal); 2382 2382 + dig_port->lane_reversal); 2415 2383 } 2416 2384 } 2417 2385 ··· 2549 2521 else 2550 2522 val |= XELPDP_PORT_BUF_PORT_DATA_10BIT; 2551 2523 2552 2552 - if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 2524 2524 + if (dig_port->lane_reversal) 2553 2525 val |= XELPDP_PORT_REVERSAL; 2554 2526 2555 2527 intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val); ··· 2611 2583 2612 2584 /* 2613 2585 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. 2614 2614 - */ 2615 2615 - intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2616 2616 - 2617 2617 - /* 2618 2586 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST 2619 2587 * Transport Select 2620 2588 */ ··· 2744 2720 * Transcoder. 2745 2721 */ 2746 2722 intel_ddi_enable_transcoder_clock(encoder, crtc_state); 2747 2747 - 2748 2748 - if (HAS_DP20(dev_priv)) 2749 2749 - intel_ddi_config_transcoder_dp2(encoder, crtc_state); 2750 2723 2751 2724 /* 2752 2725 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST ··· 2883 2862 const struct intel_crtc_state *crtc_state, 2884 2863 const struct drm_connector_state *conn_state) 2885 2864 { 2886 2886 - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2865 2865 + struct intel_display *display = to_intel_display(encoder); 2887 2866 2888 2888 - if (HAS_DP20(dev_priv)) 2867 2867 + if (HAS_DP20(display)) 2889 2868 intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder), 2890 2869 crtc_state); 2891 2870 ··· 2893 2872 if (crtc_state->has_panel_replay) 2894 2873 intel_psr_enable_sink(enc_to_intel_dp(encoder), crtc_state); 2895 2874 2896 2896 - if (DISPLAY_VER(dev_priv) >= 14) 2875 2875 + if (DISPLAY_VER(display) >= 14) 2897 2876 mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2898 2898 - else if (DISPLAY_VER(dev_priv) >= 12) 2877 2877 + else if (DISPLAY_VER(display) >= 12) 2899 2878 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); 2900 2879 else 2901 2880 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); ··· 2932 2911 crtc_state, conn_state); 2933 2912 } 2934 2913 2914 2914 + /* 2915 2915 + * Note: Also called from the ->pre_enable of the first active MST stream 2916 2916 + * encoder on its primary encoder. 2917 2917 + * 2918 2918 + * When called from DP MST code: 2919 2919 + * 2920 2920 + * - conn_state will be NULL 2921 2921 + * 2922 2922 + * - encoder will be the primary encoder (i.e. mst->primary) 2923 2923 + * 2924 2924 + * - the main connector associated with this port won't be active or linked to a 2925 2925 + * crtc 2926 2926 + * 2927 2927 + * - crtc_state will be the state of the first stream to be activated on this 2928 2928 + * port, and it may not be the same stream that will be deactivated last, but 2929 2929 + * each stream should have a state that is identical when it comes to the DP 2930 2930 + * link parameteres 2931 2931 + */ 2935 2932 static void intel_ddi_pre_enable(struct intel_atomic_state *state, 2936 2933 struct intel_encoder *encoder, 2937 2934 const struct intel_crtc_state *crtc_state, ··· 2958 2919 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2959 2920 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2960 2921 enum pipe pipe = crtc->pipe; 2961 2961 - 2962 2962 - /* 2963 2963 - * When called from DP MST code: 2964 2964 - * - conn_state will be NULL 2965 2965 - * - encoder will be the main encoder (ie. mst->primary) 2966 2966 - * - the main connector associated with this port 2967 2967 - * won't be active or linked to a crtc 2968 2968 - * - crtc_state will be the state of the first stream to 2969 2969 - * be activated on this port, and it may not be the same 2970 2970 - * stream that will be deactivated last, but each stream 2971 2971 - * should have a state that is identical when it comes to 2972 2972 - * the DP link parameteres 2973 2973 - */ 2974 2922 2975 2923 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); 2976 2924 ··· 3114 3088 3115 3089 intel_dp_sink_set_fec_ready(intel_dp, old_crtc_state, false); 3116 3090 3091 3091 + intel_ddi_config_transcoder_dp2(old_crtc_state, false); 3092 3092 + 3117 3093 /* 3118 3094 * From TGL spec: "If single stream or multi-stream master transcoder: 3119 3095 * Configure Transcoder Clock select to direct no clock to the ··· 3208 3180 } 3209 3181 } 3210 3182 3183 3183 + /* 3184 3184 + * Note: Also called from the ->post_disable of the last active MST stream 3185 3185 + * encoder on its primary encoder. See also the comment for 3186 3186 + * intel_ddi_pre_enable(). 3187 3187 + */ 3211 3188 static void intel_ddi_post_disable(struct intel_atomic_state *state, 3212 3189 struct intel_encoder *encoder, 3213 3190 const struct intel_crtc_state *old_crtc_state, ··· 3243 3210 old_conn_state); 3244 3211 } 3245 3212 3213 3213 + /* 3214 3214 + * Note: Also called from the ->post_pll_disable of the last active MST stream 3215 3215 + * encoder on its primary encoder. See also the comment for 3216 3216 + * intel_ddi_pre_enable(). 3217 3217 + */ 3246 3218 static void intel_ddi_post_pll_disable(struct intel_atomic_state *state, 3247 3219 struct intel_encoder *encoder, 3248 3220 const struct intel_crtc_state *old_crtc_state, ··· 3298 3260 crtc_state); 3299 3261 } 3300 3262 3301 3301 - static void intel_enable_ddi_dp(struct intel_atomic_state *state, 3263 3263 + static void intel_ddi_enable_dp(struct intel_atomic_state *state, 3302 3264 struct intel_encoder *encoder, 3303 3265 const struct intel_crtc_state *crtc_state, 3304 3266 const struct drm_connector_state *conn_state) ··· 3320 3282 trans_port_sync_stop_link_train(state, encoder, crtc_state); 3321 3283 } 3322 3284 3323 3323 - /* FIXME bad home for this function */ 3324 3324 - i915_reg_t hsw_chicken_trans_reg(struct drm_i915_private *i915, 3325 3325 - enum transcoder cpu_transcoder) 3326 3326 - { 3327 3327 - return DISPLAY_VER(i915) >= 14 ? 3328 3328 - MTL_CHICKEN_TRANS(cpu_transcoder) : 3329 3329 - CHICKEN_TRANS(cpu_transcoder); 3330 3330 - } 3331 3331 - 3332 3285 static i915_reg_t 3333 3333 - gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, 3334 3334 - enum port port) 3286 3286 + gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port) 3335 3287 { 3336 3288 static const enum transcoder trans[] = { 3337 3289 [PORT_A] = TRANSCODER_EDP, ··· 3331 3303 [PORT_E] = TRANSCODER_A, 3332 3304 }; 3333 3305 3334 3334 - drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); 3306 3306 + drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9); 3335 3307 3336 3336 - if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) 3308 3308 + if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E)) 3337 3309 port = PORT_A; 3338 3310 3339 3339 - return CHICKEN_TRANS(trans[port]); 3311 3311 + return CHICKEN_TRANS(display, trans[port]); 3340 3312 } 3341 3313 3342 3342 - static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, 3314 3314 + static void intel_ddi_enable_hdmi(struct intel_atomic_state *state, 3343 3315 struct intel_encoder *encoder, 3344 3316 const struct intel_crtc_state *crtc_state, 3345 3317 const struct drm_connector_state *conn_state) 3346 3318 { 3319 3319 + struct intel_display *display = to_intel_display(encoder); 3347 3320 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3348 3321 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3349 3322 struct drm_connector *connector = conn_state->connector; ··· 3375 3346 * the bits affect a specific DDI port rather than 3376 3347 * a specific transcoder. 3377 3348 */ 3378 3378 - i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); 3349 3349 + i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port); 3379 3350 u32 val; 3380 3351 3381 3352 val = intel_de_read(dev_priv, reg); ··· 3415 3386 * is filled with lane count, already set in the crtc_state. 3416 3387 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy. 3417 3388 */ 3418 3418 - buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; 3389 3389 + buf_ctl = DDI_BUF_CTL_ENABLE; 3390 3390 + 3391 3391 + if (dig_port->lane_reversal) 3392 3392 + buf_ctl |= DDI_BUF_PORT_REVERSAL; 3393 3393 + if (dig_port->ddi_a_4_lanes) 3394 3394 + buf_ctl |= DDI_A_4_LANES; 3395 3395 + 3419 3396 if (DISPLAY_VER(dev_priv) >= 14) { 3420 3397 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); 3421 3398 u32 port_buf = 0; 3422 3399 3423 3400 port_buf |= XELPDP_PORT_WIDTH(lane_count); 3424 3401 3425 3425 - if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) 3402 3402 + if (dig_port->lane_reversal) 3426 3403 port_buf |= XELPDP_PORT_REVERSAL; 3427 3404 3428 3405 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port), ··· 3448 3413 intel_wait_ddi_buf_active(encoder); 3449 3414 } 3450 3415 3451 3451 - static void intel_enable_ddi(struct intel_atomic_state *state, 3416 3416 + static void intel_ddi_enable(struct intel_atomic_state *state, 3452 3417 struct intel_encoder *encoder, 3453 3418 const struct intel_crtc_state *crtc_state, 3454 3419 const struct drm_connector_state *conn_state) ··· 3474 3439 } 3475 3440 3476 3441 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 3477 3477 - intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); 3442 3442 + intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state); 3478 3443 else 3479 3479 - intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); 3444 3444 + intel_ddi_enable_dp(state, encoder, crtc_state, conn_state); 3480 3445 3481 3446 intel_hdcp_enable(state, encoder, crtc_state, conn_state); 3482 3447 3483 3448 } 3484 3449 3485 3485 - static void intel_disable_ddi_dp(struct intel_atomic_state *state, 3450 3450 + static void intel_ddi_disable_dp(struct intel_atomic_state *state, 3486 3451 struct intel_encoder *encoder, 3487 3452 const struct intel_crtc_state *old_crtc_state, 3488 3453 const struct drm_connector_state *old_conn_state) ··· 3503 3468 false); 3504 3469 } 3505 3470 3506 3506 - static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, 3471 3471 + static void intel_ddi_disable_hdmi(struct intel_atomic_state *state, 3507 3472 struct intel_encoder *encoder, 3508 3473 const struct intel_crtc_state *old_crtc_state, 3509 3474 const struct drm_connector_state *old_conn_state) ··· 3518 3483 connector->base.id, connector->name); 3519 3484 } 3520 3485 3521 3521 - static void intel_disable_ddi(struct intel_atomic_state *state, 3486 3486 + static void intel_ddi_disable(struct intel_atomic_state *state, 3522 3487 struct intel_encoder *encoder, 3523 3488 const struct intel_crtc_state *old_crtc_state, 3524 3489 const struct drm_connector_state *old_conn_state) ··· 3528 3493 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); 3529 3494 3530 3495 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) 3531 3531 - intel_disable_ddi_hdmi(state, encoder, old_crtc_state, 3496 3496 + intel_ddi_disable_hdmi(state, encoder, old_crtc_state, 3532 3497 old_conn_state); 3533 3498 else 3534 3534 - intel_disable_ddi_dp(state, encoder, old_crtc_state, 3499 3499 + intel_ddi_disable_dp(state, encoder, old_crtc_state, 3535 3500 old_conn_state); 3536 3501 } 3537 3502 ··· 3591 3556 intel_update_active_dpll(state, pipe_crtc, encoder); 3592 3557 } 3593 3558 3559 3559 + /* 3560 3560 + * Note: Also called from the ->pre_pll_enable of the first active MST stream 3561 3561 + * encoder on its primary encoder. See also the comment for 3562 3562 + * intel_ddi_pre_enable(). 3563 3563 + */ 3594 3564 static void 3595 3565 intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 3596 3566 struct intel_encoder *encoder, ··· 3908 3868 crtc_state->sync_mode_slaves_mask); 3909 3869 } 3910 3870 3871 3871 + static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder, 3872 3872 + struct intel_crtc_state *crtc_state, 3873 3873 + u32 ddi_func_ctl) 3874 3874 + { 3875 3875 + struct intel_display *display = to_intel_display(encoder); 3876 3876 + 3877 3877 + crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI); 3878 3878 + if (DISPLAY_VER(display) >= 14) 3879 3879 + crtc_state->lane_count = 3880 3880 + ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3881 3881 + else 3882 3882 + crtc_state->lane_count = 4; 3883 3883 + } 3884 3884 + 3885 3885 + static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder, 3886 3886 + struct intel_crtc_state *crtc_state, 3887 3887 + u32 ddi_func_ctl) 3888 3888 + { 3889 3889 + crtc_state->has_hdmi_sink = true; 3890 3890 + 3891 3891 + crtc_state->infoframes.enable |= 3892 3892 + intel_hdmi_infoframes_enabled(encoder, crtc_state); 3893 3893 + 3894 3894 + if (crtc_state->infoframes.enable) 3895 3895 + crtc_state->has_infoframe = true; 3896 3896 + 3897 3897 + if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING) 3898 3898 + crtc_state->hdmi_scrambling = true; 3899 3899 + if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 3900 3900 + crtc_state->hdmi_high_tmds_clock_ratio = true; 3901 3901 + 3902 3902 + intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl); 3903 3903 + } 3904 3904 + 3905 3905 + static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder, 3906 3906 + struct intel_crtc_state *crtc_state, 3907 3907 + u32 ddi_func_ctl) 3908 3908 + { 3909 3909 + struct intel_display *display = to_intel_display(encoder); 3910 3910 + 3911 3911 + crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG); 3912 3912 + crtc_state->enhanced_framing = 3913 3913 + intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 3914 3914 + DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3915 3915 + } 3916 3916 + 3917 3917 + static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder, 3918 3918 + struct intel_crtc_state *crtc_state, 3919 3919 + u32 ddi_func_ctl) 3920 3920 + { 3921 3921 + struct intel_display *display = to_intel_display(encoder); 3922 3922 + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3923 3923 + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3924 3924 + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3925 3925 + 3926 3926 + if (encoder->type == INTEL_OUTPUT_EDP) 3927 3927 + crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP); 3928 3928 + else 3929 3929 + crtc_state->output_types |= BIT(INTEL_OUTPUT_DP); 3930 3930 + crtc_state->lane_count = 3931 3931 + ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3932 3932 + 3933 3933 + intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 3934 3934 + intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, &crtc_state->dp_m2_n2); 3935 3935 + 3936 3936 + crtc_state->enhanced_framing = 3937 3937 + intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) & 3938 3938 + DP_TP_CTL_ENHANCED_FRAME_ENABLE; 3939 3939 + 3940 3940 + if (DISPLAY_VER(display) >= 11) 3941 3941 + crtc_state->fec_enable = 3942 3942 + intel_de_read(display, 3943 3943 + dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 3944 3944 + 3945 3945 + if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 3946 3946 + crtc_state->infoframes.enable |= 3947 3947 + intel_lspcon_infoframes_enabled(encoder, crtc_state); 3948 3948 + else 3949 3949 + crtc_state->infoframes.enable |= 3950 3950 + intel_hdmi_infoframes_enabled(encoder, crtc_state); 3951 3951 + } 3952 3952 + 3953 3953 + static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder, 3954 3954 + struct intel_crtc_state *crtc_state, 3955 3955 + u32 ddi_func_ctl) 3956 3956 + { 3957 3957 + struct intel_display *display = to_intel_display(encoder); 3958 3958 + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3959 3959 + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 3960 3960 + 3961 3961 + crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST); 3962 3962 + crtc_state->lane_count = 3963 3963 + ((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 3964 3964 + 3965 3965 + if (DISPLAY_VER(display) >= 12) 3966 3966 + crtc_state->mst_master_transcoder = 3967 3967 + REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl); 3968 3968 + 3969 3969 + intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); 3970 3970 + 3971 3971 + if (DISPLAY_VER(display) >= 11) 3972 3972 + crtc_state->fec_enable = 3973 3973 + intel_de_read(display, 3974 3974 + dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE; 3975 3975 + 3976 3976 + crtc_state->infoframes.enable |= 3977 3977 + intel_hdmi_infoframes_enabled(encoder, crtc_state); 3978 3978 + } 3979 3979 + 3911 3980 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, 3912 3981 struct intel_crtc_state *pipe_config) 3913 3982 { 3983 3983 + struct intel_display *display = to_intel_display(encoder); 3914 3984 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3915 3915 - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 3916 3985 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3917 3917 - struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3918 3918 - u32 temp, flags = 0; 3986 3986 + u32 ddi_func_ctl, ddi_mode, flags = 0; 3919 3987 3920 3920 - temp = intel_de_read(dev_priv, 3921 3921 - TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3922 3922 - if (temp & TRANS_DDI_PHSYNC) 3988 3988 + ddi_func_ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); 3989 3989 + if (ddi_func_ctl & TRANS_DDI_PHSYNC) 3923 3990 flags |= DRM_MODE_FLAG_PHSYNC; 3924 3991 else 3925 3992 flags |= DRM_MODE_FLAG_NHSYNC; 3926 3926 - if (temp & TRANS_DDI_PVSYNC) 3993 3993 + if (ddi_func_ctl & TRANS_DDI_PVSYNC) 3927 3994 flags |= DRM_MODE_FLAG_PVSYNC; 3928 3995 else 3929 3996 flags |= DRM_MODE_FLAG_NVSYNC; 3930 3997 3931 3998 pipe_config->hw.adjusted_mode.flags |= flags; 3932 3999 3933 3933 - switch (temp & TRANS_DDI_BPC_MASK) { 4000 4000 + switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) { 3934 4001 case TRANS_DDI_BPC_6: 3935 4002 pipe_config->pipe_bpp = 18; 3936 4003 break; ··· 4054 3907 break; 4055 3908 } 4056 3909 4057 4057 - switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 4058 4058 - case TRANS_DDI_MODE_SELECT_HDMI: 4059 4059 - pipe_config->has_hdmi_sink = true; 3910 3910 + ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK; 4060 3911 4061 4061 - pipe_config->infoframes.enable |= 4062 4062 - intel_hdmi_infoframes_enabled(encoder, pipe_config); 4063 4063 - 4064 4064 - if (pipe_config->infoframes.enable) 4065 4065 - pipe_config->has_infoframe = true; 4066 4066 - 4067 4067 - if (temp & TRANS_DDI_HDMI_SCRAMBLING) 4068 4068 - pipe_config->hdmi_scrambling = true; 4069 4069 - if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE) 4070 4070 - pipe_config->hdmi_high_tmds_clock_ratio = true; 4071 4071 - fallthrough; 4072 4072 - case TRANS_DDI_MODE_SELECT_DVI: 4073 4073 - pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 4074 4074 - if (DISPLAY_VER(dev_priv) >= 14) 4075 4075 - pipe_config->lane_count = 4076 4076 - ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4077 4077 - else 4078 4078 - pipe_config->lane_count = 4; 4079 4079 - break; 4080 4080 - case TRANS_DDI_MODE_SELECT_DP_SST: 4081 4081 - if (encoder->type == INTEL_OUTPUT_EDP) 4082 4082 - pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 4083 4083 - else 4084 4084 - pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 4085 4085 - pipe_config->lane_count = 4086 4086 - ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4087 4087 - 4088 4088 - intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 4089 4089 - &pipe_config->dp_m_n); 4090 4090 - intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, 4091 4091 - &pipe_config->dp_m2_n2); 4092 4092 - 4093 4093 - pipe_config->enhanced_framing = 4094 4094 - intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 4095 4095 - DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4096 4096 - 4097 4097 - if (DISPLAY_VER(dev_priv) >= 11) 4098 4098 - pipe_config->fec_enable = 4099 4099 - intel_de_read(dev_priv, 4100 4100 - dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 4101 4101 - 4102 4102 - if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) 4103 4103 - pipe_config->infoframes.enable |= 4104 4104 - intel_lspcon_infoframes_enabled(encoder, pipe_config); 4105 4105 - else 4106 4106 - pipe_config->infoframes.enable |= 4107 4107 - intel_hdmi_infoframes_enabled(encoder, pipe_config); 4108 4108 - break; 4109 4109 - case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B: 4110 4110 - if (!HAS_DP20(dev_priv)) { 4111 4111 - /* FDI */ 4112 4112 - pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 4113 4113 - pipe_config->enhanced_framing = 4114 4114 - intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, pipe_config)) & 4115 4115 - DP_TP_CTL_ENHANCED_FRAME_ENABLE; 4116 4116 - break; 4117 4117 - } 4118 4118 - fallthrough; /* 128b/132b */ 4119 4119 - case TRANS_DDI_MODE_SELECT_DP_MST: 4120 4120 - pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); 4121 4121 - pipe_config->lane_count = 4122 4122 - ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; 4123 4123 - 4124 4124 - if (DISPLAY_VER(dev_priv) >= 12) 4125 4125 - pipe_config->mst_master_transcoder = 4126 4126 - REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp); 4127 4127 - 4128 4128 - intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, 4129 4129 - &pipe_config->dp_m_n); 4130 4130 - 4131 4131 - if (DISPLAY_VER(dev_priv) >= 11) 4132 4132 - pipe_config->fec_enable = 4133 4133 - intel_de_read(dev_priv, 4134 4134 - dp_tp_ctl_reg(encoder, pipe_config)) & DP_TP_CTL_FEC_ENABLE; 4135 4135 - 4136 4136 - pipe_config->infoframes.enable |= 4137 4137 - intel_hdmi_infoframes_enabled(encoder, pipe_config); 4138 4138 - break; 4139 4139 - default: 4140 4140 - break; 3912 3912 + if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) { 3913 3913 + intel_ddi_read_func_ctl_hdmi(encoder, pipe_config, ddi_func_ctl); 3914 3914 + } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) { 3915 3915 + intel_ddi_read_func_ctl_dvi(encoder, pipe_config, ddi_func_ctl); 3916 3916 + } else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) { 3917 3917 + intel_ddi_read_func_ctl_fdi(encoder, pipe_config, ddi_func_ctl); 3918 3918 + } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) { 3919 3919 + intel_ddi_read_func_ctl_dp_sst(encoder, pipe_config, ddi_func_ctl); 3920 3920 + } else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST || 3921 3921 + (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))) { 3922 3922 + intel_ddi_read_func_ctl_dp_mst(encoder, pipe_config, ddi_func_ctl); 4141 3923 } 4142 3924 } 4143 3925 3926 3926 + /* 3927 3927 + * Note: Also called from the ->get_config of the MST stream encoders on their 3928 3928 + * primary encoder, via the platform specific hooks here. See also the comment 3929 3929 + * for intel_ddi_pre_enable(). 3930 3930 + */ 4144 3931 static void intel_ddi_get_config(struct intel_encoder *encoder, 4145 3932 struct intel_crtc_state *pipe_config) 4146 3933 { ··· 4771 4690 if (dig_port->base.port != PORT_A) 4772 4691 return false; 4773 4692 4774 4774 - if (dig_port->saved_port_bits & DDI_A_4_LANES) 4693 4693 + if (dig_port->ddi_a_4_lanes) 4775 4694 return false; 4776 4695 4777 4696 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only ··· 4809 4728 if (intel_ddi_a_force_4_lanes(dig_port)) { 4810 4729 drm_dbg_kms(&dev_priv->drm, 4811 4730 "Forcing DDI_A_4_LANES for port A\n"); 4812 4812 - dig_port->saved_port_bits |= DDI_A_4_LANES; 4731 4731 + dig_port->ddi_a_4_lanes = true; 4813 4732 max_lanes = 4; 4814 4733 } 4815 4734 ··· 4988 4907 bool init_hdmi, init_dp; 4989 4908 enum port port; 4990 4909 enum phy phy; 4910 4910 + u32 ddi_buf_ctl; 4991 4911 4992 4912 port = intel_bios_encoder_port(devdata); 4993 4913 if (port == PORT_NONE) ··· 5112 5030 encoder->compute_output_type = intel_ddi_compute_output_type; 5113 5031 encoder->compute_config = intel_ddi_compute_config; 5114 5032 encoder->compute_config_late = intel_ddi_compute_config_late; 5115 5115 - encoder->enable = intel_enable_ddi; 5033 5033 + encoder->enable = intel_ddi_enable; 5116 5034 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; 5117 5035 encoder->pre_enable = intel_ddi_pre_enable; 5118 5118 - encoder->disable = intel_disable_ddi; 5036 5036 + encoder->disable = intel_ddi_disable; 5119 5037 encoder->post_pll_disable = intel_ddi_post_pll_disable; 5120 5038 encoder->post_disable = intel_ddi_post_disable; 5121 5039 encoder->update_pipe = intel_ddi_update_pipe; ··· 5238 5156 else 5239 5157 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 5240 5158 5241 5241 - if (DISPLAY_VER(dev_priv) >= 11) 5242 5242 - dig_port->saved_port_bits = 5243 5243 - intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5244 5244 - & DDI_BUF_PORT_REVERSAL; 5245 5245 - else 5246 5246 - dig_port->saved_port_bits = 5247 5247 - intel_de_read(dev_priv, DDI_BUF_CTL(port)) 5248 5248 - & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); 5159 5159 + ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 5249 5160 5250 5250 - if (intel_bios_encoder_lane_reversal(devdata)) 5251 5251 - dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; 5161 5161 + dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) || 5162 5162 + ddi_buf_ctl & DDI_BUF_PORT_REVERSAL; 5163 5163 + 5164 5164 + dig_port->ddi_a_4_lanes = DISPLAY_VER(dev_priv) < 11 && ddi_buf_ctl & DDI_A_4_LANES; 5252 5165 5253 5166 dig_port->dp.output_reg = INVALID_MMIO_REG; 5254 5167 dig_port->max_lanes = intel_ddi_max_lanes(dig_port);

+8 -4

drivers/gpu/drm/i915/display/intel_ddi.h

reviewed

··· 26 26 27 27 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, 28 28 const struct intel_crtc_state *crtc_state); 29 29 - i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, 30 30 - const struct intel_crtc_state *crtc_state); 31 31 - i915_reg_t hsw_chicken_trans_reg(struct drm_i915_private *i915, 32 32 - enum transcoder cpu_transcoder); 29 29 + 30 30 + void intel_ddi_clear_act_sent(struct intel_encoder *encoder, 31 31 + const struct intel_crtc_state *crtc_state); 32 32 + void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder, 33 33 + const struct intel_crtc_state *crtc_state); 34 34 + 33 35 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 34 36 struct intel_encoder *intel_encoder, 35 37 const struct intel_crtc_state *old_crtc_state, ··· 59 57 void intel_ddi_init(struct intel_display *display, 60 58 const struct intel_bios_encoder_data *devdata); 61 59 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); 60 60 + void intel_ddi_config_transcoder_func(struct intel_encoder *encoder, 61 61 + const struct intel_crtc_state *crtc_state); 62 62 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 63 63 const struct intel_crtc_state *crtc_state); 64 64 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);

+16 -7

drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

reviewed

··· 1687 1687 } 1688 1688 1689 1689 static const struct intel_ddi_buf_trans * 1690 1690 - mtl_get_cx0_buf_trans(struct intel_encoder *encoder, 1690 1690 + mtl_get_c10_buf_trans(struct intel_encoder *encoder, 1691 1691 const struct intel_crtc_state *crtc_state, 1692 1692 int *n_entries) 1693 1693 { 1694 1694 - if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->port_clock >= 1000000) 1694 1694 + return intel_get_buf_trans(&mtl_c10_trans_dp14, n_entries); 1695 1695 + } 1696 1696 + 1697 1697 + static const struct intel_ddi_buf_trans * 1698 1698 + mtl_get_c20_buf_trans(struct intel_encoder *encoder, 1699 1699 + const struct intel_crtc_state *crtc_state, 1700 1700 + int *n_entries) 1701 1701 + { 1702 1702 + if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(crtc_state)) 1695 1703 return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries); 1696 1696 - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && !(intel_encoder_is_c10phy(encoder))) 1704 1704 + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1697 1705 return intel_get_buf_trans(&mtl_c20_trans_hdmi, n_entries); 1698 1698 - else if (!intel_encoder_is_c10phy(encoder)) 1699 1699 - return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries); 1700 1706 else 1701 1701 - return intel_get_buf_trans(&mtl_c10_trans_dp14, n_entries); 1707 1707 + return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries); 1702 1708 } 1703 1709 1704 1710 void intel_ddi_buf_trans_init(struct intel_encoder *encoder) ··· 1712 1706 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1713 1707 1714 1708 if (DISPLAY_VER(i915) >= 14) { 1715 1715 - encoder->get_buf_trans = mtl_get_cx0_buf_trans; 1709 1709 + if (intel_encoder_is_c10phy(encoder)) 1710 1710 + encoder->get_buf_trans = mtl_get_c10_buf_trans; 1711 1711 + else 1712 1712 + encoder->get_buf_trans = mtl_get_c20_buf_trans; 1716 1713 } else if (IS_DG2(i915)) { 1717 1714 encoder->get_buf_trans = dg2_get_snps_buf_trans; 1718 1715 } else if (IS_ALDERLAKE_P(i915)) {

+10

drivers/gpu/drm/i915/display/intel_de.h

reviewed

··· 118 118 } 119 119 120 120 static inline int 121 121 + __intel_de_wait_for_register_atomic_nowl(struct intel_display *display, 122 122 + i915_reg_t reg, 123 123 + u32 mask, u32 value, 124 124 + unsigned int fast_timeout_us) 125 125 + { 126 126 + return __intel_wait_for_register(__to_uncore(display), reg, mask, 127 127 + value, fast_timeout_us, 0, NULL); 128 128 + } 129 129 + 130 130 + static inline int 121 131 intel_de_wait(struct intel_display *display, i915_reg_t reg, 122 132 u32 mask, u32 value, unsigned int timeout) 123 133 {

+51 -60

drivers/gpu/drm/i915/display/intel_display.c

reviewed

··· 511 511 512 512 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) 513 513 { 514 514 + struct intel_display *display = to_intel_display(new_crtc_state); 514 515 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 515 516 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 516 517 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; ··· 555 554 if (DISPLAY_VER(dev_priv) == 14) 556 555 set |= DP_FEC_BS_JITTER_WA; 557 556 558 558 - intel_de_rmw(dev_priv, 559 559 - hsw_chicken_trans_reg(dev_priv, cpu_transcoder), 557 557 + intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 560 558 clear, set); 561 559 } 562 560 ··· 591 591 592 592 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) 593 593 { 594 594 + struct intel_display *display = to_intel_display(old_crtc_state); 594 595 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 595 596 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 596 597 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; ··· 629 628 intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); 630 629 631 630 if (DISPLAY_VER(dev_priv) >= 12) 632 632 - intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder), 631 631 + intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 633 632 FECSTALL_DIS_DPTSTREAM_DPTTG, 0); 634 633 635 634 if ((val & TRANSCONF_ENABLE) == 0) ··· 1745 1744 1746 1745 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) 1747 1746 { 1748 1748 - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1749 1749 - struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1747 1747 + struct intel_display *display = to_intel_display(crtc_state); 1750 1748 1751 1751 - intel_de_rmw(i915, hsw_chicken_trans_reg(i915, crtc_state->cpu_transcoder), 1749 1749 + intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder), 1752 1750 HSW_FRAME_START_DELAY_MASK, 1753 1751 HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1)); 1754 1752 } ··· 2371 2371 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2372 2372 2373 2373 /* GDG double wide on either pipe, otherwise pipe A only */ 2374 2374 - return DISPLAY_VER(dev_priv) < 4 && 2374 2374 + return HAS_DOUBLE_WIDE(dev_priv) && 2375 2375 (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); 2376 2376 } 2377 2377 ··· 3137 3137 tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe)); 3138 3138 3139 3139 if (tmp & PIPE_MISC_YUV420_ENABLE) { 3140 3140 - /* We support 4:2:0 in full blend mode only */ 3141 3141 - drm_WARN_ON(&dev_priv->drm, 3142 3142 - (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 3140 3140 + /* 3141 3141 + * We support 4:2:0 in full blend mode only. 3142 3142 + * For xe3_lpd+ this is implied in YUV420 Enable bit. 3143 3143 + * Ensure the same for prior platforms in YUV420 Mode bit. 3144 3144 + */ 3145 3145 + if (DISPLAY_VER(dev_priv) < 30) 3146 3146 + drm_WARN_ON(&dev_priv->drm, 3147 3147 + (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0); 3143 3148 3144 3149 return INTEL_OUTPUT_FORMAT_YCBCR420; 3145 3150 } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) { ··· 3212 3207 3213 3208 intel_color_get_config(pipe_config); 3214 3209 3215 3215 - if (DISPLAY_VER(dev_priv) < 4) 3210 3210 + if (HAS_DOUBLE_WIDE(dev_priv)) 3216 3211 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE; 3217 3212 3218 3213 intel_get_transcoder_timings(crtc, pipe_config); ··· 3393 3388 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV; 3394 3389 3395 3390 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 3396 3396 - val |= PIPE_MISC_YUV420_ENABLE | 3397 3397 - PIPE_MISC_YUV420_MODE_FULL_BLEND; 3391 3391 + val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE : 3392 3392 + PIPE_MISC_YUV420_ENABLE | PIPE_MISC_YUV420_MODE_FULL_BLEND; 3398 3393 3399 3394 if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state)) 3400 3395 val |= PIPE_MISC_HDR_MODE_PRECISION; ··· 3751 3746 static void enabled_ultrajoiner_pipes(struct drm_i915_private *i915, 3752 3747 u8 *primary_pipes, u8 *secondary_pipes) 3753 3748 { 3749 3749 + struct intel_display *display = &i915->display; 3754 3750 struct intel_crtc *crtc; 3755 3751 3756 3752 *primary_pipes = 0; 3757 3753 *secondary_pipes = 0; 3758 3754 3759 3759 - if (!HAS_ULTRAJOINER(i915)) 3755 3755 + if (!HAS_ULTRAJOINER(display)) 3760 3756 return; 3761 3757 3762 3758 for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, ··· 4117 4111 static bool hsw_get_pipe_config(struct intel_crtc *crtc, 4118 4112 struct intel_crtc_state *pipe_config) 4119 4113 { 4114 4114 + struct intel_display *display = to_intel_display(crtc); 4120 4115 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4121 4116 bool active; 4122 4117 u32 tmp; ··· 4194 4187 } 4195 4188 4196 4189 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { 4197 4197 - tmp = intel_de_read(dev_priv, hsw_chicken_trans_reg(dev_priv, pipe_config->cpu_transcoder)); 4190 4190 + tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder)); 4198 4191 4199 4192 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; 4200 4193 } else { ··· 4552 4545 static int intel_crtc_atomic_check(struct intel_atomic_state *state, 4553 4546 struct intel_crtc *crtc) 4554 4547 { 4548 4548 + struct intel_display *display = to_intel_display(crtc); 4555 4549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4556 4550 struct intel_crtc_state *crtc_state = 4557 4551 intel_atomic_get_new_crtc_state(state, crtc); ··· 4589 4581 return ret; 4590 4582 } 4591 4583 4592 4592 - ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); 4584 4584 + ret = intel_atomic_setup_scalers(state, crtc); 4593 4585 if (ret) 4594 4586 return ret; 4595 4587 } 4596 4588 4597 4597 - if (HAS_IPS(dev_priv)) { 4589 4589 + if (HAS_IPS(display)) { 4598 4590 ret = hsw_ips_compute_config(state, crtc); 4599 4591 if (ret) 4600 4592 return ret; ··· 5216 5208 const struct drm_dp_vsc_sdp *a, 5217 5209 const struct drm_dp_vsc_sdp *b) 5218 5210 { 5219 5219 - pipe_config_mismatch(p, fastset, crtc, name, "dp sdp"); 5211 5211 + pipe_config_mismatch(p, fastset, crtc, name, "dp vsc sdp"); 5220 5212 5221 5213 drm_printf(p, "expected:\n"); 5222 5214 drm_dp_vsc_sdp_log(p, a); ··· 5225 5217 } 5226 5218 5227 5219 static void 5228 5228 - pipe_config_dp_as_sdp_mismatch(struct drm_i915_private *i915, 5229 5229 - bool fastset, const char *name, 5220 5220 + pipe_config_dp_as_sdp_mismatch(struct drm_printer *p, bool fastset, 5221 5221 + const struct intel_crtc *crtc, 5222 5222 + const char *name, 5230 5223 const struct drm_dp_as_sdp *a, 5231 5224 const struct drm_dp_as_sdp *b) 5232 5225 { 5233 5233 - struct drm_printer p; 5226 5226 + pipe_config_mismatch(p, fastset, crtc, name, "dp as sdp"); 5234 5227 5235 5235 - if (fastset) { 5236 5236 - p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, NULL); 5237 5237 - 5238 5238 - drm_printf(&p, "fastset requirement not met in %s dp sdp\n", name); 5239 5239 - } else { 5240 5240 - p = drm_err_printer(&i915->drm, NULL); 5241 5241 - 5242 5242 - drm_printf(&p, "mismatch in %s dp sdp\n", name); 5243 5243 - } 5244 5244 - 5245 5245 - drm_printf(&p, "expected:\n"); 5246 5246 - drm_dp_as_sdp_log(&p, a); 5247 5247 - drm_printf(&p, "found:\n"); 5248 5248 - drm_dp_as_sdp_log(&p, b); 5228 5228 + drm_printf(p, "expected:\n"); 5229 5229 + drm_dp_as_sdp_log(p, a); 5230 5230 + drm_printf(p, "found:\n"); 5231 5231 + drm_dp_as_sdp_log(p, b); 5249 5232 } 5250 5233 5251 5234 /* Returns the length up to and including the last differing byte */ ··· 5259 5260 const char *name, 5260 5261 const u8 *a, const u8 *b, size_t len) 5261 5262 { 5262 5262 - const char *loglevel; 5263 5263 - 5264 5264 - if (fastset) { 5265 5265 - if (!drm_debug_enabled(DRM_UT_KMS)) 5266 5266 - return; 5267 5267 - 5268 5268 - loglevel = KERN_DEBUG; 5269 5269 - } else { 5270 5270 - loglevel = KERN_ERR; 5271 5271 - } 5272 5272 - 5273 5263 pipe_config_mismatch(p, fastset, crtc, name, "buffer"); 5274 5264 5275 5265 /* only dump up to the last difference */ 5276 5266 len = memcmp_diff_len(a, b, len); 5277 5267 5278 5278 - print_hex_dump(loglevel, "expected: ", DUMP_PREFIX_NONE, 5279 5279 - 16, 0, a, len, false); 5280 5280 - print_hex_dump(loglevel, "found: ", DUMP_PREFIX_NONE, 5281 5281 - 16, 0, b, len, false); 5268 5268 + drm_print_hex_dump(p, "expected: ", a, len); 5269 5269 + drm_print_hex_dump(p, "found: ", b, len); 5282 5270 } 5283 5271 5284 5272 static void ··· 5308 5322 const struct intel_crtc_state *pipe_config, 5309 5323 bool fastset) 5310 5324 { 5325 5325 + struct intel_display *display = to_intel_display(current_config); 5311 5326 struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev); 5312 5327 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 5313 5328 struct drm_printer p; ··· 5485 5498 #define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \ 5486 5499 if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \ 5487 5500 &pipe_config->infoframes.name)) { \ 5488 5488 - pipe_config_dp_as_sdp_mismatch(dev_priv, fastset, __stringify(name), \ 5501 5501 + pipe_config_dp_as_sdp_mismatch(&p, fastset, crtc, __stringify(name), \ 5489 5502 &current_config->infoframes.name, \ 5490 5503 &pipe_config->infoframes.name); \ 5491 5504 ret = false; \ ··· 5549 5562 PIPE_CONF_CHECK_I(lane_count); 5550 5563 PIPE_CONF_CHECK_X(lane_lat_optim_mask); 5551 5564 5552 5552 - if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) { 5565 5565 + if (HAS_DOUBLE_BUFFERED_M_N(display)) { 5553 5566 if (!fastset || !pipe_config->update_m_n) 5554 5567 PIPE_CONF_CHECK_M_N(dp_m_n); 5555 5568 } else { ··· 5730 5743 PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset); 5731 5744 5732 5745 PIPE_CONF_CHECK_BOOL(dsc.compression_enable); 5733 5733 - PIPE_CONF_CHECK_BOOL(dsc.dsc_split); 5746 5746 + PIPE_CONF_CHECK_I(dsc.num_streams); 5734 5747 PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16); 5735 5748 5736 5749 PIPE_CONF_CHECK_BOOL(splitter.enable); ··· 6784 6797 int intel_atomic_check(struct drm_device *dev, 6785 6798 struct drm_atomic_state *_state) 6786 6799 { 6800 6800 + struct intel_display *display = to_intel_display(dev); 6787 6801 struct drm_i915_private *dev_priv = to_i915(dev); 6788 6802 struct intel_atomic_state *state = to_intel_atomic_state(_state); 6789 6803 struct intel_crtc_state *old_crtc_state, *new_crtc_state; ··· 6792 6804 int ret, i; 6793 6805 bool any_ms = false; 6794 6806 6795 6795 - if (!intel_display_driver_check_access(dev_priv)) 6807 6807 + if (!intel_display_driver_check_access(display)) 6796 6808 return -ENODEV; 6797 6809 6798 6810 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, ··· 7560 7572 static void intel_atomic_cleanup_work(struct work_struct *work) 7561 7573 { 7562 7574 struct intel_atomic_state *state = 7563 7563 - container_of(work, struct intel_atomic_state, base.commit_work); 7575 7575 + container_of(work, struct intel_atomic_state, cleanup_work); 7564 7576 struct drm_i915_private *i915 = to_i915(state->base.dev); 7565 7577 struct intel_crtc_state *old_crtc_state; 7566 7578 struct intel_crtc *crtc; ··· 7810 7822 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7811 7823 dev_priv->display.funcs.display->commit_modeset_enables(state); 7812 7824 7825 7825 + intel_program_dpkgc_latency(state); 7826 7826 + 7813 7827 if (state->modeset) 7814 7828 intel_set_cdclk_post_plane_update(state); 7815 7829 ··· 7917 7927 * schedule point (cond_resched()) here anyway to keep latencies 7918 7928 * down. 7919 7929 */ 7920 7920 - INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); 7921 7921 - queue_work(system_highpri_wq, &state->base.commit_work); 7930 7930 + INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work); 7931 7931 + queue_work(dev_priv->display.wq.cleanup, &state->cleanup_work); 7922 7932 } 7923 7933 7924 7934 static void intel_atomic_commit_work(struct work_struct *work) ··· 8298 8308 8299 8309 static int max_dotclock(struct drm_i915_private *i915) 8300 8310 { 8301 8301 - int max_dotclock = i915->display.cdclk.max_dotclk_freq; 8311 8311 + struct intel_display *display = &i915->display; 8312 8312 + int max_dotclock = display->cdclk.max_dotclk_freq; 8302 8313 8303 8303 - if (HAS_ULTRAJOINER(i915)) 8314 8314 + if (HAS_ULTRAJOINER(display)) 8304 8315 max_dotclock *= 4; 8305 8305 - else if (HAS_UNCOMPRESSED_JOINER(i915) || HAS_BIGJOINER(i915)) 8316 8316 + else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display)) 8306 8317 max_dotclock *= 2; 8307 8318 8308 8319 return max_dotclock;

-3

drivers/gpu/drm/i915/display/intel_display.h

reviewed

··· 238 238 for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \ 239 239 for_each_if((__phys_mask) & BIT(__phy)) 240 240 241 241 - #define for_each_crtc(dev, crtc) \ 242 242 - list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) 243 243 - 244 241 #define for_each_intel_plane(dev, intel_plane) \ 245 242 list_for_each_entry(intel_plane, \ 246 243 &(dev)->mode_config.plane_list, \

+16 -1

drivers/gpu/drm/i915/display/intel_display_core.h

reviewed

··· 453 453 } ips; 454 454 455 455 struct { 456 456 - bool display_irqs_enabled; 456 456 + /* 457 457 + * Most platforms treat the display irq block as an always-on 458 458 + * power domain. vlv/chv can disable it at runtime and need 459 459 + * special care to avoid writing any of the display block 460 460 + * registers outside of the power domain. We defer setting up 461 461 + * the display irqs in this case to the runtime pm. 462 462 + */ 463 463 + bool vlv_display_irqs_enabled; 457 464 458 465 /* For i915gm/i945gm vblank irq workaround */ 459 466 u8 vblank_enabled; ··· 512 505 /* restore state for suspend/resume and display reset */ 513 506 struct drm_atomic_state *modeset_state; 514 507 struct drm_modeset_acquire_ctx reset_ctx; 508 508 + u32 saveDSPARB; 509 509 + u32 saveSWF0[16]; 510 510 + u32 saveSWF1[16]; 511 511 + u32 saveSWF3[3]; 512 512 + u16 saveGCDGMBUS; 515 513 } restore; 516 514 517 515 struct { ··· 554 542 555 543 /* unbound hipri wq for page flips/plane updates */ 556 544 struct workqueue_struct *flip; 545 545 + 546 546 + /* hipri wq for commit cleanups */ 547 547 + struct workqueue_struct *cleanup; 557 548 } wq; 558 549 559 550 /* Grouping using named structs. Keep sorted. */

+4 -3

drivers/gpu/drm/i915/display/intel_display_debugfs.c

reviewed

··· 730 730 intel_lpsp_power_well_enabled(struct drm_i915_private *i915, 731 731 enum i915_power_well_id power_well_id) 732 732 { 733 733 + struct intel_display *display = &i915->display; 733 734 intel_wakeref_t wakeref; 734 735 bool is_enabled; 735 736 736 737 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 737 737 - is_enabled = intel_display_power_well_is_enabled(i915, 738 738 + is_enabled = intel_display_power_well_is_enabled(display, 738 739 power_well_id); 739 740 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 740 741 ··· 1332 1331 { 1333 1332 struct seq_file *m = file->private_data; 1334 1333 struct intel_connector *connector = m->private; 1335 1335 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 1334 1334 + struct intel_display *display = to_intel_display(connector); 1336 1335 int force_joined_pipes = 0; 1337 1336 int ret; 1338 1337 ··· 1350 1349 connector->force_joined_pipes = force_joined_pipes; 1351 1350 break; 1352 1351 case 4: 1353 1353 - if (HAS_ULTRAJOINER(i915)) { 1352 1352 + if (HAS_ULTRAJOINER(display)) { 1354 1353 connector->force_joined_pipes = force_joined_pipes; 1355 1354 break; 1356 1355 }

+160 -118

drivers/gpu/drm/i915/display/intel_display_device.c

reviewed

··· 16 16 #include "intel_display_params.h" 17 17 #include "intel_display_power.h" 18 18 #include "intel_display_reg_defs.h" 19 19 + #include "intel_display_types.h" 19 20 #include "intel_fbc.h" 20 21 #include "intel_step.h" 21 22 ··· 253 252 254 253 static const struct platform_desc i830_desc = { 255 254 PLATFORM(i830), 255 255 + PLATFORM_GROUP(mobile), 256 256 .info = &(const struct intel_display_device_info) { 257 257 I830_DISPLAY, 258 258 ··· 272 270 273 271 static const struct platform_desc i85x_desc = { 274 272 PLATFORM(i85x), 273 273 + PLATFORM_GROUP(mobile), 275 274 .info = &(const struct intel_display_device_info) { 276 275 I830_DISPLAY, 277 276 ··· 315 312 316 313 static const struct platform_desc i915gm_desc = { 317 314 PLATFORM(i915gm), 315 315 + PLATFORM_GROUP(mobile), 318 316 .info = &(const struct intel_display_device_info) { 319 317 GEN3_DISPLAY, 320 318 I9XX_COLORS, ··· 340 336 341 337 static const struct platform_desc i945gm_desc = { 342 338 PLATFORM(i915gm), 339 339 + PLATFORM_GROUP(mobile), 343 340 .info = &(const struct intel_display_device_info) { 344 341 GEN3_DISPLAY, 345 342 I9XX_COLORS, ··· 362 357 }, 363 358 }; 364 359 365 365 - static const struct platform_desc pnv_desc = { 360 360 + static const struct intel_display_device_info pnv_display = { 361 361 + GEN3_DISPLAY, 362 362 + I9XX_COLORS, 363 363 + .has_hotplug = 1, 364 364 + }; 365 365 + 366 366 + static const struct platform_desc pnv_g_desc = { 366 367 PLATFORM(pineview), 367 367 - .info = &(const struct intel_display_device_info) { 368 368 - GEN3_DISPLAY, 369 369 - I9XX_COLORS, 370 370 - .has_hotplug = 1, 371 371 - }, 368 368 + .info = &pnv_display, 369 369 + }; 370 370 + 371 371 + static const struct platform_desc pnv_m_desc = { 372 372 + PLATFORM(pineview), 373 373 + PLATFORM_GROUP(mobile), 374 374 + .info = &pnv_display, 372 375 }; 373 376 374 377 #define GEN4_DISPLAY \ ··· 403 390 404 391 static const struct platform_desc i965gm_desc = { 405 392 PLATFORM(i965gm), 393 393 + PLATFORM_GROUP(mobile), 406 394 .info = &(const struct intel_display_device_info) { 407 395 GEN4_DISPLAY, 408 396 .has_overlay = 1, ··· 427 413 static const struct platform_desc gm45_desc = { 428 414 PLATFORM(gm45), 429 415 PLATFORM_GROUP(g4x), 416 416 + PLATFORM_GROUP(mobile), 430 417 .info = &(const struct intel_display_device_info) { 431 418 GEN4_DISPLAY, 432 419 .supports_tv = 1, ··· 458 443 459 444 static const struct platform_desc ilk_m_desc = { 460 445 PLATFORM(ironlake), 446 446 + PLATFORM_GROUP(mobile), 461 447 .info = &(const struct intel_display_device_info) { 462 448 ILK_DISPLAY, 463 449 ··· 466 450 }, 467 451 }; 468 452 469 469 - static const struct platform_desc snb_desc = { 470 470 - PLATFORM(sandybridge), 471 471 - .info = &(const struct intel_display_device_info) { 472 472 - .has_hotplug = 1, 473 473 - I9XX_PIPE_OFFSETS, 474 474 - I9XX_CURSOR_OFFSETS, 475 475 - ILK_COLORS, 453 453 + static const struct intel_display_device_info snb_display = { 454 454 + .has_hotplug = 1, 455 455 + I9XX_PIPE_OFFSETS, 456 456 + I9XX_CURSOR_OFFSETS, 457 457 + ILK_COLORS, 476 458 477 477 - .__runtime_defaults.ip.ver = 6, 478 478 - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 479 479 - .__runtime_defaults.cpu_transcoder_mask = 480 480 - BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 481 481 - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 482 482 - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 483 483 - }, 459 459 + .__runtime_defaults.ip.ver = 6, 460 460 + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), 461 461 + .__runtime_defaults.cpu_transcoder_mask = 462 462 + BIT(TRANSCODER_A) | BIT(TRANSCODER_B), 463 463 + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 464 464 + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 484 465 }; 485 466 486 486 - static const struct platform_desc ivb_desc = { 487 487 - PLATFORM(ivybridge), 488 488 - .info = &(const struct intel_display_device_info) { 489 489 - .has_hotplug = 1, 490 490 - IVB_PIPE_OFFSETS, 491 491 - IVB_CURSOR_OFFSETS, 492 492 - IVB_COLORS, 467 467 + static const struct platform_desc snb_d_desc = { 468 468 + PLATFORM(sandybridge), 469 469 + .info = &snb_display, 470 470 + }; 493 471 494 494 - .__runtime_defaults.ip.ver = 7, 495 495 - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 496 496 - .__runtime_defaults.cpu_transcoder_mask = 497 497 - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 498 498 - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 499 499 - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 500 500 - }, 472 472 + static const struct platform_desc snb_m_desc = { 473 473 + PLATFORM(sandybridge), 474 474 + PLATFORM_GROUP(mobile), 475 475 + .info = &snb_display, 476 476 + }; 477 477 + 478 478 + static const struct intel_display_device_info ivb_display = { 479 479 + .has_hotplug = 1, 480 480 + IVB_PIPE_OFFSETS, 481 481 + IVB_CURSOR_OFFSETS, 482 482 + IVB_COLORS, 483 483 + 484 484 + .__runtime_defaults.ip.ver = 7, 485 485 + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), 486 486 + .__runtime_defaults.cpu_transcoder_mask = 487 487 + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), 488 488 + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ 489 489 + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), 490 490 + }; 491 491 + 492 492 + static const struct platform_desc ivb_d_desc = { 493 493 + PLATFORM(ivybridge), 494 494 + .info = &ivb_display, 495 495 + }; 496 496 + 497 497 + static const struct platform_desc ivb_m_desc = { 498 498 + PLATFORM(ivybridge), 499 499 + PLATFORM_GROUP(mobile), 500 500 + .info = &ivb_display, 501 501 }; 502 502 503 503 static const struct platform_desc vlv_desc = { ··· 1043 1011 1044 1012 static const struct platform_desc dg1_desc = { 1045 1013 PLATFORM(dg1), 1014 1014 + PLATFORM_GROUP(dgfx), 1046 1015 .info = &(const struct intel_display_device_info) { 1047 1016 XE_D_DISPLAY, 1048 1017 ··· 1271 1238 1272 1239 static const struct platform_desc dg2_desc = { 1273 1240 PLATFORM(dg2), 1241 1241 + PLATFORM_GROUP(dgfx), 1274 1242 .subplatforms = (const struct subplatform_desc[]) { 1275 1243 { 1276 1244 SUBPLATFORM(dg2, g10), ··· 1372 1338 1373 1339 static const struct platform_desc bmg_desc = { 1374 1340 PLATFORM(battlemage), 1341 1341 + PLATFORM_GROUP(dgfx), 1375 1342 }; 1376 1343 1377 1344 static const struct platform_desc ptl_desc = { ··· 1416 1381 INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_desc), 1417 1382 INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_desc), 1418 1383 INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_desc), 1419 1419 - INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, &pnv_desc), 1384 1384 + INTEL_PNV_G_IDS(INTEL_DISPLAY_DEVICE, &pnv_g_desc), 1385 1385 + INTEL_PNV_M_IDS(INTEL_DISPLAY_DEVICE, &pnv_m_desc), 1420 1386 INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_desc), 1421 1387 INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_desc), 1422 1422 - INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, &snb_desc), 1423 1423 - INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, &ivb_desc), 1388 1388 + INTEL_SNB_D_IDS(INTEL_DISPLAY_DEVICE, &snb_d_desc), 1389 1389 + INTEL_SNB_M_IDS(INTEL_DISPLAY_DEVICE, &snb_m_desc), 1390 1390 + INTEL_IVB_D_IDS(INTEL_DISPLAY_DEVICE, &ivb_d_desc), 1391 1391 + INTEL_IVB_M_IDS(INTEL_DISPLAY_DEVICE, &ivb_m_desc), 1424 1392 INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_desc), 1425 1393 INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_desc), 1426 1394 INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_desc), ··· 1467 1429 }; 1468 1430 1469 1431 static const struct intel_display_device_info * 1470 1470 - probe_gmdid_display(struct drm_i915_private *i915, struct intel_display_ip_ver *ip_ver) 1432 1432 + probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *ip_ver) 1471 1433 { 1472 1472 - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1434 1434 + struct pci_dev *pdev = to_pci_dev(display->drm->dev); 1473 1435 struct intel_display_ip_ver gmd_id; 1474 1436 void __iomem *addr; 1475 1437 u32 val; ··· 1477 1439 1478 1440 addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); 1479 1441 if (!addr) { 1480 1480 - drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); 1442 1442 + drm_err(display->drm, 1443 1443 + "Cannot map MMIO BAR to read display GMD_ID\n"); 1481 1444 return NULL; 1482 1445 } 1483 1446 ··· 1486 1447 pci_iounmap(pdev, addr); 1487 1448 1488 1449 if (val == 0) { 1489 1489 - drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); 1450 1450 + drm_dbg_kms(display->drm, "Device doesn't have display\n"); 1490 1451 return NULL; 1491 1452 } 1492 1453 ··· 1502 1463 } 1503 1464 } 1504 1465 1505 1505 - drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n", 1466 1466 + drm_err(display->drm, 1467 1467 + "Unrecognized display IP version %d.%02d; disabling display.\n", 1506 1468 gmd_id.ver, gmd_id.rel); 1507 1469 return NULL; 1508 1470 } ··· 1604 1564 bitmap_or(dst->bitmap, dst->bitmap, src->bitmap, display_platforms_num_bits()); 1605 1565 } 1606 1566 1607 1607 - void intel_display_device_probe(struct drm_i915_private *i915) 1567 1567 + struct intel_display *intel_display_device_probe(struct pci_dev *pdev) 1608 1568 { 1609 1609 - struct intel_display *display = &i915->display; 1610 1610 - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1569 1569 + struct intel_display *display = to_intel_display(pdev); 1611 1570 const struct intel_display_device_info *info; 1612 1571 struct intel_display_ip_ver ip_ver = {}; 1613 1572 const struct platform_desc *desc; ··· 1614 1575 enum intel_step step; 1615 1576 1616 1577 /* Add drm device backpointer as early as possible. */ 1617 1617 - i915->display.drm = &i915->drm; 1578 1578 + display->drm = pci_get_drvdata(pdev); 1618 1579 1619 1619 - intel_display_params_copy(&i915->display.params); 1580 1580 + intel_display_params_copy(&display->params); 1620 1581 1621 1582 if (has_no_display(pdev)) { 1622 1622 - drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); 1583 1583 + drm_dbg_kms(display->drm, "Device doesn't have display\n"); 1623 1584 goto no_display; 1624 1585 } 1625 1586 1626 1587 desc = find_platform_desc(pdev); 1627 1588 if (!desc) { 1628 1628 - drm_dbg_kms(&i915->drm, "Unknown device ID %04x; disabling display.\n", 1589 1589 + drm_dbg_kms(display->drm, 1590 1590 + "Unknown device ID %04x; disabling display.\n", 1629 1591 pdev->device); 1630 1592 goto no_display; 1631 1593 } 1632 1594 1633 1595 info = desc->info; 1634 1596 if (!info) 1635 1635 - info = probe_gmdid_display(i915, &ip_ver); 1597 1597 + info = probe_gmdid_display(display, &ip_ver); 1636 1598 if (!info) 1637 1599 goto no_display; 1638 1600 1639 1639 - DISPLAY_INFO(i915) = info; 1601 1601 + DISPLAY_INFO(display) = info; 1640 1602 1641 1641 - memcpy(DISPLAY_RUNTIME_INFO(i915), 1642 1642 - &DISPLAY_INFO(i915)->__runtime_defaults, 1643 1643 - sizeof(*DISPLAY_RUNTIME_INFO(i915))); 1603 1603 + memcpy(DISPLAY_RUNTIME_INFO(display), 1604 1604 + &DISPLAY_INFO(display)->__runtime_defaults, 1605 1605 + sizeof(*DISPLAY_RUNTIME_INFO(display))); 1644 1606 1645 1645 - drm_WARN_ON(&i915->drm, !desc->name || 1607 1607 + drm_WARN_ON(display->drm, !desc->name || 1646 1608 !display_platforms_weight(&desc->platforms)); 1647 1609 1648 1610 display->platform = desc->platforms; 1649 1611 1650 1612 subdesc = find_subplatform_desc(pdev, desc); 1651 1613 if (subdesc) { 1652 1652 - drm_WARN_ON(&i915->drm, !subdesc->name || 1614 1614 + drm_WARN_ON(display->drm, !subdesc->name || 1653 1615 !display_platforms_weight(&subdesc->platforms)); 1654 1616 1655 1617 display_platforms_or(&display->platform, &subdesc->platforms); 1656 1618 1657 1619 /* Ensure platform and subplatform are distinct */ 1658 1658 - drm_WARN_ON(&i915->drm, 1620 1620 + drm_WARN_ON(display->drm, 1659 1621 display_platforms_weight(&display->platform) != 1660 1622 display_platforms_weight(&desc->platforms) + 1661 1623 display_platforms_weight(&subdesc->platforms)); 1662 1624 } 1663 1625 1664 1626 if (ip_ver.ver || ip_ver.rel || ip_ver.step) { 1665 1665 - DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; 1627 1627 + DISPLAY_RUNTIME_INFO(display)->ip = ip_ver; 1666 1628 step = STEP_A0 + ip_ver.step; 1667 1629 if (step > STEP_FUTURE) { 1668 1630 drm_dbg_kms(display->drm, "Using future display stepping\n"); ··· 1674 1634 subdesc ? &subdesc->step_info : NULL); 1675 1635 } 1676 1636 1677 1677 - DISPLAY_RUNTIME_INFO(i915)->step = step; 1637 1637 + DISPLAY_RUNTIME_INFO(display)->step = step; 1678 1638 1679 1679 - drm_info(&i915->drm, "Found %s%s%s (device ID %04x) display version %u.%02u stepping %s\n", 1639 1639 + drm_info(display->drm, "Found %s%s%s (device ID %04x) %s display version %u.%02u stepping %s\n", 1680 1640 desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "", 1681 1681 - pdev->device, DISPLAY_RUNTIME_INFO(i915)->ip.ver, 1682 1682 - DISPLAY_RUNTIME_INFO(i915)->ip.rel, 1641 1641 + pdev->device, display->platform.dgfx ? "discrete" : "integrated", 1642 1642 + DISPLAY_RUNTIME_INFO(display)->ip.ver, 1643 1643 + DISPLAY_RUNTIME_INFO(display)->ip.rel, 1683 1644 step != STEP_NONE ? intel_step_name(step) : "N/A"); 1684 1645 1685 1685 - return; 1646 1646 + return display; 1686 1647 1687 1648 no_display: 1688 1688 - DISPLAY_INFO(i915) = &no_display; 1649 1649 + DISPLAY_INFO(display) = &no_display; 1650 1650 + 1651 1651 + return display; 1689 1652 } 1690 1653 1691 1691 - void intel_display_device_remove(struct drm_i915_private *i915) 1654 1654 + void intel_display_device_remove(struct intel_display *display) 1692 1655 { 1693 1693 - intel_display_params_free(&i915->display.params); 1656 1656 + intel_display_params_free(&display->params); 1694 1657 } 1695 1658 1696 1696 - static void __intel_display_device_info_runtime_init(struct drm_i915_private *i915) 1659 1659 + static void __intel_display_device_info_runtime_init(struct intel_display *display) 1697 1660 { 1698 1698 - struct intel_display *display = &i915->display; 1699 1699 - struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915); 1661 1661 + struct drm_i915_private *i915 = to_i915(display->drm); 1662 1662 + struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(display); 1700 1663 enum pipe pipe; 1701 1664 1702 1665 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES); ··· 1707 1664 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS); 1708 1665 1709 1666 /* This covers both ULT and ULX */ 1710 1710 - if (IS_HASWELL_ULT(i915) || IS_BROADWELL_ULT(i915)) 1667 1667 + if (display->platform.haswell_ult || display->platform.broadwell_ult) 1711 1668 display_runtime->port_mask &= ~BIT(PORT_D); 1712 1669 1713 1713 - if (IS_ICL_WITH_PORT_F(i915)) 1670 1670 + if (display->platform.icelake_port_f) 1714 1671 display_runtime->port_mask |= BIT(PORT_F); 1715 1672 1716 1673 /* Wa_14011765242: adl-s A0,A1 */ 1717 1717 - if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2)) 1718 1718 - for_each_pipe(i915, pipe) 1674 1674 + if (display->platform.alderlake_s && IS_DISPLAY_STEP(display, STEP_A0, STEP_A2)) 1675 1675 + for_each_pipe(display, pipe) 1719 1676 display_runtime->num_scalers[pipe] = 0; 1720 1720 - else if (DISPLAY_VER(i915) >= 11) { 1721 1721 - for_each_pipe(i915, pipe) 1677 1677 + else if (DISPLAY_VER(display) >= 11) { 1678 1678 + for_each_pipe(display, pipe) 1722 1679 display_runtime->num_scalers[pipe] = 2; 1723 1723 - } else if (DISPLAY_VER(i915) >= 9) { 1680 1680 + } else if (DISPLAY_VER(display) >= 9) { 1724 1681 display_runtime->num_scalers[PIPE_A] = 2; 1725 1682 display_runtime->num_scalers[PIPE_B] = 2; 1726 1683 display_runtime->num_scalers[PIPE_C] = 1; 1727 1684 } 1728 1685 1729 1729 - if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) 1730 1730 - for_each_pipe(i915, pipe) 1686 1686 + if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) 1687 1687 + for_each_pipe(display, pipe) 1731 1688 display_runtime->num_sprites[pipe] = 4; 1732 1732 - else if (DISPLAY_VER(i915) >= 11) 1733 1733 - for_each_pipe(i915, pipe) 1689 1689 + else if (DISPLAY_VER(display) >= 11) 1690 1690 + for_each_pipe(display, pipe) 1734 1691 display_runtime->num_sprites[pipe] = 6; 1735 1735 - else if (DISPLAY_VER(i915) == 10) 1736 1736 - for_each_pipe(i915, pipe) 1692 1692 + else if (DISPLAY_VER(display) == 10) 1693 1693 + for_each_pipe(display, pipe) 1737 1694 display_runtime->num_sprites[pipe] = 3; 1738 1738 - else if (IS_BROXTON(i915)) { 1695 1695 + else if (display->platform.broxton) { 1739 1696 /* 1740 1697 * Skylake and Broxton currently don't expose the topmost plane as its 1741 1698 * use is exclusive with the legacy cursor and we only want to expose ··· 1748 1705 display_runtime->num_sprites[PIPE_A] = 2; 1749 1706 display_runtime->num_sprites[PIPE_B] = 2; 1750 1707 display_runtime->num_sprites[PIPE_C] = 1; 1751 1751 - } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 1752 1752 - for_each_pipe(i915, pipe) 1708 1708 + } else if (display->platform.valleyview || display->platform.cherryview) { 1709 1709 + for_each_pipe(display, pipe) 1753 1710 display_runtime->num_sprites[pipe] = 2; 1754 1754 - } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) { 1755 1755 - for_each_pipe(i915, pipe) 1711 1711 + } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) { 1712 1712 + for_each_pipe(display, pipe) 1756 1713 display_runtime->num_sprites[pipe] = 1; 1757 1714 } 1758 1715 1759 1759 - if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) && 1760 1760 - !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) { 1761 1761 - drm_info(&i915->drm, "Display not present, disabling\n"); 1716 1716 + if ((display->platform.dgfx || DISPLAY_VER(display) >= 14) && 1717 1717 + !(intel_de_read(display, GU_CNTL_PROTECTED) & DEPRESENT)) { 1718 1718 + drm_info(display->drm, "Display not present, disabling\n"); 1762 1719 goto display_fused_off; 1763 1720 } 1764 1721 1765 1765 - if (IS_DISPLAY_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) { 1766 1766 - u32 fuse_strap = intel_de_read(i915, FUSE_STRAP); 1767 1767 - u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP); 1722 1722 + if (IS_DISPLAY_VER(display, 7, 8) && HAS_PCH_SPLIT(i915)) { 1723 1723 + u32 fuse_strap = intel_de_read(display, FUSE_STRAP); 1724 1724 + u32 sfuse_strap = intel_de_read(display, SFUSE_STRAP); 1768 1725 1769 1726 /* 1770 1727 * SFUSE_STRAP is supposed to have a bit signalling the display ··· 1779 1736 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED || 1780 1737 (HAS_PCH_CPT(i915) && 1781 1738 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) { 1782 1782 - drm_info(&i915->drm, 1739 1739 + drm_info(display->drm, 1783 1740 "Display fused off, disabling\n"); 1784 1741 goto display_fused_off; 1785 1742 } else if (fuse_strap & IVB_PIPE_C_DISABLE) { 1786 1786 - drm_info(&i915->drm, "PipeC fused off\n"); 1743 1743 + drm_info(display->drm, "PipeC fused off\n"); 1787 1744 display_runtime->pipe_mask &= ~BIT(PIPE_C); 1788 1745 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); 1789 1746 } 1790 1790 - } else if (DISPLAY_VER(i915) >= 9) { 1791 1791 - u32 dfsm = intel_de_read(i915, SKL_DFSM); 1747 1747 + } else if (DISPLAY_VER(display) >= 9) { 1748 1748 + u32 dfsm = intel_de_read(display, SKL_DFSM); 1792 1749 1793 1750 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) { 1794 1751 display_runtime->pipe_mask &= ~BIT(PIPE_A); ··· 1806 1763 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C); 1807 1764 } 1808 1765 1809 1809 - if (DISPLAY_VER(i915) >= 12 && 1766 1766 + if (DISPLAY_VER(display) >= 12 && 1810 1767 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) { 1811 1768 display_runtime->pipe_mask &= ~BIT(PIPE_D); 1812 1769 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); ··· 1819 1776 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE) 1820 1777 display_runtime->has_hdcp = 0; 1821 1778 1822 1822 - if (IS_DG2(i915) || DISPLAY_VER(i915) < 13) { 1779 1779 + if (display->platform.dg2 || DISPLAY_VER(display) < 13) { 1823 1780 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE) 1824 1781 display_runtime->fbc_mask = 0; 1825 1782 } 1826 1783 1827 1827 - if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 1784 1784 + if (DISPLAY_VER(display) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) 1828 1785 display_runtime->has_dmc = 0; 1829 1786 1830 1830 - if (IS_DISPLAY_VER(i915, 10, 12) && 1787 1787 + if (IS_DISPLAY_VER(display, 10, 12) && 1831 1788 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE)) 1832 1789 display_runtime->has_dsc = 0; 1833 1790 ··· 1836 1793 display_runtime->has_dbuf_overlap_detection = false; 1837 1794 } 1838 1795 1839 1839 - if (DISPLAY_VER(i915) >= 20) { 1840 1840 - u32 cap = intel_de_read(i915, XE2LPD_DE_CAP); 1796 1796 + if (DISPLAY_VER(display) >= 20) { 1797 1797 + u32 cap = intel_de_read(display, XE2LPD_DE_CAP); 1841 1798 1842 1799 if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) == 1843 1800 XE2LPD_DE_CAP_DSC_REMOVED) ··· 1845 1802 1846 1803 if (REG_FIELD_GET(XE2LPD_DE_CAP_SCALER_MASK, cap) == 1847 1804 XE2LPD_DE_CAP_SCALER_SINGLE) { 1848 1848 - for_each_pipe(i915, pipe) 1805 1805 + for_each_pipe(display, pipe) 1849 1806 if (display_runtime->num_scalers[pipe]) 1850 1807 display_runtime->num_scalers[pipe] = 1; 1851 1808 } 1852 1809 } 1853 1810 1854 1854 - if (DISPLAY_VER(i915) >= 30) 1811 1811 + if (DISPLAY_VER(display) >= 30) 1855 1812 display_runtime->edp_typec_support = 1856 1813 intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC; 1857 1814 1858 1815 display_runtime->rawclk_freq = intel_read_rawclk(display); 1859 1859 - drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq); 1816 1816 + drm_dbg_kms(display->drm, "rawclk rate: %d kHz\n", 1817 1817 + display_runtime->rawclk_freq); 1860 1818 1861 1819 return; 1862 1820 ··· 1865 1821 memset(display_runtime, 0, sizeof(*display_runtime)); 1866 1822 } 1867 1823 1868 1868 - void intel_display_device_info_runtime_init(struct drm_i915_private *i915) 1824 1824 + void intel_display_device_info_runtime_init(struct intel_display *display) 1869 1825 { 1870 1870 - if (HAS_DISPLAY(i915)) 1871 1871 - __intel_display_device_info_runtime_init(i915); 1826 1826 + if (HAS_DISPLAY(display)) 1827 1827 + __intel_display_device_info_runtime_init(display); 1872 1828 1873 1829 /* Display may have been disabled by runtime init */ 1874 1874 - if (!HAS_DISPLAY(i915)) { 1875 1875 - i915->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); 1876 1876 - i915->display.info.__device_info = &no_display; 1830 1830 + if (!HAS_DISPLAY(display)) { 1831 1831 + display->drm->driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); 1832 1832 + display->info.__device_info = &no_display; 1877 1833 } 1878 1834 1879 1835 /* Disable nuclear pageflip by default on pre-g4x */ 1880 1880 - if (!i915->display.params.nuclear_pageflip && 1881 1881 - DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) 1882 1882 - i915->drm.driver_features &= ~DRIVER_ATOMIC; 1836 1836 + if (!display->params.nuclear_pageflip && 1837 1837 + DISPLAY_VER(display) < 5 && !display->platform.g4x) 1838 1838 + display->drm->driver_features &= ~DRIVER_ATOMIC; 1883 1839 } 1884 1840 1885 1841 void intel_display_device_info_print(const struct intel_display_device_info *info, ··· 1916 1872 * Disabling display means taking over the display hardware, putting it to 1917 1873 * sleep, and preventing connectors from being connected via any means. 1918 1874 */ 1919 1919 - bool intel_display_device_enabled(struct drm_i915_private *i915) 1875 1875 + bool intel_display_device_enabled(struct intel_display *display) 1920 1876 { 1921 1921 - struct intel_display *display = &i915->display; 1922 1922 - 1923 1877 /* Only valid when HAS_DISPLAY() is true */ 1924 1878 drm_WARN_ON(display->drm, !HAS_DISPLAY(display)); 1925 1879

+81 -74

drivers/gpu/drm/i915/display/intel_display_device.h

reviewed

··· 12 12 #include "intel_display_conversion.h" 13 13 #include "intel_display_limits.h" 14 14 15 15 - struct drm_i915_private; 16 15 struct drm_printer; 16 16 + struct intel_display; 17 17 + struct pci_dev; 17 18 18 19 /* 19 20 * Display platforms and subplatforms. Keep platforms in display version based ··· 22 21 * platform. 23 22 */ 24 23 #define INTEL_DISPLAY_PLATFORMS(func) \ 24 24 + /* Platform group aliases */ \ 25 25 + func(g4x) /* g45 and gm45 */ \ 26 26 + func(mobile) /* mobile platforms */ \ 27 27 + func(dgfx) /* discrete graphics */ \ 25 28 /* Display ver 2 */ \ 26 29 func(i830) \ 27 30 func(i845g) \ ··· 43 38 func(i965gm) \ 44 39 func(g45) \ 45 40 func(gm45) \ 46 46 - func(g4x) /* group alias for g45 and gm45 */ \ 47 41 /* Display ver 5 */ \ 48 42 func(ironlake) \ 49 43 /* Display ver 6 */ \ ··· 140 136 func(overlay_needs_physical); \ 141 137 func(supports_tv); 142 138 143 143 - #define HAS_4TILE(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) 144 144 - #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) 145 145 - #define HAS_BIGJOINER(i915) (DISPLAY_VER(i915) >= 11 && HAS_DSC(i915)) 146 146 - #define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl) 147 147 - #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash) 148 148 - #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13)) 149 149 - #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915)) 150 150 - #define HAS_DBUF_OVERLAP_DETECTION(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dbuf_overlap_detection) 151 151 - #define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi) 152 152 - #define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0) 153 153 - #define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc) 154 154 - #define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915)) 155 155 - #define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst) 156 156 - #define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) 157 157 - #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13) 158 158 - #define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb) 159 159 - #define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc) 160 160 - #define HAS_DSC_MST(__i915) (DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915)) 161 161 - #define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0) 162 162 - #define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg) 163 163 - #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) >= 3) 164 164 - #define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4) 165 165 - #define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915)) 166 166 - #define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch) 167 167 - #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) 168 168 - #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc) 169 169 - #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915)) 170 170 - #define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12) 171 171 - #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10)) 172 172 - #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) 173 173 - #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) 174 174 - #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay) 175 175 - #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr) 176 176 - #define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking) 177 177 - #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) 178 178 - #define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915) && !IS_GEMINILAKE(i915)) 179 179 - #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \ 180 180 - BIT(trans)) != 0) 181 181 - #define HAS_UNCOMPRESSED_JOINER(i915) (DISPLAY_VER(i915) >= 13) 182 182 - #define HAS_ULTRAJOINER(i915) ((DISPLAY_VER(i915) >= 20 || \ 183 183 - (IS_DGFX(i915) && DISPLAY_VER(i915) == 14)) && \ 184 184 - HAS_DSC(i915)) 185 185 - #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) 186 186 - #define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13) 187 187 - #define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20) 188 188 - #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) 189 189 - #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) 190 190 - #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) 191 191 - #define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv) 139 139 + #define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) 140 140 + #define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5) 141 141 + #define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display)) 142 142 + #define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl) 143 143 + #define HAS_CDCLK_SQUASH(__display) (DISPLAY_INFO(__display)->has_cdclk_squash) 144 144 + #define HAS_CUR_FBC(__display) (!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13)) 145 145 + #define HAS_D12_PLANE_MINIMIZATION(__display) ((__display)->platform.rocketlake || (__display)->platform.alderlake_s) 146 146 + #define HAS_DBUF_OVERLAP_DETECTION(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dbuf_overlap_detection) 147 147 + #define HAS_DDI(__display) (DISPLAY_INFO(__display)->has_ddi) 148 148 + #define HAS_DISPLAY(__display) (DISPLAY_RUNTIME_INFO(__display)->pipe_mask != 0) 149 149 + #define HAS_DMC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dmc) 150 150 + #define HAS_DMC_WAKELOCK(__display) (DISPLAY_VER(__display) >= 20) 151 151 + #define HAS_DOUBLE_BUFFERED_M_N(__display) (DISPLAY_VER(__display) >= 9 || (__display)->platform.broadwell) 152 152 + #define HAS_DOUBLE_WIDE(__display) (DISPLAY_VER(__display) < 4) 153 153 + #define HAS_DP_MST(__display) (DISPLAY_INFO(__display)->has_dp_mst) 154 154 + #define HAS_DP20(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) 155 155 + #define HAS_DPT(__display) (DISPLAY_VER(__display) >= 13) 156 156 + #define HAS_DSB(__display) (DISPLAY_INFO(__display)->has_dsb) 157 157 + #define HAS_DSC(__display) (DISPLAY_RUNTIME_INFO(__display)->has_dsc) 158 158 + #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) 159 159 + #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) 160 160 + #define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg) 161 161 + #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3) 162 162 + #define HAS_GMBUS_IRQ(__display) (DISPLAY_VER(__display) >= 4) 163 163 + #define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake) 164 164 + #define HAS_GMCH(__display) (DISPLAY_INFO(__display)->has_gmch) 165 165 + #define HAS_HW_SAGV_WM(__display) (DISPLAY_VER(__display) >= 13 && !(__display)->platform.dgfx) 166 166 + #define HAS_IPC(__display) (DISPLAY_INFO(__display)->has_ipc) 167 167 + #define HAS_IPS(__display) ((__display)->platform.haswell_ult || (__display)->platform.broadwell) 168 168 + #define HAS_LRR(__display) (DISPLAY_VER(__display) >= 12) 169 169 + #define HAS_LSPCON(__display) (IS_DISPLAY_VER(__display, 9, 10)) 170 170 + #define HAS_MBUS_JOINING(__display) ((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14) 171 171 + #define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12) 172 172 + #define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay) 173 173 + #define HAS_PSR(__display) (DISPLAY_INFO(__display)->has_psr) 174 174 + #define HAS_PSR_HW_TRACKING(__display) (DISPLAY_INFO(__display)->has_psr_hw_tracking) 175 175 + #define HAS_PSR2_SEL_FETCH(__display) (DISPLAY_VER(__display) >= 12) 176 176 + #define HAS_SAGV(__display) (DISPLAY_VER(__display) >= 9 && \ 177 177 + !(__display)->platform.broxton && !(__display)->platform.geminilake) 178 178 + #define HAS_TRANSCODER(__display, trans) ((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \ 179 179 + BIT(trans)) != 0) 180 180 + #define HAS_UNCOMPRESSED_JOINER(__display) (DISPLAY_VER(__display) >= 13) 181 181 + #define HAS_ULTRAJOINER(__display) ((DISPLAY_VER(__display) >= 20 || \ 182 182 + ((__display)->platform.dgfx && DISPLAY_VER(__display) == 14)) && \ 183 183 + HAS_DSC(__display)) 184 184 + #define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11) 185 185 + #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13) 186 186 + #define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20) 187 187 + #define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask)) 188 188 + #define I915_HAS_HOTPLUG(__display) (DISPLAY_INFO(__display)->has_hotplug) 189 189 + #define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)->overlay_needs_physical) 190 190 + #define SUPPORTS_TV(__display) (DISPLAY_INFO(__display)->supports_tv) 192 191 193 192 /* Check that device has a display IP version within the specific range. */ 194 194 - #define IS_DISPLAY_VERx100(__i915, from, until) ( \ 193 193 + #define IS_DISPLAY_VERx100(__display, from, until) ( \ 195 194 BUILD_BUG_ON_ZERO((from) < 200) + \ 196 196 - (DISPLAY_VERx100(__i915) >= (from) && \ 197 197 - DISPLAY_VERx100(__i915) <= (until))) 195 195 + (DISPLAY_VERx100(__display) >= (from) && \ 196 196 + DISPLAY_VERx100(__display) <= (until))) 198 197 199 198 /* 200 199 * Check if a device has a specific IP version as well as a stepping within the ··· 208 201 * hardware fix is present and the software workaround is no longer necessary. 209 202 * E.g., 210 203 * 211 211 - * IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_A0, STEP_B2) 212 212 - * IS_DISPLAY_VERx100_STEP(i915, 1400, STEP_C0, STEP_FOREVER) 204 204 + * IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B2) 205 205 + * IS_DISPLAY_VERx100_STEP(display, 1400, STEP_C0, STEP_FOREVER) 213 206 * 214 207 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper 215 208 * stepping bound for the specified IP version. 216 209 */ 217 217 - #define IS_DISPLAY_VERx100_STEP(__i915, ipver, from, until) \ 218 218 - (IS_DISPLAY_VERx100((__i915), (ipver), (ipver)) && \ 219 219 - IS_DISPLAY_STEP((__i915), (from), (until))) 210 210 + #define IS_DISPLAY_VERx100_STEP(__display, ipver, from, until) \ 211 211 + (IS_DISPLAY_VERx100((__display), (ipver), (ipver)) && \ 212 212 + IS_DISPLAY_STEP((__display), (from), (until))) 220 213 221 221 - #define DISPLAY_INFO(i915) (__to_intel_display(i915)->info.__device_info) 222 222 - #define DISPLAY_RUNTIME_INFO(i915) (&__to_intel_display(i915)->info.__runtime_info) 214 214 + #define DISPLAY_INFO(__display) (__to_intel_display(__display)->info.__device_info) 215 215 + #define DISPLAY_RUNTIME_INFO(__display) (&__to_intel_display(__display)->info.__runtime_info) 223 216 224 224 - #define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) 225 225 - #define DISPLAY_VERx100(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver * 100 + \ 226 226 - DISPLAY_RUNTIME_INFO(i915)->ip.rel) 227 227 - #define IS_DISPLAY_VER(i915, from, until) \ 228 228 - (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 217 217 + #define DISPLAY_VER(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver) 218 218 + #define DISPLAY_VERx100(__display) (DISPLAY_RUNTIME_INFO(__display)->ip.ver * 100 + \ 219 219 + DISPLAY_RUNTIME_INFO(__display)->ip.rel) 220 220 + #define IS_DISPLAY_VER(__display, from, until) \ 221 221 + (DISPLAY_VER(__display) >= (from) && DISPLAY_VER(__display) <= (until)) 229 222 230 230 - #define INTEL_DISPLAY_STEP(__i915) (DISPLAY_RUNTIME_INFO(__i915)->step) 223 223 + #define INTEL_DISPLAY_STEP(__display) (DISPLAY_RUNTIME_INFO(__display)->step) 231 224 232 232 - #define IS_DISPLAY_STEP(__i915, since, until) \ 233 233 - (drm_WARN_ON(__to_intel_display(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 234 234 - INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until)) 225 225 + #define IS_DISPLAY_STEP(__display, since, until) \ 226 226 + (drm_WARN_ON(__to_intel_display(__display)->drm, INTEL_DISPLAY_STEP(__display) == STEP_NONE), \ 227 227 + INTEL_DISPLAY_STEP(__display) >= (since) && INTEL_DISPLAY_STEP(__display) < (until)) 235 228 236 229 struct intel_display_runtime_info { 237 230 struct intel_display_ip_ver { ··· 290 283 } color; 291 284 }; 292 285 293 293 - bool intel_display_device_enabled(struct drm_i915_private *i915); 294 294 - void intel_display_device_probe(struct drm_i915_private *i915); 295 295 - void intel_display_device_remove(struct drm_i915_private *i915); 296 296 - void intel_display_device_info_runtime_init(struct drm_i915_private *i915); 286 286 + bool intel_display_device_enabled(struct intel_display *display); 287 287 + struct intel_display *intel_display_device_probe(struct pci_dev *pdev); 288 288 + void intel_display_device_remove(struct intel_display *display); 289 289 + void intel_display_device_info_runtime_init(struct intel_display *display); 297 290 298 291 void intel_display_device_info_print(const struct intel_display_device_info *info, 299 292 const struct intel_display_runtime_info *runtime,

+159 -139

drivers/gpu/drm/i915/display/intel_display_driver.c

reviewed

··· 80 80 return false; 81 81 } 82 82 83 83 - void intel_display_driver_init_hw(struct drm_i915_private *i915) 83 83 + void intel_display_driver_init_hw(struct intel_display *display) 84 84 { 85 85 - struct intel_display *display = &i915->display; 85 85 + struct drm_i915_private *i915 = to_i915(display->drm); 86 86 struct intel_cdclk_state *cdclk_state; 87 87 88 88 - if (!HAS_DISPLAY(i915)) 88 88 + if (!HAS_DISPLAY(display)) 89 89 return; 90 90 91 91 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); ··· 112 112 .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, 113 113 }; 114 114 115 115 - static void intel_mode_config_init(struct drm_i915_private *i915) 115 115 + static void intel_mode_config_init(struct intel_display *display) 116 116 { 117 117 - struct drm_mode_config *mode_config = &i915->drm.mode_config; 117 117 + struct drm_mode_config *mode_config = &display->drm->mode_config; 118 118 119 119 - drm_mode_config_init(&i915->drm); 120 120 - INIT_LIST_HEAD(&i915->display.global.obj_list); 119 119 + drm_mode_config_init(display->drm); 120 120 + INIT_LIST_HEAD(&display->global.obj_list); 121 121 122 122 mode_config->min_width = 0; 123 123 mode_config->min_height = 0; ··· 128 128 mode_config->funcs = &intel_mode_funcs; 129 129 mode_config->helper_private = &intel_mode_config_funcs; 130 130 131 131 - mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915); 131 131 + mode_config->async_page_flip = HAS_ASYNC_FLIPS(display); 132 132 133 133 /* 134 134 * Maximum framebuffer dimensions, chosen to match 135 135 * the maximum render engine surface size on gen4+. 136 136 */ 137 137 - if (DISPLAY_VER(i915) >= 7) { 137 137 + if (DISPLAY_VER(display) >= 7) { 138 138 mode_config->max_width = 16384; 139 139 mode_config->max_height = 16384; 140 140 - } else if (DISPLAY_VER(i915) >= 4) { 140 140 + } else if (DISPLAY_VER(display) >= 4) { 141 141 mode_config->max_width = 8192; 142 142 mode_config->max_height = 8192; 143 143 - } else if (DISPLAY_VER(i915) == 3) { 143 143 + } else if (DISPLAY_VER(display) == 3) { 144 144 mode_config->max_width = 4096; 145 145 mode_config->max_height = 4096; 146 146 } else { ··· 148 148 mode_config->max_height = 2048; 149 149 } 150 150 151 151 - if (IS_I845G(i915) || IS_I865G(i915)) { 152 152 - mode_config->cursor_width = IS_I845G(i915) ? 64 : 512; 151 151 + if (display->platform.i845g || display->platform.i865g) { 152 152 + mode_config->cursor_width = display->platform.i845g ? 64 : 512; 153 153 mode_config->cursor_height = 1023; 154 154 - } else if (IS_I830(i915) || IS_I85X(i915) || 155 155 - IS_I915G(i915) || IS_I915GM(i915)) { 154 154 + } else if (display->platform.i830 || display->platform.i85x || 155 155 + display->platform.i915g || display->platform.i915gm) { 156 156 mode_config->cursor_width = 64; 157 157 mode_config->cursor_height = 64; 158 158 } else { ··· 161 161 } 162 162 } 163 163 164 164 - static void intel_mode_config_cleanup(struct drm_i915_private *i915) 164 164 + static void intel_mode_config_cleanup(struct intel_display *display) 165 165 { 166 166 + struct drm_i915_private *i915 = to_i915(display->drm); 167 167 + 166 168 intel_atomic_global_obj_cleanup(i915); 167 167 - drm_mode_config_cleanup(&i915->drm); 169 169 + drm_mode_config_cleanup(display->drm); 168 170 } 169 171 170 170 - static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) 172 172 + static void intel_plane_possible_crtcs_init(struct intel_display *display) 171 173 { 172 172 - struct intel_display *display = &dev_priv->display; 173 174 struct intel_plane *plane; 174 175 175 175 - for_each_intel_plane(&dev_priv->drm, plane) { 176 176 + for_each_intel_plane(display->drm, plane) { 176 177 struct intel_crtc *crtc = intel_crtc_for_pipe(display, 177 178 plane->pipe); 178 179 ··· 181 180 } 182 181 } 183 182 184 184 - void intel_display_driver_early_probe(struct drm_i915_private *i915) 183 183 + void intel_display_driver_early_probe(struct intel_display *display) 185 184 { 186 186 - if (!HAS_DISPLAY(i915)) 185 185 + struct drm_i915_private *i915 = to_i915(display->drm); 186 186 + 187 187 + if (!HAS_DISPLAY(display)) 187 188 return; 188 189 189 189 - spin_lock_init(&i915->display.fb_tracking.lock); 190 190 - mutex_init(&i915->display.backlight.lock); 191 191 - mutex_init(&i915->display.audio.mutex); 192 192 - mutex_init(&i915->display.wm.wm_mutex); 193 193 - mutex_init(&i915->display.pps.mutex); 194 194 - mutex_init(&i915->display.hdcp.hdcp_mutex); 190 190 + spin_lock_init(&display->fb_tracking.lock); 191 191 + mutex_init(&display->backlight.lock); 192 192 + mutex_init(&display->audio.mutex); 193 193 + mutex_init(&display->wm.wm_mutex); 194 194 + mutex_init(&display->pps.mutex); 195 195 + mutex_init(&display->hdcp.hdcp_mutex); 195 196 196 197 intel_display_irq_init(i915); 197 198 intel_dkl_phy_init(i915); 198 198 - intel_color_init_hooks(&i915->display); 199 199 - intel_init_cdclk_hooks(&i915->display); 199 199 + intel_color_init_hooks(display); 200 200 + intel_init_cdclk_hooks(display); 200 201 intel_audio_hooks_init(i915); 201 202 intel_dpll_init_clock_hook(i915); 202 203 intel_init_display_hooks(i915); 203 204 intel_fdi_init_hook(i915); 204 204 - intel_dmc_wl_init(&i915->display); 205 205 + intel_dmc_wl_init(display); 205 206 } 206 207 207 208 /* part #1: call before irq install */ 208 208 - int intel_display_driver_probe_noirq(struct drm_i915_private *i915) 209 209 + int intel_display_driver_probe_noirq(struct intel_display *display) 209 210 { 210 210 - struct intel_display *display = &i915->display; 211 211 + struct drm_i915_private *i915 = to_i915(display->drm); 211 212 int ret; 212 213 213 214 if (i915_inject_probe_failure(i915)) 214 215 return -ENODEV; 215 216 216 216 - if (HAS_DISPLAY(i915)) { 217 217 - ret = drm_vblank_init(&i915->drm, 218 218 - INTEL_NUM_PIPES(i915)); 217 217 + if (HAS_DISPLAY(display)) { 218 218 + ret = drm_vblank_init(display->drm, 219 219 + INTEL_NUM_PIPES(display)); 219 220 if (ret) 220 221 return ret; 221 222 } ··· 229 226 goto cleanup_bios; 230 227 231 228 /* FIXME: completely on the wrong abstraction layer */ 232 232 - ret = intel_power_domains_init(i915); 229 229 + ret = intel_power_domains_init(display); 233 230 if (ret < 0) 234 231 goto cleanup_vga; 235 232 236 233 intel_pmdemand_init_early(i915); 237 234 238 238 - intel_power_domains_init_hw(i915, false); 235 235 + intel_power_domains_init_hw(display, false); 239 236 240 240 - if (!HAS_DISPLAY(i915)) 237 237 + if (!HAS_DISPLAY(display)) 241 238 return 0; 242 239 243 240 intel_dmc_init(display); 244 241 245 245 - i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); 246 246 - i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | 242 242 + display->wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); 243 243 + display->wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | 247 244 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); 245 245 + display->wq.cleanup = alloc_workqueue("i915_cleanup", WQ_HIGHPRI, 0); 248 246 249 249 - intel_mode_config_init(i915); 247 247 + intel_mode_config_init(display); 250 248 251 249 ret = intel_cdclk_init(display); 252 250 if (ret) ··· 277 273 278 274 cleanup_vga_client_pw_domain_dmc: 279 275 intel_dmc_fini(display); 280 280 - intel_power_domains_driver_remove(i915); 276 276 + intel_power_domains_driver_remove(display); 281 277 cleanup_vga: 282 278 intel_vga_unregister(display); 283 279 cleanup_bios: ··· 286 282 return ret; 287 283 } 288 284 289 289 - static void set_display_access(struct drm_i915_private *i915, 285 285 + static void set_display_access(struct intel_display *display, 290 286 bool any_task_allowed, 291 287 struct task_struct *allowed_task) 292 288 { ··· 294 290 int err; 295 291 296 292 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, err) { 297 297 - err = drm_modeset_lock_all_ctx(&i915->drm, &ctx); 293 293 + err = drm_modeset_lock_all_ctx(display->drm, &ctx); 298 294 if (err) 299 295 continue; 300 296 301 301 - i915->display.access.any_task_allowed = any_task_allowed; 302 302 - i915->display.access.allowed_task = allowed_task; 297 297 + display->access.any_task_allowed = any_task_allowed; 298 298 + display->access.allowed_task = allowed_task; 303 299 } 304 300 305 305 - drm_WARN_ON(&i915->drm, err); 301 301 + drm_WARN_ON(display->drm, err); 306 302 } 307 303 308 304 /** 309 305 * intel_display_driver_enable_user_access - Enable display HW access for all threads 310 310 - * @i915: i915 device instance 306 306 + * @display: display device instance 311 307 * 312 308 * Enable the display HW access for all threads. Examples for such accesses 313 309 * are modeset commits and connector probing. ··· 315 311 * This function should be called during driver loading and system resume once 316 312 * all the HW initialization steps are done. 317 313 */ 318 318 - void intel_display_driver_enable_user_access(struct drm_i915_private *i915) 314 314 + void intel_display_driver_enable_user_access(struct intel_display *display) 319 315 { 320 320 - set_display_access(i915, true, NULL); 316 316 + struct drm_i915_private *i915 = to_i915(display->drm); 317 317 + 318 318 + set_display_access(display, true, NULL); 321 319 322 320 intel_hpd_enable_detection_work(i915); 323 321 } 324 322 325 323 /** 326 324 * intel_display_driver_disable_user_access - Disable display HW access for user threads 327 327 - * @i915: i915 device instance 325 325 + * @display: display device instance 328 326 * 329 327 * Disable the display HW access for user threads. Examples for such accesses 330 328 * are modeset commits and connector probing. For the current thread the ··· 341 335 * This function should be called during driver loading/unloading and system 342 336 * suspend/shutdown before starting the HW init/deinit programming. 343 337 */ 344 344 - void intel_display_driver_disable_user_access(struct drm_i915_private *i915) 338 338 + void intel_display_driver_disable_user_access(struct intel_display *display) 345 339 { 340 340 + struct drm_i915_private *i915 = to_i915(display->drm); 341 341 + 346 342 intel_hpd_disable_detection_work(i915); 347 343 348 348 - set_display_access(i915, false, current); 344 344 + set_display_access(display, false, current); 349 345 } 350 346 351 347 /** 352 348 * intel_display_driver_suspend_access - Suspend display HW access for all threads 353 353 - * @i915: i915 device instance 349 349 + * @display: display device instance 354 350 * 355 351 * Disable the display HW access for all threads. Examples for such accesses 356 352 * are modeset commits and connector probing. This call should be either ··· 362 354 * This function should be called during driver unloading and system 363 355 * suspend/shutdown after completing the HW deinit programming. 364 356 */ 365 365 - void intel_display_driver_suspend_access(struct drm_i915_private *i915) 357 357 + void intel_display_driver_suspend_access(struct intel_display *display) 366 358 { 367 367 - set_display_access(i915, false, NULL); 359 359 + set_display_access(display, false, NULL); 368 360 } 369 361 370 362 /** 371 363 * intel_display_driver_resume_access - Resume display HW access for the resume thread 372 372 - * @i915: i915 device instance 364 364 + * @display: display device instance 373 365 * 374 366 * Enable the display HW access for the current resume thread, keeping the 375 367 * access disabled for all other (user) threads. Examples for such accesses ··· 381 373 * This function should be called during system resume before starting the HW 382 374 * init steps. 383 375 */ 384 384 - void intel_display_driver_resume_access(struct drm_i915_private *i915) 376 376 + void intel_display_driver_resume_access(struct intel_display *display) 385 377 { 386 386 - set_display_access(i915, false, current); 378 378 + set_display_access(display, false, current); 387 379 } 388 380 389 381 /** 390 382 * intel_display_driver_check_access - Check if the current thread has disaplay HW access 391 391 - * @i915: i915 device instance 383 383 + * @display: display device instance 392 384 * 393 385 * Check whether the current thread has display HW access, print a debug 394 386 * message if it doesn't. Such accesses are modeset commits and connector ··· 397 389 * Returns %true if the current thread has display HW access, %false 398 390 * otherwise. 399 391 */ 400 400 - bool intel_display_driver_check_access(struct drm_i915_private *i915) 392 392 + bool intel_display_driver_check_access(struct intel_display *display) 401 393 { 402 394 char comm[TASK_COMM_LEN]; 403 395 char current_task[TASK_COMM_LEN + 16]; 404 396 char allowed_task[TASK_COMM_LEN + 16] = "none"; 405 397 406 406 - if (i915->display.access.any_task_allowed || 407 407 - i915->display.access.allowed_task == current) 398 398 + if (display->access.any_task_allowed || 399 399 + display->access.allowed_task == current) 408 400 return true; 409 401 410 402 snprintf(current_task, sizeof(current_task), "%s[%d]", 411 403 get_task_comm(comm, current), 412 404 task_pid_vnr(current)); 413 405 414 414 - if (i915->display.access.allowed_task) 406 406 + if (display->access.allowed_task) 415 407 snprintf(allowed_task, sizeof(allowed_task), "%s[%d]", 416 416 - get_task_comm(comm, i915->display.access.allowed_task), 417 417 - task_pid_vnr(i915->display.access.allowed_task)); 408 408 + get_task_comm(comm, display->access.allowed_task), 409 409 + task_pid_vnr(display->access.allowed_task)); 418 410 419 419 - drm_dbg_kms(&i915->drm, 411 411 + drm_dbg_kms(display->drm, 420 412 "Reject display access from task %s (allowed to %s)\n", 421 413 current_task, allowed_task); 422 414 ··· 424 416 } 425 417 426 418 /* part #2: call after irq install, but before gem init */ 427 427 - int intel_display_driver_probe_nogem(struct drm_i915_private *i915) 419 419 + int intel_display_driver_probe_nogem(struct intel_display *display) 428 420 { 429 429 - struct intel_display *display = &i915->display; 430 430 - struct drm_device *dev = display->drm; 421 421 + struct drm_i915_private *i915 = to_i915(display->drm); 431 422 enum pipe pipe; 432 423 int ret; 433 424 434 434 - if (!HAS_DISPLAY(i915)) 425 425 + if (!HAS_DISPLAY(display)) 435 426 return 0; 436 427 437 428 intel_wm_init(i915); ··· 441 434 442 435 intel_gmbus_setup(display); 443 436 444 444 - drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", 445 445 - INTEL_NUM_PIPES(i915), 446 446 - INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); 437 437 + drm_dbg_kms(display->drm, "%d display pipe%s available.\n", 438 438 + INTEL_NUM_PIPES(display), 439 439 + INTEL_NUM_PIPES(display) > 1 ? "s" : ""); 447 440 448 448 - for_each_pipe(i915, pipe) { 441 441 + for_each_pipe(display, pipe) { 449 442 ret = intel_crtc_init(i915, pipe); 450 443 if (ret) 451 444 goto err_mode_config; 452 445 } 453 446 454 454 - intel_plane_possible_crtcs_init(i915); 447 447 + intel_plane_possible_crtcs_init(display); 455 448 intel_shared_dpll_init(i915); 456 449 intel_fdi_pll_freq_update(i915); 457 450 458 451 intel_update_czclk(i915); 459 459 - intel_display_driver_init_hw(i915); 452 452 + intel_display_driver_init_hw(display); 460 453 intel_dpll_update_ref_clks(i915); 461 454 462 455 if (display->cdclk.max_cdclk_freq == 0) ··· 472 465 if (ret) 473 466 goto err_hdcp; 474 467 475 475 - intel_display_driver_disable_user_access(i915); 468 468 + intel_display_driver_disable_user_access(display); 476 469 477 477 - drm_modeset_lock_all(dev); 478 478 - intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx); 470 470 + drm_modeset_lock_all(display->drm); 471 471 + intel_modeset_setup_hw_state(i915, display->drm->mode_config.acquire_ctx); 479 472 intel_acpi_assign_connector_fwnodes(display); 480 480 - drm_modeset_unlock_all(dev); 473 473 + drm_modeset_unlock_all(display->drm); 481 474 482 482 - intel_initial_plane_config(i915); 475 475 + intel_initial_plane_config(display); 483 476 484 477 /* 485 478 * Make sure hardware watermarks really match the state we read out. 486 479 * Note that we need to do this after reconstructing the BIOS fb's 487 480 * since the watermark calculation done here will use pstate->fb. 488 481 */ 489 489 - if (!HAS_GMCH(i915)) 482 482 + if (!HAS_GMCH(display)) 490 483 ilk_wm_sanitize(i915); 491 484 492 485 return 0; ··· 494 487 err_hdcp: 495 488 intel_hdcp_component_fini(display); 496 489 err_mode_config: 497 497 - intel_mode_config_cleanup(i915); 490 490 + intel_mode_config_cleanup(display); 498 491 499 492 return ret; 500 493 } 501 494 502 495 /* part #3: call after gem init */ 503 503 - int intel_display_driver_probe(struct drm_i915_private *i915) 496 496 + int intel_display_driver_probe(struct intel_display *display) 504 497 { 505 505 - struct intel_display *display = &i915->display; 498 498 + struct drm_i915_private *i915 = to_i915(display->drm); 506 499 int ret; 507 500 508 508 - if (!HAS_DISPLAY(i915)) 501 501 + if (!HAS_DISPLAY(display)) 509 502 return 0; 510 503 511 504 /* ··· 521 514 * are already calculated and there is no assert_plane warnings 522 515 * during bootup. 523 516 */ 524 524 - ret = intel_initial_commit(&i915->drm); 517 517 + ret = intel_initial_commit(display->drm); 525 518 if (ret) 526 526 - drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret); 519 519 + drm_dbg_kms(display->drm, "Initial modeset failed, %d\n", ret); 527 520 528 528 - intel_overlay_setup(i915); 521 521 + intel_overlay_setup(display); 529 522 530 523 /* Only enable hotplug handling once the fbdev is fully set up. */ 531 524 intel_hpd_init(i915); ··· 535 528 return 0; 536 529 } 537 530 538 538 - void intel_display_driver_register(struct drm_i915_private *i915) 531 531 + void intel_display_driver_register(struct intel_display *display) 539 532 { 540 540 - struct intel_display *display = &i915->display; 541 541 - struct drm_printer p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, 533 533 + struct drm_i915_private *i915 = to_i915(display->drm); 534 534 + struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, 542 535 "i915 display info:"); 543 536 544 544 - if (!HAS_DISPLAY(i915)) 537 537 + if (!HAS_DISPLAY(display)) 545 538 return; 546 539 547 540 /* Must be done after probing outputs */ ··· 550 543 551 544 intel_audio_init(i915); 552 545 553 553 - intel_display_driver_enable_user_access(i915); 546 546 + intel_display_driver_enable_user_access(display); 554 547 555 548 intel_audio_register(i915); 556 549 ··· 561 554 * fbdev configuration, for which we use the 562 555 * fbdev->async_cookie. 563 556 */ 564 564 - drm_kms_helper_poll_init(&i915->drm); 557 557 + drm_kms_helper_poll_init(display->drm); 565 558 intel_hpd_poll_disable(i915); 566 559 567 560 intel_fbdev_setup(i915); 568 561 569 569 - intel_display_device_info_print(DISPLAY_INFO(i915), 570 570 - DISPLAY_RUNTIME_INFO(i915), &p); 562 562 + intel_display_device_info_print(DISPLAY_INFO(display), 563 563 + DISPLAY_RUNTIME_INFO(display), &p); 571 564 } 572 565 573 566 /* part #1: call before irq uninstall */ 574 574 - void intel_display_driver_remove(struct drm_i915_private *i915) 567 567 + void intel_display_driver_remove(struct intel_display *display) 575 568 { 576 576 - if (!HAS_DISPLAY(i915)) 569 569 + struct drm_i915_private *i915 = to_i915(display->drm); 570 570 + 571 571 + if (!HAS_DISPLAY(display)) 577 572 return; 578 573 579 579 - flush_workqueue(i915->display.wq.flip); 580 580 - flush_workqueue(i915->display.wq.modeset); 574 574 + flush_workqueue(display->wq.flip); 575 575 + flush_workqueue(display->wq.modeset); 576 576 + flush_workqueue(display->wq.cleanup); 581 577 582 578 /* 583 579 * MST topology needs to be suspended so we don't have any calls to ··· 591 581 } 592 582 593 583 /* part #2: call after irq uninstall */ 594 594 - void intel_display_driver_remove_noirq(struct drm_i915_private *i915) 584 584 + void intel_display_driver_remove_noirq(struct intel_display *display) 595 585 { 596 596 - struct intel_display *display = &i915->display; 586 586 + struct drm_i915_private *i915 = to_i915(display->drm); 597 587 598 598 - if (!HAS_DISPLAY(i915)) 588 588 + if (!HAS_DISPLAY(display)) 599 589 return; 600 590 601 601 - intel_display_driver_suspend_access(i915); 591 591 + intel_display_driver_suspend_access(display); 602 592 603 593 /* 604 594 * Due to the hpd irq storm handling the hotplug work can re-arm the ··· 613 603 614 604 intel_hdcp_component_fini(display); 615 605 616 616 - intel_mode_config_cleanup(i915); 606 606 + intel_mode_config_cleanup(display); 617 607 618 608 intel_dp_tunnel_mgr_cleanup(display); 619 609 620 620 - intel_overlay_cleanup(i915); 610 610 + intel_overlay_cleanup(display); 621 611 622 612 intel_gmbus_teardown(display); 623 613 624 624 - destroy_workqueue(i915->display.wq.flip); 625 625 - destroy_workqueue(i915->display.wq.modeset); 614 614 + destroy_workqueue(display->wq.flip); 615 615 + destroy_workqueue(display->wq.modeset); 616 616 + destroy_workqueue(display->wq.cleanup); 626 617 627 627 - intel_fbc_cleanup(&i915->display); 618 618 + intel_fbc_cleanup(display); 628 619 } 629 620 630 621 /* part #3: call after gem init */ 631 631 - void intel_display_driver_remove_nogem(struct drm_i915_private *i915) 622 622 + void intel_display_driver_remove_nogem(struct intel_display *display) 632 623 { 633 633 - struct intel_display *display = &i915->display; 634 634 - 635 624 intel_dmc_fini(display); 636 625 637 637 - intel_power_domains_driver_remove(i915); 626 626 + intel_power_domains_driver_remove(display); 638 627 639 628 intel_vga_unregister(display); 640 629 641 630 intel_bios_driver_remove(display); 642 631 } 643 632 644 644 - void intel_display_driver_unregister(struct drm_i915_private *i915) 633 633 + void intel_display_driver_unregister(struct intel_display *display) 645 634 { 646 646 - struct intel_display *display = &i915->display; 635 635 + struct drm_i915_private *i915 = to_i915(display->drm); 647 636 648 648 - if (!HAS_DISPLAY(i915)) 637 637 + if (!HAS_DISPLAY(display)) 649 638 return; 650 639 651 651 - drm_client_dev_unregister(&i915->drm); 640 640 + drm_client_dev_unregister(display->drm); 652 641 653 642 /* 654 643 * After flushing the fbdev (incl. a late async config which 655 644 * will have delayed queuing of a hotplug event), then flush 656 645 * the hotplug events. 657 646 */ 658 658 - drm_kms_helper_poll_fini(&i915->drm); 647 647 + drm_kms_helper_poll_fini(display->drm); 659 648 660 660 - intel_display_driver_disable_user_access(i915); 649 649 + intel_display_driver_disable_user_access(display); 661 650 662 651 intel_audio_deinit(i915); 663 652 664 664 - drm_atomic_helper_shutdown(&i915->drm); 653 653 + drm_atomic_helper_shutdown(display->drm); 665 654 666 655 acpi_video_unregister(); 667 656 intel_opregion_unregister(display); ··· 670 661 * turn all crtc's off, but do not adjust state 671 662 * This has to be paired with a call to intel_modeset_setup_hw_state. 672 663 */ 673 673 - int intel_display_driver_suspend(struct drm_i915_private *i915) 664 664 + int intel_display_driver_suspend(struct intel_display *display) 674 665 { 666 666 + struct drm_i915_private *i915 = to_i915(display->drm); 675 667 struct drm_atomic_state *state; 676 668 int ret; 677 669 678 678 - if (!HAS_DISPLAY(i915)) 670 670 + if (!HAS_DISPLAY(display)) 679 671 return 0; 680 672 681 681 - state = drm_atomic_helper_suspend(&i915->drm); 673 673 + state = drm_atomic_helper_suspend(display->drm); 682 674 ret = PTR_ERR_OR_ZERO(state); 683 675 if (ret) 684 684 - drm_err(&i915->drm, "Suspending crtc's failed with %i\n", 676 676 + drm_err(display->drm, "Suspending crtc's failed with %i\n", 685 677 ret); 686 678 else 687 687 - i915->display.restore.modeset_state = state; 679 679 + display->restore.modeset_state = state; 680 680 + 681 681 + /* ensure all DPT VMAs have been unpinned for intel_dpt_suspend() */ 682 682 + flush_workqueue(display->wq.cleanup); 683 683 + 684 684 + intel_dp_mst_suspend(i915); 685 685 + 688 686 return ret; 689 687 } 690 688 691 689 int 692 692 - __intel_display_driver_resume(struct drm_i915_private *i915, 690 690 + __intel_display_driver_resume(struct intel_display *display, 693 691 struct drm_atomic_state *state, 694 692 struct drm_modeset_acquire_ctx *ctx) 695 693 { 696 696 - struct intel_display *display = &i915->display; 694 694 + struct drm_i915_private *i915 = to_i915(display->drm); 697 695 struct drm_crtc_state *crtc_state; 698 696 struct drm_crtc *crtc; 699 697 int ret, i; ··· 726 710 } 727 711 728 712 /* ignore any reset values/BIOS leftovers in the WM registers */ 729 729 - if (!HAS_GMCH(i915)) 713 713 + if (!HAS_GMCH(display)) 730 714 to_intel_atomic_state(state)->skip_intermediate_wm = true; 731 715 732 716 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 733 717 734 734 - drm_WARN_ON(&i915->drm, ret == -EDEADLK); 718 718 + drm_WARN_ON(display->drm, ret == -EDEADLK); 735 719 736 720 return ret; 737 721 } 738 722 739 739 - void intel_display_driver_resume(struct drm_i915_private *i915) 723 723 + void intel_display_driver_resume(struct intel_display *display) 740 724 { 741 741 - struct drm_atomic_state *state = i915->display.restore.modeset_state; 725 725 + struct drm_i915_private *i915 = to_i915(display->drm); 726 726 + struct drm_atomic_state *state = display->restore.modeset_state; 742 727 struct drm_modeset_acquire_ctx ctx; 743 728 int ret; 744 729 745 745 - if (!HAS_DISPLAY(i915)) 730 730 + if (!HAS_DISPLAY(display)) 746 731 return; 747 732 748 748 - i915->display.restore.modeset_state = NULL; 733 733 + /* MST sideband requires HPD interrupts enabled */ 734 734 + intel_dp_mst_resume(i915); 735 735 + 736 736 + display->restore.modeset_state = NULL; 749 737 if (state) 750 738 state->acquire_ctx = &ctx; 751 739 752 740 drm_modeset_acquire_init(&ctx, 0); 753 741 754 742 while (1) { 755 755 - ret = drm_modeset_lock_all_ctx(&i915->drm, &ctx); 743 743 + ret = drm_modeset_lock_all_ctx(display->drm, &ctx); 756 744 if (ret != -EDEADLK) 757 745 break; 758 746 ··· 764 744 } 765 745 766 746 if (!ret) 767 767 - ret = __intel_display_driver_resume(i915, state, &ctx); 747 747 + ret = __intel_display_driver_resume(display, state, &ctx); 768 748 769 749 skl_watermark_ipc_update(i915); 770 750 drm_modeset_drop_locks(&ctx); 771 751 drm_modeset_acquire_fini(&ctx); 772 752 773 753 if (ret) 774 774 - drm_err(&i915->drm, 754 754 + drm_err(display->drm, 775 755 "Restoring old state failed with %i\n", ret); 776 756 if (state) 777 757 drm_atomic_state_put(state);

+19 -19

drivers/gpu/drm/i915/display/intel_display_driver.h

reviewed

··· 9 9 #include <linux/types.h> 10 10 11 11 struct drm_atomic_state; 12 12 - struct drm_i915_private; 13 12 struct drm_modeset_acquire_ctx; 13 13 + struct intel_display; 14 14 struct pci_dev; 15 15 16 16 bool intel_display_driver_probe_defer(struct pci_dev *pdev); 17 17 - void intel_display_driver_init_hw(struct drm_i915_private *i915); 18 18 - void intel_display_driver_early_probe(struct drm_i915_private *i915); 19 19 - int intel_display_driver_probe_noirq(struct drm_i915_private *i915); 20 20 - int intel_display_driver_probe_nogem(struct drm_i915_private *i915); 21 21 - int intel_display_driver_probe(struct drm_i915_private *i915); 22 22 - void intel_display_driver_register(struct drm_i915_private *i915); 23 23 - void intel_display_driver_remove(struct drm_i915_private *i915); 24 24 - void intel_display_driver_remove_noirq(struct drm_i915_private *i915); 25 25 - void intel_display_driver_remove_nogem(struct drm_i915_private *i915); 26 26 - void intel_display_driver_unregister(struct drm_i915_private *i915); 27 27 - int intel_display_driver_suspend(struct drm_i915_private *i915); 28 28 - void intel_display_driver_resume(struct drm_i915_private *i915); 17 17 + void intel_display_driver_init_hw(struct intel_display *display); 18 18 + void intel_display_driver_early_probe(struct intel_display *display); 19 19 + int intel_display_driver_probe_noirq(struct intel_display *display); 20 20 + int intel_display_driver_probe_nogem(struct intel_display *display); 21 21 + int intel_display_driver_probe(struct intel_display *display); 22 22 + void intel_display_driver_register(struct intel_display *display); 23 23 + void intel_display_driver_remove(struct intel_display *display); 24 24 + void intel_display_driver_remove_noirq(struct intel_display *display); 25 25 + void intel_display_driver_remove_nogem(struct intel_display *display); 26 26 + void intel_display_driver_unregister(struct intel_display *display); 27 27 + int intel_display_driver_suspend(struct intel_display *display); 28 28 + void intel_display_driver_resume(struct intel_display *display); 29 29 30 30 /* interface for intel_display_reset.c */ 31 31 - int __intel_display_driver_resume(struct drm_i915_private *i915, 31 31 + int __intel_display_driver_resume(struct intel_display *display, 32 32 struct drm_atomic_state *state, 33 33 struct drm_modeset_acquire_ctx *ctx); 34 34 35 35 - void intel_display_driver_enable_user_access(struct drm_i915_private *i915); 36 36 - void intel_display_driver_disable_user_access(struct drm_i915_private *i915); 37 37 - void intel_display_driver_suspend_access(struct drm_i915_private *i915); 38 38 - void intel_display_driver_resume_access(struct drm_i915_private *i915); 39 39 - bool intel_display_driver_check_access(struct drm_i915_private *i915); 35 35 + void intel_display_driver_enable_user_access(struct intel_display *display); 36 36 + void intel_display_driver_disable_user_access(struct intel_display *display); 37 37 + void intel_display_driver_suspend_access(struct intel_display *display); 38 38 + void intel_display_driver_resume_access(struct intel_display *display); 39 39 + bool intel_display_driver_check_access(struct intel_display *display); 40 40 41 41 #endif /* __INTEL_DISPLAY_DRIVER_H__ */ 42 42

+26 -26

drivers/gpu/drm/i915/display/intel_display_irq.c

reviewed

··· 434 434 435 435 spin_lock(&dev_priv->irq_lock); 436 436 437 437 - if (!dev_priv->display.irq.display_irqs_enabled) { 437 437 + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 438 438 + !dev_priv->display.irq.vlv_display_irqs_enabled) { 438 439 spin_unlock(&dev_priv->irq_lock); 439 440 return; 440 441 } ··· 844 843 845 844 static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) 846 845 { 847 847 - if (DISPLAY_VER(dev_priv) >= 14) 846 846 + struct intel_display *display = &dev_priv->display; 847 847 + 848 848 + if (DISPLAY_VER(display) >= 14) 848 849 return MTL_PIPEDMC_ATS_FAULT | 849 850 MTL_PLANE_ATS_FAULT | 850 851 GEN12_PIPEDMC_FAULT | ··· 856 853 GEN9_PIPE_PLANE3_FAULT | 857 854 GEN9_PIPE_PLANE2_FAULT | 858 855 GEN9_PIPE_PLANE1_FAULT; 859 859 - if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv)) 856 856 + if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) 860 857 return GEN12_PIPEDMC_FAULT | 861 858 GEN9_PIPE_CURSOR_FAULT | 862 859 GEN11_PIPE_PLANE5_FAULT | ··· 864 861 GEN9_PIPE_PLANE3_FAULT | 865 862 GEN9_PIPE_PLANE2_FAULT | 866 863 GEN9_PIPE_PLANE1_FAULT; 867 867 - else if (DISPLAY_VER(dev_priv) == 12) 864 864 + else if (DISPLAY_VER(display) == 12) 868 865 return GEN12_PIPEDMC_FAULT | 869 866 GEN9_PIPE_CURSOR_FAULT | 870 867 GEN11_PIPE_PLANE7_FAULT | ··· 874 871 GEN9_PIPE_PLANE3_FAULT | 875 872 GEN9_PIPE_PLANE2_FAULT | 876 873 GEN9_PIPE_PLANE1_FAULT; 877 877 - else if (DISPLAY_VER(dev_priv) == 11) 874 874 + else if (DISPLAY_VER(display) == 11) 878 875 return GEN9_PIPE_CURSOR_FAULT | 879 876 GEN11_PIPE_PLANE7_FAULT | 880 877 GEN11_PIPE_PLANE6_FAULT | ··· 883 880 GEN9_PIPE_PLANE3_FAULT | 884 881 GEN9_PIPE_PLANE2_FAULT | 885 882 GEN9_PIPE_PLANE1_FAULT; 886 886 - else if (DISPLAY_VER(dev_priv) >= 9) 883 883 + else if (DISPLAY_VER(display) >= 9) 887 884 return GEN9_PIPE_CURSOR_FAULT | 888 885 GEN9_PIPE_PLANE4_FAULT | 889 886 GEN9_PIPE_PLANE3_FAULT | ··· 1423 1420 { 1424 1421 struct intel_display *display = 1425 1422 container_of(work, typeof(*display), irq.vblank_dc_work); 1426 1426 - struct drm_i915_private *i915 = to_i915(display->drm); 1427 1423 int vblank_wa_num_pipes = READ_ONCE(display->irq.vblank_wa_num_pipes); 1428 1424 1429 1425 /* ··· 1431 1429 * PSR code. If DC3CO is taken into use we need take that into account 1432 1430 * here as well. 1433 1431 */ 1434 1434 - intel_display_power_set_target_dc_state(i915, vblank_wa_num_pipes ? DC_STATE_DISABLE : 1432 1432 + intel_display_power_set_target_dc_state(display, vblank_wa_num_pipes ? DC_STATE_DISABLE : 1435 1433 DC_STATE_EN_UPTO_DC6); 1436 1434 } 1437 1435 ··· 1481 1479 schedule_work(&display->irq.vblank_dc_work); 1482 1480 } 1483 1481 1484 1484 - void vlv_display_irq_reset(struct drm_i915_private *dev_priv) 1482 1482 + static void _vlv_display_irq_reset(struct drm_i915_private *dev_priv) 1485 1483 { 1486 1484 struct intel_uncore *uncore = &dev_priv->uncore; 1487 1485 ··· 1497 1495 1498 1496 gen2_irq_reset(uncore, VLV_IRQ_REGS); 1499 1497 dev_priv->irq_mask = ~0u; 1498 1498 + } 1499 1499 + 1500 1500 + void vlv_display_irq_reset(struct drm_i915_private *dev_priv) 1501 1501 + { 1502 1502 + if (dev_priv->display.irq.vlv_display_irqs_enabled) 1503 1503 + _vlv_display_irq_reset(dev_priv); 1500 1504 } 1501 1505 1502 1506 void i9xx_display_irq_reset(struct drm_i915_private *i915) ··· 1523 1515 u32 pipestat_mask; 1524 1516 u32 enable_mask; 1525 1517 enum pipe pipe; 1518 1518 + 1519 1519 + if (!dev_priv->display.irq.vlv_display_irqs_enabled) 1520 1520 + return; 1526 1521 1527 1522 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; 1528 1523 ··· 1699 1688 { 1700 1689 lockdep_assert_held(&dev_priv->irq_lock); 1701 1690 1702 1702 - if (dev_priv->display.irq.display_irqs_enabled) 1691 1691 + if (dev_priv->display.irq.vlv_display_irqs_enabled) 1703 1692 return; 1704 1693 1705 1705 - dev_priv->display.irq.display_irqs_enabled = true; 1694 1694 + dev_priv->display.irq.vlv_display_irqs_enabled = true; 1706 1695 1707 1696 if (intel_irqs_enabled(dev_priv)) { 1708 1708 - vlv_display_irq_reset(dev_priv); 1697 1697 + _vlv_display_irq_reset(dev_priv); 1709 1698 vlv_display_irq_postinstall(dev_priv); 1710 1699 } 1711 1700 } ··· 1714 1703 { 1715 1704 lockdep_assert_held(&dev_priv->irq_lock); 1716 1705 1717 1717 - if (!dev_priv->display.irq.display_irqs_enabled) 1706 1706 + if (!dev_priv->display.irq.vlv_display_irqs_enabled) 1718 1707 return; 1719 1708 1720 1720 - dev_priv->display.irq.display_irqs_enabled = false; 1709 1709 + dev_priv->display.irq.vlv_display_irqs_enabled = false; 1721 1710 1722 1711 if (intel_irqs_enabled(dev_priv)) 1723 1723 - vlv_display_irq_reset(dev_priv); 1712 1712 + _vlv_display_irq_reset(dev_priv); 1724 1713 } 1725 1714 1726 1715 void ilk_de_irq_postinstall(struct drm_i915_private *i915) ··· 1912 1901 void intel_display_irq_init(struct drm_i915_private *i915) 1913 1902 { 1914 1903 i915->drm.vblank_disable_immediate = true; 1915 1915 - 1916 1916 - /* 1917 1917 - * Most platforms treat the display irq block as an always-on power 1918 1918 - * domain. vlv/chv can disable it at runtime and need special care to 1919 1919 - * avoid writing any of the display block registers outside of the power 1920 1920 - * domain. We defer setting up the display irqs in this case to the 1921 1921 - * runtime pm. 1922 1922 - */ 1923 1923 - i915->display.irq.display_irqs_enabled = true; 1924 1924 - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 1925 1925 - i915->display.irq.display_irqs_enabled = false; 1926 1904 1927 1905 intel_hotplug_irq_init(i915); 1928 1906

+3 -3

drivers/gpu/drm/i915/display/intel_display_params.c

reviewed

··· 123 123 "(0=disabled, 1=enabled) " 124 124 "Default: 1"); 125 125 126 126 - intel_display_param_named_unsafe(enable_dmc_wl, bool, 0400, 126 126 + intel_display_param_named_unsafe(enable_dmc_wl, int, 0400, 127 127 "Enable DMC wakelock " 128 128 - "(0=disabled, 1=enabled) " 129 129 - "Default: 0"); 128 128 + "(-1=use per-chip default, 0=disabled, 1=enabled) " 129 129 + "Default: -1"); 130 130 131 131 __maybe_unused 132 132 static void _param_print_bool(struct drm_printer *p, const char *driver_name,

+1 -1

drivers/gpu/drm/i915/display/intel_display_params.h

reviewed

··· 47 47 param(int, enable_psr, -1, 0600) \ 48 48 param(bool, psr_safest_params, false, 0400) \ 49 49 param(bool, enable_psr2_sel_fetch, true, 0400) \ 50 50 - param(bool, enable_dmc_wl, false, 0400) \ 50 50 + param(int, enable_dmc_wl, -1, 0400) \ 51 51 52 52 #define MEMBER(T, member, ...) T member; 53 53 struct intel_display_params {

+488 -460

drivers/gpu/drm/i915/display/intel_display_power.c

reviewed

··· 28 28 #include "skl_watermark_regs.h" 29 29 #include "vlv_sideband.h" 30 30 31 31 - #define for_each_power_domain_well(__dev_priv, __power_well, __domain) \ 32 32 - for_each_power_well(__dev_priv, __power_well) \ 31 31 + #define for_each_power_domain_well(__display, __power_well, __domain) \ 32 32 + for_each_power_well((__display), __power_well) \ 33 33 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 34 34 35 35 - #define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \ 36 36 - for_each_power_well_reverse(__dev_priv, __power_well) \ 35 35 + #define for_each_power_domain_well_reverse(__display, __power_well, __domain) \ 36 36 + for_each_power_well_reverse((__display), __power_well) \ 37 37 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 38 38 39 39 static const char * ··· 198 198 } 199 199 } 200 200 201 201 - static bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 201 201 + static bool __intel_display_power_is_enabled(struct intel_display *display, 202 202 enum intel_display_power_domain domain) 203 203 { 204 204 struct i915_power_well *power_well; 205 205 bool is_enabled; 206 206 207 207 - if (pm_runtime_suspended(dev_priv->drm.dev)) 207 207 + if (pm_runtime_suspended(display->drm->dev)) 208 208 return false; 209 209 210 210 is_enabled = true; 211 211 212 212 - for_each_power_domain_well_reverse(dev_priv, power_well, domain) { 212 212 + for_each_power_domain_well_reverse(display, power_well, domain) { 213 213 if (intel_power_well_is_always_on(power_well)) 214 214 continue; 215 215 ··· 242 242 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 243 243 enum intel_display_power_domain domain) 244 244 { 245 245 - struct i915_power_domains *power_domains; 245 245 + struct intel_display *display = &dev_priv->display; 246 246 + struct i915_power_domains *power_domains = &display->power.domains; 246 247 bool ret; 247 248 248 248 - power_domains = &dev_priv->display.power.domains; 249 249 - 250 249 mutex_lock(&power_domains->lock); 251 251 - ret = __intel_display_power_is_enabled(dev_priv, domain); 250 250 + ret = __intel_display_power_is_enabled(display, domain); 252 251 mutex_unlock(&power_domains->lock); 253 252 254 253 return ret; 255 254 } 256 255 257 256 static u32 258 258 - sanitize_target_dc_state(struct drm_i915_private *i915, 257 257 + sanitize_target_dc_state(struct intel_display *display, 259 258 u32 target_dc_state) 260 259 { 261 261 - struct i915_power_domains *power_domains = &i915->display.power.domains; 260 260 + struct i915_power_domains *power_domains = &display->power.domains; 262 261 static const u32 states[] = { 263 262 DC_STATE_EN_UPTO_DC6, 264 263 DC_STATE_EN_UPTO_DC5, ··· 281 282 282 283 /** 283 284 * intel_display_power_set_target_dc_state - Set target dc state. 284 284 - * @dev_priv: i915 device 285 285 + * @display: display device 285 286 * @state: state which needs to be set as target_dc_state. 286 287 * 287 288 * This function set the "DC off" power well target_dc_state, 288 289 * based upon this target_dc_stste, "DC off" power well will 289 290 * enable desired DC state. 290 291 */ 291 291 - void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 292 292 + void intel_display_power_set_target_dc_state(struct intel_display *display, 292 293 u32 state) 293 294 { 294 295 struct i915_power_well *power_well; 295 296 bool dc_off_enabled; 296 296 - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 297 297 + struct i915_power_domains *power_domains = &display->power.domains; 297 298 298 299 mutex_lock(&power_domains->lock); 299 299 - power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF); 300 300 + power_well = lookup_power_well(display, SKL_DISP_DC_OFF); 300 301 301 301 - if (drm_WARN_ON(&dev_priv->drm, !power_well)) 302 302 + if (drm_WARN_ON(display->drm, !power_well)) 302 303 goto unlock; 303 304 304 304 - state = sanitize_target_dc_state(dev_priv, state); 305 305 + state = sanitize_target_dc_state(display, state); 305 306 306 307 if (state == power_domains->target_dc_state) 307 308 goto unlock; 308 309 309 309 - dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well); 310 310 + dc_off_enabled = intel_power_well_is_enabled(display, power_well); 310 311 /* 311 312 * If DC off power well is disabled, need to enable and disable the 312 313 * DC off power well to effect target DC state. 313 314 */ 314 315 if (!dc_off_enabled) 315 315 - intel_power_well_enable(dev_priv, power_well); 316 316 + intel_power_well_enable(display, power_well); 316 317 317 318 power_domains->target_dc_state = state; 318 319 319 320 if (!dc_off_enabled) 320 320 - intel_power_well_disable(dev_priv, power_well); 321 321 + intel_power_well_disable(display, power_well); 321 322 322 323 unlock: 323 324 mutex_unlock(&power_domains->lock); ··· 337 338 static bool 338 339 assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains) 339 340 { 340 340 - struct drm_i915_private *i915 = container_of(power_domains, 341 341 - struct drm_i915_private, 342 342 - display.power.domains); 341 341 + struct intel_display *display = container_of(power_domains, 342 342 + struct intel_display, 343 343 + power.domains); 343 344 344 344 - return !drm_WARN_ON(&i915->drm, 345 345 + return !drm_WARN_ON(display->drm, 345 346 bitmap_intersects(power_domains->async_put_domains[0].bits, 346 347 power_domains->async_put_domains[1].bits, 347 348 POWER_DOMAIN_NUM)); ··· 350 351 static bool 351 352 __async_put_domains_state_ok(struct i915_power_domains *power_domains) 352 353 { 353 353 - struct drm_i915_private *i915 = container_of(power_domains, 354 354 - struct drm_i915_private, 355 355 - display.power.domains); 354 354 + struct intel_display *display = container_of(power_domains, 355 355 + struct intel_display, 356 356 + power.domains); 356 357 struct intel_power_domain_mask async_put_mask; 357 358 enum intel_display_power_domain domain; 358 359 bool err = false; 359 360 360 361 err |= !assert_async_put_domain_masks_disjoint(power_domains); 361 362 __async_put_domains_mask(power_domains, &async_put_mask); 362 362 - err |= drm_WARN_ON(&i915->drm, 363 363 + err |= drm_WARN_ON(display->drm, 363 364 !!power_domains->async_put_wakeref != 364 365 !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM)); 365 366 366 367 for_each_power_domain(domain, &async_put_mask) 367 367 - err |= drm_WARN_ON(&i915->drm, 368 368 + err |= drm_WARN_ON(display->drm, 368 369 power_domains->domain_use_count[domain] != 1); 369 370 370 371 return !err; ··· 373 374 static void print_power_domains(struct i915_power_domains *power_domains, 374 375 const char *prefix, struct intel_power_domain_mask *mask) 375 376 { 376 376 - struct drm_i915_private *i915 = container_of(power_domains, 377 377 - struct drm_i915_private, 378 378 - display.power.domains); 377 377 + struct intel_display *display = container_of(power_domains, 378 378 + struct intel_display, 379 379 + power.domains); 379 380 enum intel_display_power_domain domain; 380 381 381 381 - drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); 382 382 + drm_dbg_kms(display->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM)); 382 383 for_each_power_domain(domain, mask) 383 383 - drm_dbg(&i915->drm, "%s use_count %d\n", 384 384 - intel_display_power_domain_str(domain), 385 385 - power_domains->domain_use_count[domain]); 384 384 + drm_dbg_kms(display->drm, "%s use_count %d\n", 385 385 + intel_display_power_domain_str(domain), 386 386 + power_domains->domain_use_count[domain]); 386 387 } 387 388 388 389 static void 389 390 print_async_put_domains_state(struct i915_power_domains *power_domains) 390 391 { 391 391 - struct drm_i915_private *i915 = container_of(power_domains, 392 392 - struct drm_i915_private, 393 393 - display.power.domains); 392 392 + struct intel_display *display = container_of(power_domains, 393 393 + struct intel_display, 394 394 + power.domains); 394 395 395 395 - drm_dbg(&i915->drm, "async_put_wakeref: %s\n", 396 396 - str_yes_no(power_domains->async_put_wakeref)); 396 396 + drm_dbg_kms(display->drm, "async_put_wakeref: %s\n", 397 397 + str_yes_no(power_domains->async_put_wakeref)); 397 398 398 399 print_power_domains(power_domains, "async_put_domains[0]", 399 400 &power_domains->async_put_domains[0]); ··· 453 454 } 454 455 455 456 static bool 456 456 - intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv, 457 457 + intel_display_power_grab_async_put_ref(struct intel_display *display, 457 458 enum intel_display_power_domain domain) 458 459 { 459 459 - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 460 460 + struct drm_i915_private *dev_priv = to_i915(display->drm); 461 461 + struct i915_power_domains *power_domains = &display->power.domains; 460 462 struct intel_power_domain_mask async_put_mask; 461 463 bool ret = false; 462 464 ··· 483 483 } 484 484 485 485 static void 486 486 - __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 486 486 + __intel_display_power_get_domain(struct intel_display *display, 487 487 enum intel_display_power_domain domain) 488 488 { 489 489 - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 489 489 + struct i915_power_domains *power_domains = &display->power.domains; 490 490 struct i915_power_well *power_well; 491 491 492 492 - if (intel_display_power_grab_async_put_ref(dev_priv, domain)) 492 492 + if (intel_display_power_grab_async_put_ref(display, domain)) 493 493 return; 494 494 495 495 - for_each_power_domain_well(dev_priv, power_well, domain) 496 496 - intel_power_well_get(dev_priv, power_well); 495 495 + for_each_power_domain_well(display, power_well, domain) 496 496 + intel_power_well_get(display, power_well); 497 497 498 498 power_domains->domain_use_count[domain]++; 499 499 } ··· 513 513 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 514 514 enum intel_display_power_domain domain) 515 515 { 516 516 - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 516 516 + struct intel_display *display = &dev_priv->display; 517 517 + struct i915_power_domains *power_domains = &display->power.domains; 517 518 intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 518 519 519 520 mutex_lock(&power_domains->lock); 520 520 - __intel_display_power_get_domain(dev_priv, domain); 521 521 + __intel_display_power_get_domain(display, domain); 521 522 mutex_unlock(&power_domains->lock); 522 523 523 524 return wakeref; ··· 540 539 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 541 540 enum intel_display_power_domain domain) 542 541 { 543 543 - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 542 542 + struct intel_display *display = &dev_priv->display; 543 543 + struct i915_power_domains *power_domains = &display->power.domains; 544 544 intel_wakeref_t wakeref; 545 545 bool is_enabled; 546 546 ··· 551 549 552 550 mutex_lock(&power_domains->lock); 553 551 554 554 - if (__intel_display_power_is_enabled(dev_priv, domain)) { 555 555 - __intel_display_power_get_domain(dev_priv, domain); 552 552 + if (__intel_display_power_is_enabled(display, domain)) { 553 553 + __intel_display_power_get_domain(display, domain); 556 554 is_enabled = true; 557 555 } else { 558 556 is_enabled = false; ··· 569 567 } 570 568 571 569 static void 572 572 - __intel_display_power_put_domain(struct drm_i915_private *dev_priv, 570 570 + __intel_display_power_put_domain(struct intel_display *display, 573 571 enum intel_display_power_domain domain) 574 572 { 575 575 - struct i915_power_domains *power_domains; 573 573 + struct i915_power_domains *power_domains = &display->power.domains; 576 574 struct i915_power_well *power_well; 577 575 const char *name = intel_display_power_domain_str(domain); 578 576 struct intel_power_domain_mask async_put_mask; 579 577 580 580 - power_domains = &dev_priv->display.power.domains; 581 581 - 582 582 - drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain], 578 578 + drm_WARN(display->drm, !power_domains->domain_use_count[domain], 583 579 "Use count on domain %s is already zero\n", 584 580 name); 585 581 async_put_domains_mask(power_domains, &async_put_mask); 586 586 - drm_WARN(&dev_priv->drm, 582 582 + drm_WARN(display->drm, 587 583 test_bit(domain, async_put_mask.bits), 588 584 "Async disabling of domain %s is pending\n", 589 585 name); 590 586 591 587 power_domains->domain_use_count[domain]--; 592 588 593 593 - for_each_power_domain_well_reverse(dev_priv, power_well, domain) 594 594 - intel_power_well_put(dev_priv, power_well); 589 589 + for_each_power_domain_well_reverse(display, power_well, domain) 590 590 + intel_power_well_put(display, power_well); 595 591 } 596 592 597 597 - static void __intel_display_power_put(struct drm_i915_private *dev_priv, 593 593 + static void __intel_display_power_put(struct intel_display *display, 598 594 enum intel_display_power_domain domain) 599 595 { 600 600 - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 596 596 + struct i915_power_domains *power_domains = &display->power.domains; 601 597 602 598 mutex_lock(&power_domains->lock); 603 603 - __intel_display_power_put_domain(dev_priv, domain); 599 599 + __intel_display_power_put_domain(display, domain); 604 600 mutex_unlock(&power_domains->lock); 605 601 } 606 602 ··· 607 607 intel_wakeref_t wakeref, 608 608 int delay_ms) 609 609 { 610 610 - struct drm_i915_private *i915 = container_of(power_domains, 611 611 - struct drm_i915_private, 612 612 - display.power.domains); 613 613 - drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref); 610 610 + struct intel_display *display = container_of(power_domains, 611 611 + struct intel_display, 612 612 + power.domains); 613 613 + drm_WARN_ON(display->drm, power_domains->async_put_wakeref); 614 614 power_domains->async_put_wakeref = wakeref; 615 615 - drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq, 616 616 - &power_domains->async_put_work, 617 617 - msecs_to_jiffies(delay_ms))); 615 615 + drm_WARN_ON(display->drm, !queue_delayed_work(system_unbound_wq, 616 616 + &power_domains->async_put_work, 617 617 + msecs_to_jiffies(delay_ms))); 618 618 } 619 619 620 620 static void 621 621 release_async_put_domains(struct i915_power_domains *power_domains, 622 622 struct intel_power_domain_mask *mask) 623 623 { 624 624 - struct drm_i915_private *dev_priv = 625 625 - container_of(power_domains, struct drm_i915_private, 626 626 - display.power.domains); 624 624 + struct intel_display *display = container_of(power_domains, 625 625 + struct intel_display, 626 626 + power.domains); 627 627 + struct drm_i915_private *dev_priv = to_i915(display->drm); 627 628 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 628 629 enum intel_display_power_domain domain; 629 630 intel_wakeref_t wakeref; ··· 634 633 for_each_power_domain(domain, mask) { 635 634 /* Clear before put, so put's sanity check is happy. */ 636 635 async_put_domains_clear_domain(power_domains, domain); 637 637 - __intel_display_power_put_domain(dev_priv, domain); 636 636 + __intel_display_power_put_domain(display, domain); 638 637 } 639 638 640 639 intel_runtime_pm_put(rpm, wakeref); ··· 643 642 static void 644 643 intel_display_power_put_async_work(struct work_struct *work) 645 644 { 646 646 - struct drm_i915_private *dev_priv = 647 647 - container_of(work, struct drm_i915_private, 648 648 - display.power.domains.async_put_work.work); 649 649 - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 645 645 + struct intel_display *display = container_of(work, struct intel_display, 646 646 + power.domains.async_put_work.work); 647 647 + struct drm_i915_private *dev_priv = to_i915(display->drm); 648 648 + struct i915_power_domains *power_domains = &display->power.domains; 650 649 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 651 650 intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm); 652 651 intel_wakeref_t old_work_wakeref = NULL; ··· 712 711 intel_wakeref_t wakeref, 713 712 int delay_ms) 714 713 { 715 715 - struct i915_power_domains *power_domains = &i915->display.power.domains; 714 714 + struct intel_display *display = &i915->display; 715 715 + struct i915_power_domains *power_domains = &display->power.domains; 716 716 struct intel_runtime_pm *rpm = &i915->runtime_pm; 717 717 intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm); 718 718 ··· 722 720 mutex_lock(&power_domains->lock); 723 721 724 722 if (power_domains->domain_use_count[domain] > 1) { 725 725 - __intel_display_power_put_domain(i915, domain); 723 723 + __intel_display_power_put_domain(display, domain); 726 724 727 725 goto out_verify; 728 726 } 729 727 730 730 - drm_WARN_ON(&i915->drm, power_domains->domain_use_count[domain] != 1); 728 728 + drm_WARN_ON(display->drm, power_domains->domain_use_count[domain] != 1); 731 729 732 730 /* Let a pending work requeue itself or queue a new one. */ 733 731 if (power_domains->async_put_wakeref) { ··· 766 764 */ 767 765 void intel_display_power_flush_work(struct drm_i915_private *i915) 768 766 { 769 769 - struct i915_power_domains *power_domains = &i915->display.power.domains; 767 767 + struct intel_display *display = &i915->display; 768 768 + struct i915_power_domains *power_domains = &display->power.domains; 770 769 struct intel_power_domain_mask async_put_mask; 771 770 intel_wakeref_t work_wakeref; 772 771 ··· 792 789 793 790 /** 794 791 * intel_display_power_flush_work_sync - flushes and syncs the async display power disabling work 795 795 - * @i915: i915 device instance 792 792 + * @display: display device instance 796 793 * 797 794 * Like intel_display_power_flush_work(), but also ensure that the work 798 795 * handler function is not running any more when this function returns. 799 796 */ 800 797 static void 801 801 - intel_display_power_flush_work_sync(struct drm_i915_private *i915) 798 798 + intel_display_power_flush_work_sync(struct intel_display *display) 802 799 { 803 803 - struct i915_power_domains *power_domains = &i915->display.power.domains; 800 800 + struct drm_i915_private *i915 = to_i915(display->drm); 801 801 + struct i915_power_domains *power_domains = &display->power.domains; 804 802 805 803 intel_display_power_flush_work(i915); 806 804 cancel_async_put_work(power_domains, true); 807 805 808 806 verify_async_put_domains_state(power_domains); 809 807 810 810 - drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref); 808 808 + drm_WARN_ON(display->drm, power_domains->async_put_wakeref); 811 809 } 812 810 813 811 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) ··· 826 822 enum intel_display_power_domain domain, 827 823 intel_wakeref_t wakeref) 828 824 { 829 829 - __intel_display_power_put(dev_priv, domain); 825 825 + struct intel_display *display = &dev_priv->display; 826 826 + 827 827 + __intel_display_power_put(display, domain); 830 828 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 831 829 } 832 830 #else ··· 848 842 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv, 849 843 enum intel_display_power_domain domain) 850 844 { 851 851 - __intel_display_power_put(dev_priv, domain); 845 845 + struct intel_display *display = &dev_priv->display; 846 846 + 847 847 + __intel_display_power_put(display, domain); 852 848 intel_runtime_pm_put_unchecked(&dev_priv->runtime_pm); 853 849 } 854 850 #endif ··· 860 852 struct intel_display_power_domain_set *power_domain_set, 861 853 enum intel_display_power_domain domain) 862 854 { 855 855 + struct intel_display *display = &i915->display; 863 856 intel_wakeref_t __maybe_unused wf; 864 857 865 865 - drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits)); 858 858 + drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); 866 859 867 860 wf = intel_display_power_get(i915, domain); 868 861 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) ··· 877 868 struct intel_display_power_domain_set *power_domain_set, 878 869 enum intel_display_power_domain domain) 879 870 { 871 871 + struct intel_display *display = &i915->display; 880 872 intel_wakeref_t wf; 881 873 882 882 - drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits)); 874 874 + drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); 883 875 884 876 wf = intel_display_power_get_if_enabled(i915, domain); 885 877 if (!wf) ··· 899 889 struct intel_display_power_domain_set *power_domain_set, 900 890 struct intel_power_domain_mask *mask) 901 891 { 892 892 + struct intel_display *display = &i915->display; 902 893 enum intel_display_power_domain domain; 903 894 904 904 - drm_WARN_ON(&i915->drm, 895 895 + drm_WARN_ON(display->drm, 905 896 !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM)); 906 897 907 898 for_each_power_domain(domain, mask) { ··· 917 906 } 918 907 919 908 static int 920 920 - sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 921 921 - int disable_power_well) 909 909 + sanitize_disable_power_well_option(int disable_power_well) 922 910 { 923 911 if (disable_power_well >= 0) 924 912 return !!disable_power_well; ··· 925 915 return 1; 926 916 } 927 917 928 928 - static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, 929 929 - int enable_dc) 918 918 + static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc) 930 919 { 931 920 u32 mask; 932 921 int requested_dc; 933 922 int max_dc; 934 923 935 935 - if (!HAS_DISPLAY(dev_priv)) 924 924 + if (!HAS_DISPLAY(display)) 936 925 return 0; 937 926 938 938 - if (DISPLAY_VER(dev_priv) >= 20) 927 927 + if (DISPLAY_VER(display) >= 20) 939 928 max_dc = 2; 940 940 - else if (IS_DG2(dev_priv)) 929 929 + else if (display->platform.dg2) 941 930 max_dc = 1; 942 942 - else if (IS_DG1(dev_priv)) 931 931 + else if (display->platform.dg1) 943 932 max_dc = 3; 944 944 - else if (DISPLAY_VER(dev_priv) >= 12) 933 933 + else if (DISPLAY_VER(display) >= 12) 945 934 max_dc = 4; 946 946 - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 935 935 + else if (display->platform.geminilake || display->platform.broxton) 947 936 max_dc = 1; 948 948 - else if (DISPLAY_VER(dev_priv) >= 9) 937 937 + else if (DISPLAY_VER(display) >= 9) 949 938 max_dc = 2; 950 939 else 951 940 max_dc = 0; ··· 954 945 * not depending on the DMC firmware. It's needed by system 955 946 * suspend/resume, so allow it unconditionally. 956 947 */ 957 957 - mask = IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || 958 958 - DISPLAY_VER(dev_priv) >= 11 ? 959 959 - DC_STATE_EN_DC9 : 0; 948 948 + mask = display->platform.geminilake || display->platform.broxton || 949 949 + DISPLAY_VER(display) >= 11 ? DC_STATE_EN_DC9 : 0; 960 950 961 961 - if (!dev_priv->display.params.disable_power_well) 951 951 + if (!display->params.disable_power_well) 962 952 max_dc = 0; 963 953 964 954 if (enable_dc >= 0 && enable_dc <= max_dc) { ··· 965 957 } else if (enable_dc == -1) { 966 958 requested_dc = max_dc; 967 959 } else if (enable_dc > max_dc && enable_dc <= 4) { 968 968 - drm_dbg_kms(&dev_priv->drm, 960 960 + drm_dbg_kms(display->drm, 969 961 "Adjusting requested max DC state (%d->%d)\n", 970 962 enable_dc, max_dc); 971 963 requested_dc = max_dc; 972 964 } else { 973 973 - drm_err(&dev_priv->drm, 965 965 + drm_err(display->drm, 974 966 "Unexpected value for enable_dc (%d)\n", enable_dc); 975 967 requested_dc = max_dc; 976 968 } ··· 990 982 break; 991 983 } 992 984 993 993 - drm_dbg_kms(&dev_priv->drm, "Allowed DC state mask %02x\n", mask); 985 985 + drm_dbg_kms(display->drm, "Allowed DC state mask %02x\n", mask); 994 986 995 987 return mask; 996 988 } 997 989 998 990 /** 999 991 * intel_power_domains_init - initializes the power domain structures 1000 1000 - * @dev_priv: i915 device instance 992 992 + * @display: display device instance 1001 993 * 1002 994 * Initializes the power domain structures for @dev_priv depending upon the 1003 995 * supported platform. 1004 996 */ 1005 1005 - int intel_power_domains_init(struct drm_i915_private *dev_priv) 997 997 + int intel_power_domains_init(struct intel_display *display) 1006 998 { 1007 1007 - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 999 999 + struct i915_power_domains *power_domains = &display->power.domains; 1008 1000 1009 1009 - dev_priv->display.params.disable_power_well = 1010 1010 - sanitize_disable_power_well_option(dev_priv, 1011 1011 - dev_priv->display.params.disable_power_well); 1001 1001 + display->params.disable_power_well = 1002 1002 + sanitize_disable_power_well_option(display->params.disable_power_well); 1012 1003 power_domains->allowed_dc_mask = 1013 1013 - get_allowed_dc_mask(dev_priv, dev_priv->display.params.enable_dc); 1004 1004 + get_allowed_dc_mask(display, display->params.enable_dc); 1014 1005 1015 1006 power_domains->target_dc_state = 1016 1016 - sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 1007 1007 + sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1017 1008 1018 1009 mutex_init(&power_domains->lock); 1019 1010 ··· 1024 1017 1025 1018 /** 1026 1019 * intel_power_domains_cleanup - clean up power domains resources 1027 1027 - * @dev_priv: i915 device instance 1020 1020 + * @display: display device instance 1028 1021 * 1029 1022 * Release any resources acquired by intel_power_domains_init() 1030 1023 */ 1031 1031 - void intel_power_domains_cleanup(struct drm_i915_private *dev_priv) 1024 1024 + void intel_power_domains_cleanup(struct intel_display *display) 1032 1025 { 1033 1033 - intel_display_power_map_cleanup(&dev_priv->display.power.domains); 1026 1026 + intel_display_power_map_cleanup(&display->power.domains); 1034 1027 } 1035 1028 1036 1036 - static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 1029 1029 + static void intel_power_domains_sync_hw(struct intel_display *display) 1037 1030 { 1038 1038 - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1031 1031 + struct i915_power_domains *power_domains = &display->power.domains; 1039 1032 struct i915_power_well *power_well; 1040 1033 1041 1034 mutex_lock(&power_domains->lock); 1042 1042 - for_each_power_well(dev_priv, power_well) 1043 1043 - intel_power_well_sync_hw(dev_priv, power_well); 1035 1035 + for_each_power_well(display, power_well) 1036 1036 + intel_power_well_sync_hw(display, power_well); 1044 1037 mutex_unlock(&power_domains->lock); 1045 1038 } 1046 1039 1047 1047 - static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv, 1040 1040 + static void gen9_dbuf_slice_set(struct intel_display *display, 1048 1041 enum dbuf_slice slice, bool enable) 1049 1042 { 1050 1043 i915_reg_t reg = DBUF_CTL_S(slice); 1051 1044 bool state; 1052 1045 1053 1053 - intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST, 1046 1046 + intel_de_rmw(display, reg, DBUF_POWER_REQUEST, 1054 1047 enable ? DBUF_POWER_REQUEST : 0); 1055 1055 - intel_de_posting_read(dev_priv, reg); 1048 1048 + intel_de_posting_read(display, reg); 1056 1049 udelay(10); 1057 1050 1058 1058 - state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE; 1059 1059 - drm_WARN(&dev_priv->drm, enable != state, 1051 1051 + state = intel_de_read(display, reg) & DBUF_POWER_STATE; 1052 1052 + drm_WARN(display->drm, enable != state, 1060 1053 "DBuf slice %d power %s timeout!\n", 1061 1054 slice, str_enable_disable(enable)); 1062 1055 } ··· 1064 1057 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, 1065 1058 u8 req_slices) 1066 1059 { 1067 1067 - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; 1068 1068 - u8 slice_mask = DISPLAY_INFO(dev_priv)->dbuf.slice_mask; 1060 1060 + struct intel_display *display = &dev_priv->display; 1061 1061 + struct i915_power_domains *power_domains = &display->power.domains; 1062 1062 + u8 slice_mask = DISPLAY_INFO(display)->dbuf.slice_mask; 1069 1063 enum dbuf_slice slice; 1070 1064 1071 1071 - drm_WARN(&dev_priv->drm, req_slices & ~slice_mask, 1065 1065 + drm_WARN(display->drm, req_slices & ~slice_mask, 1072 1066 "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n", 1073 1067 req_slices, slice_mask); 1074 1068 1075 1075 - drm_dbg_kms(&dev_priv->drm, "Updating dbuf slices to 0x%x\n", 1069 1069 + drm_dbg_kms(display->drm, "Updating dbuf slices to 0x%x\n", 1076 1070 req_slices); 1077 1071 1078 1072 /* ··· 1085 1077 */ 1086 1078 mutex_lock(&power_domains->lock); 1087 1079 1088 1088 - for_each_dbuf_slice(dev_priv, slice) 1089 1089 - gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice)); 1080 1080 + for_each_dbuf_slice(display, slice) 1081 1081 + gen9_dbuf_slice_set(display, slice, req_slices & BIT(slice)); 1090 1082 1091 1091 - dev_priv->display.dbuf.enabled_slices = req_slices; 1083 1083 + display->dbuf.enabled_slices = req_slices; 1092 1084 1093 1085 mutex_unlock(&power_domains->lock); 1094 1086 } 1095 1087 1096 1096 - static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) 1088 1088 + static void gen9_dbuf_enable(struct intel_display *display) 1097 1089 { 1090 1090 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1098 1091 u8 slices_mask; 1099 1092 1100 1100 - dev_priv->display.dbuf.enabled_slices = 1101 1101 - intel_enabled_dbuf_slices_mask(dev_priv); 1093 1093 + display->dbuf.enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); 1102 1094 1103 1103 - slices_mask = BIT(DBUF_S1) | dev_priv->display.dbuf.enabled_slices; 1095 1095 + slices_mask = BIT(DBUF_S1) | display->dbuf.enabled_slices; 1104 1096 1105 1105 - if (DISPLAY_VER(dev_priv) >= 14) 1097 1097 + if (DISPLAY_VER(display) >= 14) 1106 1098 intel_pmdemand_program_dbuf(dev_priv, slices_mask); 1107 1099 1108 1100 /* ··· 1112 1104 gen9_dbuf_slices_update(dev_priv, slices_mask); 1113 1105 } 1114 1106 1115 1115 - static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) 1107 1107 + static void gen9_dbuf_disable(struct intel_display *display) 1116 1108 { 1109 1109 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1110 1110 + 1117 1111 gen9_dbuf_slices_update(dev_priv, 0); 1118 1112 1119 1119 - if (DISPLAY_VER(dev_priv) >= 14) 1113 1113 + if (DISPLAY_VER(display) >= 14) 1120 1114 intel_pmdemand_program_dbuf(dev_priv, 0); 1121 1115 } 1122 1116 1123 1123 - static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) 1117 1117 + static void gen12_dbuf_slices_config(struct intel_display *display) 1124 1118 { 1125 1119 enum dbuf_slice slice; 1126 1120 1127 1127 - if (IS_ALDERLAKE_P(dev_priv)) 1121 1121 + if (display->platform.alderlake_p) 1128 1122 return; 1129 1123 1130 1130 - for_each_dbuf_slice(dev_priv, slice) 1131 1131 - intel_de_rmw(dev_priv, DBUF_CTL_S(slice), 1124 1124 + for_each_dbuf_slice(display, slice) 1125 1125 + intel_de_rmw(display, DBUF_CTL_S(slice), 1132 1126 DBUF_TRACKER_STATE_SERVICE_MASK, 1133 1127 DBUF_TRACKER_STATE_SERVICE(8)); 1134 1128 } 1135 1129 1136 1136 - static void icl_mbus_init(struct drm_i915_private *dev_priv) 1130 1130 + static void icl_mbus_init(struct intel_display *display) 1137 1131 { 1138 1138 - unsigned long abox_regs = DISPLAY_INFO(dev_priv)->abox_mask; 1132 1132 + unsigned long abox_regs = DISPLAY_INFO(display)->abox_mask; 1139 1133 u32 mask, val, i; 1140 1134 1141 1141 - if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14) 1135 1135 + if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) 1142 1136 return; 1143 1137 1144 1138 mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK | ··· 1157 1147 * expect us to program the abox_ctl0 register as well, even though 1158 1148 * we don't have to program other instance-0 registers like BW_BUDDY. 1159 1149 */ 1160 1160 - if (DISPLAY_VER(dev_priv) == 12) 1150 1150 + if (DISPLAY_VER(display) == 12) 1161 1151 abox_regs |= BIT(0); 1162 1152 1163 1153 for_each_set_bit(i, &abox_regs, sizeof(abox_regs)) 1164 1164 - intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val); 1154 1154 + intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val); 1165 1155 } 1166 1156 1167 1167 - static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) 1157 1157 + static void hsw_assert_cdclk(struct intel_display *display) 1168 1158 { 1169 1169 - u32 val = intel_de_read(dev_priv, LCPLL_CTL); 1159 1159 + u32 val = intel_de_read(display, LCPLL_CTL); 1170 1160 1171 1161 /* 1172 1162 * The LCPLL register should be turned on by the BIOS. For now ··· 1175 1165 */ 1176 1166 1177 1167 if (val & LCPLL_CD_SOURCE_FCLK) 1178 1178 - drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n"); 1168 1168 + drm_err(display->drm, "CDCLK source is not LCPLL\n"); 1179 1169 1180 1170 if (val & LCPLL_PLL_DISABLE) 1181 1181 - drm_err(&dev_priv->drm, "LCPLL is disabled\n"); 1171 1171 + drm_err(display->drm, "LCPLL is disabled\n"); 1182 1172 1183 1173 if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC) 1184 1184 - drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n"); 1174 1174 + drm_err(display->drm, "LCPLL not using non-SSC reference\n"); 1185 1175 } 1186 1176 1187 1187 - static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) 1177 1177 + static void assert_can_disable_lcpll(struct intel_display *display) 1188 1178 { 1189 1189 - struct intel_display *display = &dev_priv->display; 1179 1179 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1190 1180 struct intel_crtc *crtc; 1191 1181 1192 1182 for_each_intel_crtc(display->drm, crtc) ··· 1211 1201 INTEL_DISPLAY_STATE_WARN(display, 1212 1202 intel_de_read(display, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, 1213 1203 "CPU PWM1 enabled\n"); 1214 1214 - if (IS_HASWELL(dev_priv)) 1204 1204 + if (display->platform.haswell) 1215 1205 INTEL_DISPLAY_STATE_WARN(display, 1216 1206 intel_de_read(display, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, 1217 1207 "CPU PWM2 enabled\n"); ··· 1235 1225 "IRQs enabled\n"); 1236 1226 } 1237 1227 1238 1238 - static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv) 1228 1228 + static u32 hsw_read_dcomp(struct intel_display *display) 1239 1229 { 1240 1240 - if (IS_HASWELL(dev_priv)) 1241 1241 - return intel_de_read(dev_priv, D_COMP_HSW); 1230 1230 + if (display->platform.haswell) 1231 1231 + return intel_de_read(display, D_COMP_HSW); 1242 1232 else 1243 1243 - return intel_de_read(dev_priv, D_COMP_BDW); 1233 1233 + return intel_de_read(display, D_COMP_BDW); 1244 1234 } 1245 1235 1246 1246 - static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val) 1236 1236 + static void hsw_write_dcomp(struct intel_display *display, u32 val) 1247 1237 { 1248 1248 - if (IS_HASWELL(dev_priv)) { 1238 1238 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1239 1239 + 1240 1240 + if (display->platform.haswell) { 1249 1241 if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val)) 1250 1250 - drm_dbg_kms(&dev_priv->drm, 1251 1251 - "Failed to write to D_COMP\n"); 1242 1242 + drm_dbg_kms(display->drm, "Failed to write to D_COMP\n"); 1252 1243 } else { 1253 1253 - intel_de_write(dev_priv, D_COMP_BDW, val); 1254 1254 - intel_de_posting_read(dev_priv, D_COMP_BDW); 1244 1244 + intel_de_write(display, D_COMP_BDW, val); 1245 1245 + intel_de_posting_read(display, D_COMP_BDW); 1255 1246 } 1256 1247 } 1257 1248 ··· 1264 1253 * register. Callers should take care of disabling all the display engine 1265 1254 * functions, doing the mode unset, fixing interrupts, etc. 1266 1255 */ 1267 1267 - static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, 1256 1256 + static void hsw_disable_lcpll(struct intel_display *display, 1268 1257 bool switch_to_fclk, bool allow_power_down) 1269 1258 { 1270 1259 u32 val; 1271 1260 1272 1272 - assert_can_disable_lcpll(dev_priv); 1261 1261 + assert_can_disable_lcpll(display); 1273 1262 1274 1274 - val = intel_de_read(dev_priv, LCPLL_CTL); 1263 1263 + val = intel_de_read(display, LCPLL_CTL); 1275 1264 1276 1265 if (switch_to_fclk) { 1277 1266 val |= LCPLL_CD_SOURCE_FCLK; 1278 1278 - intel_de_write(dev_priv, LCPLL_CTL, val); 1267 1267 + intel_de_write(display, LCPLL_CTL, val); 1279 1268 1280 1280 - if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & 1269 1269 + if (wait_for_us(intel_de_read(display, LCPLL_CTL) & 1281 1270 LCPLL_CD_SOURCE_FCLK_DONE, 1)) 1282 1282 - drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); 1271 1271 + drm_err(display->drm, "Switching to FCLK failed\n"); 1283 1272 1284 1284 - val = intel_de_read(dev_priv, LCPLL_CTL); 1273 1273 + val = intel_de_read(display, LCPLL_CTL); 1285 1274 } 1286 1275 1287 1276 val |= LCPLL_PLL_DISABLE; 1288 1288 - intel_de_write(dev_priv, LCPLL_CTL, val); 1289 1289 - intel_de_posting_read(dev_priv, LCPLL_CTL); 1277 1277 + intel_de_write(display, LCPLL_CTL, val); 1278 1278 + intel_de_posting_read(display, LCPLL_CTL); 1290 1279 1291 1291 - if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) 1292 1292 - drm_err(&dev_priv->drm, "LCPLL still locked\n"); 1280 1280 + if (intel_de_wait_for_clear(display, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) 1281 1281 + drm_err(display->drm, "LCPLL still locked\n"); 1293 1282 1294 1294 - val = hsw_read_dcomp(dev_priv); 1283 1283 + val = hsw_read_dcomp(display); 1295 1284 val |= D_COMP_COMP_DISABLE; 1296 1296 - hsw_write_dcomp(dev_priv, val); 1285 1285 + hsw_write_dcomp(display, val); 1297 1286 ndelay(100); 1298 1287 1299 1299 - if (wait_for((hsw_read_dcomp(dev_priv) & 1288 1288 + if (wait_for((hsw_read_dcomp(display) & 1300 1289 D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) 1301 1301 - drm_err(&dev_priv->drm, "D_COMP RCOMP still in progress\n"); 1290 1290 + drm_err(display->drm, "D_COMP RCOMP still in progress\n"); 1302 1291 1303 1292 if (allow_power_down) { 1304 1304 - intel_de_rmw(dev_priv, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); 1305 1305 - intel_de_posting_read(dev_priv, LCPLL_CTL); 1293 1293 + intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); 1294 1294 + intel_de_posting_read(display, LCPLL_CTL); 1306 1295 } 1307 1296 } 1308 1297 ··· 1310 1299 * Fully restores LCPLL, disallowing power down and switching back to LCPLL 1311 1300 * source. 1312 1301 */ 1313 1313 - static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) 1302 1302 + static void hsw_restore_lcpll(struct intel_display *display) 1314 1303 { 1315 1315 - struct intel_display *display = &dev_priv->display; 1304 1304 + struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); 1316 1305 u32 val; 1317 1306 1318 1318 - val = intel_de_read(dev_priv, LCPLL_CTL); 1307 1307 + val = intel_de_read(display, LCPLL_CTL); 1319 1308 1320 1309 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | 1321 1310 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) ··· 1329 1318 1330 1319 if (val & LCPLL_POWER_DOWN_ALLOW) { 1331 1320 val &= ~LCPLL_POWER_DOWN_ALLOW; 1332 1332 - intel_de_write(dev_priv, LCPLL_CTL, val); 1333 1333 - intel_de_posting_read(dev_priv, LCPLL_CTL); 1321 1321 + intel_de_write(display, LCPLL_CTL, val); 1322 1322 + intel_de_posting_read(display, LCPLL_CTL); 1334 1323 } 1335 1324 1336 1336 - val = hsw_read_dcomp(dev_priv); 1325 1325 + val = hsw_read_dcomp(display); 1337 1326 val |= D_COMP_COMP_FORCE; 1338 1327 val &= ~D_COMP_COMP_DISABLE; 1339 1339 - hsw_write_dcomp(dev_priv, val); 1328 1328 + hsw_write_dcomp(display, val); 1340 1329 1341 1341 - val = intel_de_read(dev_priv, LCPLL_CTL); 1330 1330 + val = intel_de_read(display, LCPLL_CTL); 1342 1331 val &= ~LCPLL_PLL_DISABLE; 1343 1343 - intel_de_write(dev_priv, LCPLL_CTL, val); 1332 1332 + intel_de_write(display, LCPLL_CTL, val); 1344 1333 1345 1345 - if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) 1346 1346 - drm_err(&dev_priv->drm, "LCPLL not locked yet\n"); 1334 1334 + if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) 1335 1335 + drm_err(display->drm, "LCPLL not locked yet\n"); 1347 1336 1348 1337 if (val & LCPLL_CD_SOURCE_FCLK) { 1349 1349 - intel_de_rmw(dev_priv, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); 1338 1338 + intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); 1350 1339 1351 1351 - if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & 1340 1340 + if (wait_for_us((intel_de_read(display, LCPLL_CTL) & 1352 1341 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) 1353 1353 - drm_err(&dev_priv->drm, 1342 1342 + drm_err(display->drm, 1354 1343 "Switching back to LCPLL failed\n"); 1355 1344 } 1356 1345 ··· 1383 1372 * For more, read "Display Sequences for Package C8" on the hardware 1384 1373 * documentation. 1385 1374 */ 1386 1386 - static void hsw_enable_pc8(struct drm_i915_private *dev_priv) 1375 1375 + static void hsw_enable_pc8(struct intel_display *display) 1387 1376 { 1388 1388 - drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n"); 1377 1377 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1378 1378 + 1379 1379 + drm_dbg_kms(display->drm, "Enabling package C8+\n"); 1389 1380 1390 1381 if (HAS_PCH_LPT_LP(dev_priv)) 1391 1391 - intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1382 1382 + intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1392 1383 PCH_LP_PARTITION_LEVEL_DISABLE, 0); 1393 1384 1394 1385 lpt_disable_clkout_dp(dev_priv); 1395 1395 - hsw_disable_lcpll(dev_priv, true, true); 1386 1386 + hsw_disable_lcpll(display, true, true); 1396 1387 } 1397 1388 1398 1398 - static void hsw_disable_pc8(struct drm_i915_private *dev_priv) 1389 1389 + static void hsw_disable_pc8(struct intel_display *display) 1399 1390 { 1400 1400 - drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n"); 1391 1391 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1401 1392 1402 1402 - hsw_restore_lcpll(dev_priv); 1393 1393 + drm_dbg_kms(display->drm, "Disabling package C8+\n"); 1394 1394 + 1395 1395 + hsw_restore_lcpll(display); 1403 1396 intel_init_pch_refclk(dev_priv); 1404 1397 1405 1398 /* Many display registers don't survive PC8+ */ 1399 1399 + #ifdef I915 /* FIXME */ 1406 1400 intel_clock_gating_init(dev_priv); 1401 1401 + #endif 1407 1402 } 1408 1403 1409 1409 - static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, 1404 1404 + static void intel_pch_reset_handshake(struct intel_display *display, 1410 1405 bool enable) 1411 1406 { 1412 1407 i915_reg_t reg; 1413 1408 u32 reset_bits; 1414 1409 1415 1415 - if (IS_IVYBRIDGE(dev_priv)) { 1410 1410 + if (display->platform.ivybridge) { 1416 1411 reg = GEN7_MSG_CTL; 1417 1412 reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK; 1418 1413 } else { ··· 1426 1409 reset_bits = RESET_PCH_HANDSHAKE_ENABLE; 1427 1410 } 1428 1411 1429 1429 - if (DISPLAY_VER(dev_priv) >= 14) 1412 1412 + if (DISPLAY_VER(display) >= 14) 1430 1413 reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; 1431 1414 1432 1432 - intel_de_rmw(dev_priv, reg, reset_bits, enable ? reset_bits : 0); 1415 1415 + intel_de_rmw(display, reg, reset_bits, enable ? reset_bits : 0); 1433 1416 } 1434 1417 1435 1435 - static void skl_display_core_init(struct drm_i915_private *dev_priv, 1418 1418 + static void skl_display_core_init(struct intel_display *display, 1436 1419 bool resume) 1437 1420 { 1438 1438 - struct intel_display *display = &dev_priv->display; 1421 1421 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1439 1422 struct i915_power_domains *power_domains = &display->power.domains; 1440 1423 struct i915_power_well *well; 1441 1424 1442 1425 gen9_set_dc_state(display, DC_STATE_DISABLE); 1443 1426 1444 1427 /* enable PCH reset handshake */ 1445 1445 - intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); 1428 1428 + intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv)); 1446 1429 1447 1447 - if (!HAS_DISPLAY(dev_priv)) 1430 1430 + if (!HAS_DISPLAY(display)) 1448 1431 return; 1449 1432 1450 1433 /* enable PG1 and Misc I/O */ 1451 1434 mutex_lock(&power_domains->lock); 1452 1435 1453 1453 - well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1454 1454 - intel_power_well_enable(dev_priv, well); 1436 1436 + well = lookup_power_well(display, SKL_DISP_PW_1); 1437 1437 + intel_power_well_enable(display, well); 1455 1438 1456 1456 - well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 1457 1457 - intel_power_well_enable(dev_priv, well); 1439 1439 + well = lookup_power_well(display, SKL_DISP_PW_MISC_IO); 1440 1440 + intel_power_well_enable(display, well); 1458 1441 1459 1442 mutex_unlock(&power_domains->lock); 1460 1443 1461 1444 intel_cdclk_init_hw(display); 1462 1445 1463 1463 - gen9_dbuf_enable(dev_priv); 1446 1446 + gen9_dbuf_enable(display); 1464 1447 1465 1448 if (resume) 1466 1449 intel_dmc_load_program(display); 1467 1450 } 1468 1451 1469 1469 - static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 1452 1452 + static void skl_display_core_uninit(struct intel_display *display) 1470 1453 { 1471 1471 - struct intel_display *display = &dev_priv->display; 1472 1454 struct i915_power_domains *power_domains = &display->power.domains; 1473 1455 struct i915_power_well *well; 1474 1456 1475 1475 - if (!HAS_DISPLAY(dev_priv)) 1457 1457 + if (!HAS_DISPLAY(display)) 1476 1458 return; 1477 1459 1478 1460 gen9_disable_dc_states(display); 1479 1461 /* TODO: disable DMC program */ 1480 1462 1481 1481 - gen9_dbuf_disable(dev_priv); 1463 1463 + gen9_dbuf_disable(display); 1482 1464 1483 1465 intel_cdclk_uninit_hw(display); 1484 1466 ··· 1492 1476 * Note that even though the driver's request is removed power well 1 1493 1477 * may stay enabled after this due to DMC's own request on it. 1494 1478 */ 1495 1495 - well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1496 1496 - intel_power_well_disable(dev_priv, well); 1479 1479 + well = lookup_power_well(display, SKL_DISP_PW_1); 1480 1480 + intel_power_well_disable(display, well); 1497 1481 1498 1482 mutex_unlock(&power_domains->lock); 1499 1483 1500 1484 usleep_range(10, 30); /* 10 us delay per Bspec */ 1501 1485 } 1502 1486 1503 1503 - static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume) 1487 1487 + static void bxt_display_core_init(struct intel_display *display, bool resume) 1504 1488 { 1505 1505 - struct intel_display *display = &dev_priv->display; 1506 1489 struct i915_power_domains *power_domains = &display->power.domains; 1507 1490 struct i915_power_well *well; 1508 1491 ··· 1513 1498 * Move the handshake programming to initialization sequence. 1514 1499 * Previously was left up to BIOS. 1515 1500 */ 1516 1516 - intel_pch_reset_handshake(dev_priv, false); 1501 1501 + intel_pch_reset_handshake(display, false); 1517 1502 1518 1518 - if (!HAS_DISPLAY(dev_priv)) 1503 1503 + if (!HAS_DISPLAY(display)) 1519 1504 return; 1520 1505 1521 1506 /* Enable PG1 */ 1522 1507 mutex_lock(&power_domains->lock); 1523 1508 1524 1524 - well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1525 1525 - intel_power_well_enable(dev_priv, well); 1509 1509 + well = lookup_power_well(display, SKL_DISP_PW_1); 1510 1510 + intel_power_well_enable(display, well); 1526 1511 1527 1512 mutex_unlock(&power_domains->lock); 1528 1513 1529 1514 intel_cdclk_init_hw(display); 1530 1515 1531 1531 - gen9_dbuf_enable(dev_priv); 1516 1516 + gen9_dbuf_enable(display); 1532 1517 1533 1518 if (resume) 1534 1519 intel_dmc_load_program(display); 1535 1520 } 1536 1521 1537 1537 - static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 1522 1522 + static void bxt_display_core_uninit(struct intel_display *display) 1538 1523 { 1539 1539 - struct intel_display *display = &dev_priv->display; 1540 1524 struct i915_power_domains *power_domains = &display->power.domains; 1541 1525 struct i915_power_well *well; 1542 1526 1543 1543 - if (!HAS_DISPLAY(dev_priv)) 1527 1527 + if (!HAS_DISPLAY(display)) 1544 1528 return; 1545 1529 1546 1530 gen9_disable_dc_states(display); 1547 1531 /* TODO: disable DMC program */ 1548 1532 1549 1549 - gen9_dbuf_disable(dev_priv); 1533 1533 + gen9_dbuf_disable(display); 1550 1534 1551 1535 intel_cdclk_uninit_hw(display); 1552 1536 ··· 1558 1544 */ 1559 1545 mutex_lock(&power_domains->lock); 1560 1546 1561 1561 - well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1562 1562 - intel_power_well_disable(dev_priv, well); 1547 1547 + well = lookup_power_well(display, SKL_DISP_PW_1); 1548 1548 + intel_power_well_disable(display, well); 1563 1549 1564 1550 mutex_unlock(&power_domains->lock); 1565 1551 ··· 1596 1582 {} 1597 1583 }; 1598 1584 1599 1599 - static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) 1585 1585 + static void tgl_bw_buddy_init(struct intel_display *display) 1600 1586 { 1587 1587 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1601 1588 enum intel_dram_type type = dev_priv->dram_info.type; 1602 1589 u8 num_channels = dev_priv->dram_info.num_channels; 1603 1590 const struct buddy_page_mask *table; 1604 1604 - unsigned long abox_mask = DISPLAY_INFO(dev_priv)->abox_mask; 1591 1591 + unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; 1605 1592 int config, i; 1606 1593 1607 1594 /* BW_BUDDY registers are not used on dgpu's beyond DG1 */ 1608 1608 - if (IS_DGFX(dev_priv) && !IS_DG1(dev_priv)) 1595 1595 + if (display->platform.dgfx && !display->platform.dg1) 1609 1596 return; 1610 1597 1611 1611 - if (IS_ALDERLAKE_S(dev_priv) || 1612 1612 - (IS_ROCKETLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))) 1598 1598 + if (display->platform.alderlake_s || 1599 1599 + (display->platform.rocketlake && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0))) 1613 1600 /* Wa_1409767108 */ 1614 1601 table = wa_1409767108_buddy_page_masks; 1615 1602 else ··· 1622 1607 break; 1623 1608 1624 1609 if (table[config].page_mask == 0) { 1625 1625 - drm_dbg(&dev_priv->drm, 1626 1626 - "Unknown memory configuration; disabling address buddy logic.\n"); 1610 1610 + drm_dbg_kms(display->drm, 1611 1611 + "Unknown memory configuration; disabling address buddy logic.\n"); 1627 1612 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) 1628 1628 - intel_de_write(dev_priv, BW_BUDDY_CTL(i), 1613 1613 + intel_de_write(display, BW_BUDDY_CTL(i), 1629 1614 BW_BUDDY_DISABLE); 1630 1615 } else { 1631 1616 for_each_set_bit(i, &abox_mask, sizeof(abox_mask)) { 1632 1632 - intel_de_write(dev_priv, BW_BUDDY_PAGE_MASK(i), 1617 1617 + intel_de_write(display, BW_BUDDY_PAGE_MASK(i), 1633 1618 table[config].page_mask); 1634 1619 1635 1620 /* Wa_22010178259:tgl,dg1,rkl,adl-s */ 1636 1636 - if (DISPLAY_VER(dev_priv) == 12) 1637 1637 - intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), 1621 1621 + if (DISPLAY_VER(display) == 12) 1622 1622 + intel_de_rmw(display, BW_BUDDY_CTL(i), 1638 1623 BW_BUDDY_TLB_REQ_TIMER_MASK, 1639 1624 BW_BUDDY_TLB_REQ_TIMER(0x8)); 1640 1625 } 1641 1626 } 1642 1627 } 1643 1628 1644 1644 - static void icl_display_core_init(struct drm_i915_private *dev_priv, 1629 1629 + static void icl_display_core_init(struct intel_display *display, 1645 1630 bool resume) 1646 1631 { 1647 1647 - struct intel_display *display = &dev_priv->display; 1632 1632 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1648 1633 struct i915_power_domains *power_domains = &display->power.domains; 1649 1634 struct i915_power_well *well; 1650 1635 ··· 1653 1638 /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ 1654 1639 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && 1655 1640 INTEL_PCH_TYPE(dev_priv) < PCH_DG1) 1656 1656 - intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, 1641 1641 + intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0, 1657 1642 PCH_DPMGUNIT_CLOCK_GATE_DISABLE); 1658 1643 1659 1644 /* 1. Enable PCH reset handshake. */ 1660 1660 - intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); 1645 1645 + intel_pch_reset_handshake(display, !HAS_PCH_NOP(dev_priv)); 1661 1646 1662 1662 - if (!HAS_DISPLAY(dev_priv)) 1647 1647 + if (!HAS_DISPLAY(display)) 1663 1648 return; 1664 1649 1665 1650 /* 2. Initialize all combo phys */ ··· 1670 1655 * The AUX IO power wells will be enabled on demand. 1671 1656 */ 1672 1657 mutex_lock(&power_domains->lock); 1673 1673 - well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1674 1674 - intel_power_well_enable(dev_priv, well); 1658 1658 + well = lookup_power_well(display, SKL_DISP_PW_1); 1659 1659 + intel_power_well_enable(display, well); 1675 1660 mutex_unlock(&power_domains->lock); 1676 1661 1677 1677 - if (DISPLAY_VER(dev_priv) == 14) 1678 1678 - intel_de_rmw(dev_priv, DC_STATE_EN, 1662 1662 + if (DISPLAY_VER(display) == 14) 1663 1663 + intel_de_rmw(display, DC_STATE_EN, 1679 1664 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0); 1680 1665 1681 1666 /* 4. Enable CDCLK. */ 1682 1667 intel_cdclk_init_hw(display); 1683 1668 1684 1684 - if (DISPLAY_VER(dev_priv) >= 12) 1685 1685 - gen12_dbuf_slices_config(dev_priv); 1669 1669 + if (DISPLAY_VER(display) >= 12) 1670 1670 + gen12_dbuf_slices_config(display); 1686 1671 1687 1672 /* 5. Enable DBUF. */ 1688 1688 - gen9_dbuf_enable(dev_priv); 1673 1673 + gen9_dbuf_enable(display); 1689 1674 1690 1675 /* 6. Setup MBUS. */ 1691 1691 - icl_mbus_init(dev_priv); 1676 1676 + icl_mbus_init(display); 1692 1677 1693 1678 /* 7. Program arbiter BW_BUDDY registers */ 1694 1694 - if (DISPLAY_VER(dev_priv) >= 12) 1695 1695 - tgl_bw_buddy_init(dev_priv); 1679 1679 + if (DISPLAY_VER(display) >= 12) 1680 1680 + tgl_bw_buddy_init(display); 1696 1681 1697 1682 /* 8. Ensure PHYs have completed calibration and adaptation */ 1698 1698 - if (IS_DG2(dev_priv)) 1683 1683 + if (display->platform.dg2) 1699 1684 intel_snps_phy_wait_for_calibration(dev_priv); 1700 1685 1701 1686 /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ 1702 1702 - if (DISPLAY_VERx100(dev_priv) == 1401) 1703 1703 - intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); 1687 1687 + if (DISPLAY_VERx100(display) == 1401) 1688 1688 + intel_de_rmw(display, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); 1704 1689 1705 1690 if (resume) 1706 1691 intel_dmc_load_program(display); 1707 1692 1708 1693 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */ 1709 1709 - if (IS_DISPLAY_VERx100(dev_priv, 1200, 1300)) 1710 1710 - intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0, 1694 1694 + if (IS_DISPLAY_VERx100(display, 1200, 1300)) 1695 1695 + intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0, 1711 1696 DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | 1712 1697 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR); 1713 1698 1714 1699 /* Wa_14011503030:xelpd */ 1715 1715 - if (DISPLAY_VER(dev_priv) == 13) 1716 1716 - intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); 1700 1700 + if (DISPLAY_VER(display) == 13) 1701 1701 + intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, ~0); 1717 1702 1718 1703 /* Wa_15013987218 */ 1719 1719 - if (DISPLAY_VER(dev_priv) == 20) { 1720 1720 - intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1704 1704 + if (DISPLAY_VER(display) == 20) { 1705 1705 + intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1721 1706 0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE); 1722 1722 - intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 1707 1707 + intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 1723 1708 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0); 1724 1709 } 1725 1710 } 1726 1711 1727 1727 - static void icl_display_core_uninit(struct drm_i915_private *dev_priv) 1712 1712 + static void icl_display_core_uninit(struct intel_display *display) 1728 1713 { 1729 1729 - struct intel_display *display = &dev_priv->display; 1714 1714 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1730 1715 struct i915_power_domains *power_domains = &display->power.domains; 1731 1716 struct i915_power_well *well; 1732 1717 1733 1733 - if (!HAS_DISPLAY(dev_priv)) 1718 1718 + if (!HAS_DISPLAY(display)) 1734 1719 return; 1735 1720 1736 1721 gen9_disable_dc_states(display); ··· 1739 1724 /* 1. Disable all display engine functions -> aready done */ 1740 1725 1741 1726 /* 2. Disable DBUF */ 1742 1742 - gen9_dbuf_disable(dev_priv); 1727 1727 + gen9_dbuf_disable(display); 1743 1728 1744 1729 /* 3. Disable CD clock */ 1745 1730 intel_cdclk_uninit_hw(display); 1746 1731 1747 1747 - if (DISPLAY_VER(dev_priv) == 14) 1748 1748 - intel_de_rmw(dev_priv, DC_STATE_EN, 0, 1732 1732 + if (DISPLAY_VER(display) == 14) 1733 1733 + intel_de_rmw(display, DC_STATE_EN, 0, 1749 1734 HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH); 1750 1735 1751 1736 /* ··· 1754 1739 * disabled at this point. 1755 1740 */ 1756 1741 mutex_lock(&power_domains->lock); 1757 1757 - well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1758 1758 - intel_power_well_disable(dev_priv, well); 1742 1742 + well = lookup_power_well(display, SKL_DISP_PW_1); 1743 1743 + intel_power_well_disable(display, well); 1759 1744 mutex_unlock(&power_domains->lock); 1760 1745 1761 1746 /* 5. */ 1762 1747 intel_combo_phy_uninit(dev_priv); 1763 1748 } 1764 1749 1765 1765 - static void chv_phy_control_init(struct drm_i915_private *dev_priv) 1750 1750 + static void chv_phy_control_init(struct intel_display *display) 1766 1751 { 1767 1752 struct i915_power_well *cmn_bc = 1768 1768 - lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1753 1753 + lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1769 1754 struct i915_power_well *cmn_d = 1770 1770 - lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); 1755 1755 + lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1771 1756 1772 1757 /* 1773 1758 * DISPLAY_PHY_CONTROL can get corrupted if read. As a ··· 1776 1761 * power well state and lane status to reconstruct the 1777 1762 * expected initial value. 1778 1763 */ 1779 1779 - dev_priv->display.power.chv_phy_control = 1764 1764 + display->power.chv_phy_control = 1780 1765 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 1781 1766 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 1782 1767 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | ··· 1790 1775 * override and set the lane powerdown bits accding to the 1791 1776 * current lane status. 1792 1777 */ 1793 1793 - if (intel_power_well_is_enabled(dev_priv, cmn_bc)) { 1794 1794 - u32 status = intel_de_read(dev_priv, DPLL(dev_priv, PIPE_A)); 1778 1778 + if (intel_power_well_is_enabled(display, cmn_bc)) { 1779 1779 + u32 status = intel_de_read(display, DPLL(display, PIPE_A)); 1795 1780 unsigned int mask; 1796 1781 1797 1782 mask = status & DPLL_PORTB_READY_MASK; 1798 1783 if (mask == 0xf) 1799 1784 mask = 0x0; 1800 1785 else 1801 1801 - dev_priv->display.power.chv_phy_control |= 1786 1786 + display->power.chv_phy_control |= 1802 1787 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 1803 1788 1804 1804 - dev_priv->display.power.chv_phy_control |= 1789 1789 + display->power.chv_phy_control |= 1805 1790 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 1806 1791 1807 1792 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 1808 1793 if (mask == 0xf) 1809 1794 mask = 0x0; 1810 1795 else 1811 1811 - dev_priv->display.power.chv_phy_control |= 1796 1796 + display->power.chv_phy_control |= 1812 1797 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 1813 1798 1814 1814 - dev_priv->display.power.chv_phy_control |= 1799 1799 + display->power.chv_phy_control |= 1815 1800 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 1816 1801 1817 1817 - dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 1802 1802 + display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 1818 1803 1819 1819 - dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false; 1804 1804 + display->power.chv_phy_assert[DPIO_PHY0] = false; 1820 1805 } else { 1821 1821 - dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true; 1806 1806 + display->power.chv_phy_assert[DPIO_PHY0] = true; 1822 1807 } 1823 1808 1824 1824 - if (intel_power_well_is_enabled(dev_priv, cmn_d)) { 1825 1825 - u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS); 1809 1809 + if (intel_power_well_is_enabled(display, cmn_d)) { 1810 1810 + u32 status = intel_de_read(display, DPIO_PHY_STATUS); 1826 1811 unsigned int mask; 1827 1812 1828 1813 mask = status & DPLL_PORTD_READY_MASK; ··· 1830 1815 if (mask == 0xf) 1831 1816 mask = 0x0; 1832 1817 else 1833 1833 - dev_priv->display.power.chv_phy_control |= 1818 1818 + display->power.chv_phy_control |= 1834 1819 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 1835 1820 1836 1836 - dev_priv->display.power.chv_phy_control |= 1821 1821 + display->power.chv_phy_control |= 1837 1822 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 1838 1823 1839 1839 - dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 1824 1824 + display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 1840 1825 1841 1841 - dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false; 1826 1826 + display->power.chv_phy_assert[DPIO_PHY1] = false; 1842 1827 } else { 1843 1843 - dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true; 1828 1828 + display->power.chv_phy_assert[DPIO_PHY1] = true; 1844 1829 } 1845 1830 1846 1846 - drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n", 1847 1847 - dev_priv->display.power.chv_phy_control); 1831 1831 + drm_dbg_kms(display->drm, "Initial PHY_CONTROL=0x%08x\n", 1832 1832 + display->power.chv_phy_control); 1848 1833 1849 1834 /* Defer application of initial phy_control to enabling the powerwell */ 1850 1835 } 1851 1836 1852 1852 - static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 1837 1837 + static void vlv_cmnlane_wa(struct intel_display *display) 1853 1838 { 1854 1839 struct i915_power_well *cmn = 1855 1855 - lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1840 1840 + lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1856 1841 struct i915_power_well *disp2d = 1857 1857 - lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D); 1842 1842 + lookup_power_well(display, VLV_DISP_PW_DISP2D); 1858 1843 1859 1844 /* If the display might be already active skip this */ 1860 1860 - if (intel_power_well_is_enabled(dev_priv, cmn) && 1861 1861 - intel_power_well_is_enabled(dev_priv, disp2d) && 1862 1862 - intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST) 1845 1845 + if (intel_power_well_is_enabled(display, cmn) && 1846 1846 + intel_power_well_is_enabled(display, disp2d) && 1847 1847 + intel_de_read(display, DPIO_CTL) & DPIO_CMNRST) 1863 1848 return; 1864 1849 1865 1865 - drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n"); 1850 1850 + drm_dbg_kms(display->drm, "toggling display PHY side reset\n"); 1866 1851 1867 1852 /* cmnlane needs DPLL registers */ 1868 1868 - intel_power_well_enable(dev_priv, disp2d); 1853 1853 + intel_power_well_enable(display, disp2d); 1869 1854 1870 1855 /* 1871 1856 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: ··· 1874 1859 * Simply ungating isn't enough to reset the PHY enough to get 1875 1860 * ports and lanes running. 1876 1861 */ 1877 1877 - intel_power_well_disable(dev_priv, cmn); 1862 1862 + intel_power_well_disable(display, cmn); 1878 1863 } 1879 1864 1880 1880 - static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0) 1865 1865 + static bool vlv_punit_is_power_gated(struct intel_display *display, u32 reg0) 1881 1866 { 1867 1867 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1882 1868 bool ret; 1883 1869 1884 1870 vlv_punit_get(dev_priv); ··· 1889 1873 return ret; 1890 1874 } 1891 1875 1892 1892 - static void assert_ved_power_gated(struct drm_i915_private *dev_priv) 1876 1876 + static void assert_ved_power_gated(struct intel_display *display) 1893 1877 { 1894 1894 - drm_WARN(&dev_priv->drm, 1895 1895 - !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0), 1878 1878 + drm_WARN(display->drm, 1879 1879 + !vlv_punit_is_power_gated(display, PUNIT_REG_VEDSSPM0), 1896 1880 "VED not power gated\n"); 1897 1881 } 1898 1882 1899 1899 - static void assert_isp_power_gated(struct drm_i915_private *dev_priv) 1883 1883 + static void assert_isp_power_gated(struct intel_display *display) 1900 1884 { 1901 1885 static const struct pci_device_id isp_ids[] = { 1902 1886 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)}, ··· 1904 1888 {} 1905 1889 }; 1906 1890 1907 1907 - drm_WARN(&dev_priv->drm, !pci_dev_present(isp_ids) && 1908 1908 - !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0), 1891 1891 + drm_WARN(display->drm, !pci_dev_present(isp_ids) && 1892 1892 + !vlv_punit_is_power_gated(display, PUNIT_REG_ISPSSPM0), 1909 1893 "ISP not power gated\n"); 1910 1894 } 1911 1895 1912 1912 - static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); 1896 1896 + static void intel_power_domains_verify_state(struct intel_display *display); 1913 1897 1914 1898 /** 1915 1899 * intel_power_domains_init_hw - initialize hardware power domain state 1916 1916 - * @i915: i915 device instance 1900 1900 + * @display: display device instance 1917 1901 * @resume: Called from resume code paths or not 1918 1902 * 1919 1903 * This function initializes the hardware power domain state and enables all ··· 1927 1911 * intel_power_domains_enable()) and must be paired with 1928 1912 * intel_power_domains_driver_remove(). 1929 1913 */ 1930 1930 - void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) 1914 1914 + void intel_power_domains_init_hw(struct intel_display *display, bool resume) 1931 1915 { 1932 1932 - struct i915_power_domains *power_domains = &i915->display.power.domains; 1916 1916 + struct drm_i915_private *i915 = to_i915(display->drm); 1917 1917 + struct i915_power_domains *power_domains = &display->power.domains; 1933 1918 1934 1919 power_domains->initializing = true; 1935 1920 1936 1936 - if (DISPLAY_VER(i915) >= 11) { 1937 1937 - icl_display_core_init(i915, resume); 1938 1938 - } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 1939 1939 - bxt_display_core_init(i915, resume); 1940 1940 - } else if (DISPLAY_VER(i915) == 9) { 1941 1941 - skl_display_core_init(i915, resume); 1942 1942 - } else if (IS_CHERRYVIEW(i915)) { 1921 1921 + if (DISPLAY_VER(display) >= 11) { 1922 1922 + icl_display_core_init(display, resume); 1923 1923 + } else if (display->platform.geminilake || display->platform.broxton) { 1924 1924 + bxt_display_core_init(display, resume); 1925 1925 + } else if (DISPLAY_VER(display) == 9) { 1926 1926 + skl_display_core_init(display, resume); 1927 1927 + } else if (display->platform.cherryview) { 1943 1928 mutex_lock(&power_domains->lock); 1944 1944 - chv_phy_control_init(i915); 1929 1929 + chv_phy_control_init(display); 1945 1930 mutex_unlock(&power_domains->lock); 1946 1946 - assert_isp_power_gated(i915); 1947 1947 - } else if (IS_VALLEYVIEW(i915)) { 1931 1931 + assert_isp_power_gated(display); 1932 1932 + } else if (display->platform.valleyview) { 1948 1933 mutex_lock(&power_domains->lock); 1949 1949 - vlv_cmnlane_wa(i915); 1934 1934 + vlv_cmnlane_wa(display); 1950 1935 mutex_unlock(&power_domains->lock); 1951 1951 - assert_ved_power_gated(i915); 1952 1952 - assert_isp_power_gated(i915); 1953 1953 - } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) { 1954 1954 - hsw_assert_cdclk(i915); 1955 1955 - intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); 1956 1956 - } else if (IS_IVYBRIDGE(i915)) { 1957 1957 - intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); 1936 1936 + assert_ved_power_gated(display); 1937 1937 + assert_isp_power_gated(display); 1938 1938 + } else if (display->platform.broadwell || display->platform.haswell) { 1939 1939 + hsw_assert_cdclk(display); 1940 1940 + intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915)); 1941 1941 + } else if (display->platform.ivybridge) { 1942 1942 + intel_pch_reset_handshake(display, !HAS_PCH_NOP(i915)); 1958 1943 } 1959 1944 1960 1945 /* ··· 1964 1947 * resources powered until display HW readout is complete. We drop 1965 1948 * this reference in intel_power_domains_enable(). 1966 1949 */ 1967 1967 - drm_WARN_ON(&i915->drm, power_domains->init_wakeref); 1950 1950 + drm_WARN_ON(display->drm, power_domains->init_wakeref); 1968 1951 power_domains->init_wakeref = 1969 1952 intel_display_power_get(i915, POWER_DOMAIN_INIT); 1970 1953 1971 1954 /* Disable power support if the user asked so. */ 1972 1972 - if (!i915->display.params.disable_power_well) { 1973 1973 - drm_WARN_ON(&i915->drm, power_domains->disable_wakeref); 1974 1974 - i915->display.power.domains.disable_wakeref = intel_display_power_get(i915, 1975 1975 - POWER_DOMAIN_INIT); 1955 1955 + if (!display->params.disable_power_well) { 1956 1956 + drm_WARN_ON(display->drm, power_domains->disable_wakeref); 1957 1957 + display->power.domains.disable_wakeref = intel_display_power_get(i915, 1958 1958 + POWER_DOMAIN_INIT); 1976 1959 } 1977 1977 - intel_power_domains_sync_hw(i915); 1960 1960 + intel_power_domains_sync_hw(display); 1978 1961 1979 1962 power_domains->initializing = false; 1980 1963 } 1981 1964 1982 1965 /** 1983 1966 * intel_power_domains_driver_remove - deinitialize hw power domain state 1984 1984 - * @i915: i915 device instance 1967 1967 + * @display: display device instance 1985 1968 * 1986 1969 * De-initializes the display power domain HW state. It also ensures that the 1987 1970 * device stays powered up so that the driver can be reloaded. ··· 1990 1973 * intel_power_domains_disable()) and must be paired with 1991 1974 * intel_power_domains_init_hw(). 1992 1975 */ 1993 1993 - void intel_power_domains_driver_remove(struct drm_i915_private *i915) 1976 1976 + void intel_power_domains_driver_remove(struct intel_display *display) 1994 1977 { 1978 1978 + struct drm_i915_private *i915 = to_i915(display->drm); 1995 1979 intel_wakeref_t wakeref __maybe_unused = 1996 1996 - fetch_and_zero(&i915->display.power.domains.init_wakeref); 1980 1980 + fetch_and_zero(&display->power.domains.init_wakeref); 1997 1981 1998 1982 /* Remove the refcount we took to keep power well support disabled. */ 1999 1999 - if (!i915->display.params.disable_power_well) 1983 1983 + if (!display->params.disable_power_well) 2000 1984 intel_display_power_put(i915, POWER_DOMAIN_INIT, 2001 2001 - fetch_and_zero(&i915->display.power.domains.disable_wakeref)); 1985 1985 + fetch_and_zero(&display->power.domains.disable_wakeref)); 2002 1986 2003 2003 - intel_display_power_flush_work_sync(i915); 1987 1987 + intel_display_power_flush_work_sync(display); 2004 1988 2005 2005 - intel_power_domains_verify_state(i915); 1989 1989 + intel_power_domains_verify_state(display); 2006 1990 2007 1991 /* Keep the power well enabled, but cancel its rpm wakeref. */ 2008 1992 intel_runtime_pm_put(&i915->runtime_pm, wakeref); ··· 2011 1993 2012 1994 /** 2013 1995 * intel_power_domains_sanitize_state - sanitize power domains state 2014 2014 - * @i915: i915 device instance 1996 1996 + * @display: display device instance 2015 1997 * 2016 1998 * Sanitize the power domains state during driver loading and system resume. 2017 1999 * The function will disable all display power wells that BIOS has enabled ··· 2019 2001 * on it by the time this function is called, after the state of all the 2020 2002 * pipe, encoder, etc. HW resources have been sanitized). 2021 2003 */ 2022 2022 - void intel_power_domains_sanitize_state(struct drm_i915_private *i915) 2004 2004 + void intel_power_domains_sanitize_state(struct intel_display *display) 2023 2005 { 2024 2024 - struct i915_power_domains *power_domains = &i915->display.power.domains; 2006 2006 + struct i915_power_domains *power_domains = &display->power.domains; 2025 2007 struct i915_power_well *power_well; 2026 2008 2027 2009 mutex_lock(&power_domains->lock); 2028 2010 2029 2029 - for_each_power_well_reverse(i915, power_well) { 2011 2011 + for_each_power_well_reverse(display, power_well) { 2030 2012 if (power_well->desc->always_on || power_well->count || 2031 2031 - !intel_power_well_is_enabled(i915, power_well)) 2013 2013 + !intel_power_well_is_enabled(display, power_well)) 2032 2014 continue; 2033 2015 2034 2034 - drm_dbg_kms(&i915->drm, 2016 2016 + drm_dbg_kms(display->drm, 2035 2017 "BIOS left unused %s power well enabled, disabling it\n", 2036 2018 intel_power_well_name(power_well)); 2037 2037 - intel_power_well_disable(i915, power_well); 2019 2019 + intel_power_well_disable(display, power_well); 2038 2020 } 2039 2021 2040 2022 mutex_unlock(&power_domains->lock); ··· 2042 2024 2043 2025 /** 2044 2026 * intel_power_domains_enable - enable toggling of display power wells 2045 2045 - * @i915: i915 device instance 2027 2027 + * @display: display device instance 2046 2028 * 2047 2029 * Enable the ondemand enabling/disabling of the display power wells. Note that 2048 2030 * power wells not belonging to POWER_DOMAIN_INIT are allowed to be toggled ··· 2052 2034 * of display HW readout (which will acquire the power references reflecting 2053 2035 * the current HW state). 2054 2036 */ 2055 2055 - void intel_power_domains_enable(struct drm_i915_private *i915) 2037 2037 + void intel_power_domains_enable(struct intel_display *display) 2056 2038 { 2039 2039 + struct drm_i915_private *i915 = to_i915(display->drm); 2057 2040 intel_wakeref_t wakeref __maybe_unused = 2058 2058 - fetch_and_zero(&i915->display.power.domains.init_wakeref); 2041 2041 + fetch_and_zero(&display->power.domains.init_wakeref); 2059 2042 2060 2043 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 2061 2061 - intel_power_domains_verify_state(i915); 2044 2044 + intel_power_domains_verify_state(display); 2062 2045 } 2063 2046 2064 2047 /** 2065 2048 * intel_power_domains_disable - disable toggling of display power wells 2066 2066 - * @i915: i915 device instance 2049 2049 + * @display: display device instance 2067 2050 * 2068 2051 * Disable the ondemand enabling/disabling of the display power wells. See 2069 2052 * intel_power_domains_enable() for which power wells this call controls. 2070 2053 */ 2071 2071 - void intel_power_domains_disable(struct drm_i915_private *i915) 2054 2054 + void intel_power_domains_disable(struct intel_display *display) 2072 2055 { 2073 2073 - struct i915_power_domains *power_domains = &i915->display.power.domains; 2056 2056 + struct drm_i915_private *i915 = to_i915(display->drm); 2057 2057 + struct i915_power_domains *power_domains = &display->power.domains; 2074 2058 2075 2075 - drm_WARN_ON(&i915->drm, power_domains->init_wakeref); 2059 2059 + drm_WARN_ON(display->drm, power_domains->init_wakeref); 2076 2060 power_domains->init_wakeref = 2077 2061 intel_display_power_get(i915, POWER_DOMAIN_INIT); 2078 2062 2079 2079 - intel_power_domains_verify_state(i915); 2063 2063 + intel_power_domains_verify_state(display); 2080 2064 } 2081 2065 2082 2066 /** 2083 2067 * intel_power_domains_suspend - suspend power domain state 2084 2084 - * @i915: i915 device instance 2068 2068 + * @display: display device instance 2085 2069 * @s2idle: specifies whether we go to idle, or deeper sleep 2086 2070 * 2087 2071 * This function prepares the hardware power domain state before entering ··· 2092 2072 * It must be called with power domains already disabled (after a call to 2093 2073 * intel_power_domains_disable()) and paired with intel_power_domains_resume(). 2094 2074 */ 2095 2095 - void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle) 2075 2075 + void intel_power_domains_suspend(struct intel_display *display, bool s2idle) 2096 2076 { 2097 2097 - struct intel_display *display = &i915->display; 2077 2077 + struct drm_i915_private *i915 = to_i915(display->drm); 2098 2078 struct i915_power_domains *power_domains = &display->power.domains; 2099 2079 intel_wakeref_t wakeref __maybe_unused = 2100 2080 fetch_and_zero(&power_domains->init_wakeref); ··· 2111 2091 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle && 2112 2092 intel_dmc_has_payload(display)) { 2113 2093 intel_display_power_flush_work(i915); 2114 2114 - intel_power_domains_verify_state(i915); 2094 2094 + intel_power_domains_verify_state(display); 2115 2095 return; 2116 2096 } 2117 2097 ··· 2119 2099 * Even if power well support was disabled we still want to disable 2120 2100 * power wells if power domains must be deinitialized for suspend. 2121 2101 */ 2122 2122 - if (!i915->display.params.disable_power_well) 2102 2102 + if (!display->params.disable_power_well) 2123 2103 intel_display_power_put(i915, POWER_DOMAIN_INIT, 2124 2124 - fetch_and_zero(&i915->display.power.domains.disable_wakeref)); 2104 2104 + fetch_and_zero(&display->power.domains.disable_wakeref)); 2125 2105 2126 2106 intel_display_power_flush_work(i915); 2127 2127 - intel_power_domains_verify_state(i915); 2107 2107 + intel_power_domains_verify_state(display); 2128 2108 2129 2129 - if (DISPLAY_VER(i915) >= 11) 2130 2130 - icl_display_core_uninit(i915); 2131 2131 - else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 2132 2132 - bxt_display_core_uninit(i915); 2133 2133 - else if (DISPLAY_VER(i915) == 9) 2134 2134 - skl_display_core_uninit(i915); 2109 2109 + if (DISPLAY_VER(display) >= 11) 2110 2110 + icl_display_core_uninit(display); 2111 2111 + else if (display->platform.geminilake || display->platform.broxton) 2112 2112 + bxt_display_core_uninit(display); 2113 2113 + else if (DISPLAY_VER(display) == 9) 2114 2114 + skl_display_core_uninit(display); 2135 2115 2136 2116 power_domains->display_core_suspended = true; 2137 2117 } 2138 2118 2139 2119 /** 2140 2120 * intel_power_domains_resume - resume power domain state 2141 2141 - * @i915: i915 device instance 2121 2121 + * @display: display device instance 2142 2122 * 2143 2123 * This function resume the hardware power domain state during system resume. 2144 2124 * ··· 2146 2126 * intel_power_domains_enable()) and must be paired with 2147 2127 * intel_power_domains_suspend(). 2148 2128 */ 2149 2149 - void intel_power_domains_resume(struct drm_i915_private *i915) 2129 2129 + void intel_power_domains_resume(struct intel_display *display) 2150 2130 { 2151 2151 - struct i915_power_domains *power_domains = &i915->display.power.domains; 2131 2131 + struct drm_i915_private *i915 = to_i915(display->drm); 2132 2132 + struct i915_power_domains *power_domains = &display->power.domains; 2152 2133 2153 2134 if (power_domains->display_core_suspended) { 2154 2154 - intel_power_domains_init_hw(i915, true); 2135 2135 + intel_power_domains_init_hw(display, true); 2155 2136 power_domains->display_core_suspended = false; 2156 2137 } else { 2157 2157 - drm_WARN_ON(&i915->drm, power_domains->init_wakeref); 2138 2138 + drm_WARN_ON(display->drm, power_domains->init_wakeref); 2158 2139 power_domains->init_wakeref = 2159 2140 intel_display_power_get(i915, POWER_DOMAIN_INIT); 2160 2141 } 2161 2142 2162 2162 - intel_power_domains_verify_state(i915); 2143 2143 + intel_power_domains_verify_state(display); 2163 2144 } 2164 2145 2165 2146 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 2166 2147 2167 2167 - static void intel_power_domains_dump_info(struct drm_i915_private *i915) 2148 2148 + static void intel_power_domains_dump_info(struct intel_display *display) 2168 2149 { 2169 2169 - struct i915_power_domains *power_domains = &i915->display.power.domains; 2150 2150 + struct i915_power_domains *power_domains = &display->power.domains; 2170 2151 struct i915_power_well *power_well; 2171 2152 2172 2172 - for_each_power_well(i915, power_well) { 2153 2153 + for_each_power_well(display, power_well) { 2173 2154 enum intel_display_power_domain domain; 2174 2155 2175 2175 - drm_dbg(&i915->drm, "%-25s %d\n", 2176 2176 - intel_power_well_name(power_well), intel_power_well_refcount(power_well)); 2156 2156 + drm_dbg_kms(display->drm, "%-25s %d\n", 2157 2157 + intel_power_well_name(power_well), intel_power_well_refcount(power_well)); 2177 2158 2178 2159 for_each_power_domain(domain, intel_power_well_domains(power_well)) 2179 2179 - drm_dbg(&i915->drm, " %-23s %d\n", 2180 2180 - intel_display_power_domain_str(domain), 2181 2181 - power_domains->domain_use_count[domain]); 2160 2160 + drm_dbg_kms(display->drm, " %-23s %d\n", 2161 2161 + intel_display_power_domain_str(domain), 2162 2162 + power_domains->domain_use_count[domain]); 2182 2163 } 2183 2164 } 2184 2165 2185 2166 /** 2186 2167 * intel_power_domains_verify_state - verify the HW/SW state for all power wells 2187 2187 - * @i915: i915 device instance 2168 2168 + * @display: display device instance 2188 2169 * 2189 2170 * Verify if the reference count of each power well matches its HW enabled 2190 2171 * state and the total refcount of the domains it belongs to. This must be ··· 2193 2172 * acquiring reference counts for any power wells in use and disabling the 2194 2173 * ones left on by BIOS but not required by any active output. 2195 2174 */ 2196 2196 - static void intel_power_domains_verify_state(struct drm_i915_private *i915) 2175 2175 + static void intel_power_domains_verify_state(struct intel_display *display) 2197 2176 { 2198 2198 - struct i915_power_domains *power_domains = &i915->display.power.domains; 2177 2177 + struct i915_power_domains *power_domains = &display->power.domains; 2199 2178 struct i915_power_well *power_well; 2200 2179 bool dump_domain_info; 2201 2180 ··· 2204 2183 verify_async_put_domains_state(power_domains); 2205 2184 2206 2185 dump_domain_info = false; 2207 2207 - for_each_power_well(i915, power_well) { 2186 2186 + for_each_power_well(display, power_well) { 2208 2187 enum intel_display_power_domain domain; 2209 2188 int domains_count; 2210 2189 bool enabled; 2211 2190 2212 2212 - enabled = intel_power_well_is_enabled(i915, power_well); 2191 2191 + enabled = intel_power_well_is_enabled(display, power_well); 2213 2192 if ((intel_power_well_refcount(power_well) || 2214 2193 intel_power_well_is_always_on(power_well)) != 2215 2194 enabled) 2216 2216 - drm_err(&i915->drm, 2195 2195 + drm_err(display->drm, 2217 2196 "power well %s state mismatch (refcount %d/enabled %d)", 2218 2197 intel_power_well_name(power_well), 2219 2198 intel_power_well_refcount(power_well), enabled); ··· 2223 2202 domains_count += power_domains->domain_use_count[domain]; 2224 2203 2225 2204 if (intel_power_well_refcount(power_well) != domains_count) { 2226 2226 - drm_err(&i915->drm, 2205 2205 + drm_err(display->drm, 2227 2206 "power well %s refcount/domain refcount mismatch " 2228 2207 "(refcount %d/domains refcount %d)\n", 2229 2208 intel_power_well_name(power_well), ··· 2237 2216 static bool dumped; 2238 2217 2239 2218 if (!dumped) { 2240 2240 - intel_power_domains_dump_info(i915); 2219 2219 + intel_power_domains_dump_info(display); 2241 2220 dumped = true; 2242 2221 } 2243 2222 } ··· 2247 2226 2248 2227 #else 2249 2228 2250 2250 - static void intel_power_domains_verify_state(struct drm_i915_private *i915) 2229 2229 + static void intel_power_domains_verify_state(struct intel_display *display) 2251 2230 { 2252 2231 } 2253 2232 2254 2233 #endif 2255 2234 2256 2256 - void intel_display_power_suspend_late(struct drm_i915_private *i915) 2235 2235 + void intel_display_power_suspend_late(struct intel_display *display, bool s2idle) 2257 2236 { 2258 2258 - struct intel_display *display = &i915->display; 2237 2237 + struct drm_i915_private *i915 = to_i915(display->drm); 2259 2238 2260 2260 - if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || 2261 2261 - IS_BROXTON(i915)) { 2239 2239 + intel_power_domains_suspend(display, s2idle); 2240 2240 + 2241 2241 + if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || 2242 2242 + display->platform.broxton) { 2262 2243 bxt_enable_dc9(display); 2263 2263 - } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2264 2264 - hsw_enable_pc8(i915); 2244 2244 + } else if (display->platform.haswell || display->platform.broadwell) { 2245 2245 + hsw_enable_pc8(display); 2265 2246 } 2266 2247 2267 2248 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ ··· 2271 2248 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS); 2272 2249 } 2273 2250 2274 2274 - void intel_display_power_resume_early(struct drm_i915_private *i915) 2251 2251 + void intel_display_power_resume_early(struct intel_display *display) 2275 2252 { 2276 2276 - struct intel_display *display = &i915->display; 2253 2253 + struct drm_i915_private *i915 = to_i915(display->drm); 2277 2254 2278 2278 - if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || 2279 2279 - IS_BROXTON(i915)) { 2255 2255 + if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || 2256 2256 + display->platform.broxton) { 2280 2257 gen9_sanitize_dc_state(display); 2281 2258 bxt_disable_dc9(display); 2282 2282 - } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2283 2283 - hsw_disable_pc8(i915); 2259 2259 + } else if (display->platform.haswell || display->platform.broadwell) { 2260 2260 + hsw_disable_pc8(display); 2284 2261 } 2285 2262 2286 2263 /* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */ 2287 2264 if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1) 2288 2265 intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0); 2266 2266 + 2267 2267 + intel_power_domains_resume(display); 2289 2268 } 2290 2269 2291 2291 - void intel_display_power_suspend(struct drm_i915_private *i915) 2270 2270 + void intel_display_power_suspend(struct intel_display *display) 2292 2271 { 2293 2293 - struct intel_display *display = &i915->display; 2294 2294 - 2295 2295 - if (DISPLAY_VER(i915) >= 11) { 2296 2296 - icl_display_core_uninit(i915); 2272 2272 + if (DISPLAY_VER(display) >= 11) { 2273 2273 + icl_display_core_uninit(display); 2297 2274 bxt_enable_dc9(display); 2298 2298 - } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 2299 2299 - bxt_display_core_uninit(i915); 2275 2275 + } else if (display->platform.geminilake || display->platform.broxton) { 2276 2276 + bxt_display_core_uninit(display); 2300 2277 bxt_enable_dc9(display); 2301 2301 - } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2302 2302 - hsw_enable_pc8(i915); 2278 2278 + } else if (display->platform.haswell || display->platform.broadwell) { 2279 2279 + hsw_enable_pc8(display); 2303 2280 } 2304 2281 } 2305 2282 2306 2306 - void intel_display_power_resume(struct drm_i915_private *i915) 2283 2283 + void intel_display_power_resume(struct intel_display *display) 2307 2284 { 2308 2308 - struct intel_display *display = &i915->display; 2309 2285 struct i915_power_domains *power_domains = &display->power.domains; 2310 2286 2311 2311 - if (DISPLAY_VER(i915) >= 11) { 2287 2287 + if (DISPLAY_VER(display) >= 11) { 2312 2288 bxt_disable_dc9(display); 2313 2313 - icl_display_core_init(i915, true); 2289 2289 + icl_display_core_init(display, true); 2314 2290 if (intel_dmc_has_payload(display)) { 2315 2291 if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 2316 2292 skl_enable_dc6(display); 2317 2293 else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 2318 2294 gen9_enable_dc5(display); 2319 2295 } 2320 2320 - } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 2296 2296 + } else if (display->platform.geminilake || display->platform.broxton) { 2321 2297 bxt_disable_dc9(display); 2322 2322 - bxt_display_core_init(i915, true); 2298 2298 + bxt_display_core_init(display, true); 2323 2299 if (intel_dmc_has_payload(display) && 2324 2300 (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) 2325 2301 gen9_enable_dc5(display); 2326 2326 - } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2327 2327 - hsw_disable_pc8(i915); 2302 2302 + } else if (display->platform.haswell || display->platform.broadwell) { 2303 2303 + hsw_disable_pc8(display); 2328 2304 } 2329 2305 } 2330 2306 2331 2307 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m) 2332 2308 { 2333 2333 - struct i915_power_domains *power_domains = &i915->display.power.domains; 2309 2309 + struct intel_display *display = &i915->display; 2310 2310 + struct i915_power_domains *power_domains = &display->power.domains; 2334 2311 int i; 2335 2312 2336 2313 mutex_lock(&power_domains->lock); ··· 2475 2452 }; 2476 2453 2477 2454 static void 2478 2478 - intel_port_domains_for_platform(struct drm_i915_private *i915, 2455 2455 + intel_port_domains_for_platform(struct intel_display *display, 2479 2456 const struct intel_ddi_port_domains **domains, 2480 2457 int *domains_size) 2481 2458 { 2482 2482 - if (DISPLAY_VER(i915) >= 13) { 2459 2459 + if (DISPLAY_VER(display) >= 13) { 2483 2460 *domains = d13_port_domains; 2484 2461 *domains_size = ARRAY_SIZE(d13_port_domains); 2485 2485 - } else if (DISPLAY_VER(i915) >= 12) { 2462 2462 + } else if (DISPLAY_VER(display) >= 12) { 2486 2463 *domains = d12_port_domains; 2487 2464 *domains_size = ARRAY_SIZE(d12_port_domains); 2488 2488 - } else if (DISPLAY_VER(i915) >= 11) { 2465 2465 + } else if (DISPLAY_VER(display) >= 11) { 2489 2466 *domains = d11_port_domains; 2490 2467 *domains_size = ARRAY_SIZE(d11_port_domains); 2491 2468 } else { ··· 2495 2472 } 2496 2473 2497 2474 static const struct intel_ddi_port_domains * 2498 2498 - intel_port_domains_for_port(struct drm_i915_private *i915, enum port port) 2475 2475 + intel_port_domains_for_port(struct intel_display *display, enum port port) 2499 2476 { 2500 2477 const struct intel_ddi_port_domains *domains; 2501 2478 int domains_size; 2502 2479 int i; 2503 2480 2504 2504 - intel_port_domains_for_platform(i915, &domains, &domains_size); 2481 2481 + intel_port_domains_for_platform(display, &domains, &domains_size); 2505 2482 for (i = 0; i < domains_size; i++) 2506 2483 if (port >= domains[i].port_start && port <= domains[i].port_end) 2507 2484 return &domains[i]; ··· 2512 2489 enum intel_display_power_domain 2513 2490 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port) 2514 2491 { 2515 2515 - const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port); 2492 2492 + struct intel_display *display = &i915->display; 2493 2493 + const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); 2516 2494 2517 2517 - if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) 2495 2495 + if (drm_WARN_ON(display->drm, !domains || domains->ddi_io == POWER_DOMAIN_INVALID)) 2518 2496 return POWER_DOMAIN_PORT_DDI_IO_A; 2519 2497 2520 2498 return domains->ddi_io + (int)(port - domains->port_start); ··· 2524 2500 enum intel_display_power_domain 2525 2501 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port) 2526 2502 { 2527 2527 - const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port); 2503 2503 + struct intel_display *display = &i915->display; 2504 2504 + const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(display, port); 2528 2505 2529 2529 - if (drm_WARN_ON(&i915->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) 2506 2506 + if (drm_WARN_ON(display->drm, !domains || domains->ddi_lanes == POWER_DOMAIN_INVALID)) 2530 2507 return POWER_DOMAIN_PORT_DDI_LANES_A; 2531 2508 2532 2509 return domains->ddi_lanes + (int)(port - domains->port_start); 2533 2510 } 2534 2511 2535 2512 static const struct intel_ddi_port_domains * 2536 2536 - intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch) 2513 2513 + intel_port_domains_for_aux_ch(struct intel_display *display, enum aux_ch aux_ch) 2537 2514 { 2538 2515 const struct intel_ddi_port_domains *domains; 2539 2516 int domains_size; 2540 2517 int i; 2541 2518 2542 2542 - intel_port_domains_for_platform(i915, &domains, &domains_size); 2519 2519 + intel_port_domains_for_platform(display, &domains, &domains_size); 2543 2520 for (i = 0; i < domains_size; i++) 2544 2521 if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end) 2545 2522 return &domains[i]; ··· 2551 2526 enum intel_display_power_domain 2552 2527 intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2553 2528 { 2554 2554 - const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch); 2529 2529 + struct intel_display *display = &i915->display; 2530 2530 + const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2555 2531 2556 2556 - if (drm_WARN_ON(&i915->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) 2532 2532 + if (drm_WARN_ON(display->drm, !domains || domains->aux_io == POWER_DOMAIN_INVALID)) 2557 2533 return POWER_DOMAIN_AUX_IO_A; 2558 2534 2559 2535 return domains->aux_io + (int)(aux_ch - domains->aux_ch_start); ··· 2563 2537 enum intel_display_power_domain 2564 2538 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2565 2539 { 2566 2566 - const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch); 2540 2540 + struct intel_display *display = &i915->display; 2541 2541 + const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2567 2542 2568 2568 - if (drm_WARN_ON(&i915->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) 2543 2543 + if (drm_WARN_ON(display->drm, !domains || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)) 2569 2544 return POWER_DOMAIN_AUX_A; 2570 2545 2571 2546 return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start); ··· 2575 2548 enum intel_display_power_domain 2576 2549 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch) 2577 2550 { 2578 2578 - const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch); 2551 2551 + struct intel_display *display = &i915->display; 2552 2552 + const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(display, aux_ch); 2579 2553 2580 2580 - if (drm_WARN_ON(&i915->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) 2554 2554 + if (drm_WARN_ON(display->drm, !domains || domains->aux_tbt == POWER_DOMAIN_INVALID)) 2581 2555 return POWER_DOMAIN_AUX_TBT1; 2582 2556 2583 2557 return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start);

+15 -14

drivers/gpu/drm/i915/display/intel_display_power.h

reviewed

··· 15 15 enum port; 16 16 struct drm_i915_private; 17 17 struct i915_power_well; 18 18 + struct intel_display; 18 19 struct intel_encoder; 19 20 struct seq_file; 20 21 ··· 167 166 for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \ 168 167 for_each_if(test_bit((__domain), (__mask)->bits)) 169 168 170 170 - int intel_power_domains_init(struct drm_i915_private *dev_priv); 171 171 - void intel_power_domains_cleanup(struct drm_i915_private *dev_priv); 172 172 - void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume); 173 173 - void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv); 174 174 - void intel_power_domains_enable(struct drm_i915_private *dev_priv); 175 175 - void intel_power_domains_disable(struct drm_i915_private *dev_priv); 176 176 - void intel_power_domains_suspend(struct drm_i915_private *dev_priv, bool s2idle); 177 177 - void intel_power_domains_resume(struct drm_i915_private *dev_priv); 178 178 - void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv); 169 169 + int intel_power_domains_init(struct intel_display *display); 170 170 + void intel_power_domains_cleanup(struct intel_display *display); 171 171 + void intel_power_domains_init_hw(struct intel_display *display, bool resume); 172 172 + void intel_power_domains_driver_remove(struct intel_display *display); 173 173 + void intel_power_domains_enable(struct intel_display *display); 174 174 + void intel_power_domains_disable(struct intel_display *display); 175 175 + void intel_power_domains_suspend(struct intel_display *display, bool s2idle); 176 176 + void intel_power_domains_resume(struct intel_display *display); 177 177 + void intel_power_domains_sanitize_state(struct intel_display *display); 179 178 180 180 - void intel_display_power_suspend_late(struct drm_i915_private *i915); 181 181 - void intel_display_power_resume_early(struct drm_i915_private *i915); 182 182 - void intel_display_power_suspend(struct drm_i915_private *i915); 183 183 - void intel_display_power_resume(struct drm_i915_private *i915); 184 184 - void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 179 179 + void intel_display_power_suspend_late(struct intel_display *display, bool s2idle); 180 180 + void intel_display_power_resume_early(struct intel_display *display); 181 181 + void intel_display_power_suspend(struct intel_display *display); 182 182 + void intel_display_power_resume(struct intel_display *display); 183 183 + void intel_display_power_set_target_dc_state(struct intel_display *display, 185 184 u32 state); 186 185 187 186 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,

+28 -28

drivers/gpu/drm/i915/display/intel_display_power_map.c

reviewed

··· 1752 1752 const struct i915_power_well_desc_list *power_well_descs, 1753 1753 int power_well_descs_sz) 1754 1754 { 1755 1755 - struct drm_i915_private *i915 = container_of(power_domains, 1756 1756 - struct drm_i915_private, 1757 1757 - display.power.domains); 1755 1755 + struct intel_display *display = container_of(power_domains, 1756 1756 + struct intel_display, 1757 1757 + power.domains); 1758 1758 u64 power_well_ids = 0; 1759 1759 const struct i915_power_well_desc_list *desc_list; 1760 1760 const struct i915_power_well_desc *desc; ··· 1778 1778 enum i915_power_well_id id = inst->id; 1779 1779 1780 1780 pw->desc = desc; 1781 1781 - drm_WARN_ON(&i915->drm, 1781 1781 + drm_WARN_ON(display->drm, 1782 1782 overflows_type(inst - desc->instances->list, pw->instance_idx)); 1783 1783 pw->instance_idx = inst - desc->instances->list; 1784 1784 ··· 1789 1789 if (id == DISP_PW_ID_NONE) 1790 1790 continue; 1791 1791 1792 1792 - drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8); 1793 1793 - drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id)); 1792 1792 + drm_WARN_ON(display->drm, id >= sizeof(power_well_ids) * 8); 1793 1793 + drm_WARN_ON(display->drm, power_well_ids & BIT_ULL(id)); 1794 1794 power_well_ids |= BIT_ULL(id); 1795 1795 } 1796 1796 ··· 1811 1811 */ 1812 1812 int intel_display_power_map_init(struct i915_power_domains *power_domains) 1813 1813 { 1814 1814 - struct drm_i915_private *i915 = container_of(power_domains, 1815 1815 - struct drm_i915_private, 1816 1816 - display.power.domains); 1814 1814 + struct intel_display *display = container_of(power_domains, 1815 1815 + struct intel_display, 1816 1816 + power.domains); 1817 1817 /* 1818 1818 * The enabling order will be from lower to higher indexed wells, 1819 1819 * the disabling order is reversed. 1820 1820 */ 1821 1821 - if (!HAS_DISPLAY(i915)) { 1821 1821 + if (!HAS_DISPLAY(display)) { 1822 1822 power_domains->power_well_count = 0; 1823 1823 return 0; 1824 1824 } 1825 1825 1826 1826 - if (DISPLAY_VER(i915) >= 30) 1826 1826 + if (DISPLAY_VER(display) >= 30) 1827 1827 return set_power_wells(power_domains, xe3lpd_power_wells); 1828 1828 - else if (DISPLAY_VER(i915) >= 20) 1828 1828 + else if (DISPLAY_VER(display) >= 20) 1829 1829 return set_power_wells(power_domains, xe2lpd_power_wells); 1830 1830 - else if (DISPLAY_VER(i915) >= 14) 1830 1830 + else if (DISPLAY_VER(display) >= 14) 1831 1831 return set_power_wells(power_domains, xelpdp_power_wells); 1832 1832 - else if (IS_DG2(i915)) 1832 1832 + else if (display->platform.dg2) 1833 1833 return set_power_wells(power_domains, xehpd_power_wells); 1834 1834 - else if (DISPLAY_VER(i915) >= 13) 1834 1834 + else if (DISPLAY_VER(display) >= 13) 1835 1835 return set_power_wells(power_domains, xelpd_power_wells); 1836 1836 - else if (IS_DG1(i915)) 1836 1836 + else if (display->platform.dg1) 1837 1837 return set_power_wells(power_domains, dg1_power_wells); 1838 1838 - else if (IS_ALDERLAKE_S(i915)) 1838 1838 + else if (display->platform.alderlake_s) 1839 1839 return set_power_wells(power_domains, adls_power_wells); 1840 1840 - else if (IS_ROCKETLAKE(i915)) 1840 1840 + else if (display->platform.rocketlake) 1841 1841 return set_power_wells(power_domains, rkl_power_wells); 1842 1842 - else if (DISPLAY_VER(i915) == 12) 1842 1842 + else if (DISPLAY_VER(display) == 12) 1843 1843 return set_power_wells(power_domains, tgl_power_wells); 1844 1844 - else if (DISPLAY_VER(i915) == 11) 1844 1844 + else if (DISPLAY_VER(display) == 11) 1845 1845 return set_power_wells(power_domains, icl_power_wells); 1846 1846 - else if (IS_GEMINILAKE(i915)) 1846 1846 + else if (display->platform.geminilake) 1847 1847 return set_power_wells(power_domains, glk_power_wells); 1848 1848 - else if (IS_BROXTON(i915)) 1848 1848 + else if (display->platform.broxton) 1849 1849 return set_power_wells(power_domains, bxt_power_wells); 1850 1850 - else if (DISPLAY_VER(i915) == 9) 1850 1850 + else if (DISPLAY_VER(display) == 9) 1851 1851 return set_power_wells(power_domains, skl_power_wells); 1852 1852 - else if (IS_CHERRYVIEW(i915)) 1852 1852 + else if (display->platform.cherryview) 1853 1853 return set_power_wells(power_domains, chv_power_wells); 1854 1854 - else if (IS_BROADWELL(i915)) 1854 1854 + else if (display->platform.broadwell) 1855 1855 return set_power_wells(power_domains, bdw_power_wells); 1856 1856 - else if (IS_HASWELL(i915)) 1856 1856 + else if (display->platform.haswell) 1857 1857 return set_power_wells(power_domains, hsw_power_wells); 1858 1858 - else if (IS_VALLEYVIEW(i915)) 1858 1858 + else if (display->platform.valleyview) 1859 1859 return set_power_wells(power_domains, vlv_power_wells); 1860 1860 - else if (IS_I830(i915)) 1860 1860 + else if (display->platform.i830) 1861 1861 return set_power_wells(power_domains, i830_power_wells); 1862 1862 else 1863 1863 return set_power_wells(power_domains, i9xx_power_wells);

+280 -287

drivers/gpu/drm/i915/display/intel_display_power_well.c

reviewed

··· 46 46 * during driver init and resume time, possibly after first calling 47 47 * the enable/disable handlers. 48 48 */ 49 49 - void (*sync_hw)(struct drm_i915_private *i915, 49 49 + void (*sync_hw)(struct intel_display *display, 50 50 struct i915_power_well *power_well); 51 51 /* 52 52 * Enable the well and resources that depend on it (for example 53 53 * interrupts located on the well). Called after the 0->1 refcount 54 54 * transition. 55 55 */ 56 56 - void (*enable)(struct drm_i915_private *i915, 56 56 + void (*enable)(struct intel_display *display, 57 57 struct i915_power_well *power_well); 58 58 /* 59 59 * Disable the well and resources that depend on it. Called after 60 60 * the 1->0 refcount transition. 61 61 */ 62 62 - void (*disable)(struct drm_i915_private *i915, 62 62 + void (*disable)(struct intel_display *display, 63 63 struct i915_power_well *power_well); 64 64 /* Returns the hw enabled state. */ 65 65 - bool (*is_enabled)(struct drm_i915_private *i915, 65 65 + bool (*is_enabled)(struct intel_display *display, 66 66 struct i915_power_well *power_well); 67 67 }; 68 68 ··· 73 73 } 74 74 75 75 struct i915_power_well * 76 76 - lookup_power_well(struct drm_i915_private *i915, 76 76 + lookup_power_well(struct intel_display *display, 77 77 enum i915_power_well_id power_well_id) 78 78 { 79 79 struct i915_power_well *power_well; 80 80 81 81 - for_each_power_well(i915, power_well) 81 81 + for_each_power_well(display, power_well) 82 82 if (i915_power_well_instance(power_well)->id == power_well_id) 83 83 return power_well; 84 84 ··· 89 89 * the first power well and hope the WARN gets reported so we can fix 90 90 * our driver. 91 91 */ 92 92 - drm_WARN(&i915->drm, 1, 92 92 + drm_WARN(display->drm, 1, 93 93 "Power well %d not defined for this platform\n", 94 94 power_well_id); 95 95 - return &i915->display.power.domains.power_wells[0]; 95 95 + return &display->power.domains.power_wells[0]; 96 96 } 97 97 98 98 - void intel_power_well_enable(struct drm_i915_private *i915, 98 98 + void intel_power_well_enable(struct intel_display *display, 99 99 struct i915_power_well *power_well) 100 100 { 101 101 - drm_dbg_kms(&i915->drm, "enabling %s\n", intel_power_well_name(power_well)); 102 102 - power_well->desc->ops->enable(i915, power_well); 101 101 + drm_dbg_kms(display->drm, "enabling %s\n", intel_power_well_name(power_well)); 102 102 + power_well->desc->ops->enable(display, power_well); 103 103 power_well->hw_enabled = true; 104 104 } 105 105 106 106 - void intel_power_well_disable(struct drm_i915_private *i915, 106 106 + void intel_power_well_disable(struct intel_display *display, 107 107 struct i915_power_well *power_well) 108 108 { 109 109 - drm_dbg_kms(&i915->drm, "disabling %s\n", intel_power_well_name(power_well)); 109 109 + drm_dbg_kms(display->drm, "disabling %s\n", intel_power_well_name(power_well)); 110 110 power_well->hw_enabled = false; 111 111 - power_well->desc->ops->disable(i915, power_well); 111 111 + power_well->desc->ops->disable(display, power_well); 112 112 } 113 113 114 114 - void intel_power_well_sync_hw(struct drm_i915_private *i915, 114 114 + void intel_power_well_sync_hw(struct intel_display *display, 115 115 struct i915_power_well *power_well) 116 116 { 117 117 - power_well->desc->ops->sync_hw(i915, power_well); 118 118 - power_well->hw_enabled = 119 119 - power_well->desc->ops->is_enabled(i915, power_well); 117 117 + power_well->desc->ops->sync_hw(display, power_well); 118 118 + power_well->hw_enabled = power_well->desc->ops->is_enabled(display, power_well); 120 119 } 121 120 122 122 - void intel_power_well_get(struct drm_i915_private *i915, 121 121 + void intel_power_well_get(struct intel_display *display, 123 122 struct i915_power_well *power_well) 124 123 { 125 124 if (!power_well->count++) 126 126 - intel_power_well_enable(i915, power_well); 125 125 + intel_power_well_enable(display, power_well); 127 126 } 128 127 129 129 - void intel_power_well_put(struct drm_i915_private *i915, 128 128 + void intel_power_well_put(struct intel_display *display, 130 129 struct i915_power_well *power_well) 131 130 { 132 132 - drm_WARN(&i915->drm, !power_well->count, 131 131 + drm_WARN(display->drm, !power_well->count, 133 132 "Use count on power well %s is already zero", 134 133 i915_power_well_instance(power_well)->name); 135 134 136 135 if (!--power_well->count) 137 137 - intel_power_well_disable(i915, power_well); 136 136 + intel_power_well_disable(display, power_well); 138 137 } 139 138 140 140 - bool intel_power_well_is_enabled(struct drm_i915_private *i915, 139 139 + bool intel_power_well_is_enabled(struct intel_display *display, 141 140 struct i915_power_well *power_well) 142 141 { 143 143 - return power_well->desc->ops->is_enabled(i915, power_well); 142 142 + return power_well->desc->ops->is_enabled(display, power_well); 144 143 } 145 144 146 145 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well) ··· 147 148 return power_well->hw_enabled; 148 149 } 149 150 150 150 - bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 151 151 + bool intel_display_power_well_is_enabled(struct intel_display *display, 151 152 enum i915_power_well_id power_well_id) 152 153 { 153 154 struct i915_power_well *power_well; 154 155 155 155 - power_well = lookup_power_well(dev_priv, power_well_id); 156 156 + power_well = lookup_power_well(display, power_well_id); 156 157 157 157 - return intel_power_well_is_enabled(dev_priv, power_well); 158 158 + return intel_power_well_is_enabled(display, power_well); 158 159 } 159 160 160 161 bool intel_power_well_is_always_on(struct i915_power_well *power_well) ··· 183 184 * to be enabled, and it will only be disabled if none of the registers is 184 185 * requesting it to be enabled. 185 186 */ 186 186 - static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, 187 187 + static void hsw_power_well_post_enable(struct intel_display *display, 187 188 u8 irq_pipe_mask, bool has_vga) 188 189 { 189 189 - struct intel_display *display = &dev_priv->display; 190 190 + struct drm_i915_private *dev_priv = to_i915(display->drm); 190 191 191 192 if (has_vga) 192 193 intel_vga_reset_io_mem(display); ··· 195 196 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); 196 197 } 197 198 198 198 - static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, 199 199 + static void hsw_power_well_pre_disable(struct intel_display *display, 199 200 u8 irq_pipe_mask) 200 201 { 202 202 + struct drm_i915_private *dev_priv = to_i915(display->drm); 203 203 + 201 204 if (irq_pipe_mask) 202 205 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); 203 206 } ··· 222 221 } 223 222 224 223 static struct intel_digital_port * 225 225 - aux_ch_to_digital_port(struct drm_i915_private *dev_priv, 224 224 + aux_ch_to_digital_port(struct intel_display *display, 226 225 enum aux_ch aux_ch) 227 226 { 228 227 struct intel_encoder *encoder; 229 228 230 230 - for_each_intel_encoder(&dev_priv->drm, encoder) { 229 229 + for_each_intel_encoder(display->drm, encoder) { 231 230 struct intel_digital_port *dig_port; 232 231 233 232 /* We'll check the MST primary port */ ··· 243 242 return NULL; 244 243 } 245 244 246 246 - static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915, 245 245 + static enum phy icl_aux_pw_to_phy(struct intel_display *display, 247 246 const struct i915_power_well *power_well) 248 247 { 249 248 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 250 250 - struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch); 249 249 + struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 251 250 252 251 /* 253 252 * FIXME should we care about the (VBT defined) dig_port->aux_ch ··· 259 258 return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE; 260 259 } 261 260 262 262 - static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, 261 261 + static void hsw_wait_for_power_well_enable(struct intel_display *display, 263 262 struct i915_power_well *power_well, 264 263 bool timeout_expected) 265 264 { ··· 272 271 * an ack, but rather just wait a fixed amount of time and then 273 272 * proceed. This is only used on DG2. 274 273 */ 275 275 - if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) { 274 274 + if (display->platform.dg2 && power_well->desc->fixed_enable_delay) { 276 275 usleep_range(600, 1200); 277 276 return; 278 277 } 279 278 280 279 /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ 281 281 - if (intel_de_wait_for_set(dev_priv, regs->driver, 280 280 + if (intel_de_wait_for_set(display, regs->driver, 282 281 HSW_PWR_WELL_CTL_STATE(pw_idx), timeout)) { 283 283 - drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n", 282 282 + drm_dbg_kms(display->drm, "%s power well enable timeout\n", 284 283 intel_power_well_name(power_well)); 285 284 286 286 - drm_WARN_ON(&dev_priv->drm, !timeout_expected); 285 285 + drm_WARN_ON(display->drm, !timeout_expected); 287 286 288 287 } 289 288 } 290 289 291 291 - static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, 290 290 + static u32 hsw_power_well_requesters(struct intel_display *display, 292 291 const struct i915_power_well_regs *regs, 293 292 int pw_idx) 294 293 { 295 294 u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 296 295 u32 ret; 297 296 298 298 - ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0; 299 299 - ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0; 297 297 + ret = intel_de_read(display, regs->bios) & req_mask ? 1 : 0; 298 298 + ret |= intel_de_read(display, regs->driver) & req_mask ? 2 : 0; 300 299 if (regs->kvmr.reg) 301 301 - ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0; 302 302 - ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0; 300 300 + ret |= intel_de_read(display, regs->kvmr) & req_mask ? 4 : 0; 301 301 + ret |= intel_de_read(display, regs->debug) & req_mask ? 8 : 0; 303 302 304 303 return ret; 305 304 } 306 305 307 307 - static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, 306 306 + static void hsw_wait_for_power_well_disable(struct intel_display *display, 308 307 struct i915_power_well *power_well) 309 308 { 310 309 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; ··· 321 320 * Skip the wait in case any of the request bits are set and print a 322 321 * diagnostic message. 323 322 */ 324 324 - wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) & 323 323 + wait_for((disabled = !(intel_de_read(display, regs->driver) & 325 324 HSW_PWR_WELL_CTL_STATE(pw_idx))) || 326 326 - (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1); 325 325 + (reqs = hsw_power_well_requesters(display, regs, pw_idx)), 1); 327 326 if (disabled) 328 327 return; 329 328 330 330 - drm_dbg_kms(&dev_priv->drm, 329 329 + drm_dbg_kms(display->drm, 331 330 "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", 332 331 intel_power_well_name(power_well), 333 332 !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); 334 333 } 335 334 336 336 - static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, 335 335 + static void gen9_wait_for_power_well_fuses(struct intel_display *display, 337 336 enum skl_power_gate pg) 338 337 { 339 338 /* Timeout 5us for PG#0, for other PGs 1us */ 340 340 - drm_WARN_ON(&dev_priv->drm, 341 341 - intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS, 339 339 + drm_WARN_ON(display->drm, 340 340 + intel_de_wait_for_set(display, SKL_FUSE_STATUS, 342 341 SKL_FUSE_PG_DIST_STATUS(pg), 1)); 343 342 } 344 343 345 345 - static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 344 344 + static void hsw_power_well_enable(struct intel_display *display, 346 345 struct i915_power_well *power_well) 347 346 { 348 347 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; ··· 351 350 if (power_well->desc->has_fuses) { 352 351 enum skl_power_gate pg; 353 352 354 354 - pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 353 353 + pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 355 354 SKL_PW_CTL_IDX_TO_PG(pw_idx); 356 355 357 356 /* Wa_16013190616:adlp */ 358 358 - if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1) 359 359 - intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 357 357 + if (display->platform.alderlake_p && pg == SKL_PG1) 358 358 + intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); 360 359 361 360 /* 362 361 * For PW1 we have to wait both for the PW0/PG0 fuse state ··· 366 365 * after the enabling. 367 366 */ 368 367 if (pg == SKL_PG1) 369 369 - gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); 368 368 + gen9_wait_for_power_well_fuses(display, SKL_PG0); 370 369 } 371 370 372 372 - intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 371 371 + intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 373 372 374 374 - hsw_wait_for_power_well_enable(dev_priv, power_well, false); 373 373 + hsw_wait_for_power_well_enable(display, power_well, false); 375 374 376 375 if (power_well->desc->has_fuses) { 377 376 enum skl_power_gate pg; 378 377 379 379 - pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 378 378 + pg = DISPLAY_VER(display) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : 380 379 SKL_PW_CTL_IDX_TO_PG(pw_idx); 381 381 - gen9_wait_for_power_well_fuses(dev_priv, pg); 380 380 + gen9_wait_for_power_well_fuses(display, pg); 382 381 } 383 382 384 384 - hsw_power_well_post_enable(dev_priv, 383 383 + hsw_power_well_post_enable(display, 385 384 power_well->desc->irq_pipe_mask, 386 385 power_well->desc->has_vga); 387 386 } 388 387 389 389 - static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 388 388 + static void hsw_power_well_disable(struct intel_display *display, 390 389 struct i915_power_well *power_well) 391 390 { 392 391 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 393 392 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 394 393 395 395 - hsw_power_well_pre_disable(dev_priv, 394 394 + hsw_power_well_pre_disable(display, 396 395 power_well->desc->irq_pipe_mask); 397 396 398 398 - intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 399 399 - hsw_wait_for_power_well_disable(dev_priv, power_well); 397 397 + intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 398 398 + hsw_wait_for_power_well_disable(display, power_well); 400 399 } 401 400 402 402 - static bool intel_aux_ch_is_edp(struct drm_i915_private *i915, enum aux_ch aux_ch) 401 401 + static bool intel_aux_ch_is_edp(struct intel_display *display, enum aux_ch aux_ch) 403 402 { 404 404 - struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch); 403 403 + struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 405 404 406 405 return dig_port && dig_port->base.type == INTEL_OUTPUT_EDP; 407 406 } 408 407 409 408 static void 410 410 - icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 409 409 + icl_combo_phy_aux_power_well_enable(struct intel_display *display, 411 410 struct i915_power_well *power_well) 412 411 { 413 412 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 414 413 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 415 414 416 416 - drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); 415 415 + drm_WARN_ON(display->drm, !display->platform.icelake); 417 416 418 418 - intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 417 417 + intel_de_rmw(display, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); 419 418 420 419 /* 421 420 * FIXME not sure if we should derive the PHY from the pw_idx, or 422 421 * from the VBT defined AUX_CH->DDI->PHY mapping. 423 422 */ 424 424 - intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 423 423 + intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 425 424 0, ICL_LANE_ENABLE_AUX); 426 425 427 427 - hsw_wait_for_power_well_enable(dev_priv, power_well, false); 426 426 + hsw_wait_for_power_well_enable(display, power_well, false); 428 427 429 428 /* Display WA #1178: icl */ 430 429 if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && 431 431 - !intel_aux_ch_is_edp(dev_priv, ICL_AUX_PW_TO_CH(pw_idx))) 432 432 - intel_de_rmw(dev_priv, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)), 430 430 + !intel_aux_ch_is_edp(display, ICL_AUX_PW_TO_CH(pw_idx))) 431 431 + intel_de_rmw(display, ICL_PORT_TX_DW6_AUX(ICL_AUX_PW_TO_PHY(pw_idx)), 433 432 0, O_FUNC_OVRD_EN | O_LDO_BYPASS_CRI); 434 433 } 435 434 436 435 static void 437 437 - icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, 436 436 + icl_combo_phy_aux_power_well_disable(struct intel_display *display, 438 437 struct i915_power_well *power_well) 439 438 { 440 439 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 441 440 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 442 441 443 443 - drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); 442 442 + drm_WARN_ON(display->drm, !display->platform.icelake); 444 443 445 444 /* 446 445 * FIXME not sure if we should derive the PHY from the pw_idx, or 447 446 * from the VBT defined AUX_CH->DDI->PHY mapping. 448 447 */ 449 449 - intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 448 448 + intel_de_rmw(display, ICL_PORT_CL_DW12(ICL_AUX_PW_TO_PHY(pw_idx)), 450 449 ICL_LANE_ENABLE_AUX, 0); 451 450 452 452 - intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 451 451 + intel_de_rmw(display, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); 453 452 454 454 - hsw_wait_for_power_well_disable(dev_priv, power_well); 453 453 + hsw_wait_for_power_well_disable(display, power_well); 455 454 } 456 455 457 456 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) 458 457 459 459 - static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, 458 458 + static void icl_tc_port_assert_ref_held(struct intel_display *display, 460 459 struct i915_power_well *power_well, 461 460 struct intel_digital_port *dig_port) 462 461 { 463 463 - if (drm_WARN_ON(&dev_priv->drm, !dig_port)) 462 462 + if (drm_WARN_ON(display->drm, !dig_port)) 464 463 return; 465 464 466 466 - if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 465 465 + if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 467 466 return; 468 467 469 469 - drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port)); 468 468 + drm_WARN_ON(display->drm, !intel_tc_port_ref_held(dig_port)); 470 469 } 471 470 472 471 #else 473 472 474 474 - static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, 473 473 + static void icl_tc_port_assert_ref_held(struct intel_display *display, 475 474 struct i915_power_well *power_well, 476 475 struct intel_digital_port *dig_port) 477 476 { ··· 481 480 482 481 #define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1) 483 482 484 484 - static void icl_tc_cold_exit(struct drm_i915_private *i915) 483 483 + static void icl_tc_cold_exit(struct intel_display *display) 485 484 { 485 485 + struct drm_i915_private *i915 = to_i915(display->drm); 486 486 int ret, tries = 0; 487 487 488 488 while (1) { ··· 504 502 } 505 503 506 504 static void 507 507 - icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, 505 505 + icl_tc_phy_aux_power_well_enable(struct intel_display *display, 508 506 struct i915_power_well *power_well) 509 507 { 508 508 + struct drm_i915_private *dev_priv = to_i915(display->drm); 510 509 enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); 511 511 - struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch); 510 510 + struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); 512 511 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 513 512 bool is_tbt = power_well->desc->is_tc_tbt; 514 513 bool timeout_expected; 515 514 516 516 - icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port); 515 515 + icl_tc_port_assert_ref_held(display, power_well, dig_port); 517 516 518 518 - intel_de_rmw(dev_priv, DP_AUX_CH_CTL(aux_ch), 517 517 + intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch), 519 518 DP_AUX_CH_CTL_TBT_IO, is_tbt ? DP_AUX_CH_CTL_TBT_IO : 0); 520 519 521 521 - intel_de_rmw(dev_priv, regs->driver, 520 520 + intel_de_rmw(display, regs->driver, 522 521 0, 523 522 HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx)); 524 523 ··· 529 526 * exit sequence. 530 527 */ 531 528 timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port); 532 532 - if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 533 533 - icl_tc_cold_exit(dev_priv); 529 529 + if (DISPLAY_VER(display) == 11 && intel_tc_cold_requires_aux_pw(dig_port)) 530 530 + icl_tc_cold_exit(display); 534 531 535 535 - hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected); 532 532 + hsw_wait_for_power_well_enable(display, power_well, timeout_expected); 536 533 537 537 - if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) { 534 534 + if (DISPLAY_VER(display) >= 12 && !is_tbt) { 538 535 enum tc_port tc_port; 539 536 540 537 tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx); 541 538 542 539 if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) & 543 540 DKL_CMN_UC_DW27_UC_HEALTH, 1)) 544 544 - drm_warn(&dev_priv->drm, 541 541 + drm_warn(display->drm, 545 542 "Timeout waiting TC uC health\n"); 546 543 } 547 544 } 548 545 549 546 static void 550 550 - icl_aux_power_well_enable(struct drm_i915_private *dev_priv, 547 547 + icl_aux_power_well_enable(struct intel_display *display, 551 548 struct i915_power_well *power_well) 552 549 { 553 553 - enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 550 550 + struct drm_i915_private *dev_priv = to_i915(display->drm); 551 551 + enum phy phy = icl_aux_pw_to_phy(display, power_well); 554 552 555 553 if (intel_phy_is_tc(dev_priv, phy)) 556 556 - return icl_tc_phy_aux_power_well_enable(dev_priv, power_well); 557 557 - else if (IS_ICELAKE(dev_priv)) 558 558 - return icl_combo_phy_aux_power_well_enable(dev_priv, 554 554 + return icl_tc_phy_aux_power_well_enable(display, power_well); 555 555 + else if (display->platform.icelake) 556 556 + return icl_combo_phy_aux_power_well_enable(display, 559 557 power_well); 560 558 else 561 561 - return hsw_power_well_enable(dev_priv, power_well); 559 559 + return hsw_power_well_enable(display, power_well); 562 560 } 563 561 564 562 static void 565 565 - icl_aux_power_well_disable(struct drm_i915_private *dev_priv, 563 563 + icl_aux_power_well_disable(struct intel_display *display, 566 564 struct i915_power_well *power_well) 567 565 { 568 568 - enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 566 566 + struct drm_i915_private *dev_priv = to_i915(display->drm); 567 567 + enum phy phy = icl_aux_pw_to_phy(display, power_well); 569 568 570 569 if (intel_phy_is_tc(dev_priv, phy)) 571 571 - return hsw_power_well_disable(dev_priv, power_well); 572 572 - else if (IS_ICELAKE(dev_priv)) 573 573 - return icl_combo_phy_aux_power_well_disable(dev_priv, 570 570 + return hsw_power_well_disable(display, power_well); 571 571 + else if (display->platform.icelake) 572 572 + return icl_combo_phy_aux_power_well_disable(display, 574 573 power_well); 575 574 else 576 576 - return hsw_power_well_disable(dev_priv, power_well); 575 575 + return hsw_power_well_disable(display, power_well); 577 576 } 578 577 579 578 /* ··· 583 578 * enable it, so check if it's enabled and also check if we've requested it to 584 579 * be enabled. 585 580 */ 586 586 - static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 581 581 + static bool hsw_power_well_enabled(struct intel_display *display, 587 582 struct i915_power_well *power_well) 588 583 { 589 584 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; ··· 593 588 HSW_PWR_WELL_CTL_STATE(pw_idx); 594 589 u32 val; 595 590 596 596 - val = intel_de_read(dev_priv, regs->driver); 591 591 + val = intel_de_read(display, regs->driver); 597 592 598 593 /* 599 594 * On GEN9 big core due to a DMC bug the driver's request bits for PW1 ··· 601 596 * BIOS's own request bits, which are forced-on for these power wells 602 597 * when exiting DC5/6. 603 598 */ 604 604 - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && 599 599 + if (DISPLAY_VER(display) == 9 && !display->platform.broxton && 605 600 (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) 606 606 - val |= intel_de_read(dev_priv, regs->bios); 601 601 + val |= intel_de_read(display, regs->bios); 607 602 608 603 return (val & mask) == mask; 609 604 } ··· 696 691 697 692 static u32 gen9_dc_mask(struct intel_display *display) 698 693 { 699 699 - struct drm_i915_private *dev_priv = to_i915(display->drm); 700 694 u32 mask; 701 695 702 696 mask = DC_STATE_EN_UPTO_DC5; ··· 705 701 | DC_STATE_EN_DC9; 706 702 else if (DISPLAY_VER(display) == 11) 707 703 mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; 708 708 - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 704 704 + else if (display->platform.geminilake || display->platform.broxton) 709 705 mask |= DC_STATE_EN_DC9; 710 706 else 711 707 mask |= DC_STATE_EN_UPTO_DC6; ··· 802 798 803 799 static void assert_can_enable_dc5(struct intel_display *display) 804 800 { 805 805 - struct drm_i915_private *dev_priv = to_i915(display->drm); 801 801 + struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); 806 802 enum i915_power_well_id high_pg; 807 803 808 804 /* Power wells at this level and above must be disabled for DC5 entry */ ··· 812 808 high_pg = SKL_DISP_PW_2; 813 809 814 810 drm_WARN_ONCE(display->drm, 815 815 - intel_display_power_well_is_enabled(dev_priv, high_pg), 811 811 + intel_display_power_well_is_enabled(display, high_pg), 816 812 "Power wells above platform's DC5 limit still enabled.\n"); 817 813 818 814 drm_WARN_ONCE(display->drm, ··· 826 822 827 823 void gen9_enable_dc5(struct intel_display *display) 828 824 { 829 829 - struct drm_i915_private *dev_priv = to_i915(display->drm); 830 830 - 831 825 assert_can_enable_dc5(display); 832 826 833 827 drm_dbg_kms(display->drm, "Enabling DC5\n"); 834 828 835 829 /* Wa Display #1183: skl,kbl,cfl */ 836 836 - if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv)) 830 830 + if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 837 831 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 838 832 0, SKL_SELECT_ALTERNATE_DC_EXIT); 839 833 840 840 - intel_dmc_wl_enable(display); 834 834 + intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC5); 841 835 842 836 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5); 843 837 } ··· 857 855 858 856 void skl_enable_dc6(struct intel_display *display) 859 857 { 860 860 - struct drm_i915_private *dev_priv = to_i915(display->drm); 861 861 - 862 858 assert_can_enable_dc6(display); 863 859 864 860 drm_dbg_kms(display->drm, "Enabling DC6\n"); 865 861 866 862 /* Wa Display #1183: skl,kbl,cfl */ 867 867 - if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv)) 863 863 + if (DISPLAY_VER(display) == 9 && !display->platform.broxton) 868 864 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 869 865 0, SKL_SELECT_ALTERNATE_DC_EXIT); 870 866 871 871 - intel_dmc_wl_enable(display); 867 867 + intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6); 872 868 873 869 gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); 874 870 } 875 871 876 872 void bxt_enable_dc9(struct intel_display *display) 877 873 { 878 878 - struct drm_i915_private *dev_priv = to_i915(display->drm); 879 879 - 880 874 assert_can_enable_dc9(display); 881 875 882 876 drm_dbg_kms(display->drm, "Enabling DC9\n"); ··· 880 882 * Power sequencer reset is needed on BXT/GLK, because the PPS registers 881 883 * aren't always on, unlike with South Display Engine on PCH. 882 884 */ 883 883 - if (IS_BROXTON(dev_priv) || IS_GEMINILAKE(dev_priv)) 885 885 + if (display->platform.broxton || display->platform.geminilake) 884 886 bxt_pps_reset_all(display); 885 887 gen9_set_dc_state(display, DC_STATE_EN_DC9); 886 888 } ··· 896 898 intel_pps_unlock_regs_wa(display); 897 899 } 898 900 899 899 - static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 901 901 + static void hsw_power_well_sync_hw(struct intel_display *display, 900 902 struct i915_power_well *power_well) 901 903 { 902 904 const struct i915_power_well_regs *regs = power_well->desc->ops->regs; 903 905 int pw_idx = i915_power_well_instance(power_well)->hsw.idx; 904 906 u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); 905 905 - u32 bios_req = intel_de_read(dev_priv, regs->bios); 907 907 + u32 bios_req = intel_de_read(display, regs->bios); 906 908 907 909 /* Take over the request bit if set by BIOS. */ 908 910 if (bios_req & mask) { 909 909 - u32 drv_req = intel_de_read(dev_priv, regs->driver); 911 911 + u32 drv_req = intel_de_read(display, regs->driver); 910 912 911 913 if (!(drv_req & mask)) 912 912 - intel_de_write(dev_priv, regs->driver, drv_req | mask); 913 913 - intel_de_write(dev_priv, regs->bios, bios_req & ~mask); 914 914 + intel_de_write(display, regs->driver, drv_req | mask); 915 915 + intel_de_write(display, regs->bios, bios_req & ~mask); 914 916 } 915 917 } 916 918 917 917 - static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 919 919 + static void bxt_dpio_cmn_power_well_enable(struct intel_display *display, 918 920 struct i915_power_well *power_well) 919 921 { 920 920 - struct intel_display *display = &dev_priv->display; 921 921 - 922 922 bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy); 923 923 } 924 924 925 925 - static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 925 925 + static void bxt_dpio_cmn_power_well_disable(struct intel_display *display, 926 926 struct i915_power_well *power_well) 927 927 { 928 928 - struct intel_display *display = &dev_priv->display; 929 929 - 930 928 bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy); 931 929 } 932 930 933 933 - static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, 931 931 + static bool bxt_dpio_cmn_power_well_enabled(struct intel_display *display, 934 932 struct i915_power_well *power_well) 935 933 { 936 936 - struct intel_display *display = &dev_priv->display; 937 937 - 938 934 return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy); 939 935 } 940 936 941 941 - static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv) 937 937 + static void bxt_verify_dpio_phy_power_wells(struct intel_display *display) 942 938 { 943 943 - struct intel_display *display = &dev_priv->display; 944 939 struct i915_power_well *power_well; 945 940 946 946 - power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A); 941 941 + power_well = lookup_power_well(display, BXT_DISP_PW_DPIO_CMN_A); 947 942 if (intel_power_well_refcount(power_well) > 0) 948 943 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 949 944 950 950 - power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 945 945 + power_well = lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 951 946 if (intel_power_well_refcount(power_well) > 0) 952 947 bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy); 953 948 954 954 - if (IS_GEMINILAKE(dev_priv)) { 955 955 - power_well = lookup_power_well(dev_priv, 949 949 + if (display->platform.geminilake) { 950 950 + power_well = lookup_power_well(display, 956 951 GLK_DISP_PW_DPIO_CMN_C); 957 952 if (intel_power_well_refcount(power_well) > 0) 958 953 bxt_dpio_phy_verify_state(display, ··· 953 962 } 954 963 } 955 964 956 956 - static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 965 965 + static bool gen9_dc_off_power_well_enabled(struct intel_display *display, 957 966 struct i915_power_well *power_well) 958 967 { 959 959 - struct intel_display *display = &dev_priv->display; 960 960 - 961 968 return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && 962 969 (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); 963 970 } 964 971 965 965 - static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) 972 972 + static void gen9_assert_dbuf_enabled(struct intel_display *display) 966 973 { 974 974 + struct drm_i915_private *dev_priv = to_i915(display->drm); 967 975 u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv); 968 968 - u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices; 976 976 + u8 enabled_dbuf_slices = display->dbuf.enabled_slices; 969 977 970 970 - drm_WARN(&dev_priv->drm, 978 978 + drm_WARN(display->drm, 971 979 hw_enabled_dbuf_slices != enabled_dbuf_slices, 972 980 "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", 973 981 hw_enabled_dbuf_slices, ··· 978 988 struct drm_i915_private *dev_priv = to_i915(display->drm); 979 989 struct i915_power_domains *power_domains = &display->power.domains; 980 990 struct intel_cdclk_config cdclk_config = {}; 991 991 + u32 old_state = power_domains->dc_state; 981 992 982 993 if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { 983 994 tgl_disable_dc3co(display); 984 995 return; 985 996 } 986 997 987 987 - gen9_set_dc_state(display, DC_STATE_DISABLE); 988 988 - 989 989 - if (!HAS_DISPLAY(display)) 998 998 + if (HAS_DISPLAY(display)) { 999 999 + intel_dmc_wl_get_noreg(display); 1000 1000 + gen9_set_dc_state(display, DC_STATE_DISABLE); 1001 1001 + intel_dmc_wl_put_noreg(display); 1002 1002 + } else { 1003 1003 + gen9_set_dc_state(display, DC_STATE_DISABLE); 990 1004 return; 1005 1005 + } 991 1006 992 992 - intel_dmc_wl_disable(display); 1007 1007 + if (old_state == DC_STATE_EN_UPTO_DC5 || 1008 1008 + old_state == DC_STATE_EN_UPTO_DC6) 1009 1009 + intel_dmc_wl_disable(display); 993 1010 994 1011 intel_cdclk_get_cdclk(display, &cdclk_config); 995 1012 /* Can't read out voltage_level so can't use intel_cdclk_changed() */ ··· 1004 1007 intel_cdclk_clock_changed(&display->cdclk.hw, 1005 1008 &cdclk_config)); 1006 1009 1007 1007 - gen9_assert_dbuf_enabled(dev_priv); 1010 1010 + gen9_assert_dbuf_enabled(display); 1008 1011 1009 1009 - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 1010 1010 - bxt_verify_dpio_phy_power_wells(dev_priv); 1012 1012 + if (display->platform.geminilake || display->platform.broxton) 1013 1013 + bxt_verify_dpio_phy_power_wells(display); 1011 1014 1012 1015 if (DISPLAY_VER(display) >= 11) 1013 1016 /* ··· 1018 1021 intel_combo_phy_init(dev_priv); 1019 1022 } 1020 1023 1021 1021 - static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 1024 1024 + static void gen9_dc_off_power_well_enable(struct intel_display *display, 1022 1025 struct i915_power_well *power_well) 1023 1026 { 1024 1024 - struct intel_display *display = &dev_priv->display; 1025 1025 - 1026 1027 gen9_disable_dc_states(display); 1027 1028 } 1028 1029 1029 1029 - static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 1030 1030 + static void gen9_dc_off_power_well_disable(struct intel_display *display, 1030 1031 struct i915_power_well *power_well) 1031 1032 { 1032 1032 - struct intel_display *display = &dev_priv->display; 1033 1033 struct i915_power_domains *power_domains = &display->power.domains; 1034 1034 1035 1035 if (!intel_dmc_has_payload(display)) ··· 1045 1051 } 1046 1052 } 1047 1053 1048 1048 - static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, 1054 1054 + static void i9xx_power_well_sync_hw_noop(struct intel_display *display, 1049 1055 struct i915_power_well *power_well) 1050 1056 { 1051 1057 } 1052 1058 1053 1053 - static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 1059 1059 + static void i9xx_always_on_power_well_noop(struct intel_display *display, 1054 1060 struct i915_power_well *power_well) 1055 1061 { 1056 1062 } 1057 1063 1058 1058 - static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 1059 1059 - struct i915_power_well *power_well) 1064 1064 + static bool i9xx_always_on_power_well_enabled(struct intel_display *display, 1065 1065 + struct i915_power_well *power_well) 1060 1066 { 1061 1067 return true; 1062 1068 } 1063 1069 1064 1064 - static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, 1070 1070 + static void i830_pipes_power_well_enable(struct intel_display *display, 1065 1071 struct i915_power_well *power_well) 1066 1072 { 1067 1067 - struct intel_display *display = &dev_priv->display; 1068 1068 - 1069 1069 - if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0) 1073 1073 + if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0) 1070 1074 i830_enable_pipe(display, PIPE_A); 1071 1071 - if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0) 1075 1075 + if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0) 1072 1076 i830_enable_pipe(display, PIPE_B); 1073 1077 } 1074 1078 1075 1075 - static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, 1079 1079 + static void i830_pipes_power_well_disable(struct intel_display *display, 1076 1080 struct i915_power_well *power_well) 1077 1081 { 1078 1078 - struct intel_display *display = &dev_priv->display; 1079 1079 - 1080 1082 i830_disable_pipe(display, PIPE_B); 1081 1083 i830_disable_pipe(display, PIPE_A); 1082 1084 } 1083 1085 1084 1084 - static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, 1086 1086 + static bool i830_pipes_power_well_enabled(struct intel_display *display, 1085 1087 struct i915_power_well *power_well) 1086 1088 { 1087 1087 - struct intel_display *display = &dev_priv->display; 1088 1088 - 1089 1089 - return intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE && 1090 1090 - intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; 1089 1089 + return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE && 1090 1090 + intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; 1091 1091 } 1092 1092 1093 1093 - static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, 1093 1093 + static void i830_pipes_power_well_sync_hw(struct intel_display *display, 1094 1094 struct i915_power_well *power_well) 1095 1095 { 1096 1096 if (intel_power_well_refcount(power_well) > 0) 1097 1097 - i830_pipes_power_well_enable(dev_priv, power_well); 1097 1097 + i830_pipes_power_well_enable(display, power_well); 1098 1098 else 1099 1099 - i830_pipes_power_well_disable(dev_priv, power_well); 1099 1099 + i830_pipes_power_well_disable(display, power_well); 1100 1100 } 1101 1101 1102 1102 - static void vlv_set_power_well(struct drm_i915_private *dev_priv, 1102 1102 + static void vlv_set_power_well(struct intel_display *display, 1103 1103 struct i915_power_well *power_well, bool enable) 1104 1104 { 1105 1105 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1105 1106 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1106 1107 u32 mask; 1107 1108 u32 state; ··· 1120 1131 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 1121 1132 1122 1133 if (wait_for(COND, 100)) 1123 1123 - drm_err(&dev_priv->drm, 1134 1134 + drm_err(display->drm, 1124 1135 "timeout setting power well state %08x (%08x)\n", 1125 1136 state, 1126 1137 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); ··· 1131 1142 vlv_punit_put(dev_priv); 1132 1143 } 1133 1144 1134 1134 - static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 1145 1145 + static void vlv_power_well_enable(struct intel_display *display, 1135 1146 struct i915_power_well *power_well) 1136 1147 { 1137 1137 - vlv_set_power_well(dev_priv, power_well, true); 1148 1148 + vlv_set_power_well(display, power_well, true); 1138 1149 } 1139 1150 1140 1140 - static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 1151 1151 + static void vlv_power_well_disable(struct intel_display *display, 1141 1152 struct i915_power_well *power_well) 1142 1153 { 1143 1143 - vlv_set_power_well(dev_priv, power_well, false); 1154 1154 + vlv_set_power_well(display, power_well, false); 1144 1155 } 1145 1156 1146 1146 - static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 1157 1157 + static bool vlv_power_well_enabled(struct intel_display *display, 1147 1158 struct i915_power_well *power_well) 1148 1159 { 1160 1160 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1149 1161 int pw_idx = i915_power_well_instance(power_well)->vlv.idx; 1150 1162 bool enabled = false; 1151 1163 u32 mask; ··· 1163 1173 * We only ever set the power-on and power-gate states, anything 1164 1174 * else is unexpected. 1165 1175 */ 1166 1166 - drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && 1176 1176 + drm_WARN_ON(display->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && 1167 1177 state != PUNIT_PWRGT_PWR_GATE(pw_idx)); 1168 1178 if (state == ctrl) 1169 1179 enabled = true; ··· 1173 1183 * is poking at the power controls too. 1174 1184 */ 1175 1185 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 1176 1176 - drm_WARN_ON(&dev_priv->drm, ctrl != state); 1186 1186 + drm_WARN_ON(display->drm, ctrl != state); 1177 1187 1178 1188 vlv_punit_put(dev_priv); 1179 1189 1180 1190 return enabled; 1181 1191 } 1182 1192 1183 1183 - static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 1193 1193 + static void vlv_init_display_clock_gating(struct intel_display *display) 1184 1194 { 1185 1195 /* 1186 1196 * On driver load, a pipe may be active and driving a DSI display. ··· 1188 1198 * (and never recovering) in this case. intel_dsi_post_disable() will 1189 1199 * clear it when we turn off the display. 1190 1200 */ 1191 1191 - intel_de_rmw(dev_priv, DSPCLK_GATE_D(dev_priv), 1201 1201 + intel_de_rmw(display, DSPCLK_GATE_D(display), 1192 1202 ~DPOUNIT_CLOCK_GATE_DISABLE, VRHUNIT_CLOCK_GATE_DISABLE); 1193 1203 1194 1204 /* 1195 1205 * Disable trickle feed and enable pnd deadline calculation 1196 1206 */ 1197 1197 - intel_de_write(dev_priv, MI_ARB_VLV, 1207 1207 + intel_de_write(display, MI_ARB_VLV, 1198 1208 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 1199 1199 - intel_de_write(dev_priv, CBR1_VLV, 0); 1209 1209 + intel_de_write(display, CBR1_VLV, 0); 1200 1210 1201 1201 - drm_WARN_ON(&dev_priv->drm, DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq == 0); 1202 1202 - intel_de_write(dev_priv, RAWCLK_FREQ_VLV, 1203 1203 - DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq, 1211 1211 + drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0); 1212 1212 + intel_de_write(display, RAWCLK_FREQ_VLV, 1213 1213 + DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 1204 1214 1000)); 1205 1215 } 1206 1216 1207 1207 - static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 1217 1217 + static void vlv_display_power_well_init(struct intel_display *display) 1208 1218 { 1209 1209 - struct intel_display *display = &dev_priv->display; 1219 1219 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1210 1220 struct intel_encoder *encoder; 1211 1221 enum pipe pipe; 1212 1222 ··· 1218 1228 * 1219 1229 * CHV DPLL B/C have some issues if VGA mode is enabled. 1220 1230 */ 1221 1221 - for_each_pipe(dev_priv, pipe) { 1222 1222 - u32 val = intel_de_read(dev_priv, DPLL(dev_priv, pipe)); 1231 1231 + for_each_pipe(display, pipe) { 1232 1232 + u32 val = intel_de_read(display, DPLL(display, pipe)); 1223 1233 1224 1234 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1225 1235 if (pipe != PIPE_A) 1226 1236 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1227 1237 1228 1228 - intel_de_write(dev_priv, DPLL(dev_priv, pipe), val); 1238 1238 + intel_de_write(display, DPLL(display, pipe), val); 1229 1239 } 1230 1240 1231 1231 - vlv_init_display_clock_gating(dev_priv); 1241 1241 + vlv_init_display_clock_gating(display); 1232 1242 1233 1243 spin_lock_irq(&dev_priv->irq_lock); 1234 1244 valleyview_enable_display_irqs(dev_priv); ··· 1238 1248 * During driver initialization/resume we can avoid restoring the 1239 1249 * part of the HW/SW state that will be inited anyway explicitly. 1240 1250 */ 1241 1241 - if (dev_priv->display.power.domains.initializing) 1251 1251 + if (display->power.domains.initializing) 1242 1252 return; 1243 1253 1244 1254 intel_hpd_init(dev_priv); 1245 1255 intel_hpd_poll_disable(dev_priv); 1246 1256 1247 1257 /* Re-enable the ADPA, if we have one */ 1248 1248 - for_each_intel_encoder(&dev_priv->drm, encoder) { 1258 1258 + for_each_intel_encoder(display->drm, encoder) { 1249 1259 if (encoder->type == INTEL_OUTPUT_ANALOG) 1250 1260 intel_crt_reset(&encoder->base); 1251 1261 } ··· 1255 1265 intel_pps_unlock_regs_wa(display); 1256 1266 } 1257 1267 1258 1258 - static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 1268 1268 + static void vlv_display_power_well_deinit(struct intel_display *display) 1259 1269 { 1260 1260 - struct intel_display *display = &dev_priv->display; 1270 1270 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1261 1271 1262 1272 spin_lock_irq(&dev_priv->irq_lock); 1263 1273 valleyview_disable_display_irqs(dev_priv); ··· 1269 1279 vlv_pps_reset_all(display); 1270 1280 1271 1281 /* Prevent us from re-enabling polling on accident in late suspend */ 1272 1272 - if (!dev_priv->drm.dev->power.is_suspended) 1282 1282 + if (!display->drm->dev->power.is_suspended) 1273 1283 intel_hpd_poll_enable(dev_priv); 1274 1284 } 1275 1285 1276 1276 - static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 1286 1286 + static void vlv_display_power_well_enable(struct intel_display *display, 1277 1287 struct i915_power_well *power_well) 1278 1288 { 1279 1279 - vlv_set_power_well(dev_priv, power_well, true); 1289 1289 + vlv_set_power_well(display, power_well, true); 1280 1290 1281 1281 - vlv_display_power_well_init(dev_priv); 1291 1291 + vlv_display_power_well_init(display); 1282 1292 } 1283 1293 1284 1284 - static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 1294 1294 + static void vlv_display_power_well_disable(struct intel_display *display, 1285 1295 struct i915_power_well *power_well) 1286 1296 { 1287 1287 - vlv_display_power_well_deinit(dev_priv); 1297 1297 + vlv_display_power_well_deinit(display); 1288 1298 1289 1289 - vlv_set_power_well(dev_priv, power_well, false); 1299 1299 + vlv_set_power_well(display, power_well, false); 1290 1300 } 1291 1301 1292 1292 - static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1302 1302 + static void vlv_dpio_cmn_power_well_enable(struct intel_display *display, 1293 1303 struct i915_power_well *power_well) 1294 1304 { 1295 1305 /* since ref/cri clock was enabled */ 1296 1306 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1297 1307 1298 1298 - vlv_set_power_well(dev_priv, power_well, true); 1308 1308 + vlv_set_power_well(display, power_well, true); 1299 1309 1300 1310 /* 1301 1311 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - ··· 1308 1318 * both PLLs disabled, or we risk losing DPIO and PLL 1309 1319 * synchronization. 1310 1320 */ 1311 1311 - intel_de_rmw(dev_priv, DPIO_CTL, 0, DPIO_CMNRST); 1321 1321 + intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST); 1312 1322 } 1313 1323 1314 1314 - static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1324 1324 + static void vlv_dpio_cmn_power_well_disable(struct intel_display *display, 1315 1325 struct i915_power_well *power_well) 1316 1326 { 1327 1327 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1317 1328 enum pipe pipe; 1318 1329 1319 1319 - for_each_pipe(dev_priv, pipe) 1330 1330 + for_each_pipe(display, pipe) 1320 1331 assert_pll_disabled(dev_priv, pipe); 1321 1332 1322 1333 /* Assert common reset */ 1323 1323 - intel_de_rmw(dev_priv, DPIO_CTL, DPIO_CMNRST, 0); 1334 1334 + intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0); 1324 1335 1325 1325 - vlv_set_power_well(dev_priv, power_well, false); 1336 1336 + vlv_set_power_well(display, power_well, false); 1326 1337 } 1327 1338 1328 1339 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1329 1340 1330 1341 static void assert_chv_phy_status(struct intel_display *display) 1331 1342 { 1332 1332 - struct drm_i915_private *dev_priv = to_i915(display->drm); 1333 1343 struct i915_power_well *cmn_bc = 1334 1334 - lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC); 1344 1344 + lookup_power_well(display, VLV_DISP_PW_DPIO_CMN_BC); 1335 1345 struct i915_power_well *cmn_d = 1336 1336 - lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D); 1346 1346 + lookup_power_well(display, CHV_DISP_PW_DPIO_CMN_D); 1337 1347 u32 phy_control = display->power.chv_phy_control; 1338 1348 u32 phy_status = 0; 1339 1349 u32 phy_status_mask = 0xffffffff; ··· 1358 1368 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1359 1369 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1360 1370 1361 1361 - if (intel_power_well_is_enabled(dev_priv, cmn_bc)) { 1371 1371 + if (intel_power_well_is_enabled(display, cmn_bc)) { 1362 1372 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1363 1373 1364 1374 /* this assumes override is only used to enable lanes */ ··· 1399 1409 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1400 1410 } 1401 1411 1402 1402 - if (intel_power_well_is_enabled(dev_priv, cmn_d)) { 1412 1412 + if (intel_power_well_is_enabled(display, cmn_d)) { 1403 1413 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1404 1414 1405 1415 /* this assumes override is only used to enable lanes */ ··· 1434 1444 1435 1445 #undef BITS_SET 1436 1446 1437 1437 - static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1447 1447 + static void chv_dpio_cmn_power_well_enable(struct intel_display *display, 1438 1448 struct i915_power_well *power_well) 1439 1449 { 1440 1440 - struct intel_display *display = &dev_priv->display; 1450 1450 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1441 1451 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1442 1452 enum dpio_phy phy; 1443 1453 u32 tmp; ··· 1453 1463 1454 1464 /* since ref/cri clock was enabled */ 1455 1465 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1456 1456 - vlv_set_power_well(dev_priv, power_well, true); 1466 1466 + vlv_set_power_well(display, power_well, true); 1457 1467 1458 1468 /* Poll for phypwrgood signal */ 1459 1469 if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS, ··· 1497 1507 assert_chv_phy_status(display); 1498 1508 } 1499 1509 1500 1500 - static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1510 1510 + static void chv_dpio_cmn_power_well_disable(struct intel_display *display, 1501 1511 struct i915_power_well *power_well) 1502 1512 { 1503 1503 - struct intel_display *display = &dev_priv->display; 1513 1513 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1504 1514 enum i915_power_well_id id = i915_power_well_instance(power_well)->id; 1505 1515 enum dpio_phy phy; 1506 1516 ··· 1521 1531 intel_de_write(display, DISPLAY_PHY_CONTROL, 1522 1532 display->power.chv_phy_control); 1523 1533 1524 1524 - vlv_set_power_well(dev_priv, power_well, false); 1534 1534 + vlv_set_power_well(display, power_well, false); 1525 1535 1526 1536 drm_dbg_kms(display->drm, 1527 1537 "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", ··· 1533 1543 assert_chv_phy_status(display); 1534 1544 } 1535 1545 1536 1536 - static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1546 1546 + static void assert_chv_phy_powergate(struct intel_display *display, enum dpio_phy phy, 1537 1547 enum dpio_channel ch, bool override, unsigned int mask) 1538 1548 { 1549 1549 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1539 1550 u32 reg, val, expected, actual; 1540 1551 1541 1552 /* ··· 1546 1555 * reset (ie. the power well has been disabled at 1547 1556 * least once). 1548 1557 */ 1549 1549 - if (!dev_priv->display.power.chv_phy_assert[phy]) 1558 1558 + if (!display->power.chv_phy_assert[phy]) 1550 1559 return; 1551 1560 1552 1561 if (ch == DPIO_CH0) ··· 1589 1598 actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 | 1590 1599 DPIO_ALLDL_POWERDOWN_CH1, val); 1591 1600 1592 1592 - drm_WARN(&dev_priv->drm, actual != expected, 1601 1601 + drm_WARN(display->drm, actual != expected, 1593 1602 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1594 1603 !!(actual & DPIO_ALLDL_POWERDOWN), 1595 1604 !!(actual & DPIO_ANYDL_POWERDOWN), ··· 1598 1607 reg, val); 1599 1608 } 1600 1609 1601 1601 - bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1610 1610 + bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy, 1602 1611 enum dpio_channel ch, bool override) 1603 1612 { 1604 1604 - struct intel_display *display = &dev_priv->display; 1605 1613 struct i915_power_domains *power_domains = &display->power.domains; 1606 1614 bool was_override; 1607 1615 ··· 1635 1645 bool override, unsigned int mask) 1636 1646 { 1637 1647 struct intel_display *display = to_intel_display(encoder); 1638 1638 - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1639 1648 struct i915_power_domains *power_domains = &display->power.domains; 1640 1649 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1641 1650 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); ··· 1658 1669 1659 1670 assert_chv_phy_status(display); 1660 1671 1661 1661 - assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1672 1672 + assert_chv_phy_powergate(display, phy, ch, override, mask); 1662 1673 1663 1674 mutex_unlock(&power_domains->lock); 1664 1675 } 1665 1676 1666 1666 - static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1677 1677 + static bool chv_pipe_power_well_enabled(struct intel_display *display, 1667 1678 struct i915_power_well *power_well) 1668 1679 { 1680 1680 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1669 1681 enum pipe pipe = PIPE_A; 1670 1682 bool enabled; 1671 1683 u32 state, ctrl; ··· 1678 1688 * We only ever set the power-on and power-gate states, anything 1679 1689 * else is unexpected. 1680 1690 */ 1681 1681 - drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) && 1691 1691 + drm_WARN_ON(display->drm, state != DP_SSS_PWR_ON(pipe) && 1682 1692 state != DP_SSS_PWR_GATE(pipe)); 1683 1693 enabled = state == DP_SSS_PWR_ON(pipe); 1684 1694 ··· 1687 1697 * is poking at the power controls too. 1688 1698 */ 1689 1699 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); 1690 1690 - drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state); 1700 1700 + drm_WARN_ON(display->drm, ctrl << 16 != state); 1691 1701 1692 1702 vlv_punit_put(dev_priv); 1693 1703 1694 1704 return enabled; 1695 1705 } 1696 1706 1697 1697 - static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1707 1707 + static void chv_set_pipe_power_well(struct intel_display *display, 1698 1708 struct i915_power_well *power_well, 1699 1709 bool enable) 1700 1710 { 1711 1711 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1701 1712 enum pipe pipe = PIPE_A; 1702 1713 u32 state; 1703 1714 u32 ctrl; ··· 1719 1728 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl); 1720 1729 1721 1730 if (wait_for(COND, 100)) 1722 1722 - drm_err(&dev_priv->drm, 1731 1731 + drm_err(display->drm, 1723 1732 "timeout setting power well state %08x (%08x)\n", 1724 1733 state, 1725 1734 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); ··· 1730 1739 vlv_punit_put(dev_priv); 1731 1740 } 1732 1741 1733 1733 - static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1742 1742 + static void chv_pipe_power_well_sync_hw(struct intel_display *display, 1734 1743 struct i915_power_well *power_well) 1735 1744 { 1736 1736 - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, 1737 1737 - dev_priv->display.power.chv_phy_control); 1745 1745 + intel_de_write(display, DISPLAY_PHY_CONTROL, 1746 1746 + display->power.chv_phy_control); 1738 1747 } 1739 1748 1740 1740 - static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1749 1749 + static void chv_pipe_power_well_enable(struct intel_display *display, 1741 1750 struct i915_power_well *power_well) 1742 1751 { 1743 1743 - chv_set_pipe_power_well(dev_priv, power_well, true); 1752 1752 + chv_set_pipe_power_well(display, power_well, true); 1744 1753 1745 1745 - vlv_display_power_well_init(dev_priv); 1754 1754 + vlv_display_power_well_init(display); 1746 1755 } 1747 1756 1748 1748 - static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1757 1757 + static void chv_pipe_power_well_disable(struct intel_display *display, 1749 1758 struct i915_power_well *power_well) 1750 1759 { 1751 1751 - vlv_display_power_well_deinit(dev_priv); 1760 1760 + vlv_display_power_well_deinit(display); 1752 1761 1753 1753 - chv_set_pipe_power_well(dev_priv, power_well, false); 1762 1762 + chv_set_pipe_power_well(display, power_well, false); 1754 1763 } 1755 1764 1756 1765 static void 1757 1757 - tgl_tc_cold_request(struct drm_i915_private *i915, bool block) 1766 1766 + tgl_tc_cold_request(struct intel_display *display, bool block) 1758 1767 { 1768 1768 + struct drm_i915_private *i915 = to_i915(display->drm); 1759 1769 u8 tries = 0; 1760 1770 int ret; 1761 1771 ··· 1797 1805 } 1798 1806 1799 1807 static void 1800 1800 - tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915, 1808 1808 + tgl_tc_cold_off_power_well_enable(struct intel_display *display, 1801 1809 struct i915_power_well *power_well) 1802 1810 { 1803 1803 - tgl_tc_cold_request(i915, true); 1811 1811 + tgl_tc_cold_request(display, true); 1804 1812 } 1805 1813 1806 1814 static void 1807 1807 - tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915, 1815 1815 + tgl_tc_cold_off_power_well_disable(struct intel_display *display, 1808 1816 struct i915_power_well *power_well) 1809 1817 { 1810 1810 - tgl_tc_cold_request(i915, false); 1818 1818 + tgl_tc_cold_request(display, false); 1811 1819 } 1812 1820 1813 1821 static void 1814 1814 - tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915, 1822 1822 + tgl_tc_cold_off_power_well_sync_hw(struct intel_display *display, 1815 1823 struct i915_power_well *power_well) 1816 1824 { 1817 1825 if (intel_power_well_refcount(power_well) > 0) 1818 1818 - tgl_tc_cold_off_power_well_enable(i915, power_well); 1826 1826 + tgl_tc_cold_off_power_well_enable(display, power_well); 1819 1827 else 1820 1820 - tgl_tc_cold_off_power_well_disable(i915, power_well); 1828 1828 + tgl_tc_cold_off_power_well_disable(display, power_well); 1821 1829 } 1822 1830 1823 1831 static bool 1824 1824 - tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv, 1832 1832 + tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display, 1825 1833 struct i915_power_well *power_well) 1826 1834 { 1827 1835 /* ··· 1831 1839 return intel_power_well_refcount(power_well); 1832 1840 } 1833 1841 1834 1834 - static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv, 1842 1842 + static void xelpdp_aux_power_well_enable(struct intel_display *display, 1835 1843 struct i915_power_well *power_well) 1836 1844 { 1845 1845 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1837 1846 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1838 1838 - enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well); 1847 1847 + enum phy phy = icl_aux_pw_to_phy(display, power_well); 1839 1848 1840 1849 if (intel_phy_is_tc(dev_priv, phy)) 1841 1841 - icl_tc_port_assert_ref_held(dev_priv, power_well, 1842 1842 - aux_ch_to_digital_port(dev_priv, aux_ch)); 1850 1850 + icl_tc_port_assert_ref_held(display, power_well, 1851 1851 + aux_ch_to_digital_port(display, aux_ch)); 1843 1852 1844 1844 - intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch), 1853 1853 + intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1845 1854 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1846 1855 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); 1847 1856 ··· 1855 1862 usleep_range(600, 1200); 1856 1863 } 1857 1864 1858 1858 - static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv, 1865 1865 + static void xelpdp_aux_power_well_disable(struct intel_display *display, 1859 1866 struct i915_power_well *power_well) 1860 1867 { 1861 1868 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1862 1869 1863 1863 - intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch), 1870 1870 + intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), 1864 1871 XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 1865 1872 0); 1866 1873 usleep_range(10, 30); 1867 1874 } 1868 1875 1869 1869 - static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv, 1876 1876 + static bool xelpdp_aux_power_well_enabled(struct intel_display *display, 1870 1877 struct i915_power_well *power_well) 1871 1878 { 1872 1879 enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; 1873 1880 1874 1874 - return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch)) & 1881 1881 + return intel_de_read(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch)) & 1875 1882 XELPDP_DP_AUX_CH_CTL_POWER_STATUS; 1876 1883 } 1877 1884 1878 1878 - static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv, 1885 1885 + static void xe2lpd_pica_power_well_enable(struct intel_display *display, 1879 1886 struct i915_power_well *power_well) 1880 1887 { 1881 1881 - intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL, 1888 1888 + intel_de_write(display, XE2LPD_PICA_PW_CTL, 1882 1889 XE2LPD_PICA_CTL_POWER_REQUEST); 1883 1890 1884 1884 - if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL, 1891 1891 + if (intel_de_wait_for_set(display, XE2LPD_PICA_PW_CTL, 1885 1892 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1886 1886 - drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n"); 1893 1893 + drm_dbg_kms(display->drm, "pica power well enable timeout\n"); 1887 1894 1888 1888 - drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled"); 1895 1895 + drm_WARN(display->drm, 1, "Power well PICA timeout when enabled"); 1889 1896 } 1890 1897 } 1891 1898 1892 1892 - static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv, 1899 1899 + static void xe2lpd_pica_power_well_disable(struct intel_display *display, 1893 1900 struct i915_power_well *power_well) 1894 1901 { 1895 1895 - intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL, 0); 1902 1902 + intel_de_write(display, XE2LPD_PICA_PW_CTL, 0); 1896 1903 1897 1897 - if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL, 1904 1904 + if (intel_de_wait_for_clear(display, XE2LPD_PICA_PW_CTL, 1898 1905 XE2LPD_PICA_CTL_POWER_STATUS, 1)) { 1899 1899 - drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n"); 1906 1906 + drm_dbg_kms(display->drm, "pica power well disable timeout\n"); 1900 1907 1901 1901 - drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled"); 1908 1908 + drm_WARN(display->drm, 1, "Power well PICA timeout when disabled"); 1902 1909 } 1903 1910 } 1904 1911 1905 1905 - static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv, 1912 1912 + static bool xe2lpd_pica_power_well_enabled(struct intel_display *display, 1906 1913 struct i915_power_well *power_well) 1907 1914 { 1908 1908 - return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) & 1915 1915 + return intel_de_read(display, XE2LPD_PICA_PW_CTL) & 1909 1916 XE2LPD_PICA_CTL_POWER_STATUS; 1910 1917 } 1911 1918

+17 -18

drivers/gpu/drm/i915/display/intel_display_power_well.h

reviewed

··· 10 10 #include "intel_display_power.h" 11 11 #include "intel_dpio_phy.h" 12 12 13 13 - struct drm_i915_private; 14 13 struct i915_power_well_ops; 15 14 struct intel_display; 16 15 struct intel_encoder; 17 16 18 18 - #define for_each_power_well(__dev_priv, __power_well) \ 19 19 - for ((__power_well) = (__dev_priv)->display.power.domains.power_wells; \ 20 20 - (__power_well) - (__dev_priv)->display.power.domains.power_wells < \ 21 21 - (__dev_priv)->display.power.domains.power_well_count; \ 17 17 + #define for_each_power_well(___display, __power_well) \ 18 18 + for ((__power_well) = (___display)->power.domains.power_wells; \ 19 19 + (__power_well) - (___display)->power.domains.power_wells < \ 20 20 + (___display)->power.domains.power_well_count; \ 22 21 (__power_well)++) 23 22 24 24 - #define for_each_power_well_reverse(__dev_priv, __power_well) \ 25 25 - for ((__power_well) = (__dev_priv)->display.power.domains.power_wells + \ 26 26 - (__dev_priv)->display.power.domains.power_well_count - 1; \ 27 27 - (__power_well) - (__dev_priv)->display.power.domains.power_wells >= 0; \ 23 23 + #define for_each_power_well_reverse(___display, __power_well) \ 24 24 + for ((__power_well) = (___display)->power.domains.power_wells + \ 25 25 + (___display)->power.domains.power_well_count - 1; \ 26 26 + (__power_well) - (___display)->power.domains.power_wells >= 0; \ 28 27 (__power_well)--) 29 28 30 29 /* ··· 126 127 u8 instance_idx; 127 128 }; 128 129 129 129 - struct i915_power_well *lookup_power_well(struct drm_i915_private *i915, 130 130 + struct i915_power_well *lookup_power_well(struct intel_display *display, 130 131 enum i915_power_well_id id); 131 132 132 132 - void intel_power_well_enable(struct drm_i915_private *i915, 133 133 + void intel_power_well_enable(struct intel_display *display, 133 134 struct i915_power_well *power_well); 134 134 - void intel_power_well_disable(struct drm_i915_private *i915, 135 135 + void intel_power_well_disable(struct intel_display *display, 135 136 struct i915_power_well *power_well); 136 136 - void intel_power_well_sync_hw(struct drm_i915_private *i915, 137 137 + void intel_power_well_sync_hw(struct intel_display *display, 137 138 struct i915_power_well *power_well); 138 138 - void intel_power_well_get(struct drm_i915_private *i915, 139 139 + void intel_power_well_get(struct intel_display *display, 139 140 struct i915_power_well *power_well); 140 140 - void intel_power_well_put(struct drm_i915_private *i915, 141 141 + void intel_power_well_put(struct intel_display *display, 141 142 struct i915_power_well *power_well); 142 142 - bool intel_power_well_is_enabled(struct drm_i915_private *i915, 143 143 + bool intel_power_well_is_enabled(struct intel_display *display, 143 144 struct i915_power_well *power_well); 144 145 bool intel_power_well_is_enabled_cached(struct i915_power_well *power_well); 145 145 - bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 146 146 + bool intel_display_power_well_is_enabled(struct intel_display *display, 146 147 enum i915_power_well_id power_well_id); 147 148 bool intel_power_well_is_always_on(struct i915_power_well *power_well); 148 149 const char *intel_power_well_name(struct i915_power_well *power_well); ··· 151 152 152 153 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 153 154 bool override, unsigned int mask); 154 154 - bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 155 155 + bool chv_phy_powergate_ch(struct intel_display *display, enum dpio_phy phy, 155 156 enum dpio_channel ch, bool override); 156 157 157 158 void gen9_enable_dc5(struct intel_display *display);

+2 -2

drivers/gpu/drm/i915/display/intel_display_reset.c

reviewed

··· 114 114 * so need a full re-initialization. 115 115 */ 116 116 intel_pps_unlock_regs_wa(display); 117 117 - intel_display_driver_init_hw(i915); 117 117 + intel_display_driver_init_hw(display); 118 118 intel_clock_gating_init(i915); 119 119 intel_hpd_init(i915); 120 120 121 121 - ret = __intel_display_driver_resume(i915, state, ctx); 121 121 + ret = __intel_display_driver_resume(display, state, ctx); 122 122 if (ret) 123 123 drm_err(&i915->drm, 124 124 "Restoring old state failed with %i\n", ret);

+19 -6

drivers/gpu/drm/i915/display/intel_display_types.h

reviewed

··· 301 301 u32 (*hz_to_pwm)(struct intel_connector *connector, u32 hz); 302 302 }; 303 303 304 304 + /* in 100us units */ 305 305 + struct intel_pps_delays { 306 306 + u16 power_up; /* eDP: T1+T3, LVDS: T1+T2 */ 307 307 + u16 backlight_on; /* eDP: T8, LVDS: T5 */ 308 308 + u16 backlight_off; /* eDP: T9, LVDS: T6/TX */ 309 309 + u16 power_down; /* eDP: T10, LVDS: T3 */ 310 310 + u16 power_cycle; /* eDP: T11+T12, LVDS: T7+T4 */ 311 311 + }; 312 312 + 304 313 enum drrs_type { 305 314 DRRS_TYPE_NONE, 306 315 DRRS_TYPE_STATIC, ··· 337 328 int preemphasis; 338 329 int vswing; 339 330 int bpp; 340 340 - struct edp_power_seq pps; 331 331 + struct intel_pps_delays pps; 341 332 u8 drrs_msa_timing_delay; 342 333 bool low_vswing; 343 334 bool hobl; ··· 596 587 bool skip_intermediate_wm; 597 588 598 589 bool rps_interactive; 590 590 + 591 591 + struct work_struct cleanup_work; 599 592 }; 600 593 601 594 struct intel_plane_state { ··· 708 697 }; 709 698 710 699 struct intel_scaler { 711 711 - int in_use; 712 700 u32 mode; 701 701 + bool in_use; 713 702 }; 714 703 715 704 struct intel_crtc_scaler_state { ··· 1246 1235 /* Display Stream compression state */ 1247 1236 struct { 1248 1237 bool compression_enable; 1249 1249 - bool dsc_split; 1238 1238 + int num_streams; 1250 1239 /* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */ 1251 1240 u16 compressed_bpp_x16; 1252 1241 u8 slice_count; ··· 1579 1568 * requiring a reinitialization. Only relevant on BXT+. 1580 1569 */ 1581 1570 bool bxt_pps_reset; 1582 1582 - struct edp_power_seq pps_delays; 1583 1583 - struct edp_power_seq bios_pps_delays; 1571 1571 + struct intel_pps_delays pps_delays; 1572 1572 + struct intel_pps_delays bios_pps_delays; 1584 1573 }; 1585 1574 1586 1575 struct intel_psr { ··· 1814 1803 1815 1804 struct intel_digital_port { 1816 1805 struct intel_encoder base; 1817 1817 - u32 saved_port_bits; 1818 1806 struct intel_dp dp; 1819 1807 struct intel_hdmi hdmi; 1820 1808 struct intel_lspcon lspcon; 1821 1809 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool); 1810 1810 + 1811 1811 + bool lane_reversal; 1812 1812 + bool ddi_a_4_lanes; 1822 1813 bool release_cl2_override; 1823 1814 u8 max_lanes; 1824 1815 /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */

-4

drivers/gpu/drm/i915/display/intel_dmc.c

reviewed

··· 638 638 pipedmc_clock_gating_wa(display, true); 639 639 disable_all_event_handlers(display); 640 640 pipedmc_clock_gating_wa(display, false); 641 641 - 642 642 - intel_dmc_wl_disable(display); 643 641 } 644 642 645 643 void assert_dmc_loaded(struct intel_display *display) ··· 1143 1145 1144 1146 if (dmc) 1145 1147 flush_work(&dmc->work); 1146 1146 - 1147 1147 - intel_dmc_wl_disable(display); 1148 1148 1149 1149 /* Drop the reference held in case DMC isn't loaded. */ 1150 1150 if (!intel_dmc_has_payload(display))

+256 -58

drivers/gpu/drm/i915/display/intel_dmc_wl.c

reviewed

··· 5 5 6 6 #include <linux/kernel.h> 7 7 8 8 + #include <drm/drm_print.h> 9 9 + 10 10 + #include "i915_reg.h" 8 11 #include "intel_de.h" 9 12 #include "intel_dmc.h" 10 13 #include "intel_dmc_regs.h" ··· 42 39 * potential future use. 43 40 */ 44 41 45 45 - #define DMC_WAKELOCK_CTL_TIMEOUT 5 42 42 + /* 43 43 + * Define DMC_WAKELOCK_CTL_TIMEOUT_US in microseconds because we use the 44 44 + * atomic variant of waiting MMIO. 45 45 + */ 46 46 + #define DMC_WAKELOCK_CTL_TIMEOUT_US 5000 46 47 #define DMC_WAKELOCK_HOLD_TIME 50 47 48 48 49 struct intel_dmc_wl_range { ··· 54 47 u32 end; 55 48 }; 56 49 57 57 - static struct intel_dmc_wl_range lnl_wl_range[] = { 50 50 + static struct intel_dmc_wl_range powered_off_ranges[] = { 58 51 { .start = 0x60000, .end = 0x7ffff }, 52 52 + {}, 53 53 + }; 54 54 + 55 55 + static struct intel_dmc_wl_range xe3lpd_dc5_dc6_dmc_ranges[] = { 56 56 + { .start = 0x45500 }, /* DC_STATE_SEL */ 57 57 + { .start = 0x457a0, .end = 0x457b0 }, /* DC*_RESIDENCY_COUNTER */ 58 58 + { .start = 0x45504 }, /* DC_STATE_EN */ 59 59 + { .start = 0x45400, .end = 0x4540c }, /* PWR_WELL_CTL_* */ 60 60 + { .start = 0x454f0 }, /* RETENTION_CTRL */ 61 61 + 62 62 + /* DBUF_CTL_* */ 63 63 + { .start = 0x44300 }, 64 64 + { .start = 0x44304 }, 65 65 + { .start = 0x44f00 }, 66 66 + { .start = 0x44f04 }, 67 67 + { .start = 0x44fe8 }, 68 68 + { .start = 0x45008 }, 69 69 + 70 70 + { .start = 0x46070 }, /* CDCLK_PLL_ENABLE */ 71 71 + { .start = 0x46000 }, /* CDCLK_CTL */ 72 72 + { .start = 0x46008 }, /* CDCLK_SQUASH_CTL */ 73 73 + 74 74 + /* TRANS_CMTG_CTL_* */ 75 75 + { .start = 0x6fa88 }, 76 76 + { .start = 0x6fb88 }, 77 77 + 78 78 + { .start = 0x46430 }, /* CHICKEN_DCPR_1 */ 79 79 + { .start = 0x46434 }, /* CHICKEN_DCPR_2 */ 80 80 + { .start = 0x454a0 }, /* CHICKEN_DCPR_4 */ 81 81 + { .start = 0x42084 }, /* CHICKEN_MISC_2 */ 82 82 + { .start = 0x42088 }, /* CHICKEN_MISC_3 */ 83 83 + { .start = 0x46160 }, /* CMTG_CLK_SEL */ 84 84 + { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */ 85 85 + 86 86 + {}, 87 87 + }; 88 88 + 89 89 + static struct intel_dmc_wl_range xe3lpd_dc3co_dmc_ranges[] = { 90 90 + { .start = 0x454a0 }, /* CHICKEN_DCPR_4 */ 91 91 + 92 92 + { .start = 0x45504 }, /* DC_STATE_EN */ 93 93 + 94 94 + /* DBUF_CTL_* */ 95 95 + { .start = 0x44300 }, 96 96 + { .start = 0x44304 }, 97 97 + { .start = 0x44f00 }, 98 98 + { .start = 0x44f04 }, 99 99 + { .start = 0x44fe8 }, 100 100 + { .start = 0x45008 }, 101 101 + 102 102 + { .start = 0x46070 }, /* CDCLK_PLL_ENABLE */ 103 103 + { .start = 0x46000 }, /* CDCLK_CTL */ 104 104 + { .start = 0x46008 }, /* CDCLK_SQUASH_CTL */ 105 105 + { .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */ 106 106 + 107 107 + /* Scanline registers */ 108 108 + { .start = 0x70000 }, 109 109 + { .start = 0x70004 }, 110 110 + { .start = 0x70014 }, 111 111 + { .start = 0x70018 }, 112 112 + { .start = 0x71000 }, 113 113 + { .start = 0x71004 }, 114 114 + { .start = 0x71014 }, 115 115 + { .start = 0x71018 }, 116 116 + { .start = 0x72000 }, 117 117 + { .start = 0x72004 }, 118 118 + { .start = 0x72014 }, 119 119 + { .start = 0x72018 }, 120 120 + { .start = 0x73000 }, 121 121 + { .start = 0x73004 }, 122 122 + { .start = 0x73014 }, 123 123 + { .start = 0x73018 }, 124 124 + { .start = 0x7b000 }, 125 125 + { .start = 0x7b004 }, 126 126 + { .start = 0x7b014 }, 127 127 + { .start = 0x7b018 }, 128 128 + { .start = 0x7c000 }, 129 129 + { .start = 0x7c004 }, 130 130 + { .start = 0x7c014 }, 131 131 + { .start = 0x7c018 }, 132 132 + 133 133 + {}, 59 134 }; 60 135 61 136 static void __intel_dmc_wl_release(struct intel_display *display) ··· 161 72 162 73 spin_lock_irqsave(&wl->lock, flags); 163 74 164 164 - /* Bail out if refcount reached zero while waiting for the spinlock */ 165 165 - if (!refcount_read(&wl->refcount)) 75 75 + /* 76 76 + * Bail out if refcount became non-zero while waiting for the spinlock, 77 77 + * meaning that the lock is now taken again. 78 78 + */ 79 79 + if (refcount_read(&wl->refcount)) 166 80 goto out_unlock; 167 81 168 82 __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0); 169 83 170 170 - if (__intel_de_wait_for_register_nowl(display, DMC_WAKELOCK1_CTL, 171 171 - DMC_WAKELOCK_CTL_ACK, 0, 172 172 - DMC_WAKELOCK_CTL_TIMEOUT)) { 84 84 + if (__intel_de_wait_for_register_atomic_nowl(display, DMC_WAKELOCK1_CTL, 85 85 + DMC_WAKELOCK_CTL_ACK, 0, 86 86 + DMC_WAKELOCK_CTL_TIMEOUT_US)) { 173 87 WARN_RATELIMIT(1, "DMC wakelock release timed out"); 174 88 goto out_unlock; 175 89 } ··· 183 91 spin_unlock_irqrestore(&wl->lock, flags); 184 92 } 185 93 186 186 - static bool intel_dmc_wl_check_range(u32 address) 94 94 + static void __intel_dmc_wl_take(struct intel_display *display) 187 95 { 188 188 - int i; 189 189 - bool wl_needed = false; 96 96 + struct intel_dmc_wl *wl = &display->wl; 190 97 191 191 - for (i = 0; i < ARRAY_SIZE(lnl_wl_range); i++) { 192 192 - if (address >= lnl_wl_range[i].start && 193 193 - address <= lnl_wl_range[i].end) { 194 194 - wl_needed = true; 195 195 - break; 196 196 - } 98 98 + /* 99 99 + * Only try to take the wakelock if it's not marked as taken 100 100 + * yet. It may be already taken at this point if we have 101 101 + * already released the last reference, but the work has not 102 102 + * run yet. 103 103 + */ 104 104 + if (wl->taken) 105 105 + return; 106 106 + 107 107 + __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, 0, 108 108 + DMC_WAKELOCK_CTL_REQ); 109 109 + 110 110 + /* 111 111 + * We need to use the atomic variant of the waiting routine 112 112 + * because the DMC wakelock is also taken in atomic context. 113 113 + */ 114 114 + if (__intel_de_wait_for_register_atomic_nowl(display, DMC_WAKELOCK1_CTL, 115 115 + DMC_WAKELOCK_CTL_ACK, 116 116 + DMC_WAKELOCK_CTL_ACK, 117 117 + DMC_WAKELOCK_CTL_TIMEOUT_US)) { 118 118 + WARN_RATELIMIT(1, "DMC wakelock ack timed out"); 119 119 + return; 197 120 } 198 121 199 199 - return wl_needed; 122 122 + wl->taken = true; 123 123 + } 124 124 + 125 125 + static bool intel_dmc_wl_reg_in_range(i915_reg_t reg, 126 126 + const struct intel_dmc_wl_range ranges[]) 127 127 + { 128 128 + u32 offset = i915_mmio_reg_offset(reg); 129 129 + 130 130 + for (int i = 0; ranges[i].start; i++) { 131 131 + u32 end = ranges[i].end ?: ranges[i].start; 132 132 + 133 133 + if (ranges[i].start <= offset && offset <= end) 134 134 + return true; 135 135 + } 136 136 + 137 137 + return false; 138 138 + } 139 139 + 140 140 + static bool intel_dmc_wl_check_range(i915_reg_t reg, u32 dc_state) 141 141 + { 142 142 + const struct intel_dmc_wl_range *ranges; 143 143 + 144 144 + /* 145 145 + * Check that the offset is in one of the ranges for which 146 146 + * registers are powered off during DC states. 147 147 + */ 148 148 + if (intel_dmc_wl_reg_in_range(reg, powered_off_ranges)) 149 149 + return true; 150 150 + 151 151 + /* 152 152 + * Check that the offset is for a register that is touched by 153 153 + * the DMC and requires a DC exit for proper access. 154 154 + */ 155 155 + switch (dc_state) { 156 156 + case DC_STATE_EN_DC3CO: 157 157 + ranges = xe3lpd_dc3co_dmc_ranges; 158 158 + break; 159 159 + case DC_STATE_EN_UPTO_DC5: 160 160 + case DC_STATE_EN_UPTO_DC6: 161 161 + ranges = xe3lpd_dc5_dc6_dmc_ranges; 162 162 + break; 163 163 + default: 164 164 + ranges = NULL; 165 165 + } 166 166 + 167 167 + if (ranges && intel_dmc_wl_reg_in_range(reg, ranges)) 168 168 + return true; 169 169 + 170 170 + return false; 200 171 } 201 172 202 173 static bool __intel_dmc_wl_supported(struct intel_display *display) 203 174 { 204 204 - if (DISPLAY_VER(display) < 20 || 205 205 - !intel_dmc_has_payload(display) || 206 206 - !display->params.enable_dmc_wl) 207 207 - return false; 175 175 + return display->params.enable_dmc_wl && intel_dmc_has_payload(display); 176 176 + } 208 177 209 209 - return true; 178 178 + static void intel_dmc_wl_sanitize_param(struct intel_display *display) 179 179 + { 180 180 + if (!HAS_DMC_WAKELOCK(display)) 181 181 + display->params.enable_dmc_wl = 0; 182 182 + else if (display->params.enable_dmc_wl >= 0) 183 183 + display->params.enable_dmc_wl = !!display->params.enable_dmc_wl; 184 184 + else 185 185 + display->params.enable_dmc_wl = DISPLAY_VER(display) >= 30; 186 186 + 187 187 + drm_dbg_kms(display->drm, "Sanitized enable_dmc_wl value: %d\n", 188 188 + display->params.enable_dmc_wl); 210 189 } 211 190 212 191 void intel_dmc_wl_init(struct intel_display *display) 213 192 { 214 193 struct intel_dmc_wl *wl = &display->wl; 215 194 216 216 - /* don't call __intel_dmc_wl_supported(), DMC is not loaded yet */ 217 217 - if (DISPLAY_VER(display) < 20 || !display->params.enable_dmc_wl) 195 195 + intel_dmc_wl_sanitize_param(display); 196 196 + 197 197 + if (!display->params.enable_dmc_wl) 218 198 return; 219 199 220 200 INIT_DELAYED_WORK(&wl->work, intel_dmc_wl_work); ··· 294 130 refcount_set(&wl->refcount, 0); 295 131 } 296 132 297 297 - void intel_dmc_wl_enable(struct intel_display *display) 133 133 + /* Must only be called as part of enabling dynamic DC states. */ 134 134 + void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state) 298 135 { 299 136 struct intel_dmc_wl *wl = &display->wl; 300 137 unsigned long flags; ··· 305 140 306 141 spin_lock_irqsave(&wl->lock, flags); 307 142 308 308 - if (wl->enabled) 143 143 + wl->dc_state = dc_state; 144 144 + 145 145 + if (drm_WARN_ON(display->drm, wl->enabled)) 309 146 goto out_unlock; 310 147 311 148 /* ··· 318 151 __intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, 0, DMC_WAKELOCK_CFG_ENABLE); 319 152 320 153 wl->enabled = true; 321 321 - wl->taken = false; 154 154 + 155 155 + /* 156 156 + * This would be racy in the following scenario: 157 157 + * 158 158 + * 1. Function A calls intel_dmc_wl_get(); 159 159 + * 2. Some function calls intel_dmc_wl_disable(); 160 160 + * 3. Some function calls intel_dmc_wl_enable(); 161 161 + * 4. Concurrently with (3), function A performs the MMIO in between 162 162 + * setting DMC_WAKELOCK_CFG_ENABLE and asserting the lock with 163 163 + * __intel_dmc_wl_take(). 164 164 + * 165 165 + * TODO: Check with the hardware team whether it is safe to assert the 166 166 + * hardware lock before enabling to avoid such a scenario. Otherwise, we 167 167 + * would need to deal with it via software synchronization. 168 168 + */ 169 169 + if (refcount_read(&wl->refcount)) 170 170 + __intel_dmc_wl_take(display); 322 171 323 172 out_unlock: 324 173 spin_unlock_irqrestore(&wl->lock, flags); 325 174 } 326 175 176 176 + /* Must only be called as part of disabling dynamic DC states. */ 327 177 void intel_dmc_wl_disable(struct intel_display *display) 328 178 { 329 179 struct intel_dmc_wl *wl = &display->wl; ··· 349 165 if (!__intel_dmc_wl_supported(display)) 350 166 return; 351 167 352 352 - flush_delayed_work(&wl->work); 168 168 + intel_dmc_wl_flush_release_work(display); 353 169 354 170 spin_lock_irqsave(&wl->lock, flags); 355 171 356 356 - if (!wl->enabled) 172 172 + if (drm_WARN_ON(display->drm, !wl->enabled)) 357 173 goto out_unlock; 358 174 359 175 /* Disable wakelock in DMC */ 360 176 __intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, DMC_WAKELOCK_CFG_ENABLE, 0); 361 177 362 362 - refcount_set(&wl->refcount, 0); 363 178 wl->enabled = false; 179 179 + 180 180 + /* 181 181 + * The spec is not explicit about the expectation of existing 182 182 + * lock users at the moment of disabling, but it does say that we must 183 183 + * clear DMC_WAKELOCK_CTL_REQ, which gives us a clue that it is okay to 184 184 + * disable with existing lock users. 185 185 + * 186 186 + * TODO: Get the correct expectation from the hardware team. 187 187 + */ 188 188 + __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0); 189 189 + 364 190 wl->taken = false; 365 191 366 192 out_unlock: 367 193 spin_unlock_irqrestore(&wl->lock, flags); 194 194 + } 195 195 + 196 196 + void intel_dmc_wl_flush_release_work(struct intel_display *display) 197 197 + { 198 198 + struct intel_dmc_wl *wl = &display->wl; 199 199 + 200 200 + if (!__intel_dmc_wl_supported(display)) 201 201 + return; 202 202 + 203 203 + flush_delayed_work(&wl->work); 368 204 } 369 205 370 206 void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg) ··· 395 191 if (!__intel_dmc_wl_supported(display)) 396 192 return; 397 193 398 398 - if (!intel_dmc_wl_check_range(reg.reg)) 399 399 - return; 400 400 - 401 194 spin_lock_irqsave(&wl->lock, flags); 402 195 403 403 - if (!wl->enabled) 196 196 + if (i915_mmio_reg_valid(reg) && !intel_dmc_wl_check_range(reg, wl->dc_state)) 404 197 goto out_unlock; 198 198 + 199 199 + if (!wl->enabled) { 200 200 + if (!refcount_inc_not_zero(&wl->refcount)) 201 201 + refcount_set(&wl->refcount, 1); 202 202 + goto out_unlock; 203 203 + } 405 204 406 205 cancel_delayed_work(&wl->work); 407 206 ··· 413 206 414 207 refcount_set(&wl->refcount, 1); 415 208 416 416 - /* 417 417 - * Only try to take the wakelock if it's not marked as taken 418 418 - * yet. It may be already taken at this point if we have 419 419 - * already released the last reference, but the work has not 420 420 - * run yet. 421 421 - */ 422 422 - if (!wl->taken) { 423 423 - __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, 0, 424 424 - DMC_WAKELOCK_CTL_REQ); 425 425 - 426 426 - if (__intel_de_wait_for_register_nowl(display, DMC_WAKELOCK1_CTL, 427 427 - DMC_WAKELOCK_CTL_ACK, 428 428 - DMC_WAKELOCK_CTL_ACK, 429 429 - DMC_WAKELOCK_CTL_TIMEOUT)) { 430 430 - WARN_RATELIMIT(1, "DMC wakelock ack timed out"); 431 431 - goto out_unlock; 432 432 - } 433 433 - 434 434 - wl->taken = true; 435 435 - } 209 209 + __intel_dmc_wl_take(display); 436 210 437 211 out_unlock: 438 212 spin_unlock_irqrestore(&wl->lock, flags); ··· 427 239 if (!__intel_dmc_wl_supported(display)) 428 240 return; 429 241 430 430 - if (!intel_dmc_wl_check_range(reg.reg)) 431 431 - return; 432 432 - 433 242 spin_lock_irqsave(&wl->lock, flags); 434 243 435 435 - if (!wl->enabled) 244 244 + if (i915_mmio_reg_valid(reg) && !intel_dmc_wl_check_range(reg, wl->dc_state)) 436 245 goto out_unlock; 437 246 438 247 if (WARN_RATELIMIT(!refcount_read(&wl->refcount), ··· 437 252 goto out_unlock; 438 253 439 254 if (refcount_dec_and_test(&wl->refcount)) { 255 255 + if (!wl->enabled) 256 256 + goto out_unlock; 257 257 + 440 258 __intel_dmc_wl_release(display); 441 259 442 260 goto out_unlock; ··· 447 259 448 260 out_unlock: 449 261 spin_unlock_irqrestore(&wl->lock, flags); 262 262 + } 263 263 + 264 264 + void intel_dmc_wl_get_noreg(struct intel_display *display) 265 265 + { 266 266 + intel_dmc_wl_get(display, INVALID_MMIO_REG); 267 267 + } 268 268 + 269 269 + void intel_dmc_wl_put_noreg(struct intel_display *display) 270 270 + { 271 271 + intel_dmc_wl_put(display, INVALID_MMIO_REG); 450 272 }

+12 -2

drivers/gpu/drm/i915/display/intel_dmc_wl.h

reviewed

··· 15 15 struct intel_display; 16 16 17 17 struct intel_dmc_wl { 18 18 - spinlock_t lock; /* protects enabled, taken and refcount */ 18 18 + spinlock_t lock; /* protects enabled, taken, dc_state and refcount */ 19 19 bool enabled; 20 20 bool taken; 21 21 refcount_t refcount; 22 22 + /* 23 23 + * We are keeping a copy of the enabled DC state because 24 24 + * intel_display.power.domains is protected by a mutex and we do 25 25 + * not want call mutex_lock() in atomic context, where some of 26 26 + * the tracked MMIO operations happen. 27 27 + */ 28 28 + u32 dc_state; 22 29 struct delayed_work work; 23 30 }; 24 31 25 32 void intel_dmc_wl_init(struct intel_display *display); 26 26 - void intel_dmc_wl_enable(struct intel_display *display); 33 33 + void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state); 27 34 void intel_dmc_wl_disable(struct intel_display *display); 35 35 + void intel_dmc_wl_flush_release_work(struct intel_display *display); 28 36 void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg); 29 37 void intel_dmc_wl_put(struct intel_display *display, i915_reg_t reg); 38 38 + void intel_dmc_wl_get_noreg(struct intel_display *display); 39 39 + void intel_dmc_wl_put_noreg(struct intel_display *display); 30 40 31 41 #endif /* __INTEL_WAKELOCK_H__ */

+66 -44

drivers/gpu/drm/i915/display/intel_dp.c

reviewed

··· 28 28 #include <linux/export.h> 29 29 #include <linux/i2c.h> 30 30 #include <linux/notifier.h> 31 31 + #include <linux/seq_buf.h> 31 32 #include <linux/slab.h> 32 33 #include <linux/sort.h> 33 34 #include <linux/string_helpers.h> ··· 110 109 /* Constants for DP DSC configurations */ 111 110 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; 112 111 113 113 - /* With Single pipe configuration, HW is capable of supporting maximum 114 114 - * of 4 slices per line. 112 112 + /* 113 113 + * With Single pipe configuration, HW is capable of supporting maximum of: 114 114 + * 2 slices per line for ICL, BMG 115 115 + * 4 slices per line for other platforms. 116 116 + * For now consider a max of 2 slices per line, which works for all platforms. 117 117 + * With this we can have max of 4 DSC Slices per pipe. 118 118 + * 119 119 + * For higher resolutions where 12 slice support is required with 120 120 + * ultrajoiner, only then each pipe can support 3 slices. 121 121 + * 122 122 + * #TODO Split this better to use 4 slices/dsc engine where supported. 115 123 */ 116 116 - static const u8 valid_dsc_slicecount[] = {1, 2, 4}; 124 124 + static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4}; 117 125 118 126 /** 119 127 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) ··· 1030 1020 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { 1031 1021 u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes; 1032 1022 1023 1023 + /* 1024 1024 + * 3 DSC Slices per pipe need 3 DSC engines, 1025 1025 + * which is supported only with Ultrajoiner. 1026 1026 + */ 1027 1027 + if (valid_dsc_slicecount[i] == 3 && num_joined_pipes != 4) 1028 1028 + continue; 1029 1029 + 1033 1030 if (test_slice_count > 1034 1031 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) 1035 1032 break; ··· 1047 1030 * whenever bigjoiner is enabled. 1048 1031 */ 1049 1032 if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2) 1033 1033 + continue; 1034 1034 + 1035 1035 + if (mode_hdisplay % test_slice_count) 1050 1036 continue; 1051 1037 1052 1038 if (min_slice_count <= test_slice_count) ··· 1353 1333 int hdisplay, int clock) 1354 1334 { 1355 1335 struct intel_display *display = to_intel_display(intel_dp); 1356 1356 - struct drm_i915_private *i915 = to_i915(display->drm); 1357 1336 1358 1337 if (connector->force_joined_pipes) 1359 1338 return connector->force_joined_pipes; 1360 1339 1361 1361 - if (HAS_ULTRAJOINER(i915) && 1340 1340 + if (HAS_ULTRAJOINER(display) && 1362 1341 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4)) 1363 1342 return 4; 1364 1343 1365 1365 - if ((HAS_BIGJOINER(i915) || HAS_UNCOMPRESSED_JOINER(i915)) && 1344 1344 + if ((HAS_BIGJOINER(display) || HAS_UNCOMPRESSED_JOINER(display)) && 1366 1345 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2)) 1367 1346 return 2; 1368 1347 ··· 1507 1488 return DISPLAY_VER(i915) >= 10; 1508 1489 } 1509 1490 1510 1510 - static void snprintf_int_array(char *str, size_t len, 1511 1511 - const int *array, int nelem) 1491 1491 + static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem) 1512 1492 { 1513 1493 int i; 1514 1494 1515 1515 - str[0] = '\0'; 1516 1516 - 1517 1517 - for (i = 0; i < nelem; i++) { 1518 1518 - int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); 1519 1519 - if (r >= len) 1520 1520 - return; 1521 1521 - str += r; 1522 1522 - len -= r; 1523 1523 - } 1495 1495 + for (i = 0; i < nelem; i++) 1496 1496 + seq_buf_printf(s, "%s%d", i ? ", " : "", array[i]); 1524 1497 } 1525 1498 1526 1499 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1527 1500 { 1528 1528 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1529 1529 - char str[128]; /* FIXME: too big for stack? */ 1501 1501 + struct intel_display *display = to_intel_display(intel_dp); 1502 1502 + DECLARE_SEQ_BUF(s, 128); /* FIXME: too big for stack? */ 1530 1503 1531 1504 if (!drm_debug_enabled(DRM_UT_KMS)) 1532 1505 return; 1533 1506 1534 1534 - snprintf_int_array(str, sizeof(str), 1535 1535 - intel_dp->source_rates, intel_dp->num_source_rates); 1536 1536 - drm_dbg_kms(&i915->drm, "source rates: %s\n", str); 1507 1507 + seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates); 1508 1508 + drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s)); 1537 1509 1538 1538 - snprintf_int_array(str, sizeof(str), 1539 1539 - intel_dp->sink_rates, intel_dp->num_sink_rates); 1540 1540 - drm_dbg_kms(&i915->drm, "sink rates: %s\n", str); 1510 1510 + seq_buf_clear(&s); 1511 1511 + seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates); 1512 1512 + drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s)); 1541 1513 1542 1542 - snprintf_int_array(str, sizeof(str), 1543 1543 - intel_dp->common_rates, intel_dp->num_common_rates); 1544 1544 - drm_dbg_kms(&i915->drm, "common rates: %s\n", str); 1514 1514 + seq_buf_clear(&s); 1515 1515 + seq_buf_print_array(&s, intel_dp->common_rates, intel_dp->num_common_rates); 1516 1516 + drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s)); 1545 1517 } 1546 1518 1547 1519 static int forced_link_rate(struct intel_dp *intel_dp) ··· 1710 1700 1711 1701 static bool has_seamless_m_n(struct intel_connector *connector) 1712 1702 { 1713 1713 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 1703 1703 + struct intel_display *display = to_intel_display(connector); 1714 1704 1715 1705 /* 1716 1706 * Seamless M/N reprogramming only implemented 1717 1707 * for BDW+ double buffered M/N registers so far. 1718 1708 */ 1719 1719 - return HAS_DOUBLE_BUFFERED_M_N(i915) && 1709 1709 + return HAS_DOUBLE_BUFFERED_M_N(display) && 1720 1710 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 1721 1711 } 1722 1712 ··· 2030 2020 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) 2031 2021 { 2032 2022 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2023 2023 + 2024 2024 + /* 2025 2025 + * Forcing DSC and using the platform's max compressed bpp is seen to cause 2026 2026 + * underruns. Since DSC isn't needed in these cases, limit the 2027 2027 + * max compressed bpp to 18, which is a safe value across platforms with different 2028 2028 + * pipe bpps. 2029 2029 + */ 2030 2030 + if (intel_dp->force_dsc_en) 2031 2031 + return 18; 2033 2032 2034 2033 /* 2035 2034 * Max Compressed bpp for Gen 13+ is 27bpp. ··· 2424 2405 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate 2425 2406 * is greater than the maximum Cdclock and if slice count is even 2426 2407 * then we need to use 2 VDSC instances. 2408 2408 + * In case of Ultrajoiner along with 12 slices we need to use 3 2409 2409 + * VDSC instances. 2427 2410 */ 2428 2428 - if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) 2429 2429 - pipe_config->dsc.dsc_split = true; 2411 2411 + if (pipe_config->joiner_pipes && num_joined_pipes == 4 && 2412 2412 + pipe_config->dsc.slice_count == 12) 2413 2413 + pipe_config->dsc.num_streams = 3; 2414 2414 + else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) 2415 2415 + pipe_config->dsc.num_streams = 2; 2416 2416 + else 2417 2417 + pipe_config->dsc.num_streams = 1; 2430 2418 2431 2419 ret = intel_dp_dsc_compute_params(connector, pipe_config); 2432 2420 if (ret < 0) { ··· 3090 3064 struct intel_connector *connector = intel_dp->attached_connector; 3091 3065 int ret = 0, link_bpp_x16; 3092 3066 3093 3093 - if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A) 3094 3094 - pipe_config->has_pch_encoder = true; 3095 3095 - 3096 3067 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode); 3097 3068 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 3098 3069 ret = intel_panel_compute_config(connector, adjusted_mode); ··· 3171 3148 /* FIXME: abstract this better */ 3172 3149 if (pipe_config->splitter.enable) 3173 3150 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; 3174 3174 - 3175 3175 - if (!HAS_DDI(dev_priv)) 3176 3176 - g4x_dp_set_clock(encoder, pipe_config); 3177 3151 3178 3152 intel_vrr_compute_config(pipe_config, conn_state); 3179 3153 intel_dp_compute_as_sdp(intel_dp, pipe_config); ··· 3426 3406 static void 3427 3407 intel_dp_init_source_oui(struct intel_dp *intel_dp) 3428 3408 { 3429 3429 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3409 3409 + struct intel_display *display = to_intel_display(intel_dp); 3430 3410 u8 oui[] = { 0x00, 0xaa, 0x01 }; 3431 3411 u8 buf[3] = {}; 3432 3412 ··· 3440 3420 * already set to what we want, so as to avoid clearing any state by accident 3441 3421 */ 3442 3422 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) 3443 3443 - drm_err(&i915->drm, "Failed to read source OUI\n"); 3423 3423 + drm_dbg_kms(display->drm, "Failed to read source OUI\n"); 3444 3424 3445 3425 if (memcmp(oui, buf, sizeof(oui)) == 0) { 3446 3426 /* Assume the OUI was written now. */ ··· 3449 3429 } 3450 3430 3451 3431 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) { 3452 3452 - drm_info(&i915->drm, "Failed to write source OUI\n"); 3432 3432 + drm_dbg_kms(display->drm, "Failed to write source OUI\n"); 3453 3433 WRITE_ONCE(intel_dp->oui_valid, false); 3454 3434 } 3455 3435 ··· 5628 5608 struct drm_modeset_acquire_ctx *ctx, 5629 5609 bool force) 5630 5610 { 5611 5611 + struct intel_display *display = to_intel_display(connector->dev); 5631 5612 struct drm_i915_private *dev_priv = to_i915(connector->dev); 5632 5613 struct intel_connector *intel_connector = 5633 5614 to_intel_connector(connector); ··· 5643 5622 drm_WARN_ON(&dev_priv->drm, 5644 5623 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 5645 5624 5646 5646 - if (!intel_display_device_enabled(dev_priv)) 5625 5625 + if (!intel_display_device_enabled(display)) 5647 5626 return connector_status_disconnected; 5648 5627 5649 5649 - if (!intel_display_driver_check_access(dev_priv)) 5628 5628 + if (!intel_display_driver_check_access(display)) 5650 5629 return connector->status; 5651 5630 5652 5631 intel_dp_flush_connector_commits(intel_connector); ··· 5768 5747 static void 5769 5748 intel_dp_force(struct drm_connector *connector) 5770 5749 { 5750 5750 + struct intel_display *display = to_intel_display(connector->dev); 5771 5751 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 5772 5752 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5773 5753 struct intel_encoder *intel_encoder = &dig_port->base; ··· 5777 5755 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 5778 5756 connector->base.id, connector->name); 5779 5757 5780 5780 - if (!intel_display_driver_check_access(dev_priv)) 5758 5758 + if (!intel_display_driver_check_access(display)) 5781 5759 return; 5782 5760 5783 5761 intel_dp_unset_edid(intel_dp);

-1

drivers/gpu/drm/i915/display/intel_dp_aux.c

reviewed

··· 6 6 #include "i915_drv.h" 7 7 #include "i915_reg.h" 8 8 #include "i915_trace.h" 9 9 - #include "intel_bios.h" 10 9 #include "intel_de.h" 11 10 #include "intel_display_types.h" 12 11 #include "intel_dp.h"

+12 -11

drivers/gpu/drm/i915/display/intel_dp_link_training.c

reviewed

··· 898 898 899 899 voltage_tries = 1; 900 900 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 901 901 - usleep_range(delay_us, 2 * delay_us); 901 901 + fsleep(delay_us); 902 902 903 903 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 904 904 link_status) < 0) { ··· 1040 1040 } 1041 1041 1042 1042 for (tries = 0; tries < 5; tries++) { 1043 1043 - usleep_range(delay_us, 2 * delay_us); 1043 1043 + fsleep(delay_us); 1044 1044 1045 1045 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 1046 1046 link_status) < 0) { ··· 1414 1414 } 1415 1415 1416 1416 /* Time budget for the LANEx_EQ_DONE Sequence */ 1417 1417 - deadline = jiffies + msecs_to_jiffies_timeout(400); 1417 1417 + deadline = jiffies + msecs_to_jiffies_timeout(450); 1418 1418 1419 1419 for (try = 0; try < max_tries; try++) { 1420 1420 - usleep_range(delay_us, 2 * delay_us); 1421 1421 - 1422 1422 - /* 1423 1423 - * The delay may get updated. The transmitter shall read the 1424 1424 - * delay before link status during link training. 1425 1425 - */ 1426 1426 - delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1420 1420 + fsleep(delay_us); 1427 1421 1428 1422 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1429 1423 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); ··· 1445 1451 if (time_after(jiffies, deadline)) 1446 1452 timeout = true; /* try one last time after deadline */ 1447 1453 1448 1448 - /* Update signal levels and training set as requested. */ 1454 1454 + /* 1455 1455 + * During LT, Tx shall read AUX_RD_INTERVAL just before writing the new FFE 1456 1456 + * presets. 1457 1457 + */ 1458 1458 + delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1459 1459 + 1449 1460 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1461 1461 + 1462 1462 + /* Update signal levels and training set as requested. */ 1450 1463 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1451 1464 lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n"); 1452 1465 return false;

+336 -317

drivers/gpu/drm/i915/display/intel_dp_mst.c

reviewed

··· 53 53 #include "intel_vdsc.h" 54 54 #include "skl_scaler.h" 55 55 56 56 + /* 57 57 + * DP MST (DisplayPort Multi-Stream Transport) 58 58 + * 59 59 + * MST support on the source depends on the platform and port. DP initialization 60 60 + * sets up MST for each MST capable encoder. This will become the primary 61 61 + * encoder for the port. 62 62 + * 63 63 + * MST initialization of each primary encoder creates MST stream encoders, one 64 64 + * per pipe, and initializes the MST topology manager. The MST stream encoders 65 65 + * are sometimes called "fake encoders", because they're virtual, not 66 66 + * physical. Thus there are (number of MST capable ports) x (number of pipes) 67 67 + * MST stream encoders in total. 68 68 + * 69 69 + * Decision to use MST for a sink happens at detect on the connector attached to 70 70 + * the primary encoder, and this will not change while the sink is connected. We 71 71 + * always use MST when possible, including for SST sinks with sideband messaging 72 72 + * support. 73 73 + * 74 74 + * The connectors for the MST streams are added and removed dynamically by the 75 75 + * topology manager. Their connection status is also determined by the topology 76 76 + * manager. 77 77 + * 78 78 + * On hardware, each transcoder may be associated with a single DDI 79 79 + * port. Multiple transcoders may be associated with the same DDI port only if 80 80 + * the port is in MST mode. 81 81 + * 82 82 + * On TGL+, all the transcoders streaming on the same DDI port will indicate a 83 83 + * primary transcoder; the TGL_DP_TP_CTL and TGL_DP_TP_STATUS registers are 84 84 + * relevant only on the primary transcoder. Prior to that, they are port 85 85 + * registers. 86 86 + */ 87 87 + 88 88 + /* From fake MST stream encoder to primary encoder */ 89 89 + static struct intel_encoder *to_primary_encoder(struct intel_encoder *encoder) 90 90 + { 91 91 + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 92 92 + struct intel_digital_port *dig_port = intel_mst->primary; 93 93 + 94 94 + return &dig_port->base; 95 95 + } 96 96 + 97 97 + /* From fake MST stream encoder to primary DP */ 98 98 + static struct intel_dp *to_primary_dp(struct intel_encoder *encoder) 99 99 + { 100 100 + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 101 101 + struct intel_digital_port *dig_port = intel_mst->primary; 102 102 + 103 103 + return &dig_port->dp; 104 104 + } 105 105 + 56 106 static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state, 57 107 bool dsc) 58 108 { 59 59 - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 109 109 + struct intel_display *display = to_intel_display(crtc_state); 60 110 const struct drm_display_mode *adjusted_mode = 61 111 &crtc_state->hw.adjusted_mode; 62 112 63 63 - if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(i915) >= 20 || !dsc) 113 113 + if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc) 64 114 return INT_MAX; 65 115 66 116 /* ··· 211 161 num_joined_pipes); 212 162 } 213 163 214 214 - static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, 215 215 - struct intel_crtc_state *crtc_state, 216 216 - int max_bpp, 217 217 - int min_bpp, 218 218 - struct link_config_limits *limits, 219 219 - struct drm_connector_state *conn_state, 220 220 - int step, 221 221 - bool dsc) 164 164 + static int mst_stream_find_vcpi_slots_for_bpp(struct intel_dp *intel_dp, 165 165 + struct intel_crtc_state *crtc_state, 166 166 + int max_bpp, int min_bpp, 167 167 + struct link_config_limits *limits, 168 168 + struct drm_connector_state *conn_state, 169 169 + int step, bool dsc) 222 170 { 171 171 + struct intel_display *display = to_intel_display(intel_dp); 223 172 struct drm_atomic_state *state = crtc_state->uapi.state; 224 224 - struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 225 225 - struct intel_dp *intel_dp = &intel_mst->primary->dp; 226 173 struct drm_dp_mst_topology_state *mst_state; 227 174 struct intel_connector *connector = 228 175 to_intel_connector(conn_state->connector); 229 229 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 230 176 const struct drm_display_mode *adjusted_mode = 231 177 &crtc_state->hw.adjusted_mode; 232 178 int bpp, slots = -EINVAL; ··· 250 204 251 205 max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc); 252 206 if (max_bpp > max_dpt_bpp) { 253 253 - drm_dbg_kms(&i915->drm, "Limiting bpp to max DPT bpp (%d -> %d)\n", 207 207 + drm_dbg_kms(display->drm, "Limiting bpp to max DPT bpp (%d -> %d)\n", 254 208 max_bpp, max_dpt_bpp); 255 209 max_bpp = max_dpt_bpp; 256 210 } 257 211 258 258 - drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n", 212 212 + drm_dbg_kms(display->drm, "Looking for slots in range min bpp %d max bpp %d\n", 259 213 min_bpp, max_bpp); 260 214 261 215 if (dsc) { 262 216 dsc_slice_count = intel_dp_mst_dsc_get_slice_count(connector, crtc_state); 263 217 if (!dsc_slice_count) { 264 264 - drm_dbg_kms(&i915->drm, "Can't get valid DSC slice count\n"); 218 218 + drm_dbg_kms(display->drm, "Can't get valid DSC slice count\n"); 265 219 266 220 return -ENOSPC; 267 221 } ··· 274 228 int remote_tu; 275 229 fixed20_12 pbn; 276 230 277 277 - drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); 231 231 + drm_dbg_kms(display->drm, "Trying bpp %d\n", bpp); 278 232 279 233 link_bpp_x16 = fxp_q4_from_int(dsc ? bpp : 280 234 intel_dp_output_bpp(crtc_state->output_format, bpp)); ··· 327 281 pbn.full = remote_tu * mst_state->pbn_div.full; 328 282 crtc_state->pbn = dfixed_trunc(pbn); 329 283 330 330 - drm_WARN_ON(&i915->drm, remote_tu < crtc_state->dp_m_n.tu); 284 284 + drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu); 331 285 crtc_state->dp_m_n.tu = remote_tu; 332 286 333 287 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr, ··· 337 291 return slots; 338 292 339 293 if (slots >= 0) { 340 340 - drm_WARN_ON(&i915->drm, slots != crtc_state->dp_m_n.tu); 294 294 + drm_WARN_ON(display->drm, slots != crtc_state->dp_m_n.tu); 341 295 342 296 break; 343 297 } ··· 348 302 slots = ret; 349 303 350 304 if (slots < 0) { 351 351 - drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n", 305 305 + drm_dbg_kms(display->drm, "failed finding vcpi slots:%d\n", 352 306 slots); 353 307 } else { 354 308 if (!dsc) 355 309 crtc_state->pipe_bpp = bpp; 356 310 else 357 311 crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp); 358 358 - drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc); 312 312 + drm_dbg_kms(display->drm, "Got %d slots for pipe bpp %d dsc %d\n", 313 313 + slots, bpp, dsc); 359 314 } 360 315 361 316 return slots; 362 317 } 363 318 364 364 - static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, 365 365 - struct intel_crtc_state *crtc_state, 366 366 - struct drm_connector_state *conn_state, 367 367 - struct link_config_limits *limits) 319 319 + static int mst_stream_compute_link_config(struct intel_dp *intel_dp, 320 320 + struct intel_crtc_state *crtc_state, 321 321 + struct drm_connector_state *conn_state, 322 322 + struct link_config_limits *limits) 368 323 { 369 324 int slots = -EINVAL; 370 325 ··· 373 326 * FIXME: allocate the BW according to link_bpp, which in the case of 374 327 * YUV420 is only half of the pipe bpp value. 375 328 */ 376 376 - slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, 377 377 - fxp_q4_to_int(limits->link.max_bpp_x16), 378 378 - fxp_q4_to_int(limits->link.min_bpp_x16), 379 379 - limits, 380 380 - conn_state, 2 * 3, false); 329 329 + slots = mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state, 330 330 + fxp_q4_to_int(limits->link.max_bpp_x16), 331 331 + fxp_q4_to_int(limits->link.min_bpp_x16), 332 332 + limits, 333 333 + conn_state, 2 * 3, false); 381 334 382 335 if (slots < 0) 383 336 return slots; ··· 385 338 return 0; 386 339 } 387 340 388 388 - static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, 389 389 - struct intel_crtc_state *crtc_state, 390 390 - struct drm_connector_state *conn_state, 391 391 - struct link_config_limits *limits) 341 341 + static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp, 342 342 + struct intel_crtc_state *crtc_state, 343 343 + struct drm_connector_state *conn_state, 344 344 + struct link_config_limits *limits) 392 345 { 393 393 - struct intel_connector *connector = 394 394 - to_intel_connector(conn_state->connector); 346 346 + struct intel_display *display = to_intel_display(intel_dp); 347 347 + struct intel_connector *connector = to_intel_connector(conn_state->connector); 395 348 struct drm_i915_private *i915 = to_i915(connector->base.dev); 396 349 int slots = -EINVAL; 397 350 int i, num_bpc; ··· 401 354 int min_compressed_bpp, max_compressed_bpp; 402 355 403 356 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ 404 404 - if (DISPLAY_VER(i915) >= 12) 357 357 + if (DISPLAY_VER(display) >= 12) 405 358 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); 406 359 else 407 360 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc); ··· 412 365 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, 413 366 dsc_bpc); 414 367 415 415 - drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n", 368 368 + drm_dbg_kms(display->drm, "DSC Source supported min bpp %d max bpp %d\n", 416 369 min_bpp, max_bpp); 417 370 418 371 sink_max_bpp = dsc_bpc[0] * 3; ··· 425 378 sink_max_bpp = dsc_bpc[i] * 3; 426 379 } 427 380 428 428 - drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n", 381 381 + drm_dbg_kms(display->drm, "DSC Sink supported min bpp %d max bpp %d\n", 429 382 sink_min_bpp, sink_max_bpp); 430 383 431 384 if (min_bpp < sink_min_bpp) ··· 446 399 min_compressed_bpp = max(min_compressed_bpp, 447 400 fxp_q4_to_int_roundup(limits->link.min_bpp_x16)); 448 401 449 449 - drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n", 402 402 + drm_dbg_kms(display->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n", 450 403 min_compressed_bpp, max_compressed_bpp); 451 404 452 405 /* Align compressed bpps according to our own constraints */ ··· 455 408 min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp, 456 409 crtc_state->pipe_bpp); 457 410 458 458 - slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp, 459 459 - min_compressed_bpp, limits, 460 460 - conn_state, 1, true); 411 411 + slots = mst_stream_find_vcpi_slots_for_bpp(intel_dp, crtc_state, max_compressed_bpp, 412 412 + min_compressed_bpp, limits, 413 413 + conn_state, 1, true); 461 414 462 415 if (slots < 0) 463 416 return slots; 464 417 465 418 return 0; 466 419 } 467 467 - static int intel_dp_mst_update_slots(struct intel_encoder *encoder, 468 468 - struct intel_crtc_state *crtc_state, 469 469 - struct drm_connector_state *conn_state) 420 420 + 421 421 + static int mst_stream_update_slots(struct intel_dp *intel_dp, 422 422 + struct intel_crtc_state *crtc_state, 423 423 + struct drm_connector_state *conn_state) 470 424 { 471 471 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 472 472 - struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 473 473 - struct intel_dp *intel_dp = &intel_mst->primary->dp; 425 425 + struct intel_display *display = to_intel_display(intel_dp); 474 426 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr; 475 427 struct drm_dp_mst_topology_state *topology_state; 476 428 u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ? ··· 477 431 478 432 topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr); 479 433 if (IS_ERR(topology_state)) { 480 480 - drm_dbg_kms(&i915->drm, "slot update failed\n"); 434 434 + drm_dbg_kms(display->drm, "slot update failed\n"); 481 435 return PTR_ERR(topology_state); 482 436 } 483 437 ··· 525 479 struct link_config_limits *limits, 526 480 bool dsc) 527 481 { 528 528 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 482 482 + struct intel_display *display = to_intel_display(connector); 529 483 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 530 484 int min_bpp_x16 = limits->link.min_bpp_x16; 531 485 ··· 534 488 535 489 if (!dsc) { 536 490 if (intel_dp_supports_dsc(connector, crtc_state)) { 537 537 - drm_dbg_kms(&i915->drm, 491 491 + drm_dbg_kms(display->drm, 538 492 "[CRTC:%d:%s][CONNECTOR:%d:%s] DSC needed by hblank expansion quirk\n", 539 493 crtc->base.base.id, crtc->base.name, 540 494 connector->base.base.id, connector->base.name); 541 495 return false; 542 496 } 543 497 544 544 - drm_dbg_kms(&i915->drm, 498 498 + drm_dbg_kms(display->drm, 545 499 "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to 24 due to hblank expansion quirk\n", 546 500 crtc->base.base.id, crtc->base.name, 547 501 connector->base.base.id, connector->base.name); ··· 554 508 return true; 555 509 } 556 510 557 557 - drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate); 511 511 + drm_WARN_ON(display->drm, limits->min_rate != limits->max_rate); 558 512 559 513 if (limits->max_rate < 540000) 560 514 min_bpp_x16 = fxp_q4_from_int(13); ··· 564 518 if (limits->link.min_bpp_x16 >= min_bpp_x16) 565 519 return true; 566 520 567 567 - drm_dbg_kms(&i915->drm, 521 521 + drm_dbg_kms(display->drm, 568 522 "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " FXP_Q4_FMT " in DSC mode due to hblank expansion quirk\n", 569 523 crtc->base.base.id, crtc->base.name, 570 524 connector->base.base.id, connector->base.name, ··· 579 533 } 580 534 581 535 static bool 582 582 - intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp, 583 583 - const struct intel_connector *connector, 584 584 - struct intel_crtc_state *crtc_state, 585 585 - bool dsc, 586 586 - struct link_config_limits *limits) 536 536 + mst_stream_compute_config_limits(struct intel_dp *intel_dp, 537 537 + const struct intel_connector *connector, 538 538 + struct intel_crtc_state *crtc_state, 539 539 + bool dsc, 540 540 + struct link_config_limits *limits) 587 541 { 588 542 /* 589 543 * for MST we always configure max link bw - the spec doesn't ··· 620 574 dsc); 621 575 } 622 576 623 623 - static int intel_dp_mst_compute_config(struct intel_encoder *encoder, 624 624 - struct intel_crtc_state *pipe_config, 625 625 - struct drm_connector_state *conn_state) 577 577 + static int mst_stream_compute_config(struct intel_encoder *encoder, 578 578 + struct intel_crtc_state *pipe_config, 579 579 + struct drm_connector_state *conn_state) 626 580 { 581 581 + struct intel_display *display = to_intel_display(encoder); 627 582 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 628 583 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); 629 584 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 630 630 - struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 631 631 - struct intel_dp *intel_dp = &intel_mst->primary->dp; 585 585 + struct intel_dp *intel_dp = to_primary_dp(encoder); 632 586 struct intel_connector *connector = 633 587 to_intel_connector(conn_state->connector); 634 588 const struct drm_display_mode *adjusted_mode = ··· 658 612 joiner_needs_dsc = intel_dp_joiner_needs_dsc(dev_priv, num_joined_pipes); 659 613 660 614 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || 661 661 - !intel_dp_mst_compute_config_limits(intel_dp, 662 662 - connector, 663 663 - pipe_config, 664 664 - false, 665 665 - &limits); 615 615 + !mst_stream_compute_config_limits(intel_dp, connector, 616 616 + pipe_config, false, &limits); 666 617 667 618 if (!dsc_needed) { 668 668 - ret = intel_dp_mst_compute_link_config(encoder, pipe_config, 669 669 - conn_state, &limits); 619 619 + ret = mst_stream_compute_link_config(intel_dp, pipe_config, 620 620 + conn_state, &limits); 670 621 671 622 if (ret == -EDEADLK) 672 623 return ret; ··· 674 631 675 632 /* enable compression if the mode doesn't fit available BW */ 676 633 if (dsc_needed) { 677 677 - drm_dbg_kms(&dev_priv->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n", 634 634 + drm_dbg_kms(display->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n", 678 635 str_yes_no(ret), str_yes_no(joiner_needs_dsc), 679 636 str_yes_no(intel_dp->force_dsc_en)); 680 637 681 638 if (!intel_dp_supports_dsc(connector, pipe_config)) 682 639 return -EINVAL; 683 640 684 684 - if (!intel_dp_mst_compute_config_limits(intel_dp, 685 685 - connector, 686 686 - pipe_config, 687 687 - true, 688 688 - &limits)) 641 641 + if (!mst_stream_compute_config_limits(intel_dp, connector, 642 642 + pipe_config, true, 643 643 + &limits)) 689 644 return -EINVAL; 690 645 691 646 /* 692 647 * FIXME: As bpc is hardcoded to 8, as mentioned above, 693 648 * WARN and ignore the debug flag force_dsc_bpc for now. 694 649 */ 695 695 - drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n"); 650 650 + drm_WARN(display->drm, intel_dp->force_dsc_bpc, 651 651 + "Cannot Force BPC for MST\n"); 696 652 /* 697 653 * Try to get at least some timeslots and then see, if 698 654 * we can fit there with DSC. 699 655 */ 700 700 - drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n"); 656 656 + drm_dbg_kms(display->drm, "Trying to find VCPI slots in DSC mode\n"); 701 657 702 702 - ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config, 703 703 - conn_state, &limits); 658 658 + ret = mst_stream_dsc_compute_link_config(intel_dp, pipe_config, 659 659 + conn_state, &limits); 704 660 if (ret < 0) 705 661 return ret; 706 662 ··· 711 669 if (ret) 712 670 return ret; 713 671 714 714 - ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state); 672 672 + ret = mst_stream_update_slots(intel_dp, pipe_config, conn_state); 715 673 if (ret) 716 674 return ret; 717 675 718 676 pipe_config->limited_color_range = 719 677 intel_dp_limited_color_range(pipe_config, conn_state); 720 678 721 721 - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 679 679 + if (display->platform.geminilake || display->platform.broxton) 722 680 pipe_config->lane_lat_optim_mask = 723 681 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 724 682 ··· 740 698 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state, 741 699 struct intel_dp *mst_port) 742 700 { 743 743 - struct drm_i915_private *dev_priv = to_i915(state->base.dev); 701 701 + struct intel_display *display = to_intel_display(state); 744 702 const struct intel_digital_connector_state *conn_state; 745 703 struct intel_connector *connector; 746 704 u8 transcoders = 0; 747 705 int i; 748 706 749 749 - if (DISPLAY_VER(dev_priv) < 12) 707 707 + if (DISPLAY_VER(display) < 12) 750 708 return 0; 751 709 752 710 for_each_new_intel_connector_in_state(state, connector, conn_state, i) { ··· 800 758 struct drm_dp_mst_topology_mgr *mst_mgr, 801 759 struct intel_link_bw_limits *limits) 802 760 { 803 803 - struct drm_i915_private *i915 = to_i915(state->base.dev); 761 761 + struct intel_display *display = to_intel_display(state); 804 762 struct intel_crtc *crtc; 805 763 u8 mst_pipe_mask; 806 764 u8 fec_pipe_mask = 0; ··· 808 766 809 767 mst_pipe_mask = get_pipes_downstream_of_mst_port(state, mst_mgr, NULL); 810 768 811 811 - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mst_pipe_mask) { 769 769 + for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mst_pipe_mask) { 812 770 struct intel_crtc_state *crtc_state = 813 771 intel_atomic_get_new_crtc_state(state, crtc); 814 772 815 773 /* Atomic connector check should've added all the MST CRTCs. */ 816 816 - if (drm_WARN_ON(&i915->drm, !crtc_state)) 774 774 + if (drm_WARN_ON(display->drm, !crtc_state)) 817 775 return -EINVAL; 818 776 819 777 if (crtc_state->fec_enable) ··· 892 850 return 0; 893 851 } 894 852 895 895 - static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder, 896 896 - struct intel_crtc_state *crtc_state, 897 897 - struct drm_connector_state *conn_state) 853 853 + static int mst_stream_compute_config_late(struct intel_encoder *encoder, 854 854 + struct intel_crtc_state *crtc_state, 855 855 + struct drm_connector_state *conn_state) 898 856 { 899 857 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); 900 900 - struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 901 901 - struct intel_dp *intel_dp = &intel_mst->primary->dp; 858 858 + struct intel_dp *intel_dp = to_primary_dp(encoder); 902 859 903 860 /* lowest numbered transcoder will be designated master */ 904 861 crtc_state->mst_master_transcoder = ··· 920 879 * recomputation of the corresponding CRTC states. 921 880 */ 922 881 static int 923 923 - intel_dp_mst_atomic_topology_check(struct intel_connector *connector, 924 924 - struct intel_atomic_state *state) 882 882 + mst_connector_atomic_topology_check(struct intel_connector *connector, 883 883 + struct intel_atomic_state *state) 925 884 { 926 926 - struct drm_i915_private *dev_priv = to_i915(state->base.dev); 885 885 + struct intel_display *display = to_intel_display(connector); 927 886 struct drm_connector_list_iter connector_list_iter; 928 887 struct intel_connector *connector_iter; 929 888 int ret = 0; ··· 931 890 if (!intel_connector_needs_modeset(state, &connector->base)) 932 891 return 0; 933 892 934 934 - drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter); 893 893 + drm_connector_list_iter_begin(display->drm, &connector_list_iter); 935 894 for_each_intel_connector_iter(connector_iter, &connector_list_iter) { 936 895 struct intel_digital_connector_state *conn_iter_state; 937 896 struct intel_crtc_state *crtc_state; ··· 969 928 } 970 929 971 930 static int 972 972 - intel_dp_mst_atomic_check(struct drm_connector *connector, 973 973 - struct drm_atomic_state *_state) 931 931 + mst_connector_atomic_check(struct drm_connector *connector, 932 932 + struct drm_atomic_state *_state) 974 933 { 975 934 struct intel_atomic_state *state = to_intel_atomic_state(_state); 976 935 struct intel_connector *intel_connector = ··· 981 940 if (ret) 982 941 return ret; 983 942 984 984 - ret = intel_dp_mst_atomic_topology_check(intel_connector, state); 943 943 + ret = mst_connector_atomic_topology_check(intel_connector, state); 985 944 if (ret) 986 945 return ret; 987 946 ··· 998 957 intel_connector->port); 999 958 } 1000 959 1001 1001 - static void clear_act_sent(struct intel_encoder *encoder, 1002 1002 - const struct intel_crtc_state *crtc_state) 960 960 + static void mst_stream_disable(struct intel_atomic_state *state, 961 961 + struct intel_encoder *encoder, 962 962 + const struct intel_crtc_state *old_crtc_state, 963 963 + const struct drm_connector_state *old_conn_state) 1003 964 { 1004 1004 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1005 1005 - 1006 1006 - intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state), 1007 1007 - DP_TP_STATUS_ACT_SENT); 1008 1008 - } 1009 1009 - 1010 1010 - static void wait_for_act_sent(struct intel_encoder *encoder, 1011 1011 - const struct intel_crtc_state *crtc_state) 1012 1012 - { 1013 1013 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 965 965 + struct intel_display *display = to_intel_display(state); 1014 966 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 1015 1015 - struct intel_dp *intel_dp = &intel_mst->primary->dp; 1016 1016 - 1017 1017 - if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 1018 1018 - DP_TP_STATUS_ACT_SENT, 1)) 1019 1019 - drm_err(&i915->drm, "Timed out waiting for ACT sent\n"); 1020 1020 - 1021 1021 - drm_dp_check_act_status(&intel_dp->mst_mgr); 1022 1022 - } 1023 1023 - 1024 1024 - static void intel_mst_disable_dp(struct intel_atomic_state *state, 1025 1025 - struct intel_encoder *encoder, 1026 1026 - const struct intel_crtc_state *old_crtc_state, 1027 1027 - const struct drm_connector_state *old_conn_state) 1028 1028 - { 1029 1029 - struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 1030 1030 - struct intel_digital_port *dig_port = intel_mst->primary; 1031 1031 - struct intel_dp *intel_dp = &dig_port->dp; 967 967 + struct intel_dp *intel_dp = to_primary_dp(encoder); 1032 968 struct intel_connector *connector = 1033 969 to_intel_connector(old_conn_state->connector); 1034 1034 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 1035 970 1036 1036 - drm_dbg_kms(&i915->drm, "active links %d\n", 971 971 + drm_dbg_kms(display->drm, "active links %d\n", 1037 972 intel_dp->active_mst_links); 1038 973 1039 974 if (intel_dp->active_mst_links == 1) ··· 1020 1003 intel_dp_sink_disable_decompression(state, connector, old_crtc_state); 1021 1004 } 1022 1005 1023 1023 - static void intel_mst_post_disable_dp(struct intel_atomic_state *state, 1024 1024 - struct intel_encoder *encoder, 1025 1025 - const struct intel_crtc_state *old_crtc_state, 1026 1026 - const struct drm_connector_state *old_conn_state) 1006 1006 + static void mst_stream_post_disable(struct intel_atomic_state *state, 1007 1007 + struct intel_encoder *encoder, 1008 1008 + const struct intel_crtc_state *old_crtc_state, 1009 1009 + const struct drm_connector_state *old_conn_state) 1027 1010 { 1028 1011 struct intel_display *display = to_intel_display(encoder); 1029 1012 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 1030 1030 - struct intel_digital_port *dig_port = intel_mst->primary; 1031 1031 - struct intel_dp *intel_dp = &dig_port->dp; 1013 1013 + struct intel_encoder *primary_encoder = to_primary_encoder(encoder); 1014 1014 + struct intel_dp *intel_dp = to_primary_dp(encoder); 1032 1015 struct intel_connector *connector = 1033 1016 to_intel_connector(old_conn_state->connector); 1034 1017 struct drm_dp_mst_topology_state *old_mst_state = ··· 1039 1022 drm_atomic_get_mst_payload_state(old_mst_state, connector->port); 1040 1023 struct drm_dp_mst_atomic_payload *new_payload = 1041 1024 drm_atomic_get_mst_payload_state(new_mst_state, connector->port); 1042 1042 - struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1043 1025 struct intel_crtc *pipe_crtc; 1044 1026 bool last_mst_stream; 1045 1027 int i; 1046 1028 1047 1029 intel_dp->active_mst_links--; 1048 1030 last_mst_stream = intel_dp->active_mst_links == 0; 1049 1049 - drm_WARN_ON(&dev_priv->drm, 1050 1050 - DISPLAY_VER(dev_priv) >= 12 && last_mst_stream && 1031 1031 + drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && last_mst_stream && 1051 1032 !intel_dp_mst_is_master_trans(old_crtc_state)); 1052 1033 1053 1034 for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) { ··· 1059 1044 1060 1045 drm_dp_remove_payload_part1(&intel_dp->mst_mgr, new_mst_state, new_payload); 1061 1046 1062 1062 - clear_act_sent(encoder, old_crtc_state); 1047 1047 + intel_ddi_clear_act_sent(encoder, old_crtc_state); 1063 1048 1064 1064 - intel_de_rmw(dev_priv, 1065 1065 - TRANS_DDI_FUNC_CTL(dev_priv, old_crtc_state->cpu_transcoder), 1049 1049 + intel_de_rmw(display, 1050 1050 + TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder), 1066 1051 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 1067 1052 1068 1068 - wait_for_act_sent(encoder, old_crtc_state); 1053 1053 + intel_ddi_wait_for_act_sent(encoder, old_crtc_state); 1054 1054 + drm_dp_check_act_status(&intel_dp->mst_mgr); 1069 1055 1070 1056 drm_dp_remove_payload_part2(&intel_dp->mst_mgr, new_mst_state, 1071 1057 old_payload, new_payload); ··· 1079 1063 1080 1064 intel_dsc_disable(old_pipe_crtc_state); 1081 1065 1082 1082 - if (DISPLAY_VER(dev_priv) >= 9) 1066 1066 + if (DISPLAY_VER(display) >= 9) 1083 1067 skl_scaler_disable(old_pipe_crtc_state); 1084 1068 else 1085 1069 ilk_pfit_disable(old_pipe_crtc_state); ··· 1096 1080 * BSpec 4287: disable DIP after the transcoder is disabled and before 1097 1081 * the transcoder clock select is set to none. 1098 1082 */ 1099 1099 - intel_dp_set_infoframes(&dig_port->base, false, 1100 1100 - old_crtc_state, NULL); 1083 1083 + intel_dp_set_infoframes(primary_encoder, false, old_crtc_state, NULL); 1101 1084 /* 1102 1085 * From TGL spec: "If multi-stream slave transcoder: Configure 1103 1086 * Transcoder Clock Select to direct no clock to the transcoder" ··· 1104 1089 * From older GENs spec: "Configure Transcoder Clock Select to direct 1105 1090 * no clock to the transcoder" 1106 1091 */ 1107 1107 - if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream) 1092 1092 + if (DISPLAY_VER(display) < 12 || !last_mst_stream) 1108 1093 intel_ddi_disable_transcoder_clock(old_crtc_state); 1109 1094 1110 1095 1111 1096 intel_mst->connector = NULL; 1112 1097 if (last_mst_stream) 1113 1113 - dig_port->base.post_disable(state, &dig_port->base, 1114 1114 - old_crtc_state, NULL); 1098 1098 + primary_encoder->post_disable(state, primary_encoder, 1099 1099 + old_crtc_state, NULL); 1115 1100 1116 1116 - drm_dbg_kms(&dev_priv->drm, "active links %d\n", 1101 1101 + drm_dbg_kms(display->drm, "active links %d\n", 1117 1102 intel_dp->active_mst_links); 1118 1103 } 1119 1104 1120 1120 - static void intel_mst_post_pll_disable_dp(struct intel_atomic_state *state, 1121 1121 - struct intel_encoder *encoder, 1122 1122 - const struct intel_crtc_state *old_crtc_state, 1123 1123 - const struct drm_connector_state *old_conn_state) 1105 1105 + static void mst_stream_post_pll_disable(struct intel_atomic_state *state, 1106 1106 + struct intel_encoder *encoder, 1107 1107 + const struct intel_crtc_state *old_crtc_state, 1108 1108 + const struct drm_connector_state *old_conn_state) 1124 1109 { 1125 1125 - struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 1126 1126 - struct intel_digital_port *dig_port = intel_mst->primary; 1127 1127 - struct intel_dp *intel_dp = &dig_port->dp; 1110 1110 + struct intel_encoder *primary_encoder = to_primary_encoder(encoder); 1111 1111 + struct intel_dp *intel_dp = to_primary_dp(encoder); 1128 1112 1129 1113 if (intel_dp->active_mst_links == 0 && 1130 1130 - dig_port->base.post_pll_disable) 1131 1131 - dig_port->base.post_pll_disable(state, encoder, old_crtc_state, old_conn_state); 1114 1114 + primary_encoder->post_pll_disable) 1115 1115 + primary_encoder->post_pll_disable(state, primary_encoder, old_crtc_state, old_conn_state); 1132 1116 } 1133 1117 1134 1134 - static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state, 1135 1135 - struct intel_encoder *encoder, 1136 1136 - const struct intel_crtc_state *pipe_config, 1137 1137 - const struct drm_connector_state *conn_state) 1118 1118 + static void mst_stream_pre_pll_enable(struct intel_atomic_state *state, 1119 1119 + struct intel_encoder *encoder, 1120 1120 + const struct intel_crtc_state *pipe_config, 1121 1121 + const struct drm_connector_state *conn_state) 1138 1122 { 1139 1139 - struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 1140 1140 - struct intel_digital_port *dig_port = intel_mst->primary; 1141 1141 - struct intel_dp *intel_dp = &dig_port->dp; 1123 1123 + struct intel_encoder *primary_encoder = to_primary_encoder(encoder); 1124 1124 + struct intel_dp *intel_dp = to_primary_dp(encoder); 1142 1125 1143 1126 if (intel_dp->active_mst_links == 0) 1144 1144 - dig_port->base.pre_pll_enable(state, &dig_port->base, 1145 1145 - pipe_config, NULL); 1127 1127 + primary_encoder->pre_pll_enable(state, primary_encoder, 1128 1128 + pipe_config, NULL); 1146 1129 else 1147 1130 /* 1148 1131 * The port PLL state needs to get updated for secondary 1149 1132 * streams as for the primary stream. 1150 1133 */ 1151 1151 - intel_ddi_update_active_dpll(state, &dig_port->base, 1134 1134 + intel_ddi_update_active_dpll(state, primary_encoder, 1152 1135 to_intel_crtc(pipe_config->uapi.crtc)); 1153 1136 } 1154 1137 ··· 1177 1164 crtc_state->port_clock, crtc_state->lane_count); 1178 1165 } 1179 1166 1180 1180 - static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, 1181 1181 - struct intel_encoder *encoder, 1182 1182 - const struct intel_crtc_state *pipe_config, 1183 1183 - const struct drm_connector_state *conn_state) 1167 1167 + static void mst_stream_pre_enable(struct intel_atomic_state *state, 1168 1168 + struct intel_encoder *encoder, 1169 1169 + const struct intel_crtc_state *pipe_config, 1170 1170 + const struct drm_connector_state *conn_state) 1184 1171 { 1172 1172 + struct intel_display *display = to_intel_display(state); 1185 1173 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 1186 1186 - struct intel_digital_port *dig_port = intel_mst->primary; 1187 1187 - struct intel_dp *intel_dp = &dig_port->dp; 1188 1188 - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1174 1174 + struct intel_encoder *primary_encoder = to_primary_encoder(encoder); 1175 1175 + struct intel_dp *intel_dp = to_primary_dp(encoder); 1189 1176 struct intel_connector *connector = 1190 1177 to_intel_connector(conn_state->connector); 1191 1178 struct drm_dp_mst_topology_state *mst_state = ··· 1199 1186 connector->encoder = encoder; 1200 1187 intel_mst->connector = connector; 1201 1188 first_mst_stream = intel_dp->active_mst_links == 0; 1202 1202 - drm_WARN_ON(&dev_priv->drm, 1203 1203 - DISPLAY_VER(dev_priv) >= 12 && first_mst_stream && 1189 1189 + drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 12 && first_mst_stream && 1204 1190 !intel_dp_mst_is_master_trans(pipe_config)); 1205 1191 1206 1206 - drm_dbg_kms(&dev_priv->drm, "active links %d\n", 1192 1192 + drm_dbg_kms(display->drm, "active links %d\n", 1207 1193 intel_dp->active_mst_links); 1208 1194 1209 1195 if (first_mst_stream) ··· 1213 1201 intel_dp_sink_enable_decompression(state, connector, pipe_config); 1214 1202 1215 1203 if (first_mst_stream) { 1216 1216 - dig_port->base.pre_enable(state, &dig_port->base, 1217 1217 - pipe_config, NULL); 1204 1204 + primary_encoder->pre_enable(state, primary_encoder, 1205 1205 + pipe_config, NULL); 1218 1206 1219 1207 intel_mst_reprobe_topology(intel_dp, pipe_config); 1220 1208 } ··· 1224 1212 ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state, 1225 1213 drm_atomic_get_mst_payload_state(mst_state, connector->port)); 1226 1214 if (ret < 0) 1227 1227 - intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config); 1215 1215 + intel_dp_queue_modeset_retry_for_link(state, primary_encoder, pipe_config); 1228 1216 1229 1217 /* 1230 1218 * Before Gen 12 this is not done as part of 1231 1231 - * dig_port->base.pre_enable() and should be done here. For 1219 1219 + * primary_encoder->pre_enable() and should be done here. For 1232 1220 * Gen 12+ the step in which this should be done is different for the 1233 1221 * first MST stream, so it's done on the DDI for the first stream and 1234 1222 * here for the following ones. 1235 1223 */ 1236 1236 - if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) 1224 1224 + if (DISPLAY_VER(display) < 12 || !first_mst_stream) 1237 1225 intel_ddi_enable_transcoder_clock(encoder, pipe_config); 1238 1226 1239 1239 - intel_dsc_dp_pps_write(&dig_port->base, pipe_config); 1227 1227 + if (DISPLAY_VER(display) >= 13 && !first_mst_stream) 1228 1228 + intel_ddi_config_transcoder_func(encoder, pipe_config); 1229 1229 + 1230 1230 + intel_dsc_dp_pps_write(primary_encoder, pipe_config); 1240 1231 intel_ddi_set_dp_msa(pipe_config, conn_state); 1241 1232 } 1242 1233 1243 1234 static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state) 1244 1235 { 1236 1236 + struct intel_display *display = to_intel_display(crtc_state); 1245 1237 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1246 1238 u32 clear = 0; 1247 1239 u32 set = 0; ··· 1253 1237 if (!IS_ALDERLAKE_P(i915)) 1254 1238 return; 1255 1239 1256 1256 - if (!IS_DISPLAY_STEP(i915, STEP_D0, STEP_FOREVER)) 1240 1240 + if (!IS_DISPLAY_STEP(display, STEP_D0, STEP_FOREVER)) 1257 1241 return; 1258 1242 1259 1243 /* Wa_14013163432:adlp */ ··· 1261 1245 set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder); 1262 1246 1263 1247 /* Wa_14014143976:adlp */ 1264 1264 - if (IS_DISPLAY_STEP(i915, STEP_E0, STEP_FOREVER)) { 1248 1248 + if (IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER)) { 1265 1249 if (intel_dp_is_uhbr(crtc_state)) 1266 1250 set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder); 1267 1251 else if (crtc_state->fec_enable) ··· 1274 1258 if (!clear && !set) 1275 1259 return; 1276 1260 1277 1277 - intel_de_rmw(i915, CHICKEN_MISC_3, clear, set); 1261 1261 + intel_de_rmw(display, CHICKEN_MISC_3, clear, set); 1278 1262 } 1279 1263 1280 1280 - static void intel_mst_enable_dp(struct intel_atomic_state *state, 1281 1281 - struct intel_encoder *encoder, 1282 1282 - const struct intel_crtc_state *pipe_config, 1283 1283 - const struct drm_connector_state *conn_state) 1264 1264 + static void mst_stream_enable(struct intel_atomic_state *state, 1265 1265 + struct intel_encoder *encoder, 1266 1266 + const struct intel_crtc_state *pipe_config, 1267 1267 + const struct drm_connector_state *conn_state) 1284 1268 { 1285 1269 struct intel_display *display = to_intel_display(encoder); 1286 1286 - struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 1287 1287 - struct intel_digital_port *dig_port = intel_mst->primary; 1288 1288 - struct intel_dp *intel_dp = &dig_port->dp; 1270 1270 + struct intel_encoder *primary_encoder = to_primary_encoder(encoder); 1271 1271 + struct intel_dp *intel_dp = to_primary_dp(encoder); 1289 1272 struct intel_connector *connector = to_intel_connector(conn_state->connector); 1290 1290 - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1291 1273 struct drm_dp_mst_topology_state *mst_state = 1292 1274 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr); 1293 1275 enum transcoder trans = pipe_config->cpu_transcoder; ··· 1293 1279 struct intel_crtc *pipe_crtc; 1294 1280 int ret, i; 1295 1281 1296 1296 - drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); 1282 1282 + drm_WARN_ON(display->drm, pipe_config->has_pch_encoder); 1297 1283 1298 1284 if (intel_dp_is_uhbr(pipe_config)) { 1299 1285 const struct drm_display_mode *adjusted_mode = 1300 1286 &pipe_config->hw.adjusted_mode; 1301 1287 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 1302 1288 1303 1303 - intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), 1289 1289 + intel_de_write(display, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), 1304 1290 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 1305 1305 - intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), 1291 1291 + intel_de_write(display, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), 1306 1292 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 1307 1293 } 1308 1294 ··· 1310 1296 1311 1297 intel_ddi_enable_transcoder_func(encoder, pipe_config); 1312 1298 1313 1313 - clear_act_sent(encoder, pipe_config); 1299 1299 + intel_ddi_clear_act_sent(encoder, pipe_config); 1314 1300 1315 1315 - intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, trans), 0, 1301 1301 + intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, trans), 0, 1316 1302 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1317 1303 1318 1318 - drm_dbg_kms(&dev_priv->drm, "active links %d\n", 1304 1304 + drm_dbg_kms(display->drm, "active links %d\n", 1319 1305 intel_dp->active_mst_links); 1320 1306 1321 1321 - wait_for_act_sent(encoder, pipe_config); 1307 1307 + intel_ddi_wait_for_act_sent(encoder, pipe_config); 1308 1308 + drm_dp_check_act_status(&intel_dp->mst_mgr); 1322 1309 1323 1310 if (first_mst_stream) 1324 1311 intel_ddi_wait_for_fec_status(encoder, pipe_config, true); ··· 1328 1313 drm_atomic_get_mst_payload_state(mst_state, 1329 1314 connector->port)); 1330 1315 if (ret < 0) 1331 1331 - intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config); 1316 1316 + intel_dp_queue_modeset_retry_for_link(state, primary_encoder, pipe_config); 1332 1317 1333 1333 - if (DISPLAY_VER(dev_priv) >= 12) 1334 1334 - intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, trans), 1318 1318 + if (DISPLAY_VER(display) >= 12) 1319 1319 + intel_de_rmw(display, CHICKEN_TRANS(display, trans), 1335 1320 FECSTALL_DIS_DPTSTREAM_DPTTG, 1336 1321 pipe_config->fec_enable ? FECSTALL_DIS_DPTSTREAM_DPTTG : 0); 1337 1322 ··· 1349 1334 intel_hdcp_enable(state, encoder, pipe_config, conn_state); 1350 1335 } 1351 1336 1352 1352 - static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, 1353 1353 - enum pipe *pipe) 1337 1337 + static bool mst_stream_get_hw_state(struct intel_encoder *encoder, 1338 1338 + enum pipe *pipe) 1354 1339 { 1355 1340 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 1356 1341 *pipe = intel_mst->pipe; ··· 1359 1344 return false; 1360 1345 } 1361 1346 1362 1362 - static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, 1363 1363 - struct intel_crtc_state *pipe_config) 1347 1347 + static void mst_stream_get_config(struct intel_encoder *encoder, 1348 1348 + struct intel_crtc_state *pipe_config) 1364 1349 { 1365 1365 - struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 1366 1366 - struct intel_digital_port *dig_port = intel_mst->primary; 1350 1350 + struct intel_encoder *primary_encoder = to_primary_encoder(encoder); 1367 1351 1368 1368 - dig_port->base.get_config(&dig_port->base, pipe_config); 1352 1352 + primary_encoder->get_config(primary_encoder, pipe_config); 1369 1353 } 1370 1354 1371 1371 - static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder, 1372 1372 - struct intel_crtc_state *crtc_state) 1355 1355 + static bool mst_stream_initial_fastset_check(struct intel_encoder *encoder, 1356 1356 + struct intel_crtc_state *crtc_state) 1373 1357 { 1374 1374 - struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 1375 1375 - struct intel_digital_port *dig_port = intel_mst->primary; 1358 1358 + struct intel_encoder *primary_encoder = to_primary_encoder(encoder); 1376 1359 1377 1377 - return intel_dp_initial_fastset_check(&dig_port->base, crtc_state); 1360 1360 + return intel_dp_initial_fastset_check(primary_encoder, crtc_state); 1378 1361 } 1379 1362 1380 1380 - static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) 1363 1363 + static int mst_connector_get_ddc_modes(struct drm_connector *connector) 1381 1364 { 1365 1365 + struct intel_display *display = to_intel_display(connector->dev); 1382 1366 struct intel_connector *intel_connector = to_intel_connector(connector); 1383 1383 - struct drm_i915_private *i915 = to_i915(intel_connector->base.dev); 1384 1367 struct intel_dp *intel_dp = intel_connector->mst_port; 1385 1368 const struct drm_edid *drm_edid; 1386 1369 int ret; ··· 1386 1373 if (drm_connector_is_unregistered(connector)) 1387 1374 return intel_connector_update_modes(connector, NULL); 1388 1375 1389 1389 - if (!intel_display_driver_check_access(i915)) 1376 1376 + if (!intel_display_driver_check_access(display)) 1390 1377 return drm_edid_connector_add_modes(connector); 1391 1378 1392 1379 drm_edid = drm_dp_mst_edid_read(connector, &intel_dp->mst_mgr, intel_connector->port); ··· 1399 1386 } 1400 1387 1401 1388 static int 1402 1402 - intel_dp_mst_connector_late_register(struct drm_connector *connector) 1389 1389 + mst_connector_late_register(struct drm_connector *connector) 1403 1390 { 1404 1391 struct intel_connector *intel_connector = to_intel_connector(connector); 1405 1392 int ret; ··· 1418 1405 } 1419 1406 1420 1407 static void 1421 1421 - intel_dp_mst_connector_early_unregister(struct drm_connector *connector) 1408 1408 + mst_connector_early_unregister(struct drm_connector *connector) 1422 1409 { 1423 1410 struct intel_connector *intel_connector = to_intel_connector(connector); 1424 1411 ··· 1427 1414 intel_connector->port); 1428 1415 } 1429 1416 1430 1430 - static const struct drm_connector_funcs intel_dp_mst_connector_funcs = { 1417 1417 + static const struct drm_connector_funcs mst_connector_funcs = { 1431 1418 .fill_modes = drm_helper_probe_single_connector_modes, 1432 1419 .atomic_get_property = intel_digital_connector_atomic_get_property, 1433 1420 .atomic_set_property = intel_digital_connector_atomic_set_property, 1434 1434 - .late_register = intel_dp_mst_connector_late_register, 1435 1435 - .early_unregister = intel_dp_mst_connector_early_unregister, 1421 1421 + .late_register = mst_connector_late_register, 1422 1422 + .early_unregister = mst_connector_early_unregister, 1436 1423 .destroy = intel_connector_destroy, 1437 1424 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1438 1425 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1439 1426 }; 1440 1427 1441 1441 - static int intel_dp_mst_get_modes(struct drm_connector *connector) 1428 1428 + static int mst_connector_get_modes(struct drm_connector *connector) 1442 1429 { 1443 1443 - return intel_dp_mst_get_ddc_modes(connector); 1430 1430 + return mst_connector_get_ddc_modes(connector); 1444 1431 } 1445 1432 1446 1433 static int 1447 1447 - intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, 1448 1448 - struct drm_display_mode *mode, 1449 1449 - struct drm_modeset_acquire_ctx *ctx, 1450 1450 - enum drm_mode_status *status) 1434 1434 + mst_connector_mode_valid_ctx(struct drm_connector *connector, 1435 1435 + struct drm_display_mode *mode, 1436 1436 + struct drm_modeset_acquire_ctx *ctx, 1437 1437 + enum drm_mode_status *status) 1451 1438 { 1439 1439 + struct intel_display *display = to_intel_display(connector->dev); 1452 1440 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1453 1441 struct intel_connector *intel_connector = to_intel_connector(connector); 1454 1442 struct intel_dp *intel_dp = intel_connector->mst_port; 1455 1443 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr; 1456 1444 struct drm_dp_mst_port *port = intel_connector->port; 1457 1445 const int min_bpp = 18; 1458 1458 - int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; 1446 1446 + int max_dotclk = display->cdclk.max_dotclk_freq; 1459 1447 int max_rate, mode_rate, max_lanes, max_link_clock; 1460 1448 int ret; 1461 1449 bool dsc = false; ··· 1558 1544 return 0; 1559 1545 } 1560 1546 1561 1561 - static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector, 1562 1562 - struct drm_atomic_state *state) 1547 1547 + static struct drm_encoder * 1548 1548 + mst_connector_atomic_best_encoder(struct drm_connector *connector, 1549 1549 + struct drm_atomic_state *state) 1563 1550 { 1564 1551 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 1565 1552 connector); ··· 1572 1557 } 1573 1558 1574 1559 static int 1575 1575 - intel_dp_mst_detect(struct drm_connector *connector, 1576 1576 - struct drm_modeset_acquire_ctx *ctx, bool force) 1560 1560 + mst_connector_detect_ctx(struct drm_connector *connector, 1561 1561 + struct drm_modeset_acquire_ctx *ctx, bool force) 1577 1562 { 1578 1578 - struct drm_i915_private *i915 = to_i915(connector->dev); 1563 1563 + struct intel_display *display = to_intel_display(connector->dev); 1579 1564 struct intel_connector *intel_connector = to_intel_connector(connector); 1580 1565 struct intel_dp *intel_dp = intel_connector->mst_port; 1581 1566 1582 1582 - if (!intel_display_device_enabled(i915)) 1567 1567 + if (!intel_display_device_enabled(display)) 1583 1568 return connector_status_disconnected; 1584 1569 1585 1570 if (drm_connector_is_unregistered(connector)) 1586 1571 return connector_status_disconnected; 1587 1572 1588 1588 - if (!intel_display_driver_check_access(i915)) 1573 1573 + if (!intel_display_driver_check_access(display)) 1589 1574 return connector->status; 1590 1575 1591 1576 intel_dp_flush_connector_commits(intel_connector); ··· 1594 1579 intel_connector->port); 1595 1580 } 1596 1581 1597 1597 - static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = { 1598 1598 - .get_modes = intel_dp_mst_get_modes, 1599 1599 - .mode_valid_ctx = intel_dp_mst_mode_valid_ctx, 1600 1600 - .atomic_best_encoder = intel_mst_atomic_best_encoder, 1601 1601 - .atomic_check = intel_dp_mst_atomic_check, 1602 1602 - .detect_ctx = intel_dp_mst_detect, 1582 1582 + static const struct drm_connector_helper_funcs mst_connector_helper_funcs = { 1583 1583 + .get_modes = mst_connector_get_modes, 1584 1584 + .mode_valid_ctx = mst_connector_mode_valid_ctx, 1585 1585 + .atomic_best_encoder = mst_connector_atomic_best_encoder, 1586 1586 + .atomic_check = mst_connector_atomic_check, 1587 1587 + .detect_ctx = mst_connector_detect_ctx, 1603 1588 }; 1604 1589 1605 1605 - static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder) 1590 1590 + static void mst_stream_encoder_destroy(struct drm_encoder *encoder) 1606 1591 { 1607 1592 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder)); 1608 1593 ··· 1610 1595 kfree(intel_mst); 1611 1596 } 1612 1597 1613 1613 - static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = { 1614 1614 - .destroy = intel_dp_mst_encoder_destroy, 1598 1598 + static const struct drm_encoder_funcs mst_stream_encoder_funcs = { 1599 1599 + .destroy = mst_stream_encoder_destroy, 1615 1600 }; 1616 1601 1617 1617 - static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) 1602 1602 + static bool mst_connector_get_hw_state(struct intel_connector *connector) 1618 1603 { 1619 1619 - if (intel_attached_encoder(connector) && connector->base.state->crtc) { 1620 1620 - enum pipe pipe; 1621 1621 - if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe)) 1622 1622 - return false; 1623 1623 - return true; 1624 1624 - } 1625 1625 - return false; 1604 1604 + /* This is the MST stream encoder set in ->pre_enable, if any */ 1605 1605 + struct intel_encoder *encoder = intel_attached_encoder(connector); 1606 1606 + enum pipe pipe; 1607 1607 + 1608 1608 + if (!encoder || !connector->base.state->crtc) 1609 1609 + return false; 1610 1610 + 1611 1611 + return encoder->get_hw_state(encoder, &pipe); 1626 1612 } 1627 1613 1628 1628 - static int intel_dp_mst_add_properties(struct intel_dp *intel_dp, 1629 1629 - struct drm_connector *connector, 1630 1630 - const char *pathprop) 1614 1614 + static int mst_topology_add_connector_properties(struct intel_dp *intel_dp, 1615 1615 + struct drm_connector *connector, 1616 1616 + const char *pathprop) 1631 1617 { 1632 1632 - struct drm_i915_private *i915 = to_i915(connector->dev); 1618 1618 + struct intel_display *display = to_intel_display(intel_dp); 1633 1619 1634 1620 drm_object_attach_property(&connector->base, 1635 1635 - i915->drm.mode_config.path_property, 0); 1621 1621 + display->drm->mode_config.path_property, 0); 1636 1622 drm_object_attach_property(&connector->base, 1637 1637 - i915->drm.mode_config.tile_property, 0); 1623 1623 + display->drm->mode_config.tile_property, 0); 1638 1624 1639 1625 intel_attach_force_audio_property(connector); 1640 1626 intel_attach_broadcast_rgb_property(connector); ··· 1669 1653 1670 1654 static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector) 1671 1655 { 1672 1672 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 1656 1656 + struct intel_display *display = to_intel_display(connector); 1673 1657 struct drm_dp_aux *aux = connector->dp.dsc_decompression_aux; 1674 1658 struct drm_dp_desc desc; 1675 1659 u8 dpcd[DP_RECEIVER_CAP_SIZE]; ··· 1707 1691 !(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE)) 1708 1692 return false; 1709 1693 1710 1710 - drm_dbg_kms(&i915->drm, 1694 1694 + drm_dbg_kms(display->drm, 1711 1695 "[CONNECTOR:%d:%s] DSC HBLANK expansion quirk detected\n", 1712 1696 connector->base.base.id, connector->base.name); 1713 1697 1714 1698 return true; 1715 1699 } 1716 1700 1717 1717 - static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 1718 1718 - struct drm_dp_mst_port *port, 1719 1719 - const char *pathprop) 1701 1701 + static struct drm_connector * 1702 1702 + mst_topology_add_connector(struct drm_dp_mst_topology_mgr *mgr, 1703 1703 + struct drm_dp_mst_port *port, 1704 1704 + const char *pathprop) 1720 1705 { 1721 1706 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); 1707 1707 + struct intel_display *display = to_intel_display(intel_dp); 1722 1708 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1723 1723 - struct drm_device *dev = dig_port->base.base.dev; 1724 1724 - struct drm_i915_private *dev_priv = to_i915(dev); 1725 1709 struct intel_connector *intel_connector; 1726 1710 struct drm_connector *connector; 1727 1711 enum pipe pipe; ··· 1733 1717 1734 1718 connector = &intel_connector->base; 1735 1719 1736 1736 - intel_connector->get_hw_state = intel_dp_mst_get_hw_state; 1720 1720 + intel_connector->get_hw_state = mst_connector_get_hw_state; 1737 1721 intel_connector->sync_state = intel_dp_connector_sync_state; 1738 1722 intel_connector->mst_port = intel_dp; 1739 1723 intel_connector->port = port; ··· 1741 1725 1742 1726 intel_dp_init_modeset_retry_work(intel_connector); 1743 1727 1744 1744 - ret = drm_connector_dynamic_init(&dev_priv->drm, connector, &intel_dp_mst_connector_funcs, 1728 1728 + ret = drm_connector_dynamic_init(display->drm, connector, &mst_connector_funcs, 1745 1729 DRM_MODE_CONNECTOR_DisplayPort, NULL); 1746 1730 if (ret) { 1747 1731 drm_dp_mst_put_port_malloc(port); ··· 1754 1738 intel_connector->dp.dsc_hblank_expansion_quirk = 1755 1739 detect_dsc_hblank_expansion_quirk(intel_connector); 1756 1740 1757 1757 - drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs); 1741 1741 + drm_connector_helper_add(connector, &mst_connector_helper_funcs); 1758 1742 1759 1759 - for_each_pipe(dev_priv, pipe) { 1743 1743 + for_each_pipe(display, pipe) { 1760 1744 struct drm_encoder *enc = 1761 1745 &intel_dp->mst_encoders[pipe]->base.base; 1762 1746 ··· 1765 1749 goto err; 1766 1750 } 1767 1751 1768 1768 - ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop); 1752 1752 + ret = mst_topology_add_connector_properties(intel_dp, connector, pathprop); 1769 1753 if (ret) 1770 1754 goto err; 1771 1755 1772 1756 ret = intel_dp_hdcp_init(dig_port, intel_connector); 1773 1757 if (ret) 1774 1774 - drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n", 1758 1758 + drm_dbg_kms(display->drm, "[%s:%d] HDCP MST init failed, skipping.\n", 1775 1759 connector->name, connector->base.id); 1776 1760 1777 1761 return connector; ··· 1782 1766 } 1783 1767 1784 1768 static void 1785 1785 - intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) 1769 1769 + mst_topology_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) 1786 1770 { 1787 1771 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); 1788 1772 1789 1773 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); 1790 1774 } 1791 1775 1792 1792 - static const struct drm_dp_mst_topology_cbs mst_cbs = { 1793 1793 - .add_connector = intel_dp_add_mst_connector, 1794 1794 - .poll_hpd_irq = intel_dp_mst_poll_hpd_irq, 1776 1776 + static const struct drm_dp_mst_topology_cbs mst_topology_cbs = { 1777 1777 + .add_connector = mst_topology_add_connector, 1778 1778 + .poll_hpd_irq = mst_topology_poll_hpd_irq, 1795 1779 }; 1796 1780 1781 1781 + /* Create a fake encoder for an individual MST stream */ 1797 1782 static struct intel_dp_mst_encoder * 1798 1798 - intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe) 1783 1783 + mst_stream_encoder_create(struct intel_digital_port *dig_port, enum pipe pipe) 1799 1784 { 1785 1785 + struct intel_display *display = to_intel_display(dig_port); 1786 1786 + struct intel_encoder *primary_encoder = &dig_port->base; 1800 1787 struct intel_dp_mst_encoder *intel_mst; 1801 1801 - struct intel_encoder *intel_encoder; 1802 1802 - struct drm_device *dev = dig_port->base.base.dev; 1788 1788 + struct intel_encoder *encoder; 1803 1789 1804 1790 intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); 1805 1791 ··· 1809 1791 return NULL; 1810 1792 1811 1793 intel_mst->pipe = pipe; 1812 1812 - intel_encoder = &intel_mst->base; 1794 1794 + encoder = &intel_mst->base; 1813 1795 intel_mst->primary = dig_port; 1814 1796 1815 1815 - drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, 1797 1797 + drm_encoder_init(display->drm, &encoder->base, &mst_stream_encoder_funcs, 1816 1798 DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe)); 1817 1799 1818 1818 - intel_encoder->type = INTEL_OUTPUT_DP_MST; 1819 1819 - intel_encoder->power_domain = dig_port->base.power_domain; 1820 1820 - intel_encoder->port = dig_port->base.port; 1821 1821 - intel_encoder->cloneable = 0; 1800 1800 + encoder->type = INTEL_OUTPUT_DP_MST; 1801 1801 + encoder->power_domain = primary_encoder->power_domain; 1802 1802 + encoder->port = primary_encoder->port; 1803 1803 + encoder->cloneable = 0; 1822 1804 /* 1823 1805 * This is wrong, but broken userspace uses the intersection 1824 1806 * of possible_crtcs of all the encoders of a given connector ··· 1827 1809 * To keep such userspace functioning we must misconfigure 1828 1810 * this to make sure the intersection is not empty :( 1829 1811 */ 1830 1830 - intel_encoder->pipe_mask = ~0; 1812 1812 + encoder->pipe_mask = ~0; 1831 1813 1832 1832 - intel_encoder->compute_config = intel_dp_mst_compute_config; 1833 1833 - intel_encoder->compute_config_late = intel_dp_mst_compute_config_late; 1834 1834 - intel_encoder->disable = intel_mst_disable_dp; 1835 1835 - intel_encoder->post_disable = intel_mst_post_disable_dp; 1836 1836 - intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp; 1837 1837 - intel_encoder->update_pipe = intel_ddi_update_pipe; 1838 1838 - intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp; 1839 1839 - intel_encoder->pre_enable = intel_mst_pre_enable_dp; 1840 1840 - intel_encoder->enable = intel_mst_enable_dp; 1841 1841 - intel_encoder->audio_enable = intel_audio_codec_enable; 1842 1842 - intel_encoder->audio_disable = intel_audio_codec_disable; 1843 1843 - intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state; 1844 1844 - intel_encoder->get_config = intel_dp_mst_enc_get_config; 1845 1845 - intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check; 1814 1814 + encoder->compute_config = mst_stream_compute_config; 1815 1815 + encoder->compute_config_late = mst_stream_compute_config_late; 1816 1816 + encoder->disable = mst_stream_disable; 1817 1817 + encoder->post_disable = mst_stream_post_disable; 1818 1818 + encoder->post_pll_disable = mst_stream_post_pll_disable; 1819 1819 + encoder->update_pipe = intel_ddi_update_pipe; 1820 1820 + encoder->pre_pll_enable = mst_stream_pre_pll_enable; 1821 1821 + encoder->pre_enable = mst_stream_pre_enable; 1822 1822 + encoder->enable = mst_stream_enable; 1823 1823 + encoder->audio_enable = intel_audio_codec_enable; 1824 1824 + encoder->audio_disable = intel_audio_codec_disable; 1825 1825 + encoder->get_hw_state = mst_stream_get_hw_state; 1826 1826 + encoder->get_config = mst_stream_get_config; 1827 1827 + encoder->initial_fastset_check = mst_stream_initial_fastset_check; 1846 1828 1847 1829 return intel_mst; 1848 1830 1849 1831 } 1850 1832 1833 1833 + /* Create the fake encoders for MST streams */ 1851 1834 static bool 1852 1852 - intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port) 1835 1835 + mst_stream_encoders_create(struct intel_digital_port *dig_port) 1853 1836 { 1837 1837 + struct intel_display *display = to_intel_display(dig_port); 1854 1838 struct intel_dp *intel_dp = &dig_port->dp; 1855 1855 - struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 1856 1839 enum pipe pipe; 1857 1840 1858 1858 - for_each_pipe(dev_priv, pipe) 1859 1859 - intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe); 1841 1841 + for_each_pipe(display, pipe) 1842 1842 + intel_dp->mst_encoders[pipe] = mst_stream_encoder_create(dig_port, pipe); 1860 1843 return true; 1861 1844 } 1862 1845 ··· 1870 1851 int 1871 1852 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) 1872 1853 { 1873 1873 - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1854 1854 + struct intel_display *display = to_intel_display(dig_port); 1874 1855 struct intel_dp *intel_dp = &dig_port->dp; 1875 1856 enum port port = dig_port->base.port; 1876 1857 int ret; 1877 1858 1878 1878 - if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp)) 1859 1859 + if (!HAS_DP_MST(display) || intel_dp_is_edp(intel_dp)) 1879 1860 return 0; 1880 1861 1881 1881 - if (DISPLAY_VER(i915) < 12 && port == PORT_A) 1862 1862 + if (DISPLAY_VER(display) < 12 && port == PORT_A) 1882 1863 return 0; 1883 1864 1884 1884 - if (DISPLAY_VER(i915) < 11 && port == PORT_E) 1865 1865 + if (DISPLAY_VER(display) < 11 && port == PORT_E) 1885 1866 return 0; 1886 1867 1887 1887 - intel_dp->mst_mgr.cbs = &mst_cbs; 1868 1868 + intel_dp->mst_mgr.cbs = &mst_topology_cbs; 1888 1869 1889 1870 /* create encoders */ 1890 1890 - intel_dp_create_fake_mst_encoders(dig_port); 1891 1891 - ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, 1871 1871 + mst_stream_encoders_create(dig_port); 1872 1872 + ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, display->drm, 1892 1873 &intel_dp->aux, 16, 3, conn_base_id); 1893 1874 if (ret) { 1894 1875 intel_dp->mst_mgr.cbs = NULL;

+4 -3

drivers/gpu/drm/i915/display/intel_dpio_phy.c

reviewed

··· 855 855 void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 856 856 const struct intel_crtc_state *crtc_state) 857 857 { 858 858 + struct intel_display *display = to_intel_display(encoder); 858 859 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 859 860 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 860 861 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); ··· 872 871 */ 873 872 if (ch == DPIO_CH0 && pipe == PIPE_B) 874 873 dig_port->release_cl2_override = 875 875 - !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); 874 874 + !chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, true); 876 875 877 876 chv_phy_powergate_lanes(encoder, true, lane_mask); 878 877 ··· 1014 1013 1015 1014 void chv_phy_release_cl2_override(struct intel_encoder *encoder) 1016 1015 { 1016 1016 + struct intel_display *display = to_intel_display(encoder); 1017 1017 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1018 1018 - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1019 1018 1020 1019 if (dig_port->release_cl2_override) { 1021 1021 - chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); 1020 1020 + chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, false); 1022 1021 dig_port->release_cl2_override = false; 1023 1022 } 1024 1023 }

+2 -2

drivers/gpu/drm/i915/display/intel_dpt.c

reviewed

··· 205 205 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); 206 206 207 207 if (fb->dpt_vm) 208 208 - i915_ggtt_resume_vm(fb->dpt_vm); 208 208 + i915_ggtt_resume_vm(fb->dpt_vm, true); 209 209 } 210 210 mutex_unlock(&i915->drm.mode_config.fb_lock); 211 211 } ··· 233 233 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); 234 234 235 235 if (fb->dpt_vm) 236 236 - i915_ggtt_suspend_vm(fb->dpt_vm); 236 236 + i915_ggtt_suspend_vm(fb->dpt_vm, true); 237 237 } 238 238 239 239 mutex_unlock(&i915->drm.mode_config.fb_lock);

+3 -1

drivers/gpu/drm/i915/display/intel_drrs.c

reviewed

··· 68 68 bool intel_cpu_transcoder_has_drrs(struct drm_i915_private *i915, 69 69 enum transcoder cpu_transcoder) 70 70 { 71 71 - if (HAS_DOUBLE_BUFFERED_M_N(i915)) 71 71 + struct intel_display *display = &i915->display; 72 72 + 73 73 + if (HAS_DOUBLE_BUFFERED_M_N(display)) 72 74 return true; 73 75 74 76 return intel_cpu_transcoder_has_m2_n2(i915, cpu_transcoder);

+14 -44

drivers/gpu/drm/i915/display/intel_dsb.c

reviewed

··· 256 256 return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg); 257 257 } 258 258 259 259 - static bool intel_dsb_prev_ins_is_mmio_write(struct intel_dsb *dsb, i915_reg_t reg) 260 260 - { 261 261 - /* only full byte-enables can be converted to indexed writes */ 262 262 - return intel_dsb_prev_ins_is_write(dsb, 263 263 - DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT | 264 264 - DSB_BYTE_EN << DSB_BYTE_EN_SHIFT, 265 265 - reg); 266 266 - } 267 267 - 268 259 static bool intel_dsb_prev_ins_is_indexed_write(struct intel_dsb *dsb, i915_reg_t reg) 269 260 { 270 261 return intel_dsb_prev_ins_is_write(dsb, ··· 264 273 } 265 274 266 275 /** 267 267 - * intel_dsb_reg_write_indexed() - Emit register wriite to the DSB context 276 276 + * intel_dsb_reg_write_indexed() - Emit indexed register write to the DSB context 268 277 * @dsb: DSB context 269 278 * @reg: register address. 270 279 * @val: value. ··· 295 304 * we are writing odd no of dwords, Zeros will be added in the end for 296 305 * padding. 297 306 */ 298 298 - if (!intel_dsb_prev_ins_is_mmio_write(dsb, reg) && 299 299 - !intel_dsb_prev_ins_is_indexed_write(dsb, reg)) { 300 300 - intel_dsb_emit(dsb, val, 301 301 - (DSB_OPCODE_MMIO_WRITE << DSB_OPCODE_SHIFT) | 302 302 - (DSB_BYTE_EN << DSB_BYTE_EN_SHIFT) | 307 307 + if (!intel_dsb_prev_ins_is_indexed_write(dsb, reg)) 308 308 + intel_dsb_emit(dsb, 0, /* count */ 309 309 + (DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT) | 303 310 i915_mmio_reg_offset(reg)); 304 304 - } else { 305 305 - if (!assert_dsb_has_room(dsb)) 306 306 - return; 307 311 308 308 - /* convert to indexed write? */ 309 309 - if (intel_dsb_prev_ins_is_mmio_write(dsb, reg)) { 310 310 - u32 prev_val = dsb->ins[0]; 312 312 + if (!assert_dsb_has_room(dsb)) 313 313 + return; 311 314 312 312 - dsb->ins[0] = 1; /* count */ 313 313 - dsb->ins[1] = (DSB_OPCODE_INDEXED_WRITE << DSB_OPCODE_SHIFT) | 314 314 - i915_mmio_reg_offset(reg); 315 315 + /* Update the count */ 316 316 + dsb->ins[0]++; 317 317 + intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 0, 318 318 + dsb->ins[0]); 315 319 316 316 - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 0, 317 317 - dsb->ins[0]); 318 318 - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 1, 319 319 - dsb->ins[1]); 320 320 - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 2, 321 321 - prev_val); 322 322 - 323 323 - dsb->free_pos++; 324 324 - } 325 325 - 326 326 - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, val); 327 327 - /* Update the count */ 328 328 - dsb->ins[0]++; 329 329 - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 0, 330 330 - dsb->ins[0]); 331 331 - 332 332 - /* if number of data words is odd, then the last dword should be 0.*/ 333 333 - if (dsb->free_pos & 0x1) 334 334 - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos, 0); 335 335 - } 320 320 + intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, val); 321 321 + /* if number of data words is odd, then the last dword should be 0.*/ 322 322 + if (dsb->free_pos & 0x1) 323 323 + intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos, 0); 336 324 } 337 325 338 326 void intel_dsb_reg_write(struct intel_dsb *dsb,

+18 -2

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

reviewed

··· 745 745 str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 746 746 } 747 747 748 748 + static enum mipi_dsi_pixel_format vbt_to_dsi_pixel_format(unsigned int format) 749 749 + { 750 750 + switch (format) { 751 751 + case PIXEL_FORMAT_RGB888: 752 752 + return MIPI_DSI_FMT_RGB888; 753 753 + case PIXEL_FORMAT_RGB666_LOOSELY_PACKED: 754 754 + return MIPI_DSI_FMT_RGB666; 755 755 + case PIXEL_FORMAT_RGB666: 756 756 + return MIPI_DSI_FMT_RGB666_PACKED; 757 757 + case PIXEL_FORMAT_RGB565: 758 758 + return MIPI_DSI_FMT_RGB565; 759 759 + default: 760 760 + MISSING_CASE(format); 761 761 + return MIPI_DSI_FMT_RGB666; 762 762 + } 763 763 + } 764 764 + 748 765 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 749 766 { 750 767 struct drm_device *dev = intel_dsi->base.base.dev; ··· 779 762 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 780 763 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 781 764 intel_dsi->pixel_format = 782 782 - pixel_format_from_register_bits( 783 783 - mipi_config->videomode_color_format << 7); 765 765 + vbt_to_dsi_pixel_format(mipi_config->videomode_color_format); 784 766 785 767 intel_dsi->dual_link = mipi_config->dual_link; 786 768 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;

+5 -4

drivers/gpu/drm/i915/display/intel_dvo.c

reviewed

··· 318 318 static enum drm_connector_status 319 319 intel_dvo_detect(struct drm_connector *_connector, bool force) 320 320 { 321 321 + struct intel_display *display = to_intel_display(_connector->dev); 321 322 struct intel_connector *connector = to_intel_connector(_connector); 322 323 struct drm_i915_private *i915 = to_i915(connector->base.dev); 323 324 struct intel_dvo *intel_dvo = intel_attached_dvo(connector); ··· 326 325 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 327 326 connector->base.base.id, connector->base.name); 328 327 329 329 - if (!intel_display_device_enabled(i915)) 328 328 + if (!intel_display_device_enabled(display)) 330 329 return connector_status_disconnected; 331 330 332 332 - if (!intel_display_driver_check_access(i915)) 331 331 + if (!intel_display_driver_check_access(display)) 333 332 return connector->base.status; 334 333 335 334 return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); ··· 337 336 338 337 static int intel_dvo_get_modes(struct drm_connector *_connector) 339 338 { 339 339 + struct intel_display *display = to_intel_display(_connector->dev); 340 340 struct intel_connector *connector = to_intel_connector(_connector); 341 341 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 342 341 int num_modes; 343 342 344 344 - if (!intel_display_driver_check_access(i915)) 343 343 + if (!intel_display_driver_check_access(display)) 345 344 return drm_edid_connector_add_modes(&connector->base); 346 345 347 346 /*

+1 -2

drivers/gpu/drm/i915/display/intel_gmbus.c

reviewed

··· 496 496 gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg, 497 497 u32 gmbus0_reg, u32 gmbus1_index) 498 498 { 499 499 - struct drm_i915_private *i915 = to_i915(display->drm); 500 499 u8 *buf = msg->buf; 501 500 unsigned int rx_size = msg->len; 502 501 unsigned int len; 503 502 int ret; 504 503 505 504 do { 506 506 - if (HAS_GMBUS_BURST_READ(i915)) 505 505 + if (HAS_GMBUS_BURST_READ(display)) 507 506 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 508 507 else 509 508 len = min(rx_size, gmbus_max_xfer_size(display));

+22 -14

drivers/gpu/drm/i915/display/intel_hdcp.c

reviewed

··· 31 31 #define KEY_LOAD_TRIES 5 32 32 #define HDCP2_LC_RETRY_CNT 3 33 33 34 34 - /* WA: 16022217614 */ 35 34 static void 36 36 - intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, 37 37 - struct intel_hdcp *hdcp) 35 35 + intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder, 36 36 + struct intel_hdcp *hdcp, 37 37 + bool enable) 38 38 { 39 39 struct intel_display *display = to_intel_display(encoder); 40 40 + i915_reg_t rekey_reg; 41 41 + u32 rekey_bit = 0; 40 42 41 43 /* Here we assume HDMI is in TMDS mode of operation */ 42 44 if (encoder->type != INTEL_OUTPUT_HDMI) 43 45 return; 44 46 45 45 - if (DISPLAY_VER(display) >= 14) { 46 46 - if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) 47 47 - intel_de_rmw(display, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder), 48 48 - 0, HDCP_LINE_REKEY_DISABLE); 49 49 - else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || 50 50 - IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) 51 51 - intel_de_rmw(display, 52 52 - TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder), 53 53 - 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE); 47 47 + if (DISPLAY_VER(display) >= 30) { 48 48 + rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 49 49 + rekey_bit = XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 50 50 + } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || 51 51 + IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { 52 52 + rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 53 53 + rekey_bit = TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 54 54 + } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { 55 55 + rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); 56 56 + rekey_bit = HDCP_LINE_REKEY_DISABLE; 54 57 } 58 58 + 59 59 + if (rekey_bit) 60 60 + intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); 55 61 } 56 62 57 63 static int intel_conn_to_vcpi(struct intel_atomic_state *state, ··· 349 343 350 344 /* PG1 (power well #1) needs to be enabled */ 351 345 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 352 352 - enabled = intel_display_power_well_is_enabled(i915, id); 346 346 + enabled = intel_display_power_well_is_enabled(display, id); 353 347 354 348 /* 355 349 * Another req for hdcp key loadability is enabled state of pll for ··· 1053 1047 ret); 1054 1048 return ret; 1055 1049 } 1050 1050 + 1051 1051 + intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, true); 1056 1052 1057 1053 /* Incase of authentication failures, HDCP spec expects reauth. */ 1058 1054 for (i = 0; i < tries; i++) { ··· 2077 2069 connector->base.base.id, connector->base.name, 2078 2070 hdcp->content_type); 2079 2071 2080 2080 - intel_hdcp_disable_hdcp_line_rekeying(connector->encoder, hdcp); 2072 2072 + intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, false); 2081 2073 2082 2074 ret = hdcp2_authenticate_and_encrypt(state, connector); 2083 2075 if (ret) {

+3 -6

drivers/gpu/drm/i915/display/intel_hdmi.c

reviewed

··· 1600 1600 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1601 1601 struct intel_connector *connector) 1602 1602 { 1603 1603 - struct intel_display *display = to_intel_display(dig_port); 1604 1603 int retry; 1605 1604 1606 1605 for (retry = 0; retry < 3; retry++) 1607 1606 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1608 1607 return true; 1609 1608 1610 1610 - drm_err(display->drm, "Link check failed\n"); 1611 1609 return false; 1612 1610 } 1613 1611 ··· 2554 2556 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2555 2557 connector->base.id, connector->name); 2556 2558 2557 2557 - if (!intel_display_device_enabled(dev_priv)) 2559 2559 + if (!intel_display_device_enabled(display)) 2558 2560 return connector_status_disconnected; 2559 2561 2560 2560 - if (!intel_display_driver_check_access(dev_priv)) 2562 2562 + if (!intel_display_driver_check_access(display)) 2561 2563 return connector->status; 2562 2564 2563 2565 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); ··· 2584 2586 intel_hdmi_force(struct drm_connector *connector) 2585 2587 { 2586 2588 struct intel_display *display = to_intel_display(connector->dev); 2587 2587 - struct drm_i915_private *i915 = to_i915(connector->dev); 2588 2589 2589 2590 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2590 2591 connector->base.id, connector->name); 2591 2592 2592 2592 - if (!intel_display_driver_check_access(i915)) 2593 2593 + if (!intel_display_driver_check_access(display)) 2593 2594 return; 2594 2595 2595 2596 intel_hdmi_unset_edid(connector);

+3 -1

drivers/gpu/drm/i915/display/intel_hotplug.c

reviewed

··· 813 813 */ 814 814 void intel_hpd_poll_enable(struct drm_i915_private *dev_priv) 815 815 { 816 816 + struct intel_display *display = &dev_priv->display; 817 817 + 816 818 if (!HAS_DISPLAY(dev_priv) || 817 817 - !intel_display_device_enabled(dev_priv)) 819 819 + !intel_display_device_enabled(display)) 818 820 return; 819 821 820 822 WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, true);

+5 -1

drivers/gpu/drm/i915/display/intel_hotplug_irq.c

reviewed

··· 1457 1457 1458 1458 void intel_hpd_irq_setup(struct drm_i915_private *i915) 1459 1459 { 1460 1460 - if (i915->display.irq.display_irqs_enabled && i915->display.funcs.hotplug) 1460 1460 + if ((IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) && 1461 1461 + !i915->display.irq.vlv_display_irqs_enabled) 1462 1462 + return; 1463 1463 + 1464 1464 + if (i915->display.funcs.hotplug) 1461 1465 i915->display.funcs.hotplug->hpd_irq_setup(i915); 1462 1466 } 1463 1467

+25 -24

drivers/gpu/drm/i915/display/intel_lvds.c

reviewed

··· 57 57 58 58 /* Private structure for the integrated LVDS support */ 59 59 struct intel_lvds_pps { 60 60 - /* 100us units */ 61 61 - int t1_t2; 62 62 - int t3; 63 63 - int t4; 64 64 - int t5; 65 65 - int tx; 60 60 + struct intel_pps_delays delays; 66 61 67 62 int divider; 68 63 ··· 163 168 164 169 val = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, 0)); 165 170 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); 166 166 - pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); 167 167 - pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); 171 171 + pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); 172 172 + pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); 168 173 169 174 val = intel_de_read(dev_priv, PP_OFF_DELAYS(dev_priv, 0)); 170 170 - pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); 171 171 - pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); 175 175 + pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); 176 176 + pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); 172 177 173 178 val = intel_de_read(dev_priv, PP_DIVISOR(dev_priv, 0)); 174 179 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); ··· 181 186 if (val) 182 187 val--; 183 188 /* Convert from 100ms to 100us units */ 184 184 - pps->t4 = val * 1000; 189 189 + pps->delays.power_cycle = val * 1000; 185 190 186 191 if (DISPLAY_VER(dev_priv) < 5 && 187 187 - pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { 192 192 + pps->delays.power_up == 0 && 193 193 + pps->delays.backlight_on == 0 && 194 194 + pps->delays.power_down == 0 && 195 195 + pps->delays.backlight_off == 0) { 188 196 drm_dbg_kms(&dev_priv->drm, 189 197 "Panel power timings uninitialized, " 190 198 "setting defaults\n"); 191 199 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 192 192 - pps->t1_t2 = 40 * 10; 193 193 - pps->t5 = 200 * 10; 200 200 + pps->delays.power_up = 40 * 10; 201 201 + pps->delays.backlight_on = 200 * 10; 194 202 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 195 195 - pps->t3 = 35 * 10; 196 196 - pps->tx = 200 * 10; 203 203 + pps->delays.power_down = 35 * 10; 204 204 + pps->delays.backlight_off = 200 * 10; 197 205 } 198 206 199 199 - drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " 207 207 + drm_dbg(&dev_priv->drm, "LVDS PPS:power_up %d power_down %d power_cycle %d backlight_on %d backlight_off %d " 200 208 "divider %d port %d powerdown_on_reset %d\n", 201 201 - pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, 202 202 - pps->divider, pps->port, pps->powerdown_on_reset); 209 209 + pps->delays.power_up, pps->delays.power_down, 210 210 + pps->delays.power_cycle, pps->delays.backlight_on, 211 211 + pps->delays.backlight_off, pps->divider, 212 212 + pps->port, pps->powerdown_on_reset); 203 213 } 204 214 205 215 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, ··· 221 221 222 222 intel_de_write(dev_priv, PP_ON_DELAYS(dev_priv, 0), 223 223 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | 224 224 - REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | 225 225 - REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); 224 224 + REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->delays.power_up) | 225 225 + REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->delays.backlight_on)); 226 226 227 227 intel_de_write(dev_priv, PP_OFF_DELAYS(dev_priv, 0), 228 228 - REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | 229 229 - REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); 228 228 + REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->delays.power_down) | 229 229 + REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->delays.backlight_off)); 230 230 231 231 intel_de_write(dev_priv, PP_DIVISOR(dev_priv, 0), 232 232 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | 233 233 - REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); 233 233 + REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, 234 234 + DIV_ROUND_UP(pps->delays.power_cycle, 1000) + 1)); 234 235 } 235 236 236 237 static void intel_pre_enable_lvds(struct intel_atomic_state *state,

+1 -1

drivers/gpu/drm/i915/display/intel_modeset_setup.c

reviewed

··· 1024 1024 1025 1025 intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); 1026 1026 1027 1027 - intel_power_domains_sanitize_state(i915); 1027 1027 + intel_power_domains_sanitize_state(display); 1028 1028 }

+96 -88

drivers/gpu/drm/i915/display/intel_overlay.c

reviewed

··· 183 183 }; 184 184 185 185 struct intel_overlay { 186 186 - struct drm_i915_private *i915; 186 186 + struct intel_display *display; 187 187 struct intel_context *context; 188 188 struct intel_crtc *crtc; 189 189 struct i915_vma *vma; ··· 205 205 void (*flip_complete)(struct intel_overlay *ovl); 206 206 }; 207 207 208 208 - static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 208 208 + static void i830_overlay_clock_gating(struct intel_display *display, 209 209 bool enable) 210 210 { 211 211 - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 211 211 + struct pci_dev *pdev = to_pci_dev(display->drm->dev); 212 212 u8 val; 213 213 214 214 /* WA_OVERLAY_CLKGATE:alm */ 215 215 if (enable) 216 216 - intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), 0); 216 216 + intel_de_write(display, DSPCLK_GATE_D(display), 0); 217 217 else 218 218 - intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), 218 218 + intel_de_write(display, DSPCLK_GATE_D(display), 219 219 OVRUNIT_CLOCK_GATE_DISABLE); 220 220 221 221 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ ··· 253 253 /* overlay needs to be disable in OCMD reg */ 254 254 static int intel_overlay_on(struct intel_overlay *overlay) 255 255 { 256 256 - struct drm_i915_private *dev_priv = overlay->i915; 256 256 + struct intel_display *display = overlay->display; 257 257 struct i915_request *rq; 258 258 u32 *cs; 259 259 260 260 - drm_WARN_ON(&dev_priv->drm, overlay->active); 260 260 + drm_WARN_ON(display->drm, overlay->active); 261 261 262 262 rq = alloc_request(overlay, NULL); 263 263 if (IS_ERR(rq)) ··· 271 271 272 272 overlay->active = true; 273 273 274 274 - if (IS_I830(dev_priv)) 275 275 - i830_overlay_clock_gating(dev_priv, false); 274 274 + if (display->platform.i830) 275 275 + i830_overlay_clock_gating(display, false); 276 276 277 277 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 278 278 *cs++ = overlay->flip_addr | OFC_UPDATE; ··· 288 288 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 289 289 struct i915_vma *vma) 290 290 { 291 291 + struct intel_display *display = overlay->display; 292 292 + struct drm_i915_private *i915 = to_i915(display->drm); 291 293 enum pipe pipe = overlay->crtc->pipe; 292 294 struct intel_frontbuffer *frontbuffer = NULL; 293 295 294 294 - drm_WARN_ON(&overlay->i915->drm, overlay->old_vma); 296 296 + drm_WARN_ON(display->drm, overlay->old_vma); 295 297 296 298 if (vma) 297 299 frontbuffer = intel_frontbuffer_get(intel_bo_to_drm_bo(vma->obj)); ··· 305 303 intel_frontbuffer_put(overlay->frontbuffer); 306 304 overlay->frontbuffer = frontbuffer; 307 305 308 308 - intel_frontbuffer_flip_prepare(overlay->i915, 309 309 - INTEL_FRONTBUFFER_OVERLAY(pipe)); 306 306 + intel_frontbuffer_flip_prepare(i915, INTEL_FRONTBUFFER_OVERLAY(pipe)); 310 307 311 308 overlay->old_vma = overlay->vma; 312 309 if (vma) ··· 319 318 struct i915_vma *vma, 320 319 bool load_polyphase_filter) 321 320 { 322 322 - struct drm_i915_private *dev_priv = overlay->i915; 321 321 + struct intel_display *display = overlay->display; 323 322 struct i915_request *rq; 324 323 u32 flip_addr = overlay->flip_addr; 325 324 u32 tmp, *cs; 326 325 327 327 - drm_WARN_ON(&dev_priv->drm, !overlay->active); 326 326 + drm_WARN_ON(display->drm, !overlay->active); 328 327 329 328 if (load_polyphase_filter) 330 329 flip_addr |= OFC_UPDATE; 331 330 332 331 /* check for underruns */ 333 333 - tmp = intel_de_read(dev_priv, DOVSTA); 332 332 + tmp = intel_de_read(display, DOVSTA); 334 333 if (tmp & (1 << 17)) 335 335 - drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp); 334 334 + drm_dbg(display->drm, "overlay underrun, DOVSTA: %x\n", tmp); 336 335 337 336 rq = alloc_request(overlay, NULL); 338 337 if (IS_ERR(rq)) ··· 356 355 357 356 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 358 357 { 358 358 + struct intel_display *display = overlay->display; 359 359 + struct drm_i915_private *i915 = to_i915(display->drm); 359 360 struct i915_vma *vma; 360 361 361 362 vma = fetch_and_zero(&overlay->old_vma); 362 362 - if (drm_WARN_ON(&overlay->i915->drm, !vma)) 363 363 + if (drm_WARN_ON(display->drm, !vma)) 363 364 return; 364 365 365 365 - intel_frontbuffer_flip_complete(overlay->i915, 366 366 - INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 366 366 + intel_frontbuffer_flip_complete(i915, INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 367 367 368 368 i915_vma_unpin(vma); 369 369 i915_vma_put(vma); ··· 378 376 379 377 static void intel_overlay_off_tail(struct intel_overlay *overlay) 380 378 { 381 381 - struct drm_i915_private *dev_priv = overlay->i915; 379 379 + struct intel_display *display = overlay->display; 382 380 383 381 intel_overlay_release_old_vma(overlay); 384 382 ··· 386 384 overlay->crtc = NULL; 387 385 overlay->active = false; 388 386 389 389 - if (IS_I830(dev_priv)) 390 390 - i830_overlay_clock_gating(dev_priv, true); 387 387 + if (display->platform.i830) 388 388 + i830_overlay_clock_gating(display, true); 391 389 } 392 390 393 391 static void intel_overlay_last_flip_retire(struct i915_active *active) ··· 402 400 /* overlay needs to be disabled in OCMD reg */ 403 401 static int intel_overlay_off(struct intel_overlay *overlay) 404 402 { 403 403 + struct intel_display *display = overlay->display; 405 404 struct i915_request *rq; 406 405 u32 *cs, flip_addr = overlay->flip_addr; 407 406 408 408 - drm_WARN_ON(&overlay->i915->drm, !overlay->active); 407 407 + drm_WARN_ON(display->drm, !overlay->active); 409 408 410 409 /* According to intel docs the overlay hw may hang (when switching 411 410 * off) without loading the filter coeffs. It is however unclear whether ··· 455 452 */ 456 453 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 457 454 { 458 458 - struct drm_i915_private *dev_priv = overlay->i915; 455 455 + struct intel_display *display = overlay->display; 459 456 struct i915_request *rq; 460 457 u32 *cs; 461 458 ··· 466 463 if (!overlay->old_vma) 467 464 return 0; 468 465 469 469 - if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 466 466 + if (!(intel_de_read(display, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 470 467 intel_overlay_release_old_vid_tail(overlay); 471 468 return 0; 472 469 } ··· 490 487 return i915_active_wait(&overlay->last_flip); 491 488 } 492 489 493 493 - void intel_overlay_reset(struct drm_i915_private *dev_priv) 490 490 + void intel_overlay_reset(struct intel_display *display) 494 491 { 495 495 - struct intel_overlay *overlay = dev_priv->display.overlay; 492 492 + struct intel_overlay *overlay = display->overlay; 496 493 497 494 if (!overlay) 498 495 return; ··· 553 550 } 554 551 } 555 552 556 556 - static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 553 553 + static u32 calc_swidthsw(struct intel_display *display, u32 offset, u32 width) 557 554 { 558 555 u32 sw; 559 556 560 560 - if (DISPLAY_VER(dev_priv) == 2) 557 557 + if (DISPLAY_VER(display) == 2) 561 558 sw = ALIGN((offset & 31) + width, 32); 562 559 else 563 560 sw = ALIGN((offset & 63) + width, 64); ··· 792 789 struct drm_i915_gem_object *new_bo, 793 790 struct drm_intel_overlay_put_image *params) 794 791 { 792 792 + struct intel_display *display = overlay->display; 793 793 + struct drm_i915_private *dev_priv = to_i915(display->drm); 795 794 struct overlay_registers __iomem *regs = overlay->regs; 796 796 - struct drm_i915_private *dev_priv = overlay->i915; 797 795 u32 swidth, swidthsw, sheight, ostride; 798 796 enum pipe pipe = overlay->crtc->pipe; 799 797 bool scale_changed = false; 800 798 struct i915_vma *vma; 801 799 int ret, tmp_width; 802 800 803 803 - drm_WARN_ON(&dev_priv->drm, 804 804 - !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 801 801 + drm_WARN_ON(display->drm, 802 802 + !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 805 803 806 804 ret = intel_overlay_release_old_vid(overlay); 807 805 if (ret != 0) ··· 828 824 oconfig |= OCONF_CC_OUT_8BIT; 829 825 if (crtc_state->gamma_enable) 830 826 oconfig |= OCONF_GAMMA2_ENABLE; 831 831 - if (DISPLAY_VER(dev_priv) == 4) 827 827 + if (DISPLAY_VER(display) == 4) 832 828 oconfig |= OCONF_CSC_MODE_BT709; 833 829 oconfig |= pipe == 0 ? 834 830 OCONF_PIPE_A : OCONF_PIPE_B; ··· 849 845 tmp_width = params->src_width; 850 846 851 847 swidth = params->src_width; 852 852 - swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 848 848 + swidthsw = calc_swidthsw(display, params->offset_Y, tmp_width); 853 849 sheight = params->src_height; 854 850 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y); 855 851 ostride = params->stride_Y; ··· 862 858 swidth |= (params->src_width / uv_hscale) << 16; 863 859 sheight |= (params->src_height / uv_vscale) << 16; 864 860 865 865 - tmp_U = calc_swidthsw(dev_priv, params->offset_U, 861 861 + tmp_U = calc_swidthsw(display, params->offset_U, 866 862 params->src_width / uv_hscale); 867 867 - tmp_V = calc_swidthsw(dev_priv, params->offset_V, 863 863 + tmp_V = calc_swidthsw(display, params->offset_V, 868 864 params->src_width / uv_hscale); 869 865 swidthsw |= max(tmp_U, tmp_V) << 16; 870 866 ··· 903 899 904 900 int intel_overlay_switch_off(struct intel_overlay *overlay) 905 901 { 906 906 - struct drm_i915_private *dev_priv = overlay->i915; 902 902 + struct intel_display *display = overlay->display; 907 903 int ret; 908 904 909 909 - drm_WARN_ON(&dev_priv->drm, 910 910 - !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 905 905 + drm_WARN_ON(display->drm, 906 906 + !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex)); 911 907 912 908 ret = intel_overlay_recover_from_interrupt(overlay); 913 909 if (ret != 0) ··· 940 936 941 937 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 942 938 { 943 943 - struct drm_i915_private *dev_priv = overlay->i915; 939 939 + struct intel_display *display = overlay->display; 944 940 u32 ratio; 945 941 946 942 /* XXX: This is not the same logic as in the xorg driver, but more in 947 943 * line with the intel documentation for the i965 948 944 */ 949 949 - if (DISPLAY_VER(dev_priv) >= 4) { 950 950 - u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv)); 945 945 + if (DISPLAY_VER(display) >= 4) { 946 946 + u32 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 951 947 952 948 /* on i965 use the PGM reg to read out the autoscaler values */ 953 949 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp); 954 950 } else { 955 951 u32 tmp; 956 952 957 957 - if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE) 958 958 - tmp = intel_de_read(dev_priv, 959 959 - PFIT_AUTO_RATIOS(dev_priv)); 953 953 + if (intel_de_read(display, PFIT_CONTROL(display)) & PFIT_VERT_AUTO_SCALE) 954 954 + tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display)); 960 955 else 961 961 - tmp = intel_de_read(dev_priv, 962 962 - PFIT_PGM_RATIOS(dev_priv)); 956 956 + tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); 963 957 964 958 ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp); 965 959 } ··· 1002 1000 return 0; 1003 1001 } 1004 1002 1005 1005 - static int check_overlay_src(struct drm_i915_private *dev_priv, 1003 1003 + static int check_overlay_src(struct intel_display *display, 1006 1004 struct drm_intel_overlay_put_image *rec, 1007 1005 struct drm_i915_gem_object *new_bo) 1008 1006 { ··· 1013 1011 u32 tmp; 1014 1012 1015 1013 /* check src dimensions */ 1016 1016 - if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 1014 1014 + if (display->platform.i845g || display->platform.i830) { 1017 1015 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 1018 1016 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 1019 1017 return -EINVAL; ··· 1065 1063 return -EINVAL; 1066 1064 1067 1065 /* stride checking */ 1068 1068 - if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1066 1066 + if (display->platform.i830 || display->platform.i845g) 1069 1067 stride_mask = 255; 1070 1068 else 1071 1069 stride_mask = 63; 1072 1070 1073 1071 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1074 1072 return -EINVAL; 1075 1075 - if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512) 1073 1073 + if (DISPLAY_VER(display) == 4 && rec->stride_Y < 512) 1076 1074 return -EINVAL; 1077 1075 1078 1076 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? ··· 1116 1114 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1117 1115 struct drm_file *file_priv) 1118 1116 { 1117 1117 + struct intel_display *display = to_intel_display(dev); 1119 1118 struct drm_intel_overlay_put_image *params = data; 1120 1120 - struct drm_i915_private *dev_priv = to_i915(dev); 1121 1119 struct intel_overlay *overlay; 1122 1120 struct drm_crtc *drmmode_crtc; 1123 1121 struct intel_crtc *crtc; 1124 1122 struct drm_i915_gem_object *new_bo; 1125 1123 int ret; 1126 1124 1127 1127 - overlay = dev_priv->display.overlay; 1125 1125 + overlay = display->overlay; 1128 1126 if (!overlay) { 1129 1129 - drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1127 1127 + drm_dbg(display->drm, "userspace bug: no overlay\n"); 1130 1128 return -ENODEV; 1131 1129 } 1132 1130 ··· 1150 1148 drm_modeset_lock_all(dev); 1151 1149 1152 1150 if (i915_gem_object_is_tiled(new_bo)) { 1153 1153 - drm_dbg_kms(&dev_priv->drm, 1151 1151 + drm_dbg_kms(display->drm, 1154 1152 "buffer used for overlay image can not be tiled\n"); 1155 1153 ret = -EINVAL; 1156 1154 goto out_unlock; ··· 1199 1197 goto out_unlock; 1200 1198 } 1201 1199 1202 1202 - ret = check_overlay_src(dev_priv, params, new_bo); 1200 1200 + ret = check_overlay_src(display, params, new_bo); 1203 1201 if (ret != 0) 1204 1202 goto out_unlock; 1205 1203 ··· 1279 1277 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1280 1278 struct drm_file *file_priv) 1281 1279 { 1280 1280 + struct intel_display *display = to_intel_display(dev); 1282 1281 struct drm_intel_overlay_attrs *attrs = data; 1283 1283 - struct drm_i915_private *dev_priv = to_i915(dev); 1284 1282 struct intel_overlay *overlay; 1285 1283 int ret; 1286 1284 1287 1287 - overlay = dev_priv->display.overlay; 1285 1285 + overlay = display->overlay; 1288 1286 if (!overlay) { 1289 1289 - drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); 1287 1287 + drm_dbg(display->drm, "userspace bug: no overlay\n"); 1290 1288 return -ENODEV; 1291 1289 } 1292 1290 ··· 1299 1297 attrs->contrast = overlay->contrast; 1300 1298 attrs->saturation = overlay->saturation; 1301 1299 1302 1302 - if (DISPLAY_VER(dev_priv) != 2) { 1303 1303 - attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); 1304 1304 - attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); 1305 1305 - attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); 1306 1306 - attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); 1307 1307 - attrs->gamma4 = intel_de_read(dev_priv, OGAMC4); 1308 1308 - attrs->gamma5 = intel_de_read(dev_priv, OGAMC5); 1300 1300 + if (DISPLAY_VER(display) != 2) { 1301 1301 + attrs->gamma0 = intel_de_read(display, OGAMC0); 1302 1302 + attrs->gamma1 = intel_de_read(display, OGAMC1); 1303 1303 + attrs->gamma2 = intel_de_read(display, OGAMC2); 1304 1304 + attrs->gamma3 = intel_de_read(display, OGAMC3); 1305 1305 + attrs->gamma4 = intel_de_read(display, OGAMC4); 1306 1306 + attrs->gamma5 = intel_de_read(display, OGAMC5); 1309 1307 } 1310 1308 } else { 1311 1309 if (attrs->brightness < -128 || attrs->brightness > 127) ··· 1323 1321 update_reg_attrs(overlay, overlay->regs); 1324 1322 1325 1323 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1326 1326 - if (DISPLAY_VER(dev_priv) == 2) 1324 1324 + if (DISPLAY_VER(display) == 2) 1327 1325 goto out_unlock; 1328 1326 1329 1327 if (overlay->active) { ··· 1335 1333 if (ret) 1336 1334 goto out_unlock; 1337 1335 1338 1338 - intel_de_write(dev_priv, OGAMC0, attrs->gamma0); 1339 1339 - intel_de_write(dev_priv, OGAMC1, attrs->gamma1); 1340 1340 - intel_de_write(dev_priv, OGAMC2, attrs->gamma2); 1341 1341 - intel_de_write(dev_priv, OGAMC3, attrs->gamma3); 1342 1342 - intel_de_write(dev_priv, OGAMC4, attrs->gamma4); 1343 1343 - intel_de_write(dev_priv, OGAMC5, attrs->gamma5); 1336 1336 + intel_de_write(display, OGAMC0, attrs->gamma0); 1337 1337 + intel_de_write(display, OGAMC1, attrs->gamma1); 1338 1338 + intel_de_write(display, OGAMC2, attrs->gamma2); 1339 1339 + intel_de_write(display, OGAMC3, attrs->gamma3); 1340 1340 + intel_de_write(display, OGAMC4, attrs->gamma4); 1341 1341 + intel_de_write(display, OGAMC5, attrs->gamma5); 1344 1342 } 1345 1343 } 1346 1344 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; ··· 1354 1352 1355 1353 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1356 1354 { 1357 1357 - struct drm_i915_private *i915 = overlay->i915; 1355 1355 + struct intel_display *display = overlay->display; 1356 1356 + struct drm_i915_private *i915 = to_i915(display->drm); 1358 1357 struct drm_i915_gem_object *obj = ERR_PTR(-ENODEV); 1359 1358 struct i915_vma *vma; 1360 1359 int err; 1361 1360 1362 1362 - if (!IS_METEORLAKE(i915)) /* Wa_22018444074 */ 1361 1361 + if (!display->platform.meteorlake) /* Wa_22018444074 */ 1363 1362 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1364 1363 if (IS_ERR(obj)) 1365 1364 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); ··· 1393 1390 return err; 1394 1391 } 1395 1392 1396 1396 - void intel_overlay_setup(struct drm_i915_private *dev_priv) 1393 1393 + void intel_overlay_setup(struct intel_display *display) 1397 1394 { 1395 1395 + struct drm_i915_private *dev_priv = to_i915(display->drm); 1398 1396 struct intel_overlay *overlay; 1399 1397 struct intel_engine_cs *engine; 1400 1398 int ret; 1401 1399 1402 1402 - if (!HAS_OVERLAY(dev_priv)) 1400 1400 + if (!HAS_OVERLAY(display)) 1403 1401 return; 1404 1402 1405 1403 engine = to_gt(dev_priv)->engine[RCS0]; ··· 1411 1407 if (!overlay) 1412 1408 return; 1413 1409 1414 1414 - overlay->i915 = dev_priv; 1410 1410 + overlay->display = display; 1415 1411 overlay->context = engine->kernel_context; 1416 1412 overlay->color_key = 0x0101fe; 1417 1413 overlay->color_key_enabled = true; ··· 1422 1418 i915_active_init(&overlay->last_flip, 1423 1419 NULL, intel_overlay_last_flip_retire, 0); 1424 1420 1425 1425 - ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1421 1421 + ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(display)); 1426 1422 if (ret) 1427 1423 goto out_free; 1428 1424 ··· 1430 1426 update_polyphase_filter(overlay->regs); 1431 1427 update_reg_attrs(overlay, overlay->regs); 1432 1428 1433 1433 - dev_priv->display.overlay = overlay; 1434 1434 - drm_info(&dev_priv->drm, "Initialized overlay support.\n"); 1429 1429 + display->overlay = overlay; 1430 1430 + drm_info(display->drm, "Initialized overlay support.\n"); 1435 1431 return; 1436 1432 1437 1433 out_free: 1438 1434 kfree(overlay); 1439 1435 } 1440 1436 1441 1441 - void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1437 1437 + bool intel_overlay_available(struct intel_display *display) 1438 1438 + { 1439 1439 + return display->overlay; 1440 1440 + } 1441 1441 + 1442 1442 + void intel_overlay_cleanup(struct intel_display *display) 1442 1443 { 1443 1444 struct intel_overlay *overlay; 1444 1445 1445 1445 - overlay = fetch_and_zero(&dev_priv->display.overlay); 1446 1446 + overlay = fetch_and_zero(&display->overlay); 1446 1447 if (!overlay) 1447 1448 return; 1448 1449 ··· 1456 1447 * Furthermore modesetting teardown happens beforehand so the 1457 1448 * hardware should be off already. 1458 1449 */ 1459 1459 - drm_WARN_ON(&dev_priv->drm, overlay->active); 1450 1450 + drm_WARN_ON(display->drm, overlay->active); 1460 1451 1461 1452 i915_gem_object_put(overlay->reg_bo); 1462 1453 i915_active_fini(&overlay->last_flip); ··· 1476 1467 struct intel_overlay_snapshot * 1477 1468 intel_overlay_snapshot_capture(struct intel_display *display) 1478 1469 { 1479 1479 - struct drm_i915_private *dev_priv = to_i915(display->drm); 1480 1480 - struct intel_overlay *overlay = dev_priv->display.overlay; 1470 1470 + struct intel_overlay *overlay = display->overlay; 1481 1471 struct intel_overlay_snapshot *error; 1482 1472 1483 1473 if (!overlay || !overlay->active) ··· 1486 1478 if (error == NULL) 1487 1479 return NULL; 1488 1480 1489 1489 - error->dovsta = intel_de_read(dev_priv, DOVSTA); 1490 1490 - error->isr = intel_de_read(dev_priv, GEN2_ISR); 1481 1481 + error->dovsta = intel_de_read(display, DOVSTA); 1482 1482 + error->isr = intel_de_read(display, GEN2_ISR); 1491 1483 error->base = overlay->flip_addr; 1492 1484 1493 1485 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));

+12 -7

drivers/gpu/drm/i915/display/intel_overlay.h

reviewed

··· 17 17 struct intel_overlay_snapshot; 18 18 19 19 #ifdef I915 20 20 - void intel_overlay_setup(struct drm_i915_private *dev_priv); 21 21 - void intel_overlay_cleanup(struct drm_i915_private *dev_priv); 20 20 + void intel_overlay_setup(struct intel_display *display); 21 21 + bool intel_overlay_available(struct intel_display *display); 22 22 + void intel_overlay_cleanup(struct intel_display *display); 22 23 int intel_overlay_switch_off(struct intel_overlay *overlay); 23 24 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 24 25 struct drm_file *file_priv); 25 26 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 26 27 struct drm_file *file_priv); 27 27 - void intel_overlay_reset(struct drm_i915_private *dev_priv); 28 28 + void intel_overlay_reset(struct intel_display *display); 28 29 #else 29 29 - static inline void intel_overlay_setup(struct drm_i915_private *dev_priv) 30 30 + static inline void intel_overlay_setup(struct intel_display *display) 30 31 { 31 32 } 32 32 - static inline void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 33 33 + static inline bool intel_overlay_available(struct intel_display *display) 34 34 + { 35 35 + return false; 36 36 + } 37 37 + static inline void intel_overlay_cleanup(struct intel_display *display) 33 38 { 34 39 } 35 40 static inline int intel_overlay_switch_off(struct intel_overlay *overlay) ··· 42 37 return 0; 43 38 } 44 39 static inline int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 45 45 - struct drm_file *file_priv) 40 40 + struct drm_file *file_priv) 46 41 { 47 42 return 0; 48 43 } ··· 51 46 { 52 47 return 0; 53 48 } 54 54 - static inline void intel_overlay_reset(struct drm_i915_private *dev_priv) 49 49 + static inline void intel_overlay_reset(struct intel_display *display) 55 50 { 56 51 } 57 52 #endif

+3 -3

drivers/gpu/drm/i915/display/intel_panel.c

reviewed

··· 383 383 enum drm_connector_status 384 384 intel_panel_detect(struct drm_connector *connector, bool force) 385 385 { 386 386 - struct drm_i915_private *i915 = to_i915(connector->dev); 386 386 + struct intel_display *display = to_intel_display(connector->dev); 387 387 388 388 - if (!intel_display_device_enabled(i915)) 388 388 + if (!intel_display_device_enabled(display)) 389 389 return connector_status_disconnected; 390 390 391 391 - if (!intel_display_driver_check_access(i915)) 391 391 + if (!intel_display_driver_check_access(display)) 392 392 return connector->status; 393 393 394 394 return connector_status_connected;

+1

drivers/gpu/drm/i915/display/intel_pch_display.c

reviewed

··· 6 6 #include "g4x_dp.h" 7 7 #include "i915_reg.h" 8 8 #include "intel_crt.h" 9 9 + #include "intel_crt_regs.h" 9 10 #include "intel_de.h" 10 11 #include "intel_display_types.h" 11 12 #include "intel_dpll.h"

+13 -13

drivers/gpu/drm/i915/display/intel_pch_refclk.c

reviewed

··· 108 108 109 109 intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE); 110 110 111 111 - mutex_lock(&dev_priv->sb_lock); 111 111 + intel_sbi_lock(dev_priv); 112 112 113 113 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); 114 114 temp |= SBI_SSCCTL_DISABLE; 115 115 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); 116 116 117 117 - mutex_unlock(&dev_priv->sb_lock); 117 117 + intel_sbi_unlock(dev_priv); 118 118 } 119 119 120 120 struct iclkip_params { ··· 195 195 "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", 196 196 clock, p.auxdiv, p.divsel, p.phasedir, p.phaseinc); 197 197 198 198 - mutex_lock(&dev_priv->sb_lock); 198 198 + intel_sbi_lock(dev_priv); 199 199 200 200 /* Program SSCDIVINTPHASE6 */ 201 201 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); ··· 218 218 temp &= ~SBI_SSCCTL_DISABLE; 219 219 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); 220 220 221 221 - mutex_unlock(&dev_priv->sb_lock); 221 221 + intel_sbi_unlock(dev_priv); 222 222 223 223 /* Wait for initialization time */ 224 224 udelay(24); ··· 236 236 237 237 iclkip_params_init(&p); 238 238 239 239 - mutex_lock(&dev_priv->sb_lock); 239 239 + intel_sbi_lock(dev_priv); 240 240 241 241 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); 242 242 if (temp & SBI_SSCCTL_DISABLE) { 243 243 - mutex_unlock(&dev_priv->sb_lock); 243 243 + intel_sbi_unlock(dev_priv); 244 244 return 0; 245 245 } 246 246 ··· 254 254 p.auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> 255 255 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; 256 256 257 257 - mutex_unlock(&dev_priv->sb_lock); 257 257 + intel_sbi_unlock(dev_priv); 258 258 259 259 p.desired_divisor = (p.divsel + 2) * p.iclk_pi_range + p.phaseinc; 260 260 ··· 279 279 with_fdi, "LP PCH doesn't have FDI\n")) 280 280 with_fdi = false; 281 281 282 282 - mutex_lock(&dev_priv->sb_lock); 282 282 + intel_sbi_lock(dev_priv); 283 283 284 284 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); 285 285 tmp &= ~SBI_SSCCTL_DISABLE; ··· 302 302 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; 303 303 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); 304 304 305 305 - mutex_unlock(&dev_priv->sb_lock); 305 305 + intel_sbi_unlock(dev_priv); 306 306 } 307 307 308 308 /* Sequence to disable CLKOUT_DP */ ··· 310 310 { 311 311 u32 reg, tmp; 312 312 313 313 - mutex_lock(&dev_priv->sb_lock); 313 313 + intel_sbi_lock(dev_priv); 314 314 315 315 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; 316 316 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); ··· 328 328 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 329 329 } 330 330 331 331 - mutex_unlock(&dev_priv->sb_lock); 331 331 + intel_sbi_unlock(dev_priv); 332 332 } 333 333 334 334 #define BEND_IDX(steps) ((50 + (steps)) / 5) ··· 374 374 if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase))) 375 375 return; 376 376 377 377 - mutex_lock(&dev_priv->sb_lock); 377 377 + intel_sbi_lock(dev_priv); 378 378 379 379 if (steps % 10 != 0) 380 380 tmp = 0xAAAAAAAB; ··· 387 387 tmp |= sscdivintphase[idx]; 388 388 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); 389 389 390 390 - mutex_unlock(&dev_priv->sb_lock); 390 390 + intel_sbi_unlock(dev_priv); 391 391 } 392 392 393 393 #undef BEND_IDX

+30 -26

drivers/gpu/drm/i915/display/intel_plane_initial.c

reviewed

··· 20 20 struct drm_framebuffer **fb, 21 21 struct i915_vma **vma) 22 22 { 23 23 - struct drm_i915_private *i915 = to_i915(this->base.dev); 23 23 + struct intel_display *display = to_intel_display(this); 24 24 struct intel_crtc *crtc; 25 25 26 26 - for_each_intel_crtc(&i915->drm, crtc) { 26 26 + for_each_intel_crtc(display->drm, crtc) { 27 27 struct intel_plane *plane = 28 28 to_intel_plane(crtc->base.primary); 29 29 const struct intel_plane_state *plane_state = ··· 48 48 } 49 49 50 50 static bool 51 51 - initial_plane_phys_lmem(struct drm_i915_private *i915, 51 51 + initial_plane_phys_lmem(struct intel_display *display, 52 52 struct intel_initial_plane_config *plane_config) 53 53 { 54 54 + struct drm_i915_private *i915 = to_i915(display->drm); 54 55 gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm; 55 56 struct intel_memory_region *mem; 56 57 dma_addr_t dma_addr; ··· 64 63 65 64 pte = ioread64(gte); 66 65 if (!(pte & GEN12_GGTT_PTE_LM)) { 67 67 - drm_err(&i915->drm, 66 66 + drm_err(display->drm, 68 67 "Initial plane programming missing PTE_LM bit\n"); 69 68 return false; 70 69 } ··· 76 75 else 77 76 mem = i915->mm.stolen_region; 78 77 if (!mem) { 79 79 - drm_dbg_kms(&i915->drm, 78 78 + drm_dbg_kms(display->drm, 80 79 "Initial plane memory region not initialized\n"); 81 80 return false; 82 81 } ··· 86 85 * ever be placed in the stolen portion. 87 86 */ 88 87 if (dma_addr < mem->region.start || dma_addr > mem->region.end) { 89 89 - drm_err(&i915->drm, 88 88 + drm_err(display->drm, 90 89 "Initial plane programming using invalid range, dma_addr=%pa (%s [%pa-%pa])\n", 91 90 &dma_addr, mem->region.name, &mem->region.start, &mem->region.end); 92 91 return false; 93 92 } 94 93 95 95 - drm_dbg(&i915->drm, 94 94 + drm_dbg(display->drm, 96 95 "Using dma_addr=%pa, based on initial plane programming\n", 97 96 &dma_addr); 98 97 ··· 103 102 } 104 103 105 104 static bool 106 106 - initial_plane_phys_smem(struct drm_i915_private *i915, 105 105 + initial_plane_phys_smem(struct intel_display *display, 107 106 struct intel_initial_plane_config *plane_config) 108 107 { 108 108 + struct drm_i915_private *i915 = to_i915(display->drm); 109 109 struct intel_memory_region *mem; 110 110 u32 base; 111 111 ··· 114 112 115 113 mem = i915->mm.stolen_region; 116 114 if (!mem) { 117 117 - drm_dbg_kms(&i915->drm, 115 115 + drm_dbg_kms(display->drm, 118 116 "Initial plane memory region not initialized\n"); 119 117 return false; 120 118 } ··· 127 125 } 128 126 129 127 static bool 130 130 - initial_plane_phys(struct drm_i915_private *i915, 128 128 + initial_plane_phys(struct intel_display *display, 131 129 struct intel_initial_plane_config *plane_config) 132 130 { 131 131 + struct drm_i915_private *i915 = to_i915(display->drm); 132 132 + 133 133 if (IS_DGFX(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915)) 134 134 - return initial_plane_phys_lmem(i915, plane_config); 134 134 + return initial_plane_phys_lmem(display, plane_config); 135 135 else 136 136 - return initial_plane_phys_smem(i915, plane_config); 136 136 + return initial_plane_phys_smem(display, plane_config); 137 137 } 138 138 139 139 static struct i915_vma * 140 140 - initial_plane_vma(struct drm_i915_private *i915, 140 140 + initial_plane_vma(struct intel_display *display, 141 141 struct intel_initial_plane_config *plane_config) 142 142 { 143 143 + struct drm_i915_private *i915 = to_i915(display->drm); 143 144 struct intel_memory_region *mem; 144 145 struct drm_i915_gem_object *obj; 145 146 struct drm_mm_node orig_mm = {}; ··· 154 149 if (plane_config->size == 0) 155 150 return NULL; 156 151 157 157 - if (!initial_plane_phys(i915, plane_config)) 152 152 + if (!initial_plane_phys(display, plane_config)) 158 153 return NULL; 159 154 160 155 phys_base = plane_config->phys_base; ··· 173 168 if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) && 174 169 mem == i915->mm.stolen_region && 175 170 size * 2 > i915->dsm.usable_size) { 176 176 - drm_dbg_kms(&i915->drm, "Initial FB size exceeds half of stolen, discarding\n"); 171 171 + drm_dbg_kms(display->drm, "Initial FB size exceeds half of stolen, discarding\n"); 177 172 return NULL; 178 173 } 179 174 ··· 181 176 I915_BO_ALLOC_USER | 182 177 I915_BO_PREALLOC); 183 178 if (IS_ERR(obj)) { 184 184 - drm_dbg_kms(&i915->drm, "Failed to preallocate initial FB in %s\n", 179 179 + drm_dbg_kms(display->drm, "Failed to preallocate initial FB in %s\n", 185 180 mem->region.name); 186 181 return NULL; 187 182 } ··· 259 254 if (drm_mm_node_allocated(&orig_mm)) 260 255 drm_mm_remove_node(&orig_mm); 261 256 262 262 - drm_dbg_kms(&i915->drm, 257 257 + drm_dbg_kms(display->drm, 263 258 "Initial plane fb bound to 0x%x in the ggtt (original 0x%x)\n", 264 259 i915_ggtt_offset(vma), plane_config->base); 265 260 ··· 276 271 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, 277 272 struct intel_initial_plane_config *plane_config) 278 273 { 279 279 - struct drm_device *dev = crtc->base.dev; 280 280 - struct drm_i915_private *dev_priv = to_i915(dev); 274 274 + struct intel_display *display = to_intel_display(crtc); 281 275 struct drm_mode_fb_cmd2 mode_cmd = {}; 282 276 struct drm_framebuffer *fb = &plane_config->fb->base; 283 277 struct i915_vma *vma; ··· 288 284 case I915_FORMAT_MOD_4_TILED: 289 285 break; 290 286 default: 291 291 - drm_dbg(&dev_priv->drm, 287 287 + drm_dbg(display->drm, 292 288 "Unsupported modifier for initial FB: 0x%llx\n", 293 289 fb->modifier); 294 290 return false; 295 291 } 296 292 297 297 - vma = initial_plane_vma(dev_priv, plane_config); 293 293 + vma = initial_plane_vma(display, plane_config); 298 294 if (!vma) 299 295 return false; 300 296 ··· 307 303 308 304 if (intel_framebuffer_init(to_intel_framebuffer(fb), 309 305 intel_bo_to_drm_bo(vma->obj), &mode_cmd)) { 310 310 - drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n"); 306 306 + drm_dbg_kms(display->drm, "intel fb init failed\n"); 311 307 goto err_vma; 312 308 } 313 309 ··· 414 410 i915_vma_put(plane_config->vma); 415 411 } 416 412 417 417 - void intel_initial_plane_config(struct drm_i915_private *i915) 413 413 + void intel_initial_plane_config(struct intel_display *display) 418 414 { 419 415 struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {}; 420 416 struct intel_crtc *crtc; 421 417 422 422 - for_each_intel_crtc(&i915->drm, crtc) { 418 418 + for_each_intel_crtc(display->drm, crtc) { 423 419 struct intel_initial_plane_config *plane_config = 424 420 &plane_configs[crtc->pipe]; 425 421 ··· 433 429 * can even allow for smooth boot transitions if the BIOS 434 430 * fb is large enough for the active pipe configuration. 435 431 */ 436 436 - i915->display.funcs.display->get_initial_plane_config(crtc, plane_config); 432 432 + display->funcs.display->get_initial_plane_config(crtc, plane_config); 437 433 438 434 /* 439 435 * If the fb is shared between multiple heads, we'll ··· 441 437 */ 442 438 intel_find_initial_plane_obj(crtc, plane_configs); 443 439 444 444 - if (i915->display.funcs.display->fixup_initial_plane_config(crtc, plane_config)) 440 440 + if (display->funcs.display->fixup_initial_plane_config(crtc, plane_config)) 445 441 intel_crtc_wait_for_next_vblank(crtc); 446 442 447 443 plane_config_fini(plane_config);

+2 -2

drivers/gpu/drm/i915/display/intel_plane_initial.h

reviewed

··· 6 6 #ifndef __INTEL_PLANE_INITIAL_H__ 7 7 #define __INTEL_PLANE_INITIAL_H__ 8 8 9 9 - struct drm_i915_private; 9 9 + struct intel_display; 10 10 11 11 - void intel_initial_plane_config(struct drm_i915_private *i915); 11 11 + void intel_initial_plane_config(struct intel_display *display); 12 12 13 13 #endif

+93 -81

drivers/gpu/drm/i915/display/intel_pps.c

reviewed

··· 134 134 */ 135 135 if (!pll_enabled) { 136 136 release_cl_override = display->platform.cherryview && 137 137 - !chv_phy_powergate_ch(dev_priv, phy, ch, true); 137 137 + !chv_phy_powergate_ch(display, phy, ch, true); 138 138 139 139 if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) { 140 140 drm_err(display->drm, ··· 163 163 vlv_force_pll_off(dev_priv, pipe); 164 164 165 165 if (release_cl_override) 166 166 - chv_phy_powergate_ch(dev_priv, phy, ch, false); 166 166 + chv_phy_powergate_ch(display, phy, ch, false); 167 167 } 168 168 } 169 169 ··· 668 668 struct intel_display *display = to_intel_display(intel_dp); 669 669 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 670 670 ktime_t panel_power_on_time; 671 671 - s64 panel_power_off_duration; 672 672 - 673 673 - drm_dbg_kms(display->drm, 674 674 - "[ENCODER:%d:%s] %s wait for panel power cycle\n", 675 675 - dig_port->base.base.base.id, dig_port->base.base.name, 676 676 - pps_name(intel_dp)); 671 671 + s64 panel_power_off_duration, remaining; 677 672 678 673 /* take the difference of current time and panel power off time 679 679 - * and then make panel wait for t11_t12 if needed. */ 674 674 + * and then make panel wait for power_cycle if needed. */ 680 675 panel_power_on_time = ktime_get_boottime(); 681 676 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time); 682 677 678 678 + remaining = max(0, intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration); 679 679 + 680 680 + drm_dbg_kms(display->drm, 681 681 + "[ENCODER:%d:%s] %s wait for panel power cycle (%lld ms remaining)\n", 682 682 + dig_port->base.base.base.id, dig_port->base.base.name, 683 683 + pps_name(intel_dp), remaining); 684 684 + 683 685 /* When we disable the VDD override bit last we have to do the manual 684 686 * wait. */ 685 685 - if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay) 686 686 - wait_remaining_ms_from_jiffies(jiffies, 687 687 - intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration); 687 687 + if (remaining) 688 688 + wait_remaining_ms_from_jiffies(jiffies, remaining); 688 689 689 690 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 690 691 } ··· 1388 1387 } 1389 1388 1390 1389 static void 1391 1391 - intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) 1390 1390 + intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct intel_pps_delays *seq) 1392 1391 { 1393 1392 struct intel_display *display = to_intel_display(intel_dp); 1394 1394 - u32 pp_on, pp_off, pp_ctl; 1393 1393 + u32 pp_on, pp_off, pp_ctl, power_cycle_delay; 1395 1394 struct pps_registers regs; 1396 1395 1397 1396 intel_pps_get_registers(intel_dp, &regs); ··· 1406 1405 pp_off = intel_de_read(display, regs.pp_off); 1407 1406 1408 1407 /* Pull timing values out of registers */ 1409 1409 - seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); 1410 1410 - seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); 1411 1411 - seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); 1412 1412 - seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); 1408 1408 + seq->power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); 1409 1409 + seq->backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); 1410 1410 + seq->backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); 1411 1411 + seq->power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); 1413 1412 1414 1413 if (i915_mmio_reg_valid(regs.pp_div)) { 1415 1414 u32 pp_div; 1416 1415 1417 1416 pp_div = intel_de_read(display, regs.pp_div); 1418 1417 1419 1419 - seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; 1418 1418 + power_cycle_delay = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div); 1420 1419 } else { 1421 1421 - seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; 1420 1420 + power_cycle_delay = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl); 1422 1421 } 1422 1422 + 1423 1423 + /* hardware wants <delay>+1 in 100ms units */ 1424 1424 + seq->power_cycle = power_cycle_delay ? (power_cycle_delay - 1) * 1000 : 0; 1423 1425 } 1424 1426 1425 1427 static void 1426 1428 intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name, 1427 1427 - const struct edp_power_seq *seq) 1429 1429 + const struct intel_pps_delays *seq) 1428 1430 { 1429 1431 struct intel_display *display = to_intel_display(intel_dp); 1430 1432 1431 1433 drm_dbg_kms(display->drm, 1432 1432 - "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 1433 1433 - state_name, 1434 1434 - seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); 1434 1434 + "%s power_up %d backlight_on %d backlight_off %d power_down %d power_cycle %d\n", 1435 1435 + state_name, seq->power_up, seq->backlight_on, 1436 1436 + seq->backlight_off, seq->power_down, seq->power_cycle); 1435 1437 } 1436 1438 1437 1439 static void 1438 1440 intel_pps_verify_state(struct intel_dp *intel_dp) 1439 1441 { 1440 1442 struct intel_display *display = to_intel_display(intel_dp); 1441 1441 - struct edp_power_seq hw; 1442 1442 - struct edp_power_seq *sw = &intel_dp->pps.pps_delays; 1443 1443 + struct intel_pps_delays hw; 1444 1444 + struct intel_pps_delays *sw = &intel_dp->pps.pps_delays; 1443 1445 1444 1446 intel_pps_readout_hw_state(intel_dp, &hw); 1445 1447 1446 1446 - if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || 1447 1447 - hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { 1448 1448 + if (hw.power_up != sw->power_up || 1449 1449 + hw.backlight_on != sw->backlight_on || 1450 1450 + hw.backlight_off != sw->backlight_off || 1451 1451 + hw.power_down != sw->power_down || 1452 1452 + hw.power_cycle != sw->power_cycle) { 1448 1453 drm_err(display->drm, "PPS state mismatch\n"); 1449 1454 intel_pps_dump_state(intel_dp, "sw", sw); 1450 1455 intel_pps_dump_state(intel_dp, "hw", &hw); 1451 1456 } 1452 1457 } 1453 1458 1454 1454 - static bool pps_delays_valid(struct edp_power_seq *delays) 1459 1459 + static bool pps_delays_valid(struct intel_pps_delays *delays) 1455 1460 { 1456 1456 - return delays->t1_t3 || delays->t8 || delays->t9 || 1457 1457 - delays->t10 || delays->t11_t12; 1461 1461 + return delays->power_up || delays->backlight_on || delays->backlight_off || 1462 1462 + delays->power_down || delays->power_cycle; 1463 1463 + } 1464 1464 + 1465 1465 + static int msecs_to_pps_units(int msecs) 1466 1466 + { 1467 1467 + /* PPS uses 100us units */ 1468 1468 + return msecs * 10; 1469 1469 + } 1470 1470 + 1471 1471 + static int pps_units_to_msecs(int val) 1472 1472 + { 1473 1473 + /* PPS uses 100us units */ 1474 1474 + return DIV_ROUND_UP(val, 10); 1458 1475 } 1459 1476 1460 1477 static void pps_init_delays_bios(struct intel_dp *intel_dp, 1461 1461 - struct edp_power_seq *bios) 1478 1478 + struct intel_pps_delays *bios) 1462 1479 { 1463 1480 struct intel_display *display = to_intel_display(intel_dp); 1464 1481 ··· 1491 1472 } 1492 1473 1493 1474 static void pps_init_delays_vbt(struct intel_dp *intel_dp, 1494 1494 - struct edp_power_seq *vbt) 1475 1475 + struct intel_pps_delays *vbt) 1495 1476 { 1496 1477 struct intel_display *display = to_intel_display(intel_dp); 1497 1478 struct intel_connector *connector = intel_dp->attached_connector; ··· 1507 1488 * seems sufficient to avoid this problem. 1508 1489 */ 1509 1490 if (intel_has_quirk(display, QUIRK_INCREASE_T12_DELAY)) { 1510 1510 - vbt->t11_t12 = max_t(u16, vbt->t11_t12, 1300 * 10); 1491 1491 + vbt->power_cycle = max_t(u16, vbt->power_cycle, msecs_to_pps_units(1300)); 1511 1492 drm_dbg_kms(display->drm, 1512 1493 "Increasing T12 panel delay as per the quirk to %d\n", 1513 1513 - vbt->t11_t12); 1494 1494 + vbt->power_cycle); 1514 1495 } 1515 1515 - 1516 1516 - /* T11_T12 delay is special and actually in units of 100ms, but zero 1517 1517 - * based in the hw (so we need to add 100 ms). But the sw vbt 1518 1518 - * table multiplies it with 1000 to make it in units of 100usec, 1519 1519 - * too. */ 1520 1520 - vbt->t11_t12 += 100 * 10; 1521 1496 1522 1497 intel_pps_dump_state(intel_dp, "vbt", vbt); 1523 1498 } 1524 1499 1525 1500 static void pps_init_delays_spec(struct intel_dp *intel_dp, 1526 1526 - struct edp_power_seq *spec) 1501 1501 + struct intel_pps_delays *spec) 1527 1502 { 1528 1503 struct intel_display *display = to_intel_display(intel_dp); 1529 1504 1530 1505 lockdep_assert_held(&display->pps.mutex); 1531 1506 1532 1532 - /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 1533 1533 - * our hw here, which are all in 100usec. */ 1534 1534 - spec->t1_t3 = 210 * 10; 1535 1535 - spec->t8 = 50 * 10; /* no limit for t8, use t7 instead */ 1536 1536 - spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 1537 1537 - spec->t10 = 500 * 10; 1538 1538 - /* This one is special and actually in units of 100ms, but zero 1539 1539 - * based in the hw (so we need to add 100 ms). But the sw vbt 1540 1540 - * table multiplies it with 1000 to make it in units of 100usec, 1541 1541 - * too. */ 1542 1542 - spec->t11_t12 = (510 + 100) * 10; 1507 1507 + /* Upper limits from eDP 1.3 spec */ 1508 1508 + spec->power_up = msecs_to_pps_units(10 + 200); /* T1+T3 */ 1509 1509 + spec->backlight_on = msecs_to_pps_units(50); /* no limit for T8, use T7 instead */ 1510 1510 + spec->backlight_off = msecs_to_pps_units(50); /* no limit for T9, make it symmetric with T8 */ 1511 1511 + spec->power_down = msecs_to_pps_units(500); /* T10 */ 1512 1512 + spec->power_cycle = msecs_to_pps_units(10 + 500); /* T11+T12 */ 1543 1513 1544 1514 intel_pps_dump_state(intel_dp, "spec", spec); 1545 1515 } ··· 1536 1528 static void pps_init_delays(struct intel_dp *intel_dp) 1537 1529 { 1538 1530 struct intel_display *display = to_intel_display(intel_dp); 1539 1539 - struct edp_power_seq cur, vbt, spec, 1531 1531 + struct intel_pps_delays cur, vbt, spec, 1540 1532 *final = &intel_dp->pps.pps_delays; 1541 1533 1542 1534 lockdep_assert_held(&display->pps.mutex); ··· 1554 1546 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ 1555 1547 spec.field : \ 1556 1548 max(cur.field, vbt.field)) 1557 1557 - assign_final(t1_t3); 1558 1558 - assign_final(t8); 1559 1559 - assign_final(t9); 1560 1560 - assign_final(t10); 1561 1561 - assign_final(t11_t12); 1549 1549 + assign_final(power_up); 1550 1550 + assign_final(backlight_on); 1551 1551 + assign_final(backlight_off); 1552 1552 + assign_final(power_down); 1553 1553 + assign_final(power_cycle); 1562 1554 #undef assign_final 1563 1555 1564 1564 - #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) 1565 1565 - intel_dp->pps.panel_power_up_delay = get_delay(t1_t3); 1566 1566 - intel_dp->pps.backlight_on_delay = get_delay(t8); 1567 1567 - intel_dp->pps.backlight_off_delay = get_delay(t9); 1568 1568 - intel_dp->pps.panel_power_down_delay = get_delay(t10); 1569 1569 - intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12); 1570 1570 - #undef get_delay 1556 1556 + intel_dp->pps.panel_power_up_delay = pps_units_to_msecs(final->power_up); 1557 1557 + intel_dp->pps.backlight_on_delay = pps_units_to_msecs(final->backlight_on); 1558 1558 + intel_dp->pps.backlight_off_delay = pps_units_to_msecs(final->backlight_off); 1559 1559 + intel_dp->pps.panel_power_down_delay = pps_units_to_msecs(final->power_down); 1560 1560 + intel_dp->pps.panel_power_cycle_delay = pps_units_to_msecs(final->power_cycle); 1571 1561 1572 1562 drm_dbg_kms(display->drm, 1573 1563 "panel power up delay %d, power down delay %d, power cycle delay %d\n", ··· 1579 1573 1580 1574 /* 1581 1575 * We override the HW backlight delays to 1 because we do manual waits 1582 1582 - * on them. For T8, even BSpec recommends doing it. For T9, if we 1583 1583 - * don't do this, we'll end up waiting for the backlight off delay 1584 1584 - * twice: once when we do the manual sleep, and once when we disable 1585 1585 - * the panel and wait for the PP_STATUS bit to become zero. 1576 1576 + * on them. For backlight_on, even BSpec recommends doing it. For 1577 1577 + * backlight_off, if we don't do this, we'll end up waiting for the 1578 1578 + * backlight off delay twice: once when we do the manual sleep, and 1579 1579 + * once when we disable the panel and wait for the PP_STATUS bit to 1580 1580 + * become zero. 1586 1581 */ 1587 1587 - final->t8 = 1; 1588 1588 - final->t9 = 1; 1582 1582 + final->backlight_on = 1; 1583 1583 + final->backlight_off = 1; 1589 1584 1590 1585 /* 1591 1591 - * HW has only a 100msec granularity for t11_t12 so round it up 1586 1586 + * HW has only a 100msec granularity for power_cycle so round it up 1592 1587 * accordingly. 1593 1588 */ 1594 1594 - final->t11_t12 = roundup(final->t11_t12, 100 * 10); 1589 1589 + final->power_cycle = roundup(final->power_cycle, msecs_to_pps_units(100)); 1595 1590 } 1596 1591 1597 1592 static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd) ··· 1603 1596 int div = DISPLAY_RUNTIME_INFO(display)->rawclk_freq / 1000; 1604 1597 struct pps_registers regs; 1605 1598 enum port port = dp_to_dig_port(intel_dp)->base.port; 1606 1606 - const struct edp_power_seq *seq = &intel_dp->pps.pps_delays; 1599 1599 + const struct intel_pps_delays *seq = &intel_dp->pps.pps_delays; 1607 1600 1608 1601 lockdep_assert_held(&display->pps.mutex); 1609 1602 ··· 1636 1629 intel_de_write(display, regs.pp_ctrl, pp); 1637 1630 } 1638 1631 1639 1639 - pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | 1640 1640 - REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); 1641 1641 - pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | 1642 1642 - REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); 1632 1632 + pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->power_up) | 1633 1633 + REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->backlight_on); 1634 1634 + pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->backlight_off) | 1635 1635 + REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->power_down); 1643 1636 1644 1637 /* Haswell doesn't have any port selection bits for the panel 1645 1638 * power sequencer any more. */ ··· 1672 1665 */ 1673 1666 if (i915_mmio_reg_valid(regs.pp_div)) 1674 1667 intel_de_write(display, regs.pp_div, 1675 1675 - REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); 1668 1668 + REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, 1669 1669 + (100 * div) / 2 - 1) | 1670 1670 + REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, 1671 1671 + DIV_ROUND_UP(seq->power_cycle, 1000) + 1)); 1676 1672 else 1677 1673 intel_de_rmw(display, regs.pp_ctrl, BXT_POWER_CYCLE_DELAY_MASK, 1678 1674 REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, 1679 1679 - DIV_ROUND_UP(seq->t11_t12, 1000))); 1675 1675 + DIV_ROUND_UP(seq->power_cycle, 1000) + 1)); 1680 1676 1681 1677 drm_dbg_kms(display->drm, 1682 1678 "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", ··· 1820 1810 intel_dp->pps.panel_power_up_delay); 1821 1811 seq_printf(m, "Panel power down delay: %d\n", 1822 1812 intel_dp->pps.panel_power_down_delay); 1813 1813 + seq_printf(m, "Panel power cycle delay: %d\n", 1814 1814 + intel_dp->pps.panel_power_cycle_delay); 1823 1815 seq_printf(m, "Backlight on delay: %d\n", 1824 1816 intel_dp->pps.backlight_on_delay); 1825 1817 seq_printf(m, "Backlight off delay: %d\n",

+41 -45

drivers/gpu/drm/i915/display/intel_psr.c

reviewed

··· 1130 1130 static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) 1131 1131 { 1132 1132 struct intel_display *display = to_intel_display(intel_dp); 1133 1133 - struct drm_i915_private *dev_priv = to_i915(display->drm); 1134 1133 1135 1134 psr2_program_idle_frames(intel_dp, 0); 1136 1136 - intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO); 1135 1135 + intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO); 1137 1136 } 1138 1137 1139 1138 static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) 1140 1139 { 1141 1140 struct intel_display *display = to_intel_display(intel_dp); 1142 1142 - struct drm_i915_private *dev_priv = to_i915(display->drm); 1143 1141 1144 1144 - intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 1142 1142 + intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6); 1145 1143 psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp)); 1146 1144 } 1147 1145 ··· 1562 1564 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1563 1565 int entry_setup_frames; 1564 1566 1565 1565 - /* 1566 1566 - * Current PSR panels don't work reliably with VRR enabled 1567 1567 - * So if VRR is enabled, do not enable PSR. 1568 1568 - */ 1569 1569 - if (crtc_state->vrr.enable) 1570 1570 - return false; 1571 1571 - 1572 1567 if (!CAN_PSR(intel_dp)) 1573 1568 return false; 1574 1569 ··· 1635 1644 return true; 1636 1645 } 1637 1646 1647 1647 + static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp, 1648 1648 + struct intel_crtc_state *crtc_state) 1649 1649 + { 1650 1650 + struct intel_display *display = to_intel_display(intel_dp); 1651 1651 + 1652 1652 + return (DISPLAY_VER(display) == 20 && intel_dp->psr.entry_setup_frames > 0 && 1653 1653 + !crtc_state->has_sel_update); 1654 1654 + } 1655 1655 + 1638 1656 void intel_psr_compute_config(struct intel_dp *intel_dp, 1639 1657 struct intel_crtc_state *crtc_state, 1640 1658 struct drm_connector_state *conn_state) ··· 1679 1679 return; 1680 1680 } 1681 1681 1682 1682 + /* 1683 1683 + * Currently PSR/PR doesn't work reliably with VRR enabled. 1684 1684 + */ 1685 1685 + if (crtc_state->vrr.enable) 1686 1686 + return; 1687 1687 + 1682 1688 crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp, 1683 1689 crtc_state, 1684 1690 conn_state); ··· 1696 1690 return; 1697 1691 1698 1692 crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state); 1693 1693 + 1694 1694 + /* Wa_18037818876 */ 1695 1695 + if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) { 1696 1696 + crtc_state->has_psr = false; 1697 1697 + drm_dbg_kms(display->drm, 1698 1698 + "PSR disabled to workaround PSR FSM hang issue\n"); 1699 1699 + } 1699 1700 } 1700 1701 1701 1702 void intel_psr_get_config(struct intel_encoder *encoder, ··· 1786 1773 intel_dp->psr.active = true; 1787 1774 } 1788 1775 1789 1789 - static u32 wa_16013835468_bit_get(struct intel_dp *intel_dp) 1790 1790 - { 1791 1791 - switch (intel_dp->psr.pipe) { 1792 1792 - case PIPE_A: 1793 1793 - return LATENCY_REPORTING_REMOVED_PIPE_A; 1794 1794 - case PIPE_B: 1795 1795 - return LATENCY_REPORTING_REMOVED_PIPE_B; 1796 1796 - case PIPE_C: 1797 1797 - return LATENCY_REPORTING_REMOVED_PIPE_C; 1798 1798 - case PIPE_D: 1799 1799 - return LATENCY_REPORTING_REMOVED_PIPE_D; 1800 1800 - default: 1801 1801 - MISSING_CASE(intel_dp->psr.pipe); 1802 1802 - return 0; 1803 1803 - } 1804 1804 - } 1805 1805 - 1806 1776 /* 1807 1777 * Wa_16013835468 1808 1778 * Wa_14015648006 ··· 1794 1798 const struct intel_crtc_state *crtc_state) 1795 1799 { 1796 1800 struct intel_display *display = to_intel_display(intel_dp); 1797 1797 - bool set_wa_bit = false; 1801 1801 + enum pipe pipe = intel_dp->psr.pipe; 1802 1802 + bool activate = false; 1798 1803 1799 1804 /* Wa_14015648006 */ 1800 1800 - if (IS_DISPLAY_VER(display, 11, 14)) 1801 1801 - set_wa_bit |= crtc_state->wm_level_disabled; 1805 1805 + if (IS_DISPLAY_VER(display, 11, 14) && crtc_state->wm_level_disabled) 1806 1806 + activate = true; 1802 1807 1803 1808 /* Wa_16013835468 */ 1804 1804 - if (DISPLAY_VER(display) == 12) 1805 1805 - set_wa_bit |= crtc_state->hw.adjusted_mode.crtc_vblank_start != 1806 1806 - crtc_state->hw.adjusted_mode.crtc_vdisplay; 1809 1809 + if (DISPLAY_VER(display) == 12 && 1810 1810 + crtc_state->hw.adjusted_mode.crtc_vblank_start != 1811 1811 + crtc_state->hw.adjusted_mode.crtc_vdisplay) 1812 1812 + activate = true; 1807 1813 1808 1808 - if (set_wa_bit) 1814 1814 + if (activate) 1809 1815 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 1810 1810 - 0, wa_16013835468_bit_get(intel_dp)); 1816 1816 + 0, LATENCY_REPORTING_REMOVED(pipe)); 1811 1817 else 1812 1818 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 1813 1813 - wa_16013835468_bit_get(intel_dp), 0); 1819 1819 + LATENCY_REPORTING_REMOVED(pipe), 0); 1814 1820 } 1815 1821 1816 1822 static void intel_psr_enable_source(struct intel_dp *intel_dp, ··· 1906 1908 1907 1909 if (intel_dp->psr.sel_update_enabled) { 1908 1910 if (DISPLAY_VER(display) == 9) 1909 1909 - intel_de_rmw(display, CHICKEN_TRANS(cpu_transcoder), 0, 1911 1911 + intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 0, 1910 1912 PSR2_VSC_ENABLE_PROG_HEADER | 1911 1913 PSR2_ADD_VERTICAL_LINE_COUNT); 1912 1914 ··· 1918 1920 if (!intel_dp->psr.panel_replay_enabled && 1919 1921 (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_B0) || 1920 1922 IS_ALDERLAKE_P(dev_priv))) 1921 1921 - intel_de_rmw(display, hsw_chicken_trans_reg(dev_priv, cpu_transcoder), 1923 1923 + intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 1922 1924 0, ADLP_1_BASED_X_GRANULARITY); 1923 1925 1924 1926 /* Wa_16012604467:adlp,mtl[a0,b0] */ ··· 2112 2114 */ 2113 2115 if (DISPLAY_VER(display) >= 11) 2114 2116 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 2115 2115 - wa_16013835468_bit_get(intel_dp), 0); 2117 2117 + LATENCY_REPORTING_REMOVED(intel_dp->psr.pipe), 0); 2116 2118 2117 2119 if (intel_dp->psr.sel_update_enabled) { 2118 2120 /* Wa_16012604467:adlp,mtl[a0,b0] */ ··· 3333 3335 void intel_psr_init(struct intel_dp *intel_dp) 3334 3336 { 3335 3337 struct intel_display *display = to_intel_display(intel_dp); 3336 3336 - struct drm_i915_private *dev_priv = to_i915(display->drm); 3337 3338 struct intel_connector *connector = intel_dp->attached_connector; 3338 3339 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3339 3340 3340 3340 - if (!(HAS_PSR(display) || HAS_DP20(dev_priv))) 3341 3341 + if (!(HAS_PSR(display) || HAS_DP20(display))) 3341 3342 return; 3342 3343 3343 3344 /* ··· 3354 3357 return; 3355 3358 } 3356 3359 3357 3357 - if ((HAS_DP20(dev_priv) && !intel_dp_is_edp(intel_dp)) || 3360 3360 + if ((HAS_DP20(display) && !intel_dp_is_edp(intel_dp)) || 3358 3361 DISPLAY_VER(display) >= 20) 3359 3362 intel_dp->psr.source_panel_replay_support = true; 3360 3363 ··· 3971 3974 void intel_psr_connector_debugfs_add(struct intel_connector *connector) 3972 3975 { 3973 3976 struct intel_display *display = to_intel_display(connector); 3974 3974 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 3975 3977 struct dentry *root = connector->base.debugfs_entry; 3976 3978 3977 3979 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP && ··· 3980 3984 debugfs_create_file("i915_psr_sink_status", 0444, root, 3981 3985 connector, &i915_psr_sink_status_fops); 3982 3986 3983 3983 - if (HAS_PSR(display) || HAS_DP20(i915)) 3987 3987 + if (HAS_PSR(display) || HAS_DP20(display)) 3984 3988 debugfs_create_file("i915_psr_status", 0444, root, 3985 3989 connector, &i915_psr_status_fops); 3986 3990 }

+7 -5

drivers/gpu/drm/i915/display/intel_sdvo.c

reviewed

··· 2136 2136 static enum drm_connector_status 2137 2137 intel_sdvo_detect(struct drm_connector *connector, bool force) 2138 2138 { 2139 2139 + struct intel_display *display = to_intel_display(connector->dev); 2139 2140 struct drm_i915_private *i915 = to_i915(connector->dev); 2140 2141 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2141 2142 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); ··· 2146 2145 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2147 2146 connector->base.id, connector->name); 2148 2147 2149 2149 - if (!intel_display_device_enabled(i915)) 2148 2148 + if (!intel_display_device_enabled(display)) 2150 2149 return connector_status_disconnected; 2151 2150 2152 2152 - if (!intel_display_driver_check_access(i915)) 2151 2151 + if (!intel_display_driver_check_access(display)) 2153 2152 return connector->status; 2154 2153 2155 2154 if (!intel_sdvo_set_target_output(intel_sdvo, ··· 2197 2196 2198 2197 static int intel_sdvo_get_ddc_modes(struct drm_connector *connector) 2199 2198 { 2200 2200 - struct drm_i915_private *i915 = to_i915(connector->dev); 2199 2199 + struct intel_display *display = to_intel_display(connector->dev); 2201 2200 int num_modes = 0; 2202 2201 const struct drm_edid *drm_edid; 2203 2202 2204 2203 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", 2205 2204 connector->base.id, connector->name); 2206 2205 2207 2207 - if (!intel_display_driver_check_access(i915)) 2206 2206 + if (!intel_display_driver_check_access(display)) 2208 2207 return drm_edid_connector_add_modes(connector); 2209 2208 2210 2209 /* set the bus switch and get the modes */ ··· 2298 2297 2299 2298 static int intel_sdvo_get_tv_modes(struct drm_connector *connector) 2300 2299 { 2300 2300 + struct intel_display *display = to_intel_display(connector->dev); 2301 2301 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector)); 2302 2302 struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev); 2303 2303 struct intel_sdvo_connector *intel_sdvo_connector = ··· 2312 2310 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2313 2311 connector->base.id, connector->name); 2314 2312 2315 2315 - if (!intel_display_driver_check_access(i915)) 2313 2313 + if (!intel_display_driver_check_access(display)) 2316 2314 return 0; 2317 2315 2318 2316 /*

+1 -1

drivers/gpu/drm/i915/display/intel_tc.c

reviewed

··· 390 390 { 391 391 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 392 392 struct intel_tc_port *tc = to_tc_port(dig_port); 393 393 - bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; 393 393 + bool lane_reversal = dig_port->lane_reversal; 394 394 u32 val; 395 395 396 396 if (DISPLAY_VER(i915) >= 14)

+2 -3

drivers/gpu/drm/i915/display/intel_tv.c

reviewed

··· 1714 1714 bool force) 1715 1715 { 1716 1716 struct intel_display *display = to_intel_display(connector->dev); 1717 1717 - struct drm_i915_private *i915 = to_i915(connector->dev); 1718 1717 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector)); 1719 1718 enum drm_connector_status status; 1720 1719 int type; ··· 1721 1722 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n", 1722 1723 connector->base.id, connector->name, force); 1723 1724 1724 1724 - if (!intel_display_device_enabled(i915)) 1725 1725 + if (!intel_display_device_enabled(display)) 1725 1726 return connector_status_disconnected; 1726 1727 1727 1727 - if (!intel_display_driver_check_access(i915)) 1728 1728 + if (!intel_display_driver_check_access(display)) 1728 1729 return connector->status; 1729 1730 1730 1731 if (force) {

+8

drivers/gpu/drm/i915/display/intel_vbt_defs.h

reviewed

··· 1014 1014 * Block 27 - eDP VBT Block 1015 1015 */ 1016 1016 1017 1017 + struct edp_power_seq { 1018 1018 + u16 t1_t3; 1019 1019 + u16 t8; 1020 1020 + u16 t9; 1021 1021 + u16 t10; 1022 1022 + u16 t11_t12; 1023 1023 + } __packed; 1024 1024 + 1017 1025 #define EDP_18BPP 0 1018 1026 #define EDP_24BPP 1 1019 1027 #define EDP_30BPP 2

+69 -11

drivers/gpu/drm/i915/display/intel_vdsc.c

reviewed

··· 14 14 #include "intel_crtc.h" 15 15 #include "intel_de.h" 16 16 #include "intel_display_types.h" 17 17 + #include "intel_dp.h" 17 18 #include "intel_dsi.h" 18 19 #include "intel_qp_tables.h" 19 20 #include "intel_vdsc.h" ··· 380 379 381 380 static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state) 382 381 { 383 383 - return crtc_state->dsc.dsc_split ? 2 : 1; 382 382 + return crtc_state->dsc.num_streams; 384 383 } 385 384 386 385 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) ··· 403 402 404 403 pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder); 405 404 406 406 - if (dsc_reg_num >= 3) 405 405 + if (dsc_reg_num >= 4) 407 406 MISSING_CASE(dsc_reg_num); 407 407 + if (dsc_reg_num >= 3) 408 408 + dsc_reg[2] = BMG_DSC2_PPS(pipe, pps); 408 409 if (dsc_reg_num >= 2) 409 410 dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps); 410 411 if (dsc_reg_num >= 1) ··· 418 415 { 419 416 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 420 417 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 421 421 - i915_reg_t dsc_reg[2]; 418 418 + i915_reg_t dsc_reg[3]; 422 419 int i, vdsc_per_pipe, dsc_reg_num; 423 420 424 421 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); ··· 773 770 774 771 intel_dsc_pps_configure(crtc_state); 775 772 776 776 - dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; 773 773 + dss_ctl2_val |= VDSC0_ENABLE; 777 774 if (vdsc_instances_per_pipe > 1) { 778 778 - dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; 775 775 + dss_ctl2_val |= VDSC1_ENABLE; 779 776 dss_ctl1_val |= JOINER_ENABLE; 780 777 } 778 778 + 779 779 + if (vdsc_instances_per_pipe > 2) { 780 780 + dss_ctl2_val |= VDSC2_ENABLE; 781 781 + dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES; 782 782 + } 783 783 + 781 784 if (crtc_state->joiner_pipes) { 782 785 if (intel_crtc_ultrajoiner_enable_needed(crtc_state)) 783 786 dss_ctl1_val |= ULTRA_JOINER_ENABLE; ··· 818 809 { 819 810 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 820 811 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 821 821 - i915_reg_t dsc_reg[2]; 812 812 + i915_reg_t dsc_reg[3]; 822 813 int i, vdsc_per_pipe, dsc_reg_num; 823 814 u32 val; 824 815 ··· 981 972 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); 982 973 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); 983 974 984 984 - crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; 975 975 + crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE; 985 976 if (!crtc_state->dsc.compression_enable) 986 977 goto out; 987 978 988 988 - crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) && 989 989 - (dss_ctl1 & JOINER_ENABLE); 979 979 + if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES)) 980 980 + crtc_state->dsc.num_streams = 3; 981 981 + else if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & VDSC1_ENABLE) 982 982 + crtc_state->dsc.num_streams = 2; 983 983 + else 984 984 + crtc_state->dsc.num_streams = 1; 990 985 991 986 intel_dsc_get_pps_config(crtc_state); 992 987 out: ··· 1001 988 const struct intel_crtc_state *crtc_state) 1002 989 { 1003 990 drm_printf_indent(p, indent, 1004 1004 - "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, split: %s\n", 991 991 + "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n", 1005 992 FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16), 1006 993 crtc_state->dsc.slice_count, 1007 1007 - str_yes_no(crtc_state->dsc.dsc_split)); 994 994 + crtc_state->dsc.num_streams); 1008 995 } 1009 996 1010 997 void intel_vdsc_state_dump(struct drm_printer *p, int indent, ··· 1015 1002 1016 1003 intel_vdsc_dump_state(p, indent, crtc_state); 1017 1004 drm_dsc_dump_config(p, indent, &crtc_state->dsc.config); 1005 1005 + } 1006 1006 + 1007 1007 + int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) 1008 1008 + { 1009 1009 + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1010 1010 + struct intel_display *display = to_intel_display(crtc); 1011 1011 + int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); 1012 1012 + int min_cdclk; 1013 1013 + 1014 1014 + if (!crtc_state->dsc.compression_enable) 1015 1015 + return 0; 1016 1016 + 1017 1017 + /* 1018 1018 + * When we decide to use only one VDSC engine, since 1019 1019 + * each VDSC operates with 1 ppc throughput, pixel clock 1020 1020 + * cannot be higher than the VDSC clock (cdclk) 1021 1021 + * If there 2 VDSC engines, then pixel clock can't be higher than 1022 1022 + * VDSC clock(cdclk) * 2 and so on. 1023 1023 + */ 1024 1024 + min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances); 1025 1025 + 1026 1026 + if (crtc_state->joiner_pipes) { 1027 1027 + int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); 1028 1028 + 1029 1029 + /* 1030 1030 + * According to Bigjoiner bw check: 1031 1031 + * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock 1032 1032 + * 1033 1033 + * We have already computed compressed_bpp, so now compute the min CDCLK that 1034 1034 + * is required to support this compressed_bpp. 1035 1035 + * 1036 1036 + * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits) 1037 1037 + * 1038 1038 + * Since PPC = 2 with bigjoiner 1039 1039 + * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits 1040 1040 + */ 1041 1041 + int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24; 1042 1042 + int min_cdclk_bj = 1043 1043 + (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * 1044 1044 + pixel_clock) / (2 * bigjoiner_interface_bits); 1045 1045 + 1046 1046 + min_cdclk = max(min_cdclk, min_cdclk_bj); 1047 1047 + } 1048 1048 + 1049 1049 + return min_cdclk; 1018 1050 }

+1

drivers/gpu/drm/i915/display/intel_vdsc.h

reviewed

··· 31 31 const struct intel_crtc_state *crtc_state); 32 32 void intel_vdsc_state_dump(struct drm_printer *p, int indent, 33 33 const struct intel_crtc_state *crtc_state); 34 34 + int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state); 34 35 35 36 #endif /* __INTEL_VDSC_H__ */

+10 -2

drivers/gpu/drm/i915/display/intel_vdsc_regs.h

reviewed

··· 21 21 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 22 22 23 23 #define DSS_CTL2 _MMIO(0x67404) 24 24 - #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 25 25 - #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 24 24 + #define VDSC0_ENABLE REG_BIT(31) 25 25 + #define VDSC2_ENABLE REG_BIT(30) 26 26 + #define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23) 27 27 + #define VDSC1_ENABLE REG_BIT(15) 26 28 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 27 29 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 28 30 ··· 59 57 #define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4) 60 58 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 61 59 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 60 60 + #define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB 0x78970 62 61 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 63 62 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 63 63 + #define _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC 0x78A70 64 64 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 65 65 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 66 66 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) ··· 75 71 #define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ 76 72 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 77 73 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 74 74 + #define _BMG_DSC2_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ 75 75 + _BMG_DSC2_PICTURE_PARAMETER_SET_0_PB, \ 76 76 + _BMG_DSC2_PICTURE_PARAMETER_SET_0_PC) 78 77 #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) 79 78 #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) 79 79 + #define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4)) 80 80 81 81 /* PPS 0 */ 82 82 #define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23)

+1 -1

drivers/gpu/drm/i915/display/intel_vrr.c

reviewed

··· 288 288 * ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR 289 289 */ 290 290 if (IS_DISPLAY_VER(display, 12, 13)) 291 291 - intel_de_rmw(display, CHICKEN_TRANS(cpu_transcoder), 291 291 + intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), 292 292 0, PIPE_VBLANK_WITH_DELAY); 293 293 294 294 if (!intel_vrr_possible(crtc_state)) {

+146 -140

drivers/gpu/drm/i915/display/skl_scaler.c

reviewed

··· 105 105 const struct drm_format_info *format, 106 106 u64 modifier, bool need_scaler) 107 107 { 108 108 + struct intel_display *display = to_intel_display(crtc_state); 108 109 struct intel_crtc_scaler_state *scaler_state = 109 110 &crtc_state->scaler_state; 110 111 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 111 111 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 112 112 const struct drm_display_mode *adjusted_mode = 113 113 &crtc_state->hw.adjusted_mode; 114 114 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src); ··· 130 130 * Once NV12 is enabled, handle it here while allocating scaler 131 131 * for NV12. 132 132 */ 133 133 - if (DISPLAY_VER(dev_priv) >= 9 && crtc_state->hw.enable && 133 133 + if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable && 134 134 need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 135 135 - drm_dbg_kms(&dev_priv->drm, 135 135 + drm_dbg_kms(display->drm, 136 136 "Pipe/Plane scaling not supported with IF-ID mode\n"); 137 137 return -EINVAL; 138 138 } ··· 150 150 if (force_detach || !need_scaler) { 151 151 if (*scaler_id >= 0) { 152 152 scaler_state->scaler_users &= ~(1 << scaler_user); 153 153 - scaler_state->scalers[*scaler_id].in_use = 0; 153 153 + scaler_state->scalers[*scaler_id].in_use = false; 154 154 155 155 - drm_dbg_kms(&dev_priv->drm, 155 155 + drm_dbg_kms(display->drm, 156 156 "scaler_user index %u.%u: " 157 157 "Staged freeing scaler id %d scaler_users = 0x%x\n", 158 158 crtc->pipe, scaler_user, *scaler_id, ··· 164 164 165 165 if (format && intel_format_info_is_yuv_semiplanar(format, modifier) && 166 166 (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { 167 167 - drm_dbg_kms(&dev_priv->drm, 167 167 + drm_dbg_kms(display->drm, 168 168 "Planar YUV: src dimensions not met\n"); 169 169 return -EINVAL; 170 170 } ··· 174 174 min_dst_w = SKL_MIN_DST_W; 175 175 min_dst_h = SKL_MIN_DST_H; 176 176 177 177 - if (DISPLAY_VER(dev_priv) < 11) { 177 177 + if (DISPLAY_VER(display) < 11) { 178 178 max_src_w = SKL_MAX_SRC_W; 179 179 max_src_h = SKL_MAX_SRC_H; 180 180 max_dst_w = SKL_MAX_DST_W; 181 181 max_dst_h = SKL_MAX_DST_H; 182 182 - } else if (DISPLAY_VER(dev_priv) < 12) { 182 182 + } else if (DISPLAY_VER(display) < 12) { 183 183 max_src_w = ICL_MAX_SRC_W; 184 184 max_src_h = ICL_MAX_SRC_H; 185 185 max_dst_w = ICL_MAX_DST_W; 186 186 max_dst_h = ICL_MAX_DST_H; 187 187 - } else if (DISPLAY_VER(dev_priv) < 14) { 187 187 + } else if (DISPLAY_VER(display) < 14) { 188 188 max_src_w = TGL_MAX_SRC_W; 189 189 max_src_h = TGL_MAX_SRC_H; 190 190 max_dst_w = TGL_MAX_DST_W; ··· 201 201 dst_w < min_dst_w || dst_h < min_dst_h || 202 202 src_w > max_src_w || src_h > max_src_h || 203 203 dst_w > max_dst_w || dst_h > max_dst_h) { 204 204 - drm_dbg_kms(&dev_priv->drm, 204 204 + drm_dbg_kms(display->drm, 205 205 "scaler_user index %u.%u: src %ux%u dst %ux%u " 206 206 "size is out of scaler range\n", 207 207 crtc->pipe, scaler_user, src_w, src_h, ··· 218 218 * now. 219 219 */ 220 220 if (pipe_src_w > max_dst_w || pipe_src_h > max_dst_h) { 221 221 - drm_dbg_kms(&dev_priv->drm, 221 221 + drm_dbg_kms(display->drm, 222 222 "scaler_user index %u.%u: pipe src size %ux%u " 223 223 "is out of scaler range\n", 224 224 crtc->pipe, scaler_user, pipe_src_w, pipe_src_h); ··· 227 227 228 228 /* mark this plane as a scaler user in crtc_state */ 229 229 scaler_state->scaler_users |= (1 << scaler_user); 230 230 - drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: " 230 230 + drm_dbg_kms(display->drm, "scaler_user index %u.%u: " 231 231 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", 232 232 crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, 233 233 scaler_state->scaler_users); ··· 268 268 int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, 269 269 struct intel_plane_state *plane_state) 270 270 { 271 271 - struct intel_plane *intel_plane = 272 272 - to_intel_plane(plane_state->uapi.plane); 273 273 - struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); 271 271 + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 272 272 + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 274 273 struct drm_framebuffer *fb = plane_state->hw.fb; 275 274 bool force_detach = !fb || !plane_state->uapi.visible; 276 275 bool need_scaler = false; 277 276 278 277 /* Pre-gen11 and SDR planes always need a scaler for planar formats. */ 279 279 - if (!icl_is_hdr_plane(dev_priv, intel_plane->id) && 278 278 + if (!icl_is_hdr_plane(dev_priv, plane->id) && 280 279 fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 281 280 need_scaler = true; 282 281 283 282 return skl_update_scaler(crtc_state, force_detach, 284 284 - drm_plane_index(&intel_plane->base), 283 283 + drm_plane_index(&plane->base), 285 284 &plane_state->scaler_id, 286 285 drm_rect_width(&plane_state->uapi.src) >> 16, 287 286 drm_rect_height(&plane_state->uapi.src) >> 16, ··· 291 292 need_scaler); 292 293 } 293 294 295 295 + static int intel_allocate_scaler(struct intel_crtc_scaler_state *scaler_state, 296 296 + struct intel_crtc *crtc) 297 297 + { 298 298 + int i; 299 299 + 300 300 + for (i = 0; i < crtc->num_scalers; i++) { 301 301 + if (scaler_state->scalers[i].in_use) 302 302 + continue; 303 303 + 304 304 + scaler_state->scalers[i].in_use = true; 305 305 + 306 306 + return i; 307 307 + } 308 308 + 309 309 + return -1; 310 310 + } 311 311 + 294 312 static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state, 295 295 - int num_scalers_need, struct intel_crtc *intel_crtc, 313 313 + int num_scalers_need, struct intel_crtc *crtc, 296 314 const char *name, int idx, 297 315 struct intel_plane_state *plane_state, 298 316 int *scaler_id) 299 317 { 300 300 - struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); 301 301 - int j; 318 318 + struct intel_display *display = to_intel_display(crtc); 319 319 + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 302 320 u32 mode; 303 321 304 304 - if (*scaler_id < 0) { 305 305 - /* find a free scaler */ 306 306 - for (j = 0; j < intel_crtc->num_scalers; j++) { 307 307 - if (scaler_state->scalers[j].in_use) 308 308 - continue; 322 322 + if (*scaler_id < 0) 323 323 + *scaler_id = intel_allocate_scaler(scaler_state, crtc); 309 324 310 310 - *scaler_id = j; 311 311 - scaler_state->scalers[*scaler_id].in_use = 1; 312 312 - break; 313 313 - } 314 314 - } 315 315 - 316 316 - if (drm_WARN(&dev_priv->drm, *scaler_id < 0, 325 325 + if (drm_WARN(display->drm, *scaler_id < 0, 317 326 "Cannot find scaler for %s:%d\n", name, idx)) 318 327 return -EINVAL; 319 328 ··· 331 324 plane_state->hw.fb->format->num_planes > 1) { 332 325 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 333 326 334 334 - if (DISPLAY_VER(dev_priv) == 9) { 327 327 + if (DISPLAY_VER(display) == 9) { 335 328 mode = SKL_PS_SCALER_MODE_NV12; 336 329 } else if (icl_is_hdr_plane(dev_priv, plane->id)) { 337 330 /* ··· 349 342 if (linked) 350 343 mode |= PS_BINDING_Y_PLANE(linked->id); 351 344 } 352 352 - } else if (DISPLAY_VER(dev_priv) >= 10) { 345 345 + } else if (DISPLAY_VER(display) >= 10) { 353 346 mode = PS_SCALER_MODE_NORMAL; 354 354 - } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) { 347 347 + } else if (num_scalers_need == 1 && crtc->num_scalers > 1) { 355 348 /* 356 349 * when only 1 scaler is in use on a pipe with 2 scalers 357 350 * scaler 0 operates in high quality (HQ) mode. 358 351 * In this case use scaler 0 to take advantage of HQ mode 359 352 */ 360 360 - scaler_state->scalers[*scaler_id].in_use = 0; 353 353 + scaler_state->scalers[*scaler_id].in_use = false; 361 354 *scaler_id = 0; 362 362 - scaler_state->scalers[0].in_use = 1; 355 355 + scaler_state->scalers[0].in_use = true; 363 356 mode = SKL_PS_SCALER_MODE_HQ; 364 357 } else { 365 358 mode = SKL_PS_SCALER_MODE_DYN; ··· 383 376 * unnecessarily. 384 377 */ 385 378 386 386 - if (DISPLAY_VER(dev_priv) >= 14) { 379 379 + if (DISPLAY_VER(display) >= 14) { 387 380 /* 388 381 * On versions 14 and up, only the first 389 382 * scaler supports a vertical scaling factor ··· 396 389 else 397 390 max_vscale = 0x10000; 398 391 399 399 - } else if (DISPLAY_VER(dev_priv) >= 10 || 392 392 + } else if (DISPLAY_VER(display) >= 10 || 400 393 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) { 401 394 max_hscale = 0x30000 - 1; 402 395 max_vscale = 0x30000 - 1; ··· 415 408 vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale); 416 409 417 410 if (hscale < 0 || vscale < 0) { 418 418 - drm_dbg_kms(&dev_priv->drm, 411 411 + drm_dbg_kms(display->drm, 419 412 "Scaler %d doesn't support required plane scaling\n", 420 413 *scaler_id); 421 414 drm_rect_debug_print("src: ", src, true); ··· 425 418 } 426 419 } 427 420 428 428 - drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n", 429 429 - intel_crtc->pipe, *scaler_id, name, idx); 421 421 + drm_dbg_kms(display->drm, "Attached scaler id %u.%u to %s:%d\n", 422 422 + crtc->pipe, *scaler_id, name, idx); 430 423 scaler_state->scalers[*scaler_id].mode = mode; 431 424 432 425 return 0; 433 426 } 434 427 428 428 + static int setup_crtc_scaler(struct intel_atomic_state *state, 429 429 + struct intel_crtc *crtc) 430 430 + { 431 431 + struct intel_crtc_state *crtc_state = 432 432 + intel_atomic_get_new_crtc_state(state, crtc); 433 433 + struct intel_crtc_scaler_state *scaler_state = 434 434 + &crtc_state->scaler_state; 435 435 + 436 436 + return intel_atomic_setup_scaler(scaler_state, 437 437 + hweight32(scaler_state->scaler_users), 438 438 + crtc, "CRTC", crtc->base.base.id, 439 439 + NULL, &scaler_state->scaler_id); 440 440 + } 441 441 + 442 442 + static int setup_plane_scaler(struct intel_atomic_state *state, 443 443 + struct intel_crtc *crtc, 444 444 + struct intel_plane *plane) 445 445 + { 446 446 + struct intel_display *display = to_intel_display(state); 447 447 + struct intel_crtc_state *crtc_state = 448 448 + intel_atomic_get_new_crtc_state(state, crtc); 449 449 + struct intel_crtc_scaler_state *scaler_state = 450 450 + &crtc_state->scaler_state; 451 451 + struct intel_plane_state *plane_state; 452 452 + 453 453 + /* plane on different crtc cannot be a scaler user of this crtc */ 454 454 + if (drm_WARN_ON(display->drm, plane->pipe != crtc->pipe)) 455 455 + return 0; 456 456 + 457 457 + plane_state = intel_atomic_get_new_plane_state(state, plane); 458 458 + 459 459 + /* 460 460 + * GLK+ scalers don't have a HQ mode so it 461 461 + * isn't necessary to change between HQ and dyn mode 462 462 + * on those platforms. 463 463 + */ 464 464 + if (!plane_state && DISPLAY_VER(display) >= 10) 465 465 + return 0; 466 466 + 467 467 + plane_state = intel_atomic_get_plane_state(state, plane); 468 468 + if (IS_ERR(plane_state)) 469 469 + return PTR_ERR(plane_state); 470 470 + 471 471 + return intel_atomic_setup_scaler(scaler_state, 472 472 + hweight32(scaler_state->scaler_users), 473 473 + crtc, "PLANE", plane->base.base.id, 474 474 + plane_state, &plane_state->scaler_id); 475 475 + } 476 476 + 435 477 /** 436 478 * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests 437 437 - * @dev_priv: i915 device 438 438 - * @intel_crtc: intel crtc 439 439 - * @crtc_state: incoming crtc_state to validate and setup scalers 479 479 + * @state: atomic state 480 480 + * @crtc: crtc 440 481 * 441 482 * This function sets up scalers based on staged scaling requests for 442 483 * a @crtc and its planes. It is called from crtc level check path. If request ··· 497 442 * 0 - scalers were setup successfully 498 443 * error code - otherwise 499 444 */ 500 500 - int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, 501 501 - struct intel_crtc *intel_crtc, 502 502 - struct intel_crtc_state *crtc_state) 445 445 + int intel_atomic_setup_scalers(struct intel_atomic_state *state, 446 446 + struct intel_crtc *crtc) 503 447 { 504 504 - struct drm_plane *plane = NULL; 505 505 - struct intel_plane *intel_plane; 448 448 + struct intel_display *display = to_intel_display(crtc); 449 449 + struct intel_crtc_state *crtc_state = 450 450 + intel_atomic_get_new_crtc_state(state, crtc); 506 451 struct intel_crtc_scaler_state *scaler_state = 507 452 &crtc_state->scaler_state; 508 508 - struct drm_atomic_state *drm_state = crtc_state->uapi.state; 509 509 - struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state); 510 453 int num_scalers_need; 511 454 int i; 512 455 ··· 523 470 */ 524 471 525 472 /* fail if required scalers > available scalers */ 526 526 - if (num_scalers_need > intel_crtc->num_scalers) { 527 527 - drm_dbg_kms(&dev_priv->drm, 473 473 + if (num_scalers_need > crtc->num_scalers) { 474 474 + drm_dbg_kms(display->drm, 528 475 "Too many scaling requests %d > %d\n", 529 529 - num_scalers_need, intel_crtc->num_scalers); 476 476 + num_scalers_need, crtc->num_scalers); 530 477 return -EINVAL; 531 478 } 532 479 533 480 /* walkthrough scaler_users bits and start assigning scalers */ 534 481 for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) { 535 535 - struct intel_plane_state *plane_state = NULL; 536 536 - int *scaler_id; 537 537 - const char *name; 538 538 - int idx, ret; 482 482 + int ret; 539 483 540 484 /* skip if scaler not required */ 541 485 if (!(scaler_state->scaler_users & (1 << i))) 542 486 continue; 543 487 544 488 if (i == SKL_CRTC_INDEX) { 545 545 - name = "CRTC"; 546 546 - idx = intel_crtc->base.base.id; 547 547 - 548 548 - /* panel fitter case: assign as a crtc scaler */ 549 549 - scaler_id = &scaler_state->scaler_id; 489 489 + ret = setup_crtc_scaler(state, crtc); 490 490 + if (ret) 491 491 + return ret; 550 492 } else { 551 551 - name = "PLANE"; 493 493 + struct intel_plane *plane = 494 494 + to_intel_plane(drm_plane_from_index(display->drm, i)); 552 495 553 553 - /* plane scaler case: assign as a plane scaler */ 554 554 - /* find the plane that set the bit as scaler_user */ 555 555 - plane = drm_state->planes[i].ptr; 556 556 - 557 557 - /* 558 558 - * to enable/disable hq mode, add planes that are using scaler 559 559 - * into this transaction 560 560 - */ 561 561 - if (!plane) { 562 562 - struct drm_plane_state *state; 563 563 - 564 564 - /* 565 565 - * GLK+ scalers don't have a HQ mode so it 566 566 - * isn't necessary to change between HQ and dyn mode 567 567 - * on those platforms. 568 568 - */ 569 569 - if (DISPLAY_VER(dev_priv) >= 10) 570 570 - continue; 571 571 - 572 572 - plane = drm_plane_from_index(&dev_priv->drm, i); 573 573 - state = drm_atomic_get_plane_state(drm_state, plane); 574 574 - if (IS_ERR(state)) { 575 575 - drm_dbg_kms(&dev_priv->drm, 576 576 - "Failed to add [PLANE:%d] to drm_state\n", 577 577 - plane->base.id); 578 578 - return PTR_ERR(state); 579 579 - } 580 580 - } 581 581 - 582 582 - intel_plane = to_intel_plane(plane); 583 583 - idx = plane->base.id; 584 584 - 585 585 - /* plane on different crtc cannot be a scaler user of this crtc */ 586 586 - if (drm_WARN_ON(&dev_priv->drm, 587 587 - intel_plane->pipe != intel_crtc->pipe)) 588 588 - continue; 589 589 - 590 590 - plane_state = intel_atomic_get_new_plane_state(intel_state, 591 591 - intel_plane); 592 592 - scaler_id = &plane_state->scaler_id; 496 496 + ret = setup_plane_scaler(state, crtc, plane); 497 497 + if (ret) 498 498 + return ret; 593 499 } 594 594 - 595 595 - ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need, 596 596 - intel_crtc, name, idx, 597 597 - plane_state, scaler_id); 598 598 - if (ret < 0) 599 599 - return ret; 600 500 } 601 501 602 502 return 0; ··· 602 596 * 603 597 */ 604 598 605 605 - static void glk_program_nearest_filter_coefs(struct drm_i915_private *dev_priv, 599 599 + static void glk_program_nearest_filter_coefs(struct intel_display *display, 606 600 enum pipe pipe, int id, int set) 607 601 { 608 602 int i; 609 603 610 610 - intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 604 604 + intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(pipe, id, set), 611 605 PS_COEF_INDEX_AUTO_INC); 612 606 613 607 for (i = 0; i < 17 * 7; i += 2) { ··· 620 614 t = glk_coef_tap(i + 1); 621 615 tmp |= glk_nearest_filter_coef(t) << 16; 622 616 623 623 - intel_de_write_fw(dev_priv, GLK_PS_COEF_DATA_SET(pipe, id, set), 617 617 + intel_de_write_fw(display, GLK_PS_COEF_DATA_SET(pipe, id, set), 624 618 tmp); 625 619 } 626 620 627 627 - intel_de_write_fw(dev_priv, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); 621 621 + intel_de_write_fw(display, GLK_PS_COEF_INDEX_SET(pipe, id, set), 0); 628 622 } 629 623 630 624 static u32 skl_scaler_get_filter_select(enum drm_scaling_filter filter, int set) ··· 640 634 return PS_FILTER_MEDIUM; 641 635 } 642 636 643 643 - static void skl_scaler_setup_filter(struct drm_i915_private *dev_priv, enum pipe pipe, 637 637 + static void skl_scaler_setup_filter(struct intel_display *display, enum pipe pipe, 644 638 int id, int set, enum drm_scaling_filter filter) 645 639 { 646 640 switch (filter) { 647 641 case DRM_SCALING_FILTER_DEFAULT: 648 642 break; 649 643 case DRM_SCALING_FILTER_NEAREST_NEIGHBOR: 650 650 - glk_program_nearest_filter_coefs(dev_priv, pipe, id, set); 644 644 + glk_program_nearest_filter_coefs(display, pipe, id, set); 651 645 break; 652 646 default: 653 647 MISSING_CASE(filter); ··· 656 650 657 651 void skl_pfit_enable(const struct intel_crtc_state *crtc_state) 658 652 { 653 653 + struct intel_display *display = to_intel_display(crtc_state); 659 654 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 660 660 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 661 655 const struct intel_crtc_scaler_state *scaler_state = 662 656 &crtc_state->scaler_state; 663 657 const struct drm_rect *dst = &crtc_state->pch_pfit.dst; ··· 675 669 if (!crtc_state->pch_pfit.enabled) 676 670 return; 677 671 678 678 - if (drm_WARN_ON(&dev_priv->drm, 672 672 + if (drm_WARN_ON(display->drm, 679 673 crtc_state->scaler_state.scaler_id < 0)) 680 674 return; 681 675 ··· 694 688 ps_ctrl = PS_SCALER_EN | PS_BINDING_PIPE | scaler_state->scalers[id].mode | 695 689 skl_scaler_get_filter_select(crtc_state->hw.scaling_filter, 0); 696 690 697 697 - skl_scaler_setup_filter(dev_priv, pipe, id, 0, 691 691 + skl_scaler_setup_filter(display, pipe, id, 0, 698 692 crtc_state->hw.scaling_filter); 699 693 700 700 - intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), ps_ctrl); 694 694 + intel_de_write_fw(display, SKL_PS_CTRL(pipe, id), ps_ctrl); 701 695 702 702 - intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), 696 696 + intel_de_write_fw(display, SKL_PS_VPHASE(pipe, id), 703 697 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 704 704 - intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), 698 698 + intel_de_write_fw(display, SKL_PS_HPHASE(pipe, id), 705 699 PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 706 706 - intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id), 700 700 + intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, id), 707 701 PS_WIN_XPOS(x) | PS_WIN_YPOS(y)); 708 708 - intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id), 702 702 + intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, id), 709 703 PS_WIN_XSIZE(width) | PS_WIN_YSIZE(height)); 710 704 } 711 705 ··· 714 708 const struct intel_crtc_state *crtc_state, 715 709 const struct intel_plane_state *plane_state) 716 710 { 711 711 + struct intel_display *display = to_intel_display(plane); 717 712 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 718 713 const struct drm_framebuffer *fb = plane_state->hw.fb; 719 714 enum pipe pipe = plane->pipe; ··· 758 751 ps_ctrl = PS_SCALER_EN | PS_BINDING_PLANE(plane->id) | scaler->mode | 759 752 skl_scaler_get_filter_select(plane_state->hw.scaling_filter, 0); 760 753 761 761 - skl_scaler_setup_filter(dev_priv, pipe, scaler_id, 0, 754 754 + skl_scaler_setup_filter(display, pipe, scaler_id, 0, 762 755 plane_state->hw.scaling_filter); 763 756 764 764 - intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); 765 765 - intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id), 757 757 + intel_de_write_fw(display, SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); 758 758 + intel_de_write_fw(display, SKL_PS_VPHASE(pipe, scaler_id), 766 759 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 767 767 - intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id), 760 760 + intel_de_write_fw(display, SKL_PS_HPHASE(pipe, scaler_id), 768 761 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 769 769 - intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id), 762 762 + intel_de_write_fw(display, SKL_PS_WIN_POS(pipe, scaler_id), 770 763 PS_WIN_XPOS(crtc_x) | PS_WIN_YPOS(crtc_y)); 771 771 - intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id), 764 764 + intel_de_write_fw(display, SKL_PS_WIN_SZ(pipe, scaler_id), 772 765 PS_WIN_XSIZE(crtc_w) | PS_WIN_YSIZE(crtc_h)); 773 766 } 774 767 775 768 static void skl_detach_scaler(struct intel_crtc *crtc, int id) 776 769 { 777 777 - struct drm_device *dev = crtc->base.dev; 778 778 - struct drm_i915_private *dev_priv = to_i915(dev); 770 770 + struct intel_display *display = to_intel_display(crtc); 779 771 780 780 - intel_de_write_fw(dev_priv, SKL_PS_CTRL(crtc->pipe, id), 0); 781 781 - intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(crtc->pipe, id), 0); 782 782 - intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, id), 0); 772 772 + intel_de_write_fw(display, SKL_PS_CTRL(crtc->pipe, id), 0); 773 773 + intel_de_write_fw(display, SKL_PS_WIN_POS(crtc->pipe, id), 0); 774 774 + intel_de_write_fw(display, SKL_PS_WIN_SZ(crtc->pipe, id), 0); 783 775 } 784 776 785 777 /* ··· 809 803 810 804 void skl_scaler_get_config(struct intel_crtc_state *crtc_state) 811 805 { 806 806 + struct intel_display *display = to_intel_display(crtc_state); 812 807 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 813 813 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 814 808 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; 815 809 int id = -1; 816 810 int i; ··· 819 813 for (i = 0; i < crtc->num_scalers; i++) { 820 814 u32 ctl, pos, size; 821 815 822 822 - ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); 816 816 + ctl = intel_de_read(display, SKL_PS_CTRL(crtc->pipe, i)); 823 817 if ((ctl & (PS_SCALER_EN | PS_BINDING_MASK)) != (PS_SCALER_EN | PS_BINDING_PIPE)) 824 818 continue; 825 819 826 820 id = i; 827 821 crtc_state->pch_pfit.enabled = true; 828 822 829 829 - pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)); 830 830 - size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)); 823 823 + pos = intel_de_read(display, SKL_PS_WIN_POS(crtc->pipe, i)); 824 824 + size = intel_de_read(display, SKL_PS_WIN_SZ(crtc->pipe, i)); 831 825 832 826 drm_rect_init(&crtc_state->pch_pfit.dst, 833 827 REG_FIELD_GET(PS_WIN_XPOS_MASK, pos),

+3 -8

drivers/gpu/drm/i915/display/skl_scaler.h

reviewed

··· 5 5 #ifndef INTEL_SCALER_H 6 6 #define INTEL_SCALER_H 7 7 8 8 - #include <linux/types.h> 9 9 - 10 10 - enum drm_scaling_filter; 11 11 - enum pipe; 12 12 - struct drm_i915_private; 8 8 + struct intel_atomic_state; 13 9 struct intel_crtc; 14 10 struct intel_crtc_state; 15 11 struct intel_plane; ··· 16 20 int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, 17 21 struct intel_plane_state *plane_state); 18 22 19 19 - int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, 20 20 - struct intel_crtc *intel_crtc, 21 21 - struct intel_crtc_state *crtc_state); 23 23 + int intel_atomic_setup_scalers(struct intel_atomic_state *state, 24 24 + struct intel_crtc *crtc); 22 25 23 26 void skl_pfit_enable(const struct intel_crtc_state *crtc_state); 24 27

+14 -11

drivers/gpu/drm/i915/display/skl_universal_plane.c

reviewed

··· 239 239 240 240 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) 241 241 { 242 242 - if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) 242 242 + struct intel_display *display = &i915->display; 243 243 + 244 244 + if (DISPLAY_VER(display) >= 13 || HAS_D12_PLANE_MINIMIZATION(display)) 243 245 return BIT(PLANE_4) | BIT(PLANE_5); 244 246 else 245 247 return BIT(PLANE_6) | BIT(PLANE_7); ··· 736 734 const struct intel_crtc_state *crtc_state) 737 735 { 738 736 struct intel_display *display = to_intel_display(plane->base.dev); 739 739 - struct drm_i915_private *i915 = to_i915(plane->base.dev); 740 737 enum plane_id plane_id = plane->id; 741 738 enum pipe pipe = plane->pipe; 742 739 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; ··· 745 744 &crtc_state->wm.skl.plane_ddb_y[plane_id]; 746 745 int level; 747 746 748 748 - for (level = 0; level < i915->display.wm.num_levels; level++) 747 747 + for (level = 0; level < display->wm.num_levels; level++) 749 748 intel_de_write_dsb(display, dsb, PLANE_WM(pipe, plane_id, level), 750 749 skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); 751 750 752 751 intel_de_write_dsb(display, dsb, PLANE_WM_TRANS(pipe, plane_id), 753 752 skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); 754 753 755 755 - if (HAS_HW_SAGV_WM(i915)) { 754 754 + if (HAS_HW_SAGV_WM(display)) { 756 755 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; 757 756 758 757 intel_de_write_dsb(display, dsb, PLANE_WM_SAGV(pipe, plane_id), ··· 764 763 intel_de_write_dsb(display, dsb, PLANE_BUF_CFG(pipe, plane_id), 765 764 skl_plane_ddb_reg_val(ddb)); 766 765 767 767 - if (DISPLAY_VER(i915) < 11) 766 766 + if (DISPLAY_VER(display) < 11) 768 767 intel_de_write_dsb(display, dsb, PLANE_NV12_BUF_CFG(pipe, plane_id), 769 768 skl_plane_ddb_reg_val(ddb_y)); 770 769 } ··· 2549 2548 static u8 skl_get_plane_caps(struct drm_i915_private *i915, 2550 2549 enum pipe pipe, enum plane_id plane_id) 2551 2550 { 2551 2551 + struct intel_display *display = &i915->display; 2552 2552 u8 caps = INTEL_PLANE_CAP_TILING_X; 2553 2553 2554 2554 - if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915)) 2554 2554 + if (DISPLAY_VER(display) < 13 || display->platform.alderlake_p) 2555 2555 caps |= INTEL_PLANE_CAP_TILING_Y; 2556 2556 - if (DISPLAY_VER(i915) < 12) 2556 2556 + if (DISPLAY_VER(display) < 12) 2557 2557 caps |= INTEL_PLANE_CAP_TILING_Yf; 2558 2558 - if (HAS_4TILE(i915)) 2558 2558 + if (HAS_4TILE(display)) 2559 2559 caps |= INTEL_PLANE_CAP_TILING_4; 2560 2560 2561 2561 if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(i915)) ··· 2564 2562 2565 2563 if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) { 2566 2564 caps |= INTEL_PLANE_CAP_CCS_RC; 2567 2567 - if (DISPLAY_VER(i915) >= 12) 2565 2565 + if (DISPLAY_VER(display) >= 12) 2568 2566 caps |= INTEL_PLANE_CAP_CCS_RC_CC; 2569 2567 } 2570 2568 2571 2569 if (tgl_plane_has_mc_ccs(i915, plane_id)) 2572 2570 caps |= INTEL_PLANE_CAP_CCS_MC; 2573 2571 2574 2574 - if (DISPLAY_VER(i915) >= 14 && IS_DGFX(i915)) 2572 2572 + if (DISPLAY_VER(display) >= 14 && display->platform.dgfx) 2575 2573 caps |= INTEL_PLANE_CAP_NEED64K_PHYS; 2576 2574 2577 2575 return caps; ··· 2745 2743 skl_get_initial_plane_config(struct intel_crtc *crtc, 2746 2744 struct intel_initial_plane_config *plane_config) 2747 2745 { 2746 2746 + struct intel_display *display = to_intel_display(crtc); 2748 2747 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); 2749 2748 struct drm_device *dev = crtc->base.dev; 2750 2749 struct drm_i915_private *dev_priv = to_i915(dev); ··· 2827 2824 fb->modifier = I915_FORMAT_MOD_Y_TILED; 2828 2825 break; 2829 2826 case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */ 2830 2830 - if (HAS_4TILE(dev_priv)) { 2827 2827 + if (HAS_4TILE(display)) { 2831 2828 u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE | 2832 2829 PLANE_CTL_CLEAR_COLOR_DISABLE; 2833 2830

+397 -327

drivers/gpu/drm/i915/display/skl_watermark.c

reviewed

··· 77 77 bool 78 78 intel_has_sagv(struct drm_i915_private *i915) 79 79 { 80 80 - return HAS_SAGV(i915) && 81 81 - i915->display.sagv.status != I915_SAGV_NOT_CONTROLLED; 80 80 + struct intel_display *display = &i915->display; 81 81 + 82 82 + return HAS_SAGV(display) && display->sagv.status != I915_SAGV_NOT_CONTROLLED; 82 83 } 83 84 84 85 static u32 85 86 intel_sagv_block_time(struct drm_i915_private *i915) 86 87 { 87 87 - if (DISPLAY_VER(i915) >= 14) { 88 88 + struct intel_display *display = &i915->display; 89 89 + 90 90 + if (DISPLAY_VER(display) >= 14) { 88 91 u32 val; 89 92 90 90 - val = intel_de_read(i915, MTL_LATENCY_SAGV); 93 93 + val = intel_de_read(display, MTL_LATENCY_SAGV); 91 94 92 95 return REG_FIELD_GET(MTL_LATENCY_QCLK_SAGV, val); 93 93 - } else if (DISPLAY_VER(i915) >= 12) { 96 96 + } else if (DISPLAY_VER(display) >= 12) { 94 97 u32 val = 0; 95 98 int ret; 96 99 ··· 101 98 GEN12_PCODE_READ_SAGV_BLOCK_TIME_US, 102 99 &val, NULL); 103 100 if (ret) { 104 104 - drm_dbg_kms(&i915->drm, "Couldn't read SAGV block time!\n"); 101 101 + drm_dbg_kms(display->drm, "Couldn't read SAGV block time!\n"); 105 102 return 0; 106 103 } 107 104 108 105 return val; 109 109 - } else if (DISPLAY_VER(i915) == 11) { 106 106 + } else if (DISPLAY_VER(display) == 11) { 110 107 return 10; 111 111 - } else if (HAS_SAGV(i915)) { 108 108 + } else if (HAS_SAGV(display)) { 112 109 return 30; 113 110 } else { 114 111 return 0; ··· 117 114 118 115 static void intel_sagv_init(struct drm_i915_private *i915) 119 116 { 120 120 - if (!HAS_SAGV(i915)) 121 121 - i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; 117 117 + struct intel_display *display = &i915->display; 118 118 + 119 119 + if (!HAS_SAGV(display)) 120 120 + display->sagv.status = I915_SAGV_NOT_CONTROLLED; 122 121 123 122 /* 124 123 * Probe to see if we have working SAGV control. 125 124 * For icl+ this was already determined by intel_bw_init_hw(). 126 125 */ 127 127 - if (DISPLAY_VER(i915) < 11) 126 126 + if (DISPLAY_VER(display) < 11) 128 127 skl_sagv_disable(i915); 129 128 130 130 - drm_WARN_ON(&i915->drm, i915->display.sagv.status == I915_SAGV_UNKNOWN); 129 129 + drm_WARN_ON(display->drm, display->sagv.status == I915_SAGV_UNKNOWN); 131 130 132 132 - i915->display.sagv.block_time_us = intel_sagv_block_time(i915); 131 131 + display->sagv.block_time_us = intel_sagv_block_time(i915); 133 132 134 134 - drm_dbg_kms(&i915->drm, "SAGV supported: %s, original SAGV block time: %u us\n", 135 135 - str_yes_no(intel_has_sagv(i915)), i915->display.sagv.block_time_us); 133 133 + drm_dbg_kms(display->drm, "SAGV supported: %s, original SAGV block time: %u us\n", 134 134 + str_yes_no(intel_has_sagv(i915)), display->sagv.block_time_us); 136 135 137 136 /* avoid overflow when adding with wm0 latency/etc. */ 138 138 - if (drm_WARN(&i915->drm, i915->display.sagv.block_time_us > U16_MAX, 137 137 + if (drm_WARN(display->drm, display->sagv.block_time_us > U16_MAX, 139 138 "Excessive SAGV block time %u, ignoring\n", 140 140 - i915->display.sagv.block_time_us)) 141 141 - i915->display.sagv.block_time_us = 0; 139 139 + display->sagv.block_time_us)) 140 140 + display->sagv.block_time_us = 0; 142 141 143 142 if (!intel_has_sagv(i915)) 144 144 - i915->display.sagv.block_time_us = 0; 143 143 + display->sagv.block_time_us = 0; 145 144 } 146 145 147 146 /* ··· 449 444 450 445 static int intel_compute_sagv_mask(struct intel_atomic_state *state) 451 446 { 447 447 + struct intel_display *display = to_intel_display(state); 452 448 struct drm_i915_private *i915 = to_i915(state->base.dev); 453 449 int ret; 454 450 struct intel_crtc *crtc; ··· 485 479 * other crtcs can't be allowed to use the more optimal 486 480 * normal (ie. non-SAGV) watermarks. 487 481 */ 488 488 - pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(i915) && 482 482 + pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(display) && 489 483 DISPLAY_VER(i915) >= 12 && 490 484 intel_crtc_can_enable_sagv(new_crtc_state); 491 485 ··· 2502 2496 static int 2503 2497 skl_compute_ddb(struct intel_atomic_state *state) 2504 2498 { 2499 2499 + struct intel_display *display = to_intel_display(state); 2505 2500 struct drm_i915_private *i915 = to_i915(state->base.dev); 2506 2501 const struct intel_dbuf_state *old_dbuf_state; 2507 2502 struct intel_dbuf_state *new_dbuf_state = NULL; ··· 2531 2524 return ret; 2532 2525 } 2533 2526 2534 2534 - if (HAS_MBUS_JOINING(i915)) { 2527 2527 + if (HAS_MBUS_JOINING(display)) { 2535 2528 new_dbuf_state->joined_mbus = 2536 2529 adlp_check_mbus_joined(new_dbuf_state->active_pipes); 2537 2530 ··· 2749 2742 const struct skl_pipe_wm *old_pipe_wm, 2750 2743 const struct skl_pipe_wm *new_pipe_wm) 2751 2744 { 2752 2752 - struct drm_i915_private *i915 = to_i915(plane->base.dev); 2745 2745 + struct intel_display *display = to_intel_display(plane); 2753 2746 int level; 2754 2747 2755 2755 - for (level = 0; level < i915->display.wm.num_levels; level++) { 2748 2748 + for (level = 0; level < display->wm.num_levels; level++) { 2756 2749 /* 2757 2750 * We don't check uv_wm as the hardware doesn't actually 2758 2751 * use it. It only gets used for calculating the required ··· 2763 2756 return false; 2764 2757 } 2765 2758 2766 2766 - if (HAS_HW_SAGV_WM(i915)) { 2759 2759 + if (HAS_HW_SAGV_WM(display)) { 2767 2760 const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id]; 2768 2761 const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id]; 2769 2762 ··· 2854 2847 * Program DEEP PKG_C_LATENCY Pkg C with all 1's. 2855 2848 * Program PKG_C_LATENCY Added Wake Time = 0 2856 2849 */ 2857 2857 - static void 2858 2858 - skl_program_dpkgc_latency(struct drm_i915_private *i915, bool enable_dpkgc) 2850 2850 + void 2851 2851 + intel_program_dpkgc_latency(struct intel_atomic_state *state) 2859 2852 { 2860 2860 - u32 max_latency = 0; 2861 2861 - u32 clear = 0, val = 0; 2853 2853 + struct intel_display *display = to_intel_display(state); 2854 2854 + struct drm_i915_private *i915 = to_i915(display->drm); 2855 2855 + struct intel_crtc *crtc; 2856 2856 + struct intel_crtc_state *new_crtc_state; 2857 2857 + u32 latency = LNL_PKG_C_LATENCY_MASK; 2862 2858 u32 added_wake_time = 0; 2859 2859 + u32 max_linetime = 0; 2860 2860 + u32 clear, val; 2861 2861 + bool fixed_refresh_rate = false; 2862 2862 + int i; 2863 2863 2864 2864 - if (DISPLAY_VER(i915) < 20) 2864 2864 + if (DISPLAY_VER(display) < 20) 2865 2865 return; 2866 2866 2867 2867 - if (enable_dpkgc) { 2868 2868 - max_latency = skl_watermark_max_latency(i915, 1); 2869 2869 - if (max_latency == 0) 2870 2870 - max_latency = LNL_PKG_C_LATENCY_MASK; 2871 2871 - added_wake_time = DSB_EXE_TIME + 2872 2872 - i915->display.sagv.block_time_us; 2873 2873 - } else { 2874 2874 - max_latency = LNL_PKG_C_LATENCY_MASK; 2875 2875 - added_wake_time = 0; 2867 2867 + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2868 2868 + if (!new_crtc_state->vrr.enable || 2869 2869 + (new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax && 2870 2870 + new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline)) 2871 2871 + fixed_refresh_rate = true; 2872 2872 + 2873 2873 + max_linetime = max(new_crtc_state->linetime, max_linetime); 2876 2874 } 2877 2875 2878 2878 - clear |= LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; 2879 2879 - val |= REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, max_latency); 2880 2880 - val |= REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time); 2876 2876 + if (fixed_refresh_rate) { 2877 2877 + latency = skl_watermark_max_latency(i915, 1); 2878 2878 + /* Wa_22020299601 */ 2879 2879 + if ((latency && max_linetime) && 2880 2880 + (DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30)) { 2881 2881 + latency = max_linetime * DIV_ROUND_UP(latency, max_linetime); 2882 2882 + } else if (!latency) { 2883 2883 + latency = LNL_PKG_C_LATENCY_MASK; 2884 2884 + } 2881 2885 2882 2882 - intel_uncore_rmw(&i915->uncore, LNL_PKG_C_LATENCY, clear, val); 2886 2886 + added_wake_time = DSB_EXE_TIME + 2887 2887 + display->sagv.block_time_us; 2888 2888 + } 2889 2889 + 2890 2890 + clear = LNL_ADDED_WAKE_TIME_MASK | LNL_PKG_C_LATENCY_MASK; 2891 2891 + val = REG_FIELD_PREP(LNL_PKG_C_LATENCY_MASK, latency) | 2892 2892 + REG_FIELD_PREP(LNL_ADDED_WAKE_TIME_MASK, added_wake_time); 2893 2893 + 2894 2894 + intel_de_rmw(display, LNL_PKG_C_LATENCY, clear, val); 2883 2895 } 2884 2896 2885 2897 static int ··· 2907 2881 struct intel_crtc *crtc; 2908 2882 struct intel_crtc_state __maybe_unused *new_crtc_state; 2909 2883 int ret, i; 2910 2910 - bool enable_dpkgc = false; 2911 2884 2912 2885 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { 2913 2886 ret = skl_build_pipe_wm(state, crtc); ··· 2931 2906 ret = skl_wm_add_affected_planes(state, crtc); 2932 2907 if (ret) 2933 2908 return ret; 2934 2934 - 2935 2935 - if ((new_crtc_state->vrr.vmin == new_crtc_state->vrr.vmax && 2936 2936 - new_crtc_state->vrr.vmin == new_crtc_state->vrr.flipline) || 2937 2937 - !new_crtc_state->vrr.enable) 2938 2938 - enable_dpkgc = true; 2939 2909 } 2940 2940 - 2941 2941 - skl_program_dpkgc_latency(to_i915(state->base.dev), enable_dpkgc); 2942 2910 2943 2911 skl_print_wm_changes(state); 2944 2912 ··· 2949 2931 static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, 2950 2932 struct skl_pipe_wm *out) 2951 2933 { 2934 2934 + struct intel_display *display = to_intel_display(crtc); 2952 2935 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 2953 2936 enum pipe pipe = crtc->pipe; 2954 2937 enum plane_id plane_id; ··· 2975 2956 2976 2957 skl_wm_level_from_reg_val(val, &wm->trans_wm); 2977 2958 2978 2978 - if (HAS_HW_SAGV_WM(i915)) { 2959 2959 + if (HAS_HW_SAGV_WM(display)) { 2979 2960 if (plane_id != PLANE_CURSOR) 2980 2961 val = intel_de_read(i915, PLANE_WM_SAGV(pipe, plane_id)); 2981 2962 else ··· 3003 2984 to_intel_dbuf_state(i915->display.dbuf.obj.state); 3004 2985 struct intel_crtc *crtc; 3005 2986 3006 3006 - if (HAS_MBUS_JOINING(i915)) 2987 2987 + if (HAS_MBUS_JOINING(display)) 3007 2988 dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN; 3008 2989 3009 2990 dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw); ··· 3065 3046 } 3066 3047 3067 3048 dbuf_state->enabled_slices = i915->display.dbuf.enabled_slices; 3068 3068 - } 3069 3069 - 3070 3070 - static bool skl_dbuf_is_misconfigured(struct drm_i915_private *i915) 3071 3071 - { 3072 3072 - const struct intel_dbuf_state *dbuf_state = 3073 3073 - to_intel_dbuf_state(i915->display.dbuf.obj.state); 3074 3074 - struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 3075 3075 - struct intel_crtc *crtc; 3076 3076 - 3077 3077 - for_each_intel_crtc(&i915->drm, crtc) { 3078 3078 - const struct intel_crtc_state *crtc_state = 3079 3079 - to_intel_crtc_state(crtc->base.state); 3080 3080 - 3081 3081 - entries[crtc->pipe] = crtc_state->wm.skl.ddb; 3082 3082 - } 3083 3083 - 3084 3084 - for_each_intel_crtc(&i915->drm, crtc) { 3085 3085 - const struct intel_crtc_state *crtc_state = 3086 3086 - to_intel_crtc_state(crtc->base.state); 3087 3087 - u8 slices; 3088 3088 - 3089 3089 - slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, 3090 3090 - dbuf_state->joined_mbus); 3091 3091 - if (dbuf_state->slices[crtc->pipe] & ~slices) 3092 3092 - return true; 3093 3093 - 3094 3094 - if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries, 3095 3095 - I915_MAX_PIPES, crtc->pipe)) 3096 3096 - return true; 3097 3097 - } 3098 3098 - 3099 3099 - return false; 3100 3100 - } 3101 3101 - 3102 3102 - static void skl_wm_sanitize(struct drm_i915_private *i915) 3103 3103 - { 3104 3104 - struct intel_crtc *crtc; 3105 3105 - 3106 3106 - /* 3107 3107 - * On TGL/RKL (at least) the BIOS likes to assign the planes 3108 3108 - * to the wrong DBUF slices. This will cause an infinite loop 3109 3109 - * in skl_commit_modeset_enables() as it can't find a way to 3110 3110 - * transition between the old bogus DBUF layout to the new 3111 3111 - * proper DBUF layout without DBUF allocation overlaps between 3112 3112 - * the planes (which cannot be allowed or else the hardware 3113 3113 - * may hang). If we detect a bogus DBUF layout just turn off 3114 3114 - * all the planes so that skl_commit_modeset_enables() can 3115 3115 - * simply ignore them. 3116 3116 - */ 3117 3117 - if (!skl_dbuf_is_misconfigured(i915)) 3118 3118 - return; 3119 3119 - 3120 3120 - drm_dbg_kms(&i915->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n"); 3121 3121 - 3122 3122 - for_each_intel_crtc(&i915->drm, crtc) { 3123 3123 - struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3124 3124 - const struct intel_plane_state *plane_state = 3125 3125 - to_intel_plane_state(plane->base.state); 3126 3126 - struct intel_crtc_state *crtc_state = 3127 3127 - to_intel_crtc_state(crtc->base.state); 3128 3128 - 3129 3129 - if (plane_state->uapi.visible) 3130 3130 - intel_plane_disable_noatomic(crtc, plane); 3131 3131 - 3132 3132 - drm_WARN_ON(&i915->drm, crtc_state->active_planes != 0); 3133 3133 - 3134 3134 - memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); 3135 3135 - } 3136 3136 - } 3137 3137 - 3138 3138 - static void skl_wm_get_hw_state_and_sanitize(struct drm_i915_private *i915) 3139 3139 - { 3140 3140 - skl_wm_get_hw_state(i915); 3141 3141 - skl_wm_sanitize(i915); 3142 3142 - } 3143 3143 - 3144 3144 - void intel_wm_state_verify(struct intel_atomic_state *state, 3145 3145 - struct intel_crtc *crtc) 3146 3146 - { 3147 3147 - struct drm_i915_private *i915 = to_i915(state->base.dev); 3148 3148 - const struct intel_crtc_state *new_crtc_state = 3149 3149 - intel_atomic_get_new_crtc_state(state, crtc); 3150 3150 - struct skl_hw_state { 3151 3151 - struct skl_ddb_entry ddb[I915_MAX_PLANES]; 3152 3152 - struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 3153 3153 - struct skl_pipe_wm wm; 3154 3154 - } *hw; 3155 3155 - const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 3156 3156 - struct intel_plane *plane; 3157 3157 - u8 hw_enabled_slices; 3158 3158 - int level; 3159 3159 - 3160 3160 - if (DISPLAY_VER(i915) < 9 || !new_crtc_state->hw.active) 3161 3161 - return; 3162 3162 - 3163 3163 - hw = kzalloc(sizeof(*hw), GFP_KERNEL); 3164 3164 - if (!hw) 3165 3165 - return; 3166 3166 - 3167 3167 - skl_pipe_wm_get_hw_state(crtc, &hw->wm); 3168 3168 - 3169 3169 - skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); 3170 3170 - 3171 3171 - hw_enabled_slices = intel_enabled_dbuf_slices_mask(i915); 3172 3172 - 3173 3173 - if (DISPLAY_VER(i915) >= 11 && 3174 3174 - hw_enabled_slices != i915->display.dbuf.enabled_slices) 3175 3175 - drm_err(&i915->drm, 3176 3176 - "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 3177 3177 - i915->display.dbuf.enabled_slices, 3178 3178 - hw_enabled_slices); 3179 3179 - 3180 3180 - for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 3181 3181 - const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 3182 3182 - const struct skl_wm_level *hw_wm_level, *sw_wm_level; 3183 3183 - 3184 3184 - /* Watermarks */ 3185 3185 - for (level = 0; level < i915->display.wm.num_levels; level++) { 3186 3186 - hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 3187 3187 - sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 3188 3188 - 3189 3189 - if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 3190 3190 - continue; 3191 3191 - 3192 3192 - drm_err(&i915->drm, 3193 3193 - "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3194 3194 - plane->base.base.id, plane->base.name, level, 3195 3195 - sw_wm_level->enable, 3196 3196 - sw_wm_level->blocks, 3197 3197 - sw_wm_level->lines, 3198 3198 - hw_wm_level->enable, 3199 3199 - hw_wm_level->blocks, 3200 3200 - hw_wm_level->lines); 3201 3201 - } 3202 3202 - 3203 3203 - hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 3204 3204 - sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 3205 3205 - 3206 3206 - if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3207 3207 - drm_err(&i915->drm, 3208 3208 - "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3209 3209 - plane->base.base.id, plane->base.name, 3210 3210 - sw_wm_level->enable, 3211 3211 - sw_wm_level->blocks, 3212 3212 - sw_wm_level->lines, 3213 3213 - hw_wm_level->enable, 3214 3214 - hw_wm_level->blocks, 3215 3215 - hw_wm_level->lines); 3216 3216 - } 3217 3217 - 3218 3218 - hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 3219 3219 - sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 3220 3220 - 3221 3221 - if (HAS_HW_SAGV_WM(i915) && 3222 3222 - !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3223 3223 - drm_err(&i915->drm, 3224 3224 - "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3225 3225 - plane->base.base.id, plane->base.name, 3226 3226 - sw_wm_level->enable, 3227 3227 - sw_wm_level->blocks, 3228 3228 - sw_wm_level->lines, 3229 3229 - hw_wm_level->enable, 3230 3230 - hw_wm_level->blocks, 3231 3231 - hw_wm_level->lines); 3232 3232 - } 3233 3233 - 3234 3234 - hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 3235 3235 - sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 3236 3236 - 3237 3237 - if (HAS_HW_SAGV_WM(i915) && 3238 3238 - !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3239 3239 - drm_err(&i915->drm, 3240 3240 - "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3241 3241 - plane->base.base.id, plane->base.name, 3242 3242 - sw_wm_level->enable, 3243 3243 - sw_wm_level->blocks, 3244 3244 - sw_wm_level->lines, 3245 3245 - hw_wm_level->enable, 3246 3246 - hw_wm_level->blocks, 3247 3247 - hw_wm_level->lines); 3248 3248 - } 3249 3249 - 3250 3250 - /* DDB */ 3251 3251 - hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 3252 3252 - sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 3253 3253 - 3254 3254 - if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 3255 3255 - drm_err(&i915->drm, 3256 3256 - "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 3257 3257 - plane->base.base.id, plane->base.name, 3258 3258 - sw_ddb_entry->start, sw_ddb_entry->end, 3259 3259 - hw_ddb_entry->start, hw_ddb_entry->end); 3260 3260 - } 3261 3261 - } 3262 3262 - 3263 3263 - kfree(hw); 3264 3049 } 3265 3050 3266 3051 bool skl_watermark_ipc_enabled(struct drm_i915_private *i915) ··· 3209 3386 3210 3387 static void skl_setup_wm_latency(struct drm_i915_private *i915) 3211 3388 { 3212 3212 - if (HAS_HW_SAGV_WM(i915)) 3213 3213 - i915->display.wm.num_levels = 6; 3389 3389 + struct intel_display *display = &i915->display; 3390 3390 + 3391 3391 + if (HAS_HW_SAGV_WM(display)) 3392 3392 + display->wm.num_levels = 6; 3214 3393 else 3215 3215 - i915->display.wm.num_levels = 8; 3394 3394 + display->wm.num_levels = 8; 3216 3395 3217 3217 - if (DISPLAY_VER(i915) >= 14) 3218 3218 - mtl_read_wm_latency(i915, i915->display.wm.skl_latency); 3396 3396 + if (DISPLAY_VER(display) >= 14) 3397 3397 + mtl_read_wm_latency(i915, display->wm.skl_latency); 3219 3398 else 3220 3220 - skl_read_wm_latency(i915, i915->display.wm.skl_latency); 3399 3399 + skl_read_wm_latency(i915, display->wm.skl_latency); 3221 3400 3222 3222 - intel_print_wm_latency(i915, "Gen9 Plane", i915->display.wm.skl_latency); 3223 3223 - } 3224 3224 - 3225 3225 - static const struct intel_wm_funcs skl_wm_funcs = { 3226 3226 - .compute_global_watermarks = skl_compute_wm, 3227 3227 - .get_hw_state = skl_wm_get_hw_state_and_sanitize, 3228 3228 - }; 3229 3229 - 3230 3230 - void skl_wm_init(struct drm_i915_private *i915) 3231 3231 - { 3232 3232 - intel_sagv_init(i915); 3233 3233 - 3234 3234 - skl_setup_wm_latency(i915); 3235 3235 - 3236 3236 - i915->display.funcs.wm = &skl_wm_funcs; 3401 3401 + intel_print_wm_latency(i915, "Gen9 Plane", display->wm.skl_latency); 3237 3402 } 3238 3403 3239 3404 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj) ··· 3277 3466 { 3278 3467 switch (pipe) { 3279 3468 case PIPE_A: 3280 3280 - return !(active_pipes & BIT(PIPE_D)); 3281 3469 case PIPE_D: 3282 3282 - return !(active_pipes & BIT(PIPE_A)); 3470 3470 + active_pipes &= BIT(PIPE_A) | BIT(PIPE_D); 3471 3471 + break; 3283 3472 case PIPE_B: 3284 3284 - return !(active_pipes & BIT(PIPE_C)); 3285 3473 case PIPE_C: 3286 3286 - return !(active_pipes & BIT(PIPE_B)); 3474 3474 + active_pipes &= BIT(PIPE_B) | BIT(PIPE_C); 3475 3475 + break; 3287 3476 default: /* to suppress compiler warning */ 3288 3477 MISSING_CASE(pipe); 3289 3289 - break; 3478 3478 + return false; 3290 3479 } 3291 3480 3292 3292 - return false; 3481 3481 + return is_power_of_2(active_pipes); 3293 3482 } 3294 3483 3295 3295 - static void intel_mbus_dbox_update(struct intel_atomic_state *state) 3484 3484 + static u32 pipe_mbus_dbox_ctl(const struct intel_crtc *crtc, 3485 3485 + const struct intel_dbuf_state *dbuf_state) 3296 3486 { 3297 3297 - struct drm_i915_private *i915 = to_i915(state->base.dev); 3298 3298 - const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; 3299 3299 - const struct intel_crtc *crtc; 3487 3487 + struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3300 3488 u32 val = 0; 3301 3301 - 3302 3302 - if (DISPLAY_VER(i915) < 11) 3303 3303 - return; 3304 3304 - 3305 3305 - new_dbuf_state = intel_atomic_get_new_dbuf_state(state); 3306 3306 - old_dbuf_state = intel_atomic_get_old_dbuf_state(state); 3307 3307 - if (!new_dbuf_state || 3308 3308 - (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus && 3309 3309 - new_dbuf_state->active_pipes == old_dbuf_state->active_pipes)) 3310 3310 - return; 3311 3489 3312 3490 if (DISPLAY_VER(i915) >= 14) 3313 3491 val |= MBUS_DBOX_I_CREDIT(2); ··· 3308 3508 } 3309 3509 3310 3510 if (DISPLAY_VER(i915) >= 14) 3311 3311 - val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(12) : 3312 3312 - MBUS_DBOX_A_CREDIT(8); 3511 3511 + val |= dbuf_state->joined_mbus ? 3512 3512 + MBUS_DBOX_A_CREDIT(12) : MBUS_DBOX_A_CREDIT(8); 3313 3513 else if (IS_ALDERLAKE_P(i915)) 3314 3514 /* Wa_22010947358:adl-p */ 3315 3315 - val |= new_dbuf_state->joined_mbus ? MBUS_DBOX_A_CREDIT(6) : 3316 3316 - MBUS_DBOX_A_CREDIT(4); 3515 3515 + val |= dbuf_state->joined_mbus ? 3516 3516 + MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4); 3317 3517 else 3318 3518 val |= MBUS_DBOX_A_CREDIT(2); 3319 3519 ··· 3330 3530 val |= MBUS_DBOX_B_CREDIT(8); 3331 3531 } 3332 3532 3333 3333 - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) { 3334 3334 - u32 pipe_val = val; 3335 3335 - 3336 3336 - if (DISPLAY_VERx100(i915) == 1400) { 3337 3337 - if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, 3338 3338 - new_dbuf_state->active_pipes)) 3339 3339 - pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL; 3340 3340 - else 3341 3341 - pipe_val |= MBUS_DBOX_BW_4CREDITS_MTL; 3342 3342 - } 3343 3343 - 3344 3344 - intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), pipe_val); 3533 3533 + if (DISPLAY_VERx100(i915) == 1400) { 3534 3534 + if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, dbuf_state->active_pipes)) 3535 3535 + val |= MBUS_DBOX_BW_8CREDITS_MTL; 3536 3536 + else 3537 3537 + val |= MBUS_DBOX_BW_4CREDITS_MTL; 3345 3538 } 3539 3539 + 3540 3540 + return val; 3541 3541 + } 3542 3542 + 3543 3543 + static void pipe_mbus_dbox_ctl_update(struct drm_i915_private *i915, 3544 3544 + const struct intel_dbuf_state *dbuf_state) 3545 3545 + { 3546 3546 + struct intel_crtc *crtc; 3547 3547 + 3548 3548 + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, dbuf_state->active_pipes) 3549 3549 + intel_de_write(i915, PIPE_MBUS_DBOX_CTL(crtc->pipe), 3550 3550 + pipe_mbus_dbox_ctl(crtc, dbuf_state)); 3551 3551 + } 3552 3552 + 3553 3553 + static void intel_mbus_dbox_update(struct intel_atomic_state *state) 3554 3554 + { 3555 3555 + struct drm_i915_private *i915 = to_i915(state->base.dev); 3556 3556 + const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state; 3557 3557 + 3558 3558 + if (DISPLAY_VER(i915) < 11) 3559 3559 + return; 3560 3560 + 3561 3561 + new_dbuf_state = intel_atomic_get_new_dbuf_state(state); 3562 3562 + old_dbuf_state = intel_atomic_get_old_dbuf_state(state); 3563 3563 + if (!new_dbuf_state || 3564 3564 + (new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus && 3565 3565 + new_dbuf_state->active_pipes == old_dbuf_state->active_pipes)) 3566 3566 + return; 3567 3567 + 3568 3568 + pipe_mbus_dbox_ctl_update(i915, new_dbuf_state); 3346 3569 } 3347 3570 3348 3571 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state, ··· 3385 3562 void intel_dbuf_mdclk_cdclk_ratio_update(struct drm_i915_private *i915, 3386 3563 int ratio, bool joined_mbus) 3387 3564 { 3565 3565 + struct intel_display *display = &i915->display; 3388 3566 enum dbuf_slice slice; 3389 3567 3390 3390 - if (!HAS_MBUS_JOINING(i915)) 3568 3568 + if (!HAS_MBUS_JOINING(display)) 3391 3569 return; 3392 3570 3393 3393 - if (DISPLAY_VER(i915) >= 20) 3394 3394 - intel_de_rmw(i915, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK, 3571 3571 + if (DISPLAY_VER(display) >= 20) 3572 3572 + intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK, 3395 3573 MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1)); 3396 3574 3397 3575 if (joined_mbus) 3398 3576 ratio *= 2; 3399 3577 3400 3400 - drm_dbg_kms(&i915->drm, "Updating dbuf ratio to %d (mbus joined: %s)\n", 3578 3578 + drm_dbg_kms(display->drm, "Updating dbuf ratio to %d (mbus joined: %s)\n", 3401 3579 ratio, str_yes_no(joined_mbus)); 3402 3580 3403 3403 - for_each_dbuf_slice(i915, slice) 3404 3404 - intel_de_rmw(i915, DBUF_CTL_S(slice), 3581 3581 + for_each_dbuf_slice(display, slice) 3582 3582 + intel_de_rmw(display, DBUF_CTL_S(slice), 3405 3583 DBUF_MIN_TRACKER_STATE_SERVICE_MASK, 3406 3584 DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1)); 3407 3585 } ··· 3449 3625 return INVALID_PIPE; 3450 3626 } 3451 3627 3452 3452 - static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state, 3453 3453 - enum pipe pipe) 3628 3628 + static void mbus_ctl_join_update(struct drm_i915_private *i915, 3629 3629 + const struct intel_dbuf_state *dbuf_state, 3630 3630 + enum pipe pipe) 3454 3631 { 3455 3455 - struct drm_i915_private *i915 = to_i915(state->base.dev); 3456 3456 - const struct intel_dbuf_state *old_dbuf_state = 3457 3457 - intel_atomic_get_old_dbuf_state(state); 3458 3458 - const struct intel_dbuf_state *new_dbuf_state = 3459 3459 - intel_atomic_get_new_dbuf_state(state); 3460 3632 u32 mbus_ctl; 3461 3633 3462 3462 - drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n", 3463 3463 - str_yes_no(old_dbuf_state->joined_mbus), 3464 3464 - str_yes_no(new_dbuf_state->joined_mbus), 3465 3465 - pipe != INVALID_PIPE ? pipe_name(pipe) : '*'); 3466 3466 - 3467 3467 - if (new_dbuf_state->joined_mbus) 3634 3634 + if (dbuf_state->joined_mbus) 3468 3635 mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN; 3469 3636 else 3470 3637 mbus_ctl = MBUS_HASHING_MODE_2x2; ··· 3468 3653 intel_de_rmw(i915, MBUS_CTL, 3469 3654 MBUS_HASHING_MODE_MASK | MBUS_JOIN | 3470 3655 MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl); 3656 3656 + } 3657 3657 + 3658 3658 + static void intel_dbuf_mbus_join_update(struct intel_atomic_state *state, 3659 3659 + enum pipe pipe) 3660 3660 + { 3661 3661 + struct drm_i915_private *i915 = to_i915(state->base.dev); 3662 3662 + const struct intel_dbuf_state *old_dbuf_state = 3663 3663 + intel_atomic_get_old_dbuf_state(state); 3664 3664 + const struct intel_dbuf_state *new_dbuf_state = 3665 3665 + intel_atomic_get_new_dbuf_state(state); 3666 3666 + 3667 3667 + drm_dbg_kms(&i915->drm, "Changing mbus joined: %s -> %s (pipe: %c)\n", 3668 3668 + str_yes_no(old_dbuf_state->joined_mbus), 3669 3669 + str_yes_no(new_dbuf_state->joined_mbus), 3670 3670 + pipe != INVALID_PIPE ? pipe_name(pipe) : '*'); 3671 3671 + 3672 3672 + mbus_ctl_join_update(i915, new_dbuf_state, pipe); 3471 3673 } 3472 3674 3473 3675 void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state) ··· 3589 3757 gen9_dbuf_slices_update(i915, new_slices); 3590 3758 } 3591 3759 3760 3760 + static void skl_mbus_sanitize(struct drm_i915_private *i915) 3761 3761 + { 3762 3762 + struct intel_display *display = &i915->display; 3763 3763 + struct intel_dbuf_state *dbuf_state = 3764 3764 + to_intel_dbuf_state(display->dbuf.obj.state); 3765 3765 + 3766 3766 + if (!HAS_MBUS_JOINING(display)) 3767 3767 + return; 3768 3768 + 3769 3769 + if (!dbuf_state->joined_mbus || 3770 3770 + adlp_check_mbus_joined(dbuf_state->active_pipes)) 3771 3771 + return; 3772 3772 + 3773 3773 + drm_dbg_kms(display->drm, "Disabling redundant MBUS joining (active pipes 0x%x)\n", 3774 3774 + dbuf_state->active_pipes); 3775 3775 + 3776 3776 + dbuf_state->joined_mbus = false; 3777 3777 + intel_dbuf_mdclk_cdclk_ratio_update(i915, 3778 3778 + dbuf_state->mdclk_cdclk_ratio, 3779 3779 + dbuf_state->joined_mbus); 3780 3780 + pipe_mbus_dbox_ctl_update(i915, dbuf_state); 3781 3781 + mbus_ctl_join_update(i915, dbuf_state, INVALID_PIPE); 3782 3782 + } 3783 3783 + 3784 3784 + static bool skl_dbuf_is_misconfigured(struct drm_i915_private *i915) 3785 3785 + { 3786 3786 + const struct intel_dbuf_state *dbuf_state = 3787 3787 + to_intel_dbuf_state(i915->display.dbuf.obj.state); 3788 3788 + struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; 3789 3789 + struct intel_crtc *crtc; 3790 3790 + 3791 3791 + for_each_intel_crtc(&i915->drm, crtc) { 3792 3792 + const struct intel_crtc_state *crtc_state = 3793 3793 + to_intel_crtc_state(crtc->base.state); 3794 3794 + 3795 3795 + entries[crtc->pipe] = crtc_state->wm.skl.ddb; 3796 3796 + } 3797 3797 + 3798 3798 + for_each_intel_crtc(&i915->drm, crtc) { 3799 3799 + const struct intel_crtc_state *crtc_state = 3800 3800 + to_intel_crtc_state(crtc->base.state); 3801 3801 + u8 slices; 3802 3802 + 3803 3803 + slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, 3804 3804 + dbuf_state->joined_mbus); 3805 3805 + if (dbuf_state->slices[crtc->pipe] & ~slices) 3806 3806 + return true; 3807 3807 + 3808 3808 + if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.ddb, entries, 3809 3809 + I915_MAX_PIPES, crtc->pipe)) 3810 3810 + return true; 3811 3811 + } 3812 3812 + 3813 3813 + return false; 3814 3814 + } 3815 3815 + 3816 3816 + static void skl_dbuf_sanitize(struct drm_i915_private *i915) 3817 3817 + { 3818 3818 + struct intel_crtc *crtc; 3819 3819 + 3820 3820 + /* 3821 3821 + * On TGL/RKL (at least) the BIOS likes to assign the planes 3822 3822 + * to the wrong DBUF slices. This will cause an infinite loop 3823 3823 + * in skl_commit_modeset_enables() as it can't find a way to 3824 3824 + * transition between the old bogus DBUF layout to the new 3825 3825 + * proper DBUF layout without DBUF allocation overlaps between 3826 3826 + * the planes (which cannot be allowed or else the hardware 3827 3827 + * may hang). If we detect a bogus DBUF layout just turn off 3828 3828 + * all the planes so that skl_commit_modeset_enables() can 3829 3829 + * simply ignore them. 3830 3830 + */ 3831 3831 + if (!skl_dbuf_is_misconfigured(i915)) 3832 3832 + return; 3833 3833 + 3834 3834 + drm_dbg_kms(&i915->drm, "BIOS has misprogrammed the DBUF, disabling all planes\n"); 3835 3835 + 3836 3836 + for_each_intel_crtc(&i915->drm, crtc) { 3837 3837 + struct intel_plane *plane = to_intel_plane(crtc->base.primary); 3838 3838 + const struct intel_plane_state *plane_state = 3839 3839 + to_intel_plane_state(plane->base.state); 3840 3840 + struct intel_crtc_state *crtc_state = 3841 3841 + to_intel_crtc_state(crtc->base.state); 3842 3842 + 3843 3843 + if (plane_state->uapi.visible) 3844 3844 + intel_plane_disable_noatomic(crtc, plane); 3845 3845 + 3846 3846 + drm_WARN_ON(&i915->drm, crtc_state->active_planes != 0); 3847 3847 + 3848 3848 + memset(&crtc_state->wm.skl.ddb, 0, sizeof(crtc_state->wm.skl.ddb)); 3849 3849 + } 3850 3850 + } 3851 3851 + 3852 3852 + static void skl_wm_get_hw_state_and_sanitize(struct drm_i915_private *i915) 3853 3853 + { 3854 3854 + skl_wm_get_hw_state(i915); 3855 3855 + 3856 3856 + skl_mbus_sanitize(i915); 3857 3857 + skl_dbuf_sanitize(i915); 3858 3858 + } 3859 3859 + 3860 3860 + void intel_wm_state_verify(struct intel_atomic_state *state, 3861 3861 + struct intel_crtc *crtc) 3862 3862 + { 3863 3863 + struct intel_display *display = to_intel_display(state); 3864 3864 + struct drm_i915_private *i915 = to_i915(state->base.dev); 3865 3865 + const struct intel_crtc_state *new_crtc_state = 3866 3866 + intel_atomic_get_new_crtc_state(state, crtc); 3867 3867 + struct skl_hw_state { 3868 3868 + struct skl_ddb_entry ddb[I915_MAX_PLANES]; 3869 3869 + struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; 3870 3870 + struct skl_pipe_wm wm; 3871 3871 + } *hw; 3872 3872 + const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal; 3873 3873 + struct intel_plane *plane; 3874 3874 + u8 hw_enabled_slices; 3875 3875 + int level; 3876 3876 + 3877 3877 + if (DISPLAY_VER(i915) < 9 || !new_crtc_state->hw.active) 3878 3878 + return; 3879 3879 + 3880 3880 + hw = kzalloc(sizeof(*hw), GFP_KERNEL); 3881 3881 + if (!hw) 3882 3882 + return; 3883 3883 + 3884 3884 + skl_pipe_wm_get_hw_state(crtc, &hw->wm); 3885 3885 + 3886 3886 + skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y); 3887 3887 + 3888 3888 + hw_enabled_slices = intel_enabled_dbuf_slices_mask(i915); 3889 3889 + 3890 3890 + if (DISPLAY_VER(i915) >= 11 && 3891 3891 + hw_enabled_slices != i915->display.dbuf.enabled_slices) 3892 3892 + drm_err(&i915->drm, 3893 3893 + "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", 3894 3894 + i915->display.dbuf.enabled_slices, 3895 3895 + hw_enabled_slices); 3896 3896 + 3897 3897 + for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { 3898 3898 + const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; 3899 3899 + const struct skl_wm_level *hw_wm_level, *sw_wm_level; 3900 3900 + 3901 3901 + /* Watermarks */ 3902 3902 + for (level = 0; level < i915->display.wm.num_levels; level++) { 3903 3903 + hw_wm_level = &hw->wm.planes[plane->id].wm[level]; 3904 3904 + sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level); 3905 3905 + 3906 3906 + if (skl_wm_level_equals(hw_wm_level, sw_wm_level)) 3907 3907 + continue; 3908 3908 + 3909 3909 + drm_err(&i915->drm, 3910 3910 + "[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3911 3911 + plane->base.base.id, plane->base.name, level, 3912 3912 + sw_wm_level->enable, 3913 3913 + sw_wm_level->blocks, 3914 3914 + sw_wm_level->lines, 3915 3915 + hw_wm_level->enable, 3916 3916 + hw_wm_level->blocks, 3917 3917 + hw_wm_level->lines); 3918 3918 + } 3919 3919 + 3920 3920 + hw_wm_level = &hw->wm.planes[plane->id].trans_wm; 3921 3921 + sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id); 3922 3922 + 3923 3923 + if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3924 3924 + drm_err(&i915->drm, 3925 3925 + "[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3926 3926 + plane->base.base.id, plane->base.name, 3927 3927 + sw_wm_level->enable, 3928 3928 + sw_wm_level->blocks, 3929 3929 + sw_wm_level->lines, 3930 3930 + hw_wm_level->enable, 3931 3931 + hw_wm_level->blocks, 3932 3932 + hw_wm_level->lines); 3933 3933 + } 3934 3934 + 3935 3935 + hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0; 3936 3936 + sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0; 3937 3937 + 3938 3938 + if (HAS_HW_SAGV_WM(display) && 3939 3939 + !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3940 3940 + drm_err(&i915->drm, 3941 3941 + "[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3942 3942 + plane->base.base.id, plane->base.name, 3943 3943 + sw_wm_level->enable, 3944 3944 + sw_wm_level->blocks, 3945 3945 + sw_wm_level->lines, 3946 3946 + hw_wm_level->enable, 3947 3947 + hw_wm_level->blocks, 3948 3948 + hw_wm_level->lines); 3949 3949 + } 3950 3950 + 3951 3951 + hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm; 3952 3952 + sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm; 3953 3953 + 3954 3954 + if (HAS_HW_SAGV_WM(display) && 3955 3955 + !skl_wm_level_equals(hw_wm_level, sw_wm_level)) { 3956 3956 + drm_err(&i915->drm, 3957 3957 + "[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", 3958 3958 + plane->base.base.id, plane->base.name, 3959 3959 + sw_wm_level->enable, 3960 3960 + sw_wm_level->blocks, 3961 3961 + sw_wm_level->lines, 3962 3962 + hw_wm_level->enable, 3963 3963 + hw_wm_level->blocks, 3964 3964 + hw_wm_level->lines); 3965 3965 + } 3966 3966 + 3967 3967 + /* DDB */ 3968 3968 + hw_ddb_entry = &hw->ddb[PLANE_CURSOR]; 3969 3969 + sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR]; 3970 3970 + 3971 3971 + if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { 3972 3972 + drm_err(&i915->drm, 3973 3973 + "[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n", 3974 3974 + plane->base.base.id, plane->base.name, 3975 3975 + sw_ddb_entry->start, sw_ddb_entry->end, 3976 3976 + hw_ddb_entry->start, hw_ddb_entry->end); 3977 3977 + } 3978 3978 + } 3979 3979 + 3980 3980 + kfree(hw); 3981 3981 + } 3982 3982 + 3983 3983 + static const struct intel_wm_funcs skl_wm_funcs = { 3984 3984 + .compute_global_watermarks = skl_compute_wm, 3985 3985 + .get_hw_state = skl_wm_get_hw_state_and_sanitize, 3986 3986 + }; 3987 3987 + 3988 3988 + void skl_wm_init(struct drm_i915_private *i915) 3989 3989 + { 3990 3990 + intel_sagv_init(i915); 3991 3991 + 3992 3992 + skl_setup_wm_latency(i915); 3993 3993 + 3994 3994 + i915->display.funcs.wm = &skl_wm_funcs; 3995 3995 + } 3996 3996 + 3592 3997 static int skl_watermark_ipc_status_show(struct seq_file *m, void *data) 3593 3998 { 3594 3999 struct drm_i915_private *i915 = m->private; ··· 3899 3830 3900 3831 void skl_watermark_debugfs_register(struct drm_i915_private *i915) 3901 3832 { 3902 3902 - struct drm_minor *minor = i915->drm.primary; 3833 3833 + struct intel_display *display = &i915->display; 3834 3834 + struct drm_minor *minor = display->drm->primary; 3903 3835 3904 3904 - if (HAS_IPC(i915)) 3836 3836 + if (HAS_IPC(display)) 3905 3837 debugfs_create_file("i915_ipc_status", 0644, minor->debugfs_root, i915, 3906 3838 &skl_watermark_ipc_status_fops); 3907 3839 3908 3908 - if (HAS_SAGV(i915)) 3840 3840 + if (HAS_SAGV(display)) 3909 3841 debugfs_create_file("i915_sagv_status", 0444, minor->debugfs_root, i915, 3910 3842 &intel_sagv_status_fops); 3911 3843 }

+1

drivers/gpu/drm/i915/display/skl_watermark.h

reviewed

··· 87 87 int ratio, bool joined_mbus); 88 88 void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state); 89 89 void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state); 90 90 + void intel_program_dpkgc_latency(struct intel_atomic_state *state); 90 91 91 92 #endif /* __SKL_WATERMARK_H__ */ 92 93

+26 -2

drivers/gpu/drm/i915/display/vlv_dsi.c

reviewed

··· 67 67 (bpp * burst_mode_ratio)); 68 68 } 69 69 70 70 - enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 70 70 + static enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 71 71 { 72 72 - /* It just so happens the VBT matches register contents. */ 73 72 switch (fmt) { 74 73 case VID_MODE_FORMAT_RGB888: 75 74 return MIPI_DSI_FMT_RGB888; ··· 1757 1758 intel_dsi->clk_hs_to_lp_count += extra_byte_count; 1758 1759 1759 1760 intel_dsi_log_params(intel_dsi); 1761 1761 + } 1762 1762 + 1763 1763 + int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state) 1764 1764 + { 1765 1765 + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 1766 1766 + 1767 1767 + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1768 1768 + return 0; 1769 1769 + 1770 1770 + /* 1771 1771 + * On Valleyview some DSI panels lose (v|h)sync when the clock is lower 1772 1772 + * than 320000KHz. 1773 1773 + */ 1774 1774 + if (IS_VALLEYVIEW(dev_priv)) 1775 1775 + return 320000; 1776 1776 + 1777 1777 + /* 1778 1778 + * On Geminilake once the CDCLK gets as low as 79200 1779 1779 + * picture gets unstable, despite that values are 1780 1780 + * correct for DSI PLL and DE PLL. 1781 1781 + */ 1782 1782 + if (IS_GEMINILAKE(dev_priv)) 1783 1783 + return 158400; 1784 1784 + 1785 1785 + return 0; 1760 1786 } 1761 1787 1762 1788 typedef void (*vlv_dsi_dmi_quirk_func)(struct intel_dsi *intel_dsi);

+3 -4

drivers/gpu/drm/i915/display/vlv_dsi.h

reviewed

··· 6 6 #ifndef __VLV_DSI_H__ 7 7 #define __VLV_DSI_H__ 8 8 9 9 - #include <linux/types.h> 10 10 - 11 9 enum port; 12 10 struct drm_i915_private; 11 11 + struct intel_crtc_state; 13 12 struct intel_dsi; 14 13 15 14 #ifdef I915 16 15 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port); 17 17 - enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt); 16 16 + int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state); 18 17 void vlv_dsi_init(struct drm_i915_private *dev_priv); 19 18 #else 20 19 static inline void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) 21 20 { 22 21 } 23 23 - static inline enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) 22 22 + static inline int vlv_dsi_min_cdclk(const struct intel_crtc_state *crtc_state) 24 23 { 25 24 return 0; 26 25 }

+1 -3

drivers/gpu/drm/i915/gem/i915_gem_object.h

reviewed

··· 283 283 static inline bool 284 284 i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj) 285 285 { 286 286 - /* TODO: make DPT shrinkable when it has no bound vmas */ 287 287 - return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE) && 288 288 - !obj->is_dpt; 286 286 + return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE); 289 287 } 290 288 291 289 static inline bool

+14 -5

drivers/gpu/drm/i915/gt/intel_ggtt.c

reviewed

··· 107 107 /** 108 108 * i915_ggtt_suspend_vm - Suspend the memory mappings for a GGTT or DPT VM 109 109 * @vm: The VM to suspend the mappings for 110 110 + * @evict_all: Evict all VMAs 110 111 * 111 112 * Suspend the memory mappings for all objects mapped to HW via the GGTT or a 112 113 * DPT page table. 113 114 */ 114 114 - void i915_ggtt_suspend_vm(struct i915_address_space *vm) 115 115 + void i915_ggtt_suspend_vm(struct i915_address_space *vm, bool evict_all) 115 116 { 116 117 struct i915_vma *vma, *vn; 117 118 int save_skip_rewrite; ··· 158 157 goto retry; 159 158 } 160 159 161 161 - if (!i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND)) { 160 160 + if (evict_all || !i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND)) { 162 161 i915_vma_wait_for_bind(vma); 163 162 164 163 __i915_vma_evict(vma, false); ··· 173 172 vm->skip_pte_rewrite = save_skip_rewrite; 174 173 175 174 mutex_unlock(&vm->mutex); 175 175 + 176 176 + drm_WARN_ON(&vm->i915->drm, evict_all && !list_empty(&vm->bound_list)); 176 177 } 177 178 178 179 void i915_ggtt_suspend(struct i915_ggtt *ggtt) 179 180 { 180 181 struct intel_gt *gt; 181 182 182 182 - i915_ggtt_suspend_vm(&ggtt->vm); 183 183 + i915_ggtt_suspend_vm(&ggtt->vm, false); 183 184 ggtt->invalidate(ggtt); 184 185 185 186 list_for_each_entry(gt, &ggtt->gt_list, ggtt_link) ··· 1548 1545 /** 1549 1546 * i915_ggtt_resume_vm - Restore the memory mappings for a GGTT or DPT VM 1550 1547 * @vm: The VM to restore the mappings for 1548 1548 + * @all_evicted: Were all VMAs expected to be evicted on suspend? 1551 1549 * 1552 1550 * Restore the memory mappings for all objects mapped to HW via the GGTT or a 1553 1551 * DPT page table. ··· 1556 1552 * Returns %true if restoring the mapping for any object that was in a write 1557 1553 * domain before suspend. 1558 1554 */ 1559 1559 - bool i915_ggtt_resume_vm(struct i915_address_space *vm) 1555 1555 + bool i915_ggtt_resume_vm(struct i915_address_space *vm, bool all_evicted) 1560 1556 { 1561 1557 struct i915_vma *vma; 1562 1558 bool write_domain_objs = false; 1563 1559 1564 1560 drm_WARN_ON(&vm->i915->drm, !vm->is_ggtt && !vm->is_dpt); 1561 1561 + 1562 1562 + if (all_evicted) { 1563 1563 + drm_WARN_ON(&vm->i915->drm, !list_empty(&vm->bound_list)); 1564 1564 + return false; 1565 1565 + } 1565 1566 1566 1567 /* First fill our portion of the GTT with scratch pages */ 1567 1568 vm->clear_range(vm, 0, vm->total); ··· 1607 1598 list_for_each_entry(gt, &ggtt->gt_list, ggtt_link) 1608 1599 intel_gt_check_and_clear_faults(gt); 1609 1600 1610 1610 - flush = i915_ggtt_resume_vm(&ggtt->vm); 1601 1601 + flush = i915_ggtt_resume_vm(&ggtt->vm, false); 1611 1602 1612 1603 if (drm_mm_node_allocated(&ggtt->error_capture)) 1613 1604 ggtt->vm.scratch_range(&ggtt->vm, ggtt->error_capture.start,

+2 -2

drivers/gpu/drm/i915/gt/intel_gtt.h

reviewed

··· 608 608 struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt, 609 609 unsigned long lmem_pt_obj_flags); 610 610 611 611 - void i915_ggtt_suspend_vm(struct i915_address_space *vm); 612 612 - bool i915_ggtt_resume_vm(struct i915_address_space *vm); 611 611 + void i915_ggtt_suspend_vm(struct i915_address_space *vm, bool evict_all); 612 612 + bool i915_ggtt_resume_vm(struct i915_address_space *vm, bool all_evicted); 613 613 void i915_ggtt_suspend(struct i915_ggtt *gtt); 614 614 void i915_ggtt_resume(struct i915_ggtt *ggtt); 615 615

+2 -1

drivers/gpu/drm/i915/gt/intel_reset.c

reviewed

··· 1198 1198 intel_engine_mask_t stalled_mask, 1199 1199 const char *reason) 1200 1200 { 1201 1201 + struct intel_display *display = &gt->i915->display; 1201 1202 intel_engine_mask_t awake; 1202 1203 int ret; 1203 1204 ··· 1244 1243 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display) 1245 1244 intel_irq_resume(gt->i915); 1246 1245 1247 1247 - intel_overlay_reset(gt->i915); 1246 1246 + intel_overlay_reset(display); 1248 1247 1249 1248 /* sanitize uC after engine reset */ 1250 1249 if (!intel_uc_uses_guc_submission(&gt->uc))

+1

drivers/gpu/drm/i915/gvt/display.c

reviewed

··· 40 40 41 41 #include "display/bxt_dpio_phy_regs.h" 42 42 #include "display/i9xx_plane_regs.h" 43 43 + #include "display/intel_crt_regs.h" 43 44 #include "display/intel_cursor_regs.h" 44 45 #include "display/intel_display.h" 45 46 #include "display/intel_dpio_phy.h"

+1

drivers/gpu/drm/i915/gvt/handlers.c

reviewed

··· 45 45 #include "intel_mchbar_regs.h" 46 46 #include "display/bxt_dpio_phy_regs.h" 47 47 #include "display/i9xx_plane_regs.h" 48 48 + #include "display/intel_crt_regs.h" 48 49 #include "display/intel_cursor_regs.h" 49 50 #include "display/intel_display_types.h" 50 51 #include "display/intel_dmc_regs.h"

+66 -49

drivers/gpu/drm/i915/i915_driver.c

reviewed

··· 45 45 #include <drm/drm_managed.h> 46 46 #include <drm/drm_probe_helper.h> 47 47 48 48 + #include "display/i9xx_display_sr.h" 48 49 #include "display/intel_acpi.h" 49 50 #include "display/intel_bw.h" 50 51 #include "display/intel_cdclk.h" ··· 61 60 #include "display/intel_pch_refclk.h" 62 61 #include "display/intel_pps.h" 63 62 #include "display/intel_sprite_uapi.h" 63 63 + #include "display/intel_vga.h" 64 64 #include "display/skl_watermark.h" 65 65 66 66 #include "gem/i915_gem_context.h" ··· 95 93 #include "i915_memcpy.h" 96 94 #include "i915_perf.h" 97 95 #include "i915_query.h" 98 98 - #include "i915_suspend.h" 99 96 #include "i915_switcheroo.h" 100 97 #include "i915_sysfs.h" 101 98 #include "i915_utils.h" ··· 105 104 #include "intel_pci_config.h" 106 105 #include "intel_pcode.h" 107 106 #include "intel_region_ttm.h" 107 107 + #include "intel_sbi.h" 108 108 + #include "vlv_sideband.h" 108 109 #include "vlv_suspend.h" 109 110 110 111 static const struct drm_driver i915_drm_driver; ··· 220 217 */ 221 218 static int i915_driver_early_probe(struct drm_i915_private *dev_priv) 222 219 { 220 220 + struct intel_display *display = &dev_priv->display; 223 221 int ret = 0; 224 222 225 223 if (i915_inject_probe_failure(dev_priv)) ··· 235 231 spin_lock_init(&dev_priv->irq_lock); 236 232 spin_lock_init(&dev_priv->gpu_error.lock); 237 233 234 234 + intel_sbi_init(dev_priv); 235 235 + vlv_iosf_sb_init(dev_priv); 238 236 mutex_init(&dev_priv->sb_lock); 239 239 - cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE); 240 237 241 238 i915_memcpy_init_early(dev_priv); 242 239 intel_runtime_pm_init_early(&dev_priv->runtime_pm); ··· 264 259 intel_detect_pch(dev_priv); 265 260 266 261 intel_irq_init(dev_priv); 267 267 - intel_display_driver_early_probe(dev_priv); 262 262 + intel_display_driver_early_probe(display); 268 263 intel_clock_gating_hooks_init(dev_priv); 269 264 270 265 intel_detect_preproduction_hw(dev_priv); ··· 287 282 */ 288 283 static void i915_driver_late_release(struct drm_i915_private *dev_priv) 289 284 { 285 285 + struct intel_display *display = &dev_priv->display; 286 286 + 290 287 intel_irq_fini(dev_priv); 291 291 - intel_power_domains_cleanup(dev_priv); 288 288 + intel_power_domains_cleanup(display); 292 289 i915_gem_cleanup_early(dev_priv); 293 290 intel_gt_driver_late_release_all(dev_priv); 294 291 intel_region_ttm_device_fini(dev_priv); 295 292 vlv_suspend_cleanup(dev_priv); 296 293 i915_workqueues_cleanup(dev_priv); 297 294 298 298 - cpu_latency_qos_remove_request(&dev_priv->sb_qos); 299 295 mutex_destroy(&dev_priv->sb_lock); 296 296 + vlv_iosf_sb_fini(dev_priv); 297 297 + intel_sbi_fini(dev_priv); 300 298 301 299 i915_params_free(&dev_priv->params); 302 300 } ··· 315 307 */ 316 308 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv) 317 309 { 310 310 + struct intel_display *display = &dev_priv->display; 318 311 struct intel_gt *gt; 319 312 int ret, i; 320 313 ··· 341 332 /* Try to make sure MCHBAR is enabled before poking at it */ 342 333 intel_gmch_bar_setup(dev_priv); 343 334 intel_device_info_runtime_init(dev_priv); 344 344 - intel_display_device_info_runtime_init(dev_priv); 335 335 + intel_display_device_info_runtime_init(display); 345 336 346 337 for_each_gt(gt, dev_priv, i) { 347 338 ret = intel_gt_init_mmio(gt); ··· 608 599 */ 609 600 static void i915_driver_register(struct drm_i915_private *dev_priv) 610 601 { 602 602 + struct intel_display *display = &dev_priv->display; 611 603 struct intel_gt *gt; 612 604 unsigned int i; 613 605 ··· 637 627 638 628 i915_hwmon_register(dev_priv); 639 629 640 640 - intel_display_driver_register(dev_priv); 630 630 + intel_display_driver_register(display); 641 631 642 642 - intel_power_domains_enable(dev_priv); 632 632 + intel_power_domains_enable(display); 643 633 intel_runtime_pm_enable(&dev_priv->runtime_pm); 644 634 645 635 intel_register_dsm_handler(); ··· 654 644 */ 655 645 static void i915_driver_unregister(struct drm_i915_private *dev_priv) 656 646 { 647 647 + struct intel_display *display = &dev_priv->display; 657 648 struct intel_gt *gt; 658 649 unsigned int i; 659 650 ··· 663 652 intel_unregister_dsm_handler(); 664 653 665 654 intel_runtime_pm_disable(&dev_priv->runtime_pm); 666 666 - intel_power_domains_disable(dev_priv); 655 655 + intel_power_domains_disable(display); 667 656 668 668 - intel_display_driver_unregister(dev_priv); 657 657 + intel_display_driver_unregister(display); 669 658 670 659 intel_pxp_fini(dev_priv); 671 660 ··· 742 731 /* Set up device info and initial runtime info. */ 743 732 intel_device_info_driver_create(i915, pdev->device, match_info); 744 733 745 745 - intel_display_device_probe(i915); 734 734 + intel_display_device_probe(pdev); 746 735 747 736 return i915; 748 737 } ··· 761 750 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 762 751 { 763 752 struct drm_i915_private *i915; 753 753 + struct intel_display *display; 764 754 int ret; 765 755 766 756 ret = pci_enable_device(pdev); ··· 775 763 pci_disable_device(pdev); 776 764 return PTR_ERR(i915); 777 765 } 766 766 + 767 767 + display = &i915->display; 778 768 779 769 ret = i915_driver_early_probe(i915); 780 770 if (ret < 0) ··· 798 784 if (ret < 0) 799 785 goto out_cleanup_mmio; 800 786 801 801 - ret = intel_display_driver_probe_noirq(i915); 787 787 + ret = intel_display_driver_probe_noirq(display); 802 788 if (ret < 0) 803 789 goto out_cleanup_hw; 804 790 ··· 806 792 if (ret) 807 793 goto out_cleanup_modeset; 808 794 809 809 - ret = intel_display_driver_probe_nogem(i915); 795 795 + ret = intel_display_driver_probe_nogem(display); 810 796 if (ret) 811 797 goto out_cleanup_irq; 812 798 ··· 818 804 if (ret && ret != -ENODEV) 819 805 drm_dbg(&i915->drm, "pxp init failed with %d\n", ret); 820 806 821 821 - ret = intel_display_driver_probe(i915); 807 807 + ret = intel_display_driver_probe(display); 822 808 if (ret) 823 809 goto out_cleanup_gem; 824 810 ··· 838 824 i915_gem_driver_release(i915); 839 825 out_cleanup_modeset2: 840 826 /* FIXME clean up the error path */ 841 841 - intel_display_driver_remove(i915); 827 827 + intel_display_driver_remove(display); 842 828 intel_irq_uninstall(i915); 843 843 - intel_display_driver_remove_noirq(i915); 829 829 + intel_display_driver_remove_noirq(display); 844 830 goto out_cleanup_modeset; 845 831 out_cleanup_irq: 846 832 intel_irq_uninstall(i915); 847 833 out_cleanup_modeset: 848 848 - intel_display_driver_remove_nogem(i915); 834 834 + intel_display_driver_remove_nogem(display); 849 835 out_cleanup_hw: 850 836 i915_driver_hw_remove(i915); 851 837 intel_memory_regions_driver_release(i915); ··· 865 851 866 852 void i915_driver_remove(struct drm_i915_private *i915) 867 853 { 854 854 + struct intel_display *display = &i915->display; 868 855 intel_wakeref_t wakeref; 869 856 870 857 wakeref = intel_runtime_pm_get(&i915->runtime_pm); ··· 879 864 880 865 intel_gvt_driver_remove(i915); 881 866 882 882 - intel_display_driver_remove(i915); 867 867 + intel_display_driver_remove(display); 883 868 884 869 intel_irq_uninstall(i915); 885 870 886 886 - intel_display_driver_remove_noirq(i915); 871 871 + intel_display_driver_remove_noirq(display); 887 872 888 873 i915_reset_error_state(i915); 889 874 i915_gem_driver_remove(i915); 890 875 891 891 - intel_display_driver_remove_nogem(i915); 876 876 + intel_display_driver_remove_nogem(display); 892 877 893 878 i915_driver_hw_remove(i915); 894 879 ··· 898 883 static void i915_driver_release(struct drm_device *dev) 899 884 { 900 885 struct drm_i915_private *dev_priv = to_i915(dev); 886 886 + struct intel_display *display = &dev_priv->display; 901 887 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 902 888 intel_wakeref_t wakeref; 903 889 ··· 922 906 923 907 i915_driver_late_release(dev_priv); 924 908 925 925 - intel_display_device_remove(dev_priv); 909 909 + intel_display_device_remove(display); 926 910 } 927 911 928 912 static int i915_driver_open(struct drm_device *dev, struct drm_file *file) ··· 952 936 953 937 void i915_driver_shutdown(struct drm_i915_private *i915) 954 938 { 939 939 + struct intel_display *display = &i915->display; 940 940 + 955 941 disable_rpm_wakeref_asserts(&i915->runtime_pm); 956 942 intel_runtime_pm_disable(&i915->runtime_pm); 957 957 - intel_power_domains_disable(i915); 943 943 + intel_power_domains_disable(display); 958 944 959 945 intel_fbdev_set_suspend(&i915->drm, FBINFO_STATE_SUSPENDED, true); 960 946 if (HAS_DISPLAY(i915)) { 961 947 drm_kms_helper_poll_disable(&i915->drm); 962 962 - intel_display_driver_disable_user_access(i915); 948 948 + intel_display_driver_disable_user_access(display); 963 949 964 950 drm_atomic_helper_shutdown(&i915->drm); 965 951 } ··· 972 954 intel_hpd_cancel_work(i915); 973 955 974 956 if (HAS_DISPLAY(i915)) 975 975 - intel_display_driver_suspend_access(i915); 957 957 + intel_display_driver_suspend_access(display); 976 958 977 959 intel_encoder_suspend_all(&i915->display); 978 960 intel_encoder_shutdown_all(&i915->display); ··· 992 974 * - unify the driver remove and system/runtime suspend sequences with 993 975 * the above unified shutdown/poweroff sequence. 994 976 */ 995 995 - intel_power_domains_driver_remove(i915); 977 977 + intel_power_domains_driver_remove(display); 996 978 enable_rpm_wakeref_asserts(&i915->runtime_pm); 997 979 998 980 intel_runtime_pm_driver_last_release(&i915->runtime_pm); ··· 1040 1022 1041 1023 /* We do a lot of poking in a lot of registers, make sure they work 1042 1024 * properly. */ 1043 1043 - intel_power_domains_disable(dev_priv); 1025 1025 + intel_power_domains_disable(display); 1044 1026 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 1045 1027 if (HAS_DISPLAY(dev_priv)) { 1046 1028 drm_kms_helper_poll_disable(dev); 1047 1047 - intel_display_driver_disable_user_access(dev_priv); 1029 1029 + intel_display_driver_disable_user_access(display); 1048 1030 } 1049 1031 1050 1032 pci_save_state(pdev); 1051 1033 1052 1052 - intel_display_driver_suspend(dev_priv); 1053 1053 - 1054 1054 - intel_dp_mst_suspend(dev_priv); 1034 1034 + intel_display_driver_suspend(display); 1055 1035 1056 1036 intel_irq_suspend(dev_priv); 1057 1037 intel_hpd_cancel_work(dev_priv); 1058 1038 1059 1039 if (HAS_DISPLAY(dev_priv)) 1060 1060 - intel_display_driver_suspend_access(dev_priv); 1040 1040 + intel_display_driver_suspend_access(display); 1061 1041 1062 1042 intel_encoder_suspend_all(&dev_priv->display); 1063 1043 ··· 1063 1047 intel_dpt_suspend(dev_priv); 1064 1048 i915_ggtt_suspend(to_gt(dev_priv)->ggtt); 1065 1049 1066 1066 - i915_save_display(dev_priv); 1050 1050 + i9xx_display_sr_save(display); 1067 1051 1068 1052 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 1069 1053 intel_opregion_suspend(display, opregion_target_state); ··· 1082 1066 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) 1083 1067 { 1084 1068 struct drm_i915_private *dev_priv = to_i915(dev); 1069 1069 + struct intel_display *display = &dev_priv->display; 1085 1070 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1086 1071 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; 1087 1072 struct intel_gt *gt; ··· 1098 1081 for_each_gt(gt, dev_priv, i) 1099 1082 intel_uncore_suspend(gt->uncore); 1100 1083 1101 1101 - intel_power_domains_suspend(dev_priv, s2idle); 1102 1102 - 1103 1103 - intel_display_power_suspend_late(dev_priv); 1084 1084 + intel_display_power_suspend_late(display, s2idle); 1104 1085 1105 1086 ret = vlv_suspend_complete(dev_priv); 1106 1087 if (ret) { 1107 1088 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret); 1108 1108 - intel_power_domains_resume(dev_priv); 1089 1089 + intel_display_power_resume_early(display); 1109 1090 1110 1091 goto out; 1111 1092 } ··· 1181 1166 1182 1167 intel_dmc_resume(display); 1183 1168 1184 1184 - i915_restore_display(dev_priv); 1169 1169 + i9xx_display_sr_restore(display); 1170 1170 + 1171 1171 + intel_vga_redisable(display); 1172 1172 + 1173 1173 + intel_gmbus_reset(display); 1174 1174 + 1185 1175 intel_pps_unlock_regs_wa(display); 1186 1176 1187 1177 intel_init_pch_refclk(dev_priv); ··· 1208 1188 1209 1189 i915_gem_resume(dev_priv); 1210 1190 1211 1211 - intel_display_driver_init_hw(dev_priv); 1191 1191 + intel_display_driver_init_hw(display); 1212 1192 1213 1193 intel_clock_gating_init(dev_priv); 1214 1194 1215 1195 if (HAS_DISPLAY(dev_priv)) 1216 1216 - intel_display_driver_resume_access(dev_priv); 1196 1196 + intel_display_driver_resume_access(display); 1217 1197 1218 1198 intel_hpd_init(dev_priv); 1219 1199 1220 1220 - /* MST sideband requires HPD interrupts enabled */ 1221 1221 - intel_dp_mst_resume(dev_priv); 1222 1222 - intel_display_driver_resume(dev_priv); 1200 1200 + intel_display_driver_resume(display); 1223 1201 1224 1202 if (HAS_DISPLAY(dev_priv)) { 1225 1225 - intel_display_driver_enable_user_access(dev_priv); 1203 1203 + intel_display_driver_enable_user_access(display); 1226 1204 drm_kms_helper_poll_enable(dev); 1227 1205 } 1228 1206 intel_hpd_poll_disable(dev_priv); ··· 1229 1211 1230 1212 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 1231 1213 1232 1232 - intel_power_domains_enable(dev_priv); 1214 1214 + intel_power_domains_enable(display); 1233 1215 1234 1216 intel_gvt_resume(dev_priv); 1235 1217 ··· 1241 1223 static int i915_drm_resume_early(struct drm_device *dev) 1242 1224 { 1243 1225 struct drm_i915_private *dev_priv = to_i915(dev); 1226 1226 + struct intel_display *display = &dev_priv->display; 1244 1227 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 1245 1228 struct intel_gt *gt; 1246 1229 int ret, i; ··· 1301 1282 for_each_gt(gt, dev_priv, i) 1302 1283 intel_gt_resume_early(gt); 1303 1284 1304 1304 - intel_display_power_resume_early(dev_priv); 1305 1305 - 1306 1306 - intel_power_domains_resume(dev_priv); 1285 1285 + intel_display_power_resume_early(display); 1307 1286 1308 1287 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); 1309 1288 ··· 1503 1486 for_each_gt(gt, dev_priv, i) 1504 1487 intel_uncore_suspend(gt->uncore); 1505 1488 1506 1506 - intel_display_power_suspend(dev_priv); 1489 1489 + intel_display_power_suspend(display); 1507 1490 1508 1491 ret = vlv_suspend_complete(dev_priv); 1509 1492 if (ret) { ··· 1597 1580 drm_dbg(&dev_priv->drm, 1598 1581 "Unclaimed access during suspend, bios?\n"); 1599 1582 1600 1600 - intel_display_power_resume(dev_priv); 1583 1583 + intel_display_power_resume(display); 1601 1584 1602 1585 ret = vlv_resume_prepare(dev_priv, true); 1603 1586

+9 -10

drivers/gpu/drm/i915/i915_drv.h

reviewed

··· 101 101 resource_size_t usable_size; 102 102 }; 103 103 104 104 - struct i915_suspend_saved_registers { 105 105 - u32 saveDSPARB; 106 106 - u32 saveSWF0[16]; 107 107 - u32 saveSWF1[16]; 108 108 - u32 saveSWF3[3]; 109 109 - u16 saveGCDGMBUS; 110 110 - }; 111 111 - 112 104 #define MAX_L3_SLICES 2 113 105 struct intel_l3_parity { 114 106 u32 *remap_info[MAX_L3_SLICES]; ··· 228 236 spinlock_t irq_lock; 229 237 bool irqs_enabled; 230 238 239 239 + /* LPT/WPT IOSF sideband protection */ 240 240 + struct mutex sbi_lock; 241 241 + 242 242 + /* VLV/CHV IOSF sideband */ 243 243 + struct { 244 244 + struct mutex lock; /* protect sideband access */ 245 245 + struct pm_qos_request qos; 246 246 + } vlv_iosf_sb; 247 247 + 231 248 /* Sideband mailbox protection */ 232 249 struct mutex sb_lock; 233 233 - struct pm_qos_request sb_qos; 234 250 235 251 /** Cached value of IMR to avoid reads in updating the bitfield */ 236 252 u32 irq_mask; ··· 291 291 struct i915_gpu_error gpu_error; 292 292 293 293 u32 suspend_count; 294 294 - struct i915_suspend_saved_registers regfile; 295 294 struct vlv_s0ix_state *vlv_s0ix_state; 296 295 297 296 struct dram_info {

+1 -1

drivers/gpu/drm/i915/i915_gem_gtt.c

reviewed

··· 71 71 * i915_gem_gtt_reserve - reserve a node in an address_space (GTT) 72 72 * @vm: the &struct i915_address_space 73 73 * @ww: An optional struct i915_gem_ww_ctx. 74 74 - * @node: the &struct drm_mm_node (typically i915_vma.mode) 74 74 + * @node: the &struct drm_mm_node (typically i915_vma.node) 75 75 * @size: how much space to allocate inside the GTT, 76 76 * must be #I915_GTT_PAGE_SIZE aligned 77 77 * @offset: where to insert inside the GTT,

+3 -2

drivers/gpu/drm/i915/i915_getparam.c

reviewed

··· 2 2 * SPDX-License-Identifier: MIT 3 3 */ 4 4 5 5 + #include "display/intel_overlay.h" 5 6 #include "gem/i915_gem_mman.h" 6 7 #include "gt/intel_engine_user.h" 7 7 - 8 8 #include "pxp/intel_pxp.h" 9 9 10 10 #include "i915_cmd_parser.h" ··· 16 16 struct drm_file *file_priv) 17 17 { 18 18 struct drm_i915_private *i915 = to_i915(dev); 19 19 + struct intel_display *display = &i915->display; 19 20 struct pci_dev *pdev = to_pci_dev(dev->dev); 20 21 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; 21 22 drm_i915_getparam_t *param = data; ··· 39 38 value = to_gt(i915)->ggtt->num_fences; 40 39 break; 41 40 case I915_PARAM_HAS_OVERLAY: 42 42 - value = !!i915->display.overlay; 41 41 + value = intel_overlay_available(display); 43 42 break; 44 43 case I915_PARAM_HAS_BSD: 45 44 value = !!intel_engine_lookup_user(i915,

+4 -8

drivers/gpu/drm/i915/i915_irq.c

reviewed

··· 658 658 gen5_gt_irq_reset(to_gt(dev_priv)); 659 659 660 660 spin_lock_irq(&dev_priv->irq_lock); 661 661 - if (dev_priv->display.irq.display_irqs_enabled) 662 662 - vlv_display_irq_reset(dev_priv); 661 661 + vlv_display_irq_reset(dev_priv); 663 662 spin_unlock_irq(&dev_priv->irq_lock); 664 663 } 665 664 ··· 722 723 gen2_irq_reset(uncore, GEN8_PCU_IRQ_REGS); 723 724 724 725 spin_lock_irq(&dev_priv->irq_lock); 725 725 - if (dev_priv->display.irq.display_irqs_enabled) 726 726 - vlv_display_irq_reset(dev_priv); 726 726 + vlv_display_irq_reset(dev_priv); 727 727 spin_unlock_irq(&dev_priv->irq_lock); 728 728 } 729 729 ··· 738 740 gen5_gt_irq_postinstall(to_gt(dev_priv)); 739 741 740 742 spin_lock_irq(&dev_priv->irq_lock); 741 741 - if (dev_priv->display.irq.display_irqs_enabled) 742 742 - vlv_display_irq_postinstall(dev_priv); 743 743 + vlv_display_irq_postinstall(dev_priv); 743 744 spin_unlock_irq(&dev_priv->irq_lock); 744 745 745 746 intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); ··· 791 794 gen8_gt_irq_postinstall(to_gt(dev_priv)); 792 795 793 796 spin_lock_irq(&dev_priv->irq_lock); 794 794 - if (dev_priv->display.irq.display_irqs_enabled) 795 795 - vlv_display_irq_postinstall(dev_priv); 797 797 + vlv_display_irq_postinstall(dev_priv); 796 798 spin_unlock_irq(&dev_priv->irq_lock); 797 799 798 800 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);

+42 -80

drivers/gpu/drm/i915/i915_reg.h

reviewed

··· 1147 1147 #define _TRANS_MULT_B 0x6102c 1148 1148 #define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) 1149 1149 1150 1150 - /* VGA port control */ 1151 1151 - #define ADPA _MMIO(0x61100) 1152 1152 - #define PCH_ADPA _MMIO(0xe1100) 1153 1153 - #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) 1154 1154 - #define ADPA_DAC_ENABLE (1 << 31) 1155 1155 - #define ADPA_DAC_DISABLE 0 1156 1156 - #define ADPA_PIPE_SEL_SHIFT 30 1157 1157 - #define ADPA_PIPE_SEL_MASK (1 << 30) 1158 1158 - #define ADPA_PIPE_SEL(pipe) ((pipe) << 30) 1159 1159 - #define ADPA_PIPE_SEL_SHIFT_CPT 29 1160 1160 - #define ADPA_PIPE_SEL_MASK_CPT (3 << 29) 1161 1161 - #define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29) 1162 1162 - #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */ 1163 1163 - #define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24) 1164 1164 - #define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24) 1165 1165 - #define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24) 1166 1166 - #define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24) 1167 1167 - #define ADPA_CRT_HOTPLUG_ENABLE (1 << 23) 1168 1168 - #define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22) 1169 1169 - #define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22) 1170 1170 - #define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21) 1171 1171 - #define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21) 1172 1172 - #define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20) 1173 1173 - #define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20) 1174 1174 - #define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18) 1175 1175 - #define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18) 1176 1176 - #define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18) 1177 1177 - #define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18) 1178 1178 - #define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17) 1179 1179 - #define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17) 1180 1180 - #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16) 1181 1181 - #define ADPA_USE_VGA_HVPOLARITY (1 << 15) 1182 1182 - #define ADPA_SETS_HVPOLARITY 0 1183 1183 - #define ADPA_VSYNC_CNTL_DISABLE (1 << 10) 1184 1184 - #define ADPA_VSYNC_CNTL_ENABLE 0 1185 1185 - #define ADPA_HSYNC_CNTL_DISABLE (1 << 11) 1186 1186 - #define ADPA_HSYNC_CNTL_ENABLE 0 1187 1187 - #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4) 1188 1188 - #define ADPA_VSYNC_ACTIVE_LOW 0 1189 1189 - #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3) 1190 1190 - #define ADPA_HSYNC_ACTIVE_LOW 0 1191 1191 - #define ADPA_DPMS_MASK (~(3 << 10)) 1192 1192 - #define ADPA_DPMS_ON (0 << 10) 1193 1193 - #define ADPA_DPMS_SUSPEND (1 << 10) 1194 1194 - #define ADPA_DPMS_STANDBY (2 << 10) 1195 1195 - #define ADPA_DPMS_OFF (3 << 10) 1196 1196 - 1197 1150 /* Hotplug control (945+ only) */ 1198 1151 #define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) 1199 1152 #define PORTB_HOTPLUG_INT_EN (1 << 29) ··· 2755 2802 #define _CHICKEN_TRANS_C 0x420c8 2756 2803 #define _CHICKEN_TRANS_EDP 0x420cc 2757 2804 #define _CHICKEN_TRANS_D 0x420d8 2758 2758 - #define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 2805 2805 + #define _CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ 2759 2806 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ 2760 2807 [TRANSCODER_A] = _CHICKEN_TRANS_A, \ 2761 2808 [TRANSCODER_B] = _CHICKEN_TRANS_B, \ ··· 2763 2810 [TRANSCODER_D] = _CHICKEN_TRANS_D)) 2764 2811 #define _MTL_CHICKEN_TRANS_A 0x604e0 2765 2812 #define _MTL_CHICKEN_TRANS_B 0x614e0 2766 2766 - #define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ 2813 2813 + #define _MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \ 2767 2814 _MTL_CHICKEN_TRANS_A, \ 2768 2815 _MTL_CHICKEN_TRANS_B) 2816 2816 + #define CHICKEN_TRANS(display, trans) (DISPLAY_VER(display) >= 14 ? _MTL_CHICKEN_TRANS(trans) : _CHICKEN_TRANS(trans)) 2769 2817 #define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */ 2770 2818 #define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */ 2771 2819 #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) ··· 2817 2863 #define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) 2818 2864 2819 2865 #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) 2820 2820 - #define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31) 2866 2866 + #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31) 2821 2867 #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) 2822 2822 - #define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 2823 2823 - #define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 2824 2824 - #define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 2868 2868 + #define _LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25) 2869 2869 + #define _LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24) 2870 2870 + #define _LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23) 2871 2871 + #define LATENCY_REPORTING_REMOVED(pipe) _PICK((pipe), \ 2872 2872 + _LATENCY_REPORTING_REMOVED_PIPE_A, \ 2873 2873 + _LATENCY_REPORTING_REMOVED_PIPE_B, \ 2874 2874 + _LATENCY_REPORTING_REMOVED_PIPE_C, \ 2875 2875 + _LATENCY_REPORTING_REMOVED_PIPE_D) 2825 2876 #define ICL_DELAY_PMRSP REG_BIT(22) 2826 2877 #define DISABLE_FLR_SRC REG_BIT(15) 2827 2878 #define MASK_WAKEMEM REG_BIT(13) ··· 3778 3819 #define TRANS_DDI_PVSYNC (1 << 17) 3779 3820 #define TRANS_DDI_PHSYNC (1 << 16) 3780 3821 #define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15) 3822 3822 + #define XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(15) 3781 3823 #define TRANS_DDI_EDP_INPUT_MASK (7 << 12) 3782 3824 #define TRANS_DDI_EDP_INPUT_A_ON (0 << 12) 3783 3825 #define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12) ··· 3823 3863 #define _TGL_DP_TP_CTL_A 0x60540 3824 3864 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) 3825 3865 #define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A) 3826 3826 - #define DP_TP_CTL_ENABLE (1 << 31) 3827 3827 - #define DP_TP_CTL_FEC_ENABLE (1 << 30) 3828 3828 - #define DP_TP_CTL_MODE_SST (0 << 27) 3829 3829 - #define DP_TP_CTL_MODE_MST (1 << 27) 3830 3830 - #define DP_TP_CTL_FORCE_ACT (1 << 25) 3831 3831 - #define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19) 3832 3832 - #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A (0 << 19) 3833 3833 - #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B (1 << 19) 3834 3834 - #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C (2 << 19) 3835 3835 - #define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18) 3836 3836 - #define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15) 3837 3837 - #define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8) 3838 3838 - #define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8) 3839 3839 - #define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8) 3840 3840 - #define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8) 3841 3841 - #define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8) 3842 3842 - #define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8) 3843 3843 - #define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8) 3844 3844 - #define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7) 3866 3866 + #define DP_TP_CTL_ENABLE REG_BIT(31) 3867 3867 + #define DP_TP_CTL_FEC_ENABLE REG_BIT(30) 3868 3868 + #define DP_TP_CTL_MODE_MASK REG_BIT(27) 3869 3869 + #define DP_TP_CTL_MODE_SST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 0) 3870 3870 + #define DP_TP_CTL_MODE_MST REG_FIELD_PREP(DP_TP_CTL_MODE_MASK, 1) 3871 3871 + #define DP_TP_CTL_FORCE_ACT REG_BIT(25) 3872 3872 + #define DP_TP_CTL_TRAIN_PAT4_SEL_MASK REG_GENMASK(20, 19) 3873 3873 + #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 0) 3874 3874 + #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 1) 3875 3875 + #define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C REG_FIELD_PREP(DP_TP_CTL_TRAIN_PAT4_SEL_MASK, 2) 3876 3876 + #define DP_TP_CTL_ENHANCED_FRAME_ENABLE REG_BIT(18) 3877 3877 + #define DP_TP_CTL_FDI_AUTOTRAIN REG_BIT(15) 3878 3878 + #define DP_TP_CTL_LINK_TRAIN_MASK REG_GENMASK(10, 8) 3879 3879 + #define DP_TP_CTL_LINK_TRAIN_PAT1 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 0) 3880 3880 + #define DP_TP_CTL_LINK_TRAIN_PAT2 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 1) 3881 3881 + #define DP_TP_CTL_LINK_TRAIN_PAT3 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 4) 3882 3882 + #define DP_TP_CTL_LINK_TRAIN_PAT4 REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 5) 3883 3883 + #define DP_TP_CTL_LINK_TRAIN_IDLE REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 2) 3884 3884 + #define DP_TP_CTL_LINK_TRAIN_NORMAL REG_FIELD_PREP(DP_TP_CTL_LINK_TRAIN_MASK, 3) 3885 3885 + #define DP_TP_CTL_SCRAMBLE_DISABLE REG_BIT(7) 3845 3886 3846 3887 /* DisplayPort Transport Status */ 3847 3888 #define _DP_TP_STATUS_A 0x64044 ··· 3850 3889 #define _TGL_DP_TP_STATUS_A 0x60544 3851 3890 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) 3852 3891 #define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A) 3853 3853 - #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) 3854 3854 - #define DP_TP_STATUS_IDLE_DONE (1 << 25) 3855 3855 - #define DP_TP_STATUS_ACT_SENT (1 << 24) 3856 3856 - #define DP_TP_STATUS_MODE_STATUS_MST (1 << 23) 3857 3857 - #define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12) 3858 3858 - #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8) 3859 3859 - #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4) 3860 3860 - #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0) 3892 3892 + #define DP_TP_STATUS_FEC_ENABLE_LIVE REG_BIT(28) 3893 3893 + #define DP_TP_STATUS_IDLE_DONE REG_BIT(25) 3894 3894 + #define DP_TP_STATUS_ACT_SENT REG_BIT(24) 3895 3895 + #define DP_TP_STATUS_MODE_STATUS_MST REG_BIT(23) 3896 3896 + #define DP_TP_STATUS_STREAMS_ENABLED_MASK REG_GENMASK(18, 16) /* 17:16 on hsw but bit 18 mbz */ 3897 3897 + #define DP_TP_STATUS_AUTOTRAIN_DONE REG_BIT(12) 3898 3898 + #define DP_TP_STATUS_PAYLOAD_MAPPING_VC2_MASK REG_GENMASK(9, 8) 3899 3899 + #define DP_TP_STATUS_PAYLOAD_MAPPING_VC1_MASK REG_GENMASK(5, 4) 3900 3900 + #define DP_TP_STATUS_PAYLOAD_MAPPING_VC0_MASK REG_GENMASK(1, 0) 3861 3901 3862 3902 /* DDI Buffer Control */ 3863 3903 #define _DDI_BUF_CTL_A 0x64000

-141

drivers/gpu/drm/i915/i915_suspend.c

reviewed

··· 1 1 - /* 2 2 - * 3 3 - * Copyright 2008 (c) Intel Corporation 4 4 - * Jesse Barnes <jbarnes@virtuousgeek.org> 5 5 - * 6 6 - * Permission is hereby granted, free of charge, to any person obtaining a 7 7 - * copy of this software and associated documentation files (the 8 8 - * "Software"), to deal in the Software without restriction, including 9 9 - * without limitation the rights to use, copy, modify, merge, publish, 10 10 - * distribute, sub license, and/or sell copies of the Software, and to 11 11 - * permit persons to whom the Software is furnished to do so, subject to 12 12 - * the following conditions: 13 13 - * 14 14 - * The above copyright notice and this permission notice (including the 15 15 - * next paragraph) shall be included in all copies or substantial portions 16 16 - * of the Software. 17 17 - * 18 18 - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 19 - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 20 - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 21 - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 22 - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 23 - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 24 - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 25 - */ 26 26 - 27 27 - #include "display/intel_de.h" 28 28 - #include "display/intel_gmbus.h" 29 29 - #include "display/intel_vga.h" 30 30 - 31 31 - #include "i915_drv.h" 32 32 - #include "i915_reg.h" 33 33 - #include "i915_suspend.h" 34 34 - #include "intel_pci_config.h" 35 35 - 36 36 - static void intel_save_swf(struct drm_i915_private *dev_priv) 37 37 - { 38 38 - int i; 39 39 - 40 40 - /* Scratch space */ 41 41 - if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { 42 42 - for (i = 0; i < 7; i++) { 43 43 - dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, 44 44 - SWF0(dev_priv, i)); 45 45 - dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, 46 46 - SWF1(dev_priv, i)); 47 47 - } 48 48 - for (i = 0; i < 3; i++) 49 49 - dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, 50 50 - SWF3(dev_priv, i)); 51 51 - } else if (GRAPHICS_VER(dev_priv) == 2) { 52 52 - for (i = 0; i < 7; i++) 53 53 - dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, 54 54 - SWF1(dev_priv, i)); 55 55 - } else if (HAS_GMCH(dev_priv)) { 56 56 - for (i = 0; i < 16; i++) { 57 57 - dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, 58 58 - SWF0(dev_priv, i)); 59 59 - dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, 60 60 - SWF1(dev_priv, i)); 61 61 - } 62 62 - for (i = 0; i < 3; i++) 63 63 - dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, 64 64 - SWF3(dev_priv, i)); 65 65 - } 66 66 - } 67 67 - 68 68 - static void intel_restore_swf(struct drm_i915_private *dev_priv) 69 69 - { 70 70 - int i; 71 71 - 72 72 - /* Scratch space */ 73 73 - if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { 74 74 - for (i = 0; i < 7; i++) { 75 75 - intel_de_write(dev_priv, SWF0(dev_priv, i), 76 76 - dev_priv->regfile.saveSWF0[i]); 77 77 - intel_de_write(dev_priv, SWF1(dev_priv, i), 78 78 - dev_priv->regfile.saveSWF1[i]); 79 79 - } 80 80 - for (i = 0; i < 3; i++) 81 81 - intel_de_write(dev_priv, SWF3(dev_priv, i), 82 82 - dev_priv->regfile.saveSWF3[i]); 83 83 - } else if (GRAPHICS_VER(dev_priv) == 2) { 84 84 - for (i = 0; i < 7; i++) 85 85 - intel_de_write(dev_priv, SWF1(dev_priv, i), 86 86 - dev_priv->regfile.saveSWF1[i]); 87 87 - } else if (HAS_GMCH(dev_priv)) { 88 88 - for (i = 0; i < 16; i++) { 89 89 - intel_de_write(dev_priv, SWF0(dev_priv, i), 90 90 - dev_priv->regfile.saveSWF0[i]); 91 91 - intel_de_write(dev_priv, SWF1(dev_priv, i), 92 92 - dev_priv->regfile.saveSWF1[i]); 93 93 - } 94 94 - for (i = 0; i < 3; i++) 95 95 - intel_de_write(dev_priv, SWF3(dev_priv, i), 96 96 - dev_priv->regfile.saveSWF3[i]); 97 97 - } 98 98 - } 99 99 - 100 100 - void i915_save_display(struct drm_i915_private *dev_priv) 101 101 - { 102 102 - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 103 103 - 104 104 - if (!HAS_DISPLAY(dev_priv)) 105 105 - return; 106 106 - 107 107 - /* Display arbitration control */ 108 108 - if (GRAPHICS_VER(dev_priv) <= 4) 109 109 - dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, 110 110 - DSPARB(dev_priv)); 111 111 - 112 112 - if (GRAPHICS_VER(dev_priv) == 4) 113 113 - pci_read_config_word(pdev, GCDGMBUS, 114 114 - &dev_priv->regfile.saveGCDGMBUS); 115 115 - 116 116 - intel_save_swf(dev_priv); 117 117 - } 118 118 - 119 119 - void i915_restore_display(struct drm_i915_private *dev_priv) 120 120 - { 121 121 - struct intel_display *display = &dev_priv->display; 122 122 - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 123 123 - 124 124 - if (!HAS_DISPLAY(dev_priv)) 125 125 - return; 126 126 - 127 127 - intel_restore_swf(dev_priv); 128 128 - 129 129 - if (GRAPHICS_VER(dev_priv) == 4) 130 130 - pci_write_config_word(pdev, GCDGMBUS, 131 131 - dev_priv->regfile.saveGCDGMBUS); 132 132 - 133 133 - /* Display arbitration */ 134 134 - if (GRAPHICS_VER(dev_priv) <= 4) 135 135 - intel_de_write(dev_priv, DSPARB(dev_priv), 136 136 - dev_priv->regfile.saveDSPARB); 137 137 - 138 138 - intel_vga_redisable(display); 139 139 - 140 140 - intel_gmbus_reset(display); 141 141 - }

-14

drivers/gpu/drm/i915/i915_suspend.h

reviewed

··· 1 1 - /* SPDX-License-Identifier: MIT */ 2 2 - /* 3 3 - * Copyright © 2019 Intel Corporation 4 4 - */ 5 5 - 6 6 - #ifndef __I915_SUSPEND_H__ 7 7 - #define __I915_SUSPEND_H__ 8 8 - 9 9 - struct drm_i915_private; 10 10 - 11 11 - void i915_save_display(struct drm_i915_private *i915); 12 12 - void i915_restore_display(struct drm_i915_private *i915); 13 13 - 14 14 - #endif /* __I915_SUSPEND_H__ */

+1

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

reviewed

··· 8 8 #include "display/intel_audio_regs.h" 9 9 #include "display/intel_backlight_regs.h" 10 10 #include "display/intel_color_regs.h" 11 11 + #include "display/intel_crt_regs.h" 11 12 #include "display/intel_cursor_regs.h" 12 13 #include "display/intel_display_types.h" 13 14 #include "display/intel_dmc_regs.h"

+21 -1

drivers/gpu/drm/i915/intel_sbi.c

reviewed

··· 17 17 struct intel_uncore *uncore = &i915->uncore; 18 18 u32 cmd; 19 19 20 20 - lockdep_assert_held(&i915->sb_lock); 20 20 + lockdep_assert_held(&i915->sbi_lock); 21 21 22 22 if (intel_wait_for_register_fw(uncore, 23 23 SBI_CTL_STAT, SBI_BUSY, 0, ··· 57 57 return 0; 58 58 } 59 59 60 60 + void intel_sbi_lock(struct drm_i915_private *i915) 61 61 + { 62 62 + mutex_lock(&i915->sbi_lock); 63 63 + } 64 64 + 65 65 + void intel_sbi_unlock(struct drm_i915_private *i915) 66 66 + { 67 67 + mutex_unlock(&i915->sbi_lock); 68 68 + } 69 69 + 60 70 u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg, 61 71 enum intel_sbi_destination destination) 62 72 { ··· 81 71 enum intel_sbi_destination destination) 82 72 { 83 73 intel_sbi_rw(i915, reg, destination, &value, false); 74 74 + } 75 75 + 76 76 + void intel_sbi_init(struct drm_i915_private *i915) 77 77 + { 78 78 + mutex_init(&i915->sbi_lock); 79 79 + } 80 80 + 81 81 + void intel_sbi_fini(struct drm_i915_private *i915) 82 82 + { 83 83 + mutex_destroy(&i915->sbi_lock); 84 84 }

+4

drivers/gpu/drm/i915/intel_sbi.h

reviewed

··· 15 15 SBI_MPHY, 16 16 }; 17 17 18 18 + void intel_sbi_init(struct drm_i915_private *i915); 19 19 + void intel_sbi_fini(struct drm_i915_private *i915); 20 20 + void intel_sbi_lock(struct drm_i915_private *i915); 21 21 + void intel_sbi_unlock(struct drm_i915_private *i915); 18 22 u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg, 19 23 enum intel_sbi_destination destination); 20 24 void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,

+1 -1

drivers/gpu/drm/i915/selftests/mock_gem_device.c

reviewed

··· 180 180 /* Set up device info and initial runtime info. */ 181 181 intel_device_info_driver_create(i915, pdev->device, &mock_info); 182 182 183 183 - intel_display_device_probe(i915); 183 183 + intel_display_device_probe(pdev); 184 184 185 185 dev_pm_domain_set(&pdev->dev, &pm_domain); 186 186 pm_runtime_enable(&pdev->dev);

+23 -5

drivers/gpu/drm/i915/vlv_sideband.c

reviewed

··· 43 43 * to the Valleyview P-unit and not all sideband communications. 44 44 */ 45 45 if (IS_VALLEYVIEW(i915)) { 46 46 - cpu_latency_qos_update_request(&i915->sb_qos, 0); 46 46 + cpu_latency_qos_update_request(&i915->vlv_iosf_sb.qos, 0); 47 47 on_each_cpu(ping, NULL, 1); 48 48 } 49 49 } ··· 51 51 static void __vlv_punit_put(struct drm_i915_private *i915) 52 52 { 53 53 if (IS_VALLEYVIEW(i915)) 54 54 - cpu_latency_qos_update_request(&i915->sb_qos, 54 54 + cpu_latency_qos_update_request(&i915->vlv_iosf_sb.qos, 55 55 PM_QOS_DEFAULT_VALUE); 56 56 57 57 iosf_mbi_punit_release(); ··· 62 62 if (ports & BIT(VLV_IOSF_SB_PUNIT)) 63 63 __vlv_punit_get(i915); 64 64 65 65 - mutex_lock(&i915->sb_lock); 65 65 + mutex_lock(&i915->vlv_iosf_sb.lock); 66 66 } 67 67 68 68 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports) 69 69 { 70 70 - mutex_unlock(&i915->sb_lock); 70 70 + mutex_unlock(&i915->vlv_iosf_sb.lock); 71 71 72 72 if (ports & BIT(VLV_IOSF_SB_PUNIT)) 73 73 __vlv_punit_put(i915); ··· 81 81 const bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP); 82 82 int err; 83 83 84 84 - lockdep_assert_held(&i915->sb_lock); 84 84 + lockdep_assert_held(&i915->vlv_iosf_sb.lock); 85 85 if (port == IOSF_PORT_PUNIT) 86 86 iosf_mbi_assert_punit_acquired(); 87 87 ··· 248 248 { 249 249 vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP, 250 250 reg, &val); 251 251 + } 252 252 + 253 253 + void vlv_iosf_sb_init(struct drm_i915_private *i915) 254 254 + { 255 255 + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 256 256 + mutex_init(&i915->vlv_iosf_sb.lock); 257 257 + 258 258 + if (IS_VALLEYVIEW(i915)) 259 259 + cpu_latency_qos_add_request(&i915->vlv_iosf_sb.qos, PM_QOS_DEFAULT_VALUE); 260 260 + } 261 261 + 262 262 + void vlv_iosf_sb_fini(struct drm_i915_private *i915) 263 263 + { 264 264 + if (IS_VALLEYVIEW(i915)) 265 265 + cpu_latency_qos_remove_request(&i915->vlv_iosf_sb.qos); 266 266 + 267 267 + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 268 268 + mutex_destroy(&i915->vlv_iosf_sb.lock); 251 269 }

+3

drivers/gpu/drm/i915/vlv_sideband.h

reviewed

··· 25 25 VLV_IOSF_SB_PUNIT, 26 26 }; 27 27 28 28 + void vlv_iosf_sb_init(struct drm_i915_private *i915); 29 29 + void vlv_iosf_sb_fini(struct drm_i915_private *i915); 30 30 + 28 31 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports); 29 32 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports); 30 33

+10 -1

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

reviewed

··· 117 117 unsigned int slow_timeout_ms, u32 *out_value) 118 118 { 119 119 struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg)); 120 120 + bool atomic; 121 121 + 122 122 + /* 123 123 + * Replicate the behavior from i915 here, in which sleep is not 124 124 + * performed if slow_timeout_ms == 0. This is necessary because 125 125 + * of some paths in display code where waits are done in atomic 126 126 + * context. 127 127 + */ 128 128 + atomic = !slow_timeout_ms && fast_timeout_us > 0; 120 129 121 130 return xe_mmio_wait32(__compat_uncore_to_mmio(uncore), reg, mask, value, 122 131 fast_timeout_us + 1000 * slow_timeout_ms, 123 123 - out_value, false); 132 132 + out_value, atomic); 124 133 } 125 134 126 135 static inline u32 intel_uncore_read_fw(struct intel_uncore *uncore,

+71 -43

drivers/gpu/drm/xe/display/xe_display.c

reviewed

··· 22 22 #include "intel_display_irq.h" 23 23 #include "intel_display_types.h" 24 24 #include "intel_dmc.h" 25 25 + #include "intel_dmc_wl.h" 25 26 #include "intel_dp.h" 26 27 #include "intel_encoder.h" 27 28 #include "intel_fbdev.h" ··· 104 103 static void xe_display_fini_nommio(struct drm_device *dev, void *dummy) 105 104 { 106 105 struct xe_device *xe = to_xe_device(dev); 106 106 + struct intel_display *display = &xe->display; 107 107 108 108 if (!xe->info.probe_display) 109 109 return; 110 110 111 111 - intel_power_domains_cleanup(xe); 111 111 + intel_power_domains_cleanup(display); 112 112 } 113 113 114 114 int xe_display_init_nommio(struct xe_device *xe) ··· 134 132 if (!xe->info.probe_display) 135 133 return; 136 134 137 137 - intel_display_driver_remove_noirq(xe); 135 135 + intel_display_driver_remove_noirq(display); 138 136 intel_opregion_cleanup(display); 139 137 } 140 138 ··· 146 144 if (!xe->info.probe_display) 147 145 return 0; 148 146 149 149 - intel_display_driver_early_probe(xe); 147 147 + intel_display_driver_early_probe(display); 150 148 151 149 /* Early display init.. */ 152 150 intel_opregion_setup(display); ··· 159 157 160 158 intel_bw_init_hw(xe); 161 159 162 162 - intel_display_device_info_runtime_init(xe); 160 160 + intel_display_device_info_runtime_init(display); 163 161 164 164 - err = intel_display_driver_probe_noirq(xe); 162 162 + err = intel_display_driver_probe_noirq(display); 165 163 if (err) { 166 164 intel_opregion_cleanup(display); 167 165 return err; ··· 173 171 static void xe_display_fini_noaccel(void *arg) 174 172 { 175 173 struct xe_device *xe = arg; 174 174 + struct intel_display *display = &xe->display; 176 175 177 176 if (!xe->info.probe_display) 178 177 return; 179 178 180 180 - intel_display_driver_remove_nogem(xe); 179 179 + intel_display_driver_remove_nogem(display); 181 180 } 182 181 183 182 int xe_display_init_noaccel(struct xe_device *xe) 184 183 { 184 184 + struct intel_display *display = &xe->display; 185 185 int err; 186 186 187 187 if (!xe->info.probe_display) 188 188 return 0; 189 189 190 190 - err = intel_display_driver_probe_nogem(xe); 190 190 + err = intel_display_driver_probe_nogem(display); 191 191 if (err) 192 192 return err; 193 193 ··· 198 194 199 195 int xe_display_init(struct xe_device *xe) 200 196 { 197 197 + struct intel_display *display = &xe->display; 198 198 + 201 199 if (!xe->info.probe_display) 202 200 return 0; 203 201 204 204 - return intel_display_driver_probe(xe); 202 202 + return intel_display_driver_probe(display); 205 203 } 206 204 207 205 void xe_display_fini(struct xe_device *xe) ··· 221 215 222 216 void xe_display_register(struct xe_device *xe) 223 217 { 218 218 + struct intel_display *display = &xe->display; 219 219 + 224 220 if (!xe->info.probe_display) 225 221 return; 226 222 227 227 - intel_display_driver_register(xe); 223 223 + intel_display_driver_register(display); 224 224 + intel_power_domains_enable(display); 228 225 intel_register_dsm_handler(); 229 229 - intel_power_domains_enable(xe); 230 226 } 231 227 232 228 void xe_display_unregister(struct xe_device *xe) 233 229 { 230 230 + struct intel_display *display = &xe->display; 231 231 + 234 232 if (!xe->info.probe_display) 235 233 return; 236 234 237 235 intel_unregister_dsm_handler(); 238 238 - intel_power_domains_disable(xe); 239 239 - intel_display_driver_unregister(xe); 236 236 + intel_power_domains_disable(display); 237 237 + intel_display_driver_unregister(display); 240 238 } 241 239 242 240 void xe_display_driver_remove(struct xe_device *xe) 243 241 { 242 242 + struct intel_display *display = &xe->display; 243 243 + 244 244 if (!xe->info.probe_display) 245 245 return; 246 246 247 247 - intel_display_driver_remove(xe); 247 247 + intel_display_driver_remove(display); 248 248 } 249 249 250 250 /* IRQ-related functions */ ··· 334 322 * We do a lot of poking in a lot of registers, make sure they work 335 323 * properly. 336 324 */ 337 337 - intel_power_domains_disable(xe); 325 325 + intel_power_domains_disable(display); 338 326 if (!runtime) 339 327 intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_SUSPENDED, true); 340 328 341 329 if (!runtime && has_display(xe)) { 342 330 drm_kms_helper_poll_disable(&xe->drm); 343 343 - intel_display_driver_disable_user_access(xe); 344 344 - intel_display_driver_suspend(xe); 331 331 + intel_display_driver_disable_user_access(display); 332 332 + intel_display_driver_suspend(display); 345 333 } 346 334 347 335 xe_display_flush_cleanup_work(xe); 348 336 349 349 - if (!runtime) 350 350 - intel_dp_mst_suspend(xe); 351 351 - 352 337 intel_hpd_cancel_work(xe); 353 338 354 339 if (!runtime && has_display(xe)) { 355 355 - intel_display_driver_suspend_access(xe); 340 340 + intel_display_driver_suspend_access(display); 356 341 intel_encoder_suspend_all(&xe->display); 357 342 } 358 343 ··· 373 364 if (!xe->info.probe_display) 374 365 return; 375 366 376 376 - intel_power_domains_disable(xe); 367 367 + intel_power_domains_disable(display); 377 368 intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_SUSPENDED, true); 378 369 if (has_display(xe)) { 379 370 drm_kms_helper_poll_disable(&xe->drm); 380 380 - intel_display_driver_disable_user_access(xe); 381 381 - intel_display_driver_suspend(xe); 371 371 + intel_display_driver_disable_user_access(display); 372 372 + intel_display_driver_suspend(display); 382 373 } 383 374 384 375 xe_display_flush_cleanup_work(xe); ··· 386 377 intel_hpd_cancel_work(xe); 387 378 388 379 if (has_display(xe)) 389 389 - intel_display_driver_suspend_access(xe); 380 380 + intel_display_driver_suspend_access(display); 390 381 391 382 intel_encoder_suspend_all(display); 392 383 intel_encoder_shutdown_all(display); ··· 411 402 412 403 void xe_display_pm_suspend_late(struct xe_device *xe) 413 404 { 405 405 + struct intel_display *display = &xe->display; 414 406 bool s2idle = suspend_to_idle(); 407 407 + 415 408 if (!xe->info.probe_display) 416 409 return; 417 410 418 418 - intel_power_domains_suspend(xe, s2idle); 411 411 + intel_display_power_suspend_late(display, s2idle); 412 412 + } 419 413 420 420 - intel_display_power_suspend_late(xe); 414 414 + void xe_display_pm_runtime_suspend_late(struct xe_device *xe) 415 415 + { 416 416 + struct intel_display *display = &xe->display; 417 417 + 418 418 + if (!xe->info.probe_display) 419 419 + return; 420 420 + 421 421 + if (xe->d3cold.allowed) 422 422 + xe_display_pm_suspend_late(xe); 423 423 + 424 424 + /* 425 425 + * If xe_display_pm_suspend_late() is not called, it is likely 426 426 + * that we will be on dynamic DC states with DMC wakelock enabled. We 427 427 + * need to flush the release work in that case. 428 428 + */ 429 429 + intel_dmc_wl_flush_release_work(display); 421 430 } 422 431 423 432 void xe_display_pm_shutdown_late(struct xe_device *xe) 424 433 { 434 434 + struct intel_display *display = &xe->display; 435 435 + 425 436 if (!xe->info.probe_display) 426 437 return; 427 438 ··· 450 421 * for now leaving all display power wells in the INIT power domain 451 422 * enabled. 452 423 */ 453 453 - intel_power_domains_driver_remove(xe); 424 424 + intel_power_domains_driver_remove(display); 454 425 } 455 426 456 427 void xe_display_pm_resume_early(struct xe_device *xe) 457 428 { 429 429 + struct intel_display *display = &xe->display; 430 430 + 458 431 if (!xe->info.probe_display) 459 432 return; 460 433 461 461 - intel_display_power_resume_early(xe); 462 462 - 463 463 - intel_power_domains_resume(xe); 434 434 + intel_display_power_resume_early(display); 464 435 } 465 436 466 437 static void __xe_display_pm_resume(struct xe_device *xe, bool runtime) ··· 475 446 if (has_display(xe)) 476 447 drm_mode_config_reset(&xe->drm); 477 448 478 478 - intel_display_driver_init_hw(xe); 479 479 - intel_hpd_init(xe); 449 449 + intel_display_driver_init_hw(display); 480 450 481 451 if (!runtime && has_display(xe)) 482 482 - intel_display_driver_resume_access(xe); 452 452 + intel_display_driver_resume_access(display); 483 453 484 484 - /* MST sideband requires HPD interrupts enabled */ 485 485 - if (!runtime) 486 486 - intel_dp_mst_resume(xe); 454 454 + intel_hpd_init(xe); 487 455 488 456 if (!runtime && has_display(xe)) { 489 489 - intel_display_driver_resume(xe); 457 457 + intel_display_driver_resume(display); 490 458 drm_kms_helper_poll_enable(&xe->drm); 491 491 - intel_display_driver_enable_user_access(xe); 459 459 + intel_display_driver_enable_user_access(display); 492 460 } 493 461 494 462 if (has_display(xe)) ··· 496 470 if (!runtime) 497 471 intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_RUNNING, false); 498 472 499 499 - intel_power_domains_enable(xe); 473 473 + intel_power_domains_enable(display); 500 474 } 501 475 502 476 void xe_display_pm_resume(struct xe_device *xe) ··· 521 495 522 496 static void display_device_remove(struct drm_device *dev, void *arg) 523 497 { 524 524 - struct xe_device *xe = arg; 498 498 + struct intel_display *display = arg; 525 499 526 526 - intel_display_device_remove(xe); 500 500 + intel_display_device_remove(display); 527 501 } 528 502 529 503 int xe_display_probe(struct xe_device *xe) 530 504 { 505 505 + struct pci_dev *pdev = to_pci_dev(xe->drm.dev); 506 506 + struct intel_display *display; 531 507 int err; 532 508 533 509 if (!xe->info.probe_display) 534 510 goto no_display; 535 511 536 536 - intel_display_device_probe(xe); 512 512 + display = intel_display_device_probe(pdev); 537 513 538 538 - err = drmm_add_action_or_reset(&xe->drm, display_device_remove, xe); 514 514 + err = drmm_add_action_or_reset(&xe->drm, display_device_remove, display); 539 515 if (err) 540 516 return err; 541 517

+2

drivers/gpu/drm/xe/display/xe_display.h

reviewed

··· 41 41 void xe_display_pm_resume_early(struct xe_device *xe); 42 42 void xe_display_pm_resume(struct xe_device *xe); 43 43 void xe_display_pm_runtime_suspend(struct xe_device *xe); 44 44 + void xe_display_pm_runtime_suspend_late(struct xe_device *xe); 44 45 void xe_display_pm_runtime_resume(struct xe_device *xe); 45 46 46 47 #else ··· 75 74 static inline void xe_display_pm_resume_early(struct xe_device *xe) {} 76 75 static inline void xe_display_pm_resume(struct xe_device *xe) {} 77 76 static inline void xe_display_pm_runtime_suspend(struct xe_device *xe) {} 77 77 + static inline void xe_display_pm_runtime_suspend_late(struct xe_device *xe) {} 78 78 static inline void xe_display_pm_runtime_resume(struct xe_device *xe) {} 79 79 80 80 #endif /* CONFIG_DRM_XE_DISPLAY */

+4 -4

drivers/gpu/drm/xe/display/xe_plane_initial.c

reviewed

··· 275 275 } 276 276 } 277 277 278 278 - void intel_initial_plane_config(struct drm_i915_private *i915) 278 278 + void intel_initial_plane_config(struct intel_display *display) 279 279 { 280 280 struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {}; 281 281 struct intel_crtc *crtc; 282 282 283 283 - for_each_intel_crtc(&i915->drm, crtc) { 283 283 + for_each_intel_crtc(display->drm, crtc) { 284 284 struct intel_initial_plane_config *plane_config = 285 285 &plane_configs[crtc->pipe]; 286 286 ··· 294 294 * can even allow for smooth boot transitions if the BIOS 295 295 * fb is large enough for the active pipe configuration. 296 296 */ 297 297 - i915->display.funcs.display->get_initial_plane_config(crtc, plane_config); 297 297 + display->funcs.display->get_initial_plane_config(crtc, plane_config); 298 298 299 299 /* 300 300 * If the fb is shared between multiple heads, we'll ··· 302 302 */ 303 303 intel_find_initial_plane_obj(crtc, plane_configs); 304 304 305 305 - if (i915->display.funcs.display->fixup_initial_plane_config(crtc, plane_config)) 305 305 + if (display->funcs.display->fixup_initial_plane_config(crtc, plane_config)) 306 306 intel_crtc_wait_for_next_vblank(crtc); 307 307 308 308 plane_config_fini(plane_config);

+2 -2

drivers/gpu/drm/xe/xe_pm.c

reviewed

··· 414 414 415 415 xe_irq_suspend(xe); 416 416 417 417 - if (xe->d3cold.allowed) 418 418 - xe_display_pm_suspend_late(xe); 417 417 + xe_display_pm_runtime_suspend_late(xe); 418 418 + 419 419 out: 420 420 if (err) 421 421 xe_display_pm_runtime_resume(xe);

+2

include/drm/drm_print.h

reviewed

··· 199 199 void drm_print_regset32(struct drm_printer *p, struct debugfs_regset32 *regset); 200 200 void drm_print_bits(struct drm_printer *p, unsigned long value, 201 201 const char * const bits[], unsigned int nbits); 202 202 + void drm_print_hex_dump(struct drm_printer *p, const char *prefix, 203 203 + const u8 *buf, size_t len); 202 204 203 205 __printf(2, 0) 204 206 /**