Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm: import A6xx XML display registers database
Import Adreno registers database for A6xx from the Mesa, commit
639488f924d9 ("freedreno/registers: limit the rules schema").
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/585856/
Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-9-4bdb277a85a1@linaro.org
+5198
+4970
drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+4970
drivers/gpu/drm/msm/registers/adreno/a6xx.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
<import file="adreno/adreno_common.xml"/>
7
+
<import file="adreno/adreno_pm4.xml"/>
8
+
9
+
<!--
10
+
Each register that is actually being used by driver should have "usage" defined,
11
+
currently there are following usages:
12
+
- "cmd" - the register is used outside of renderpass and blits,
13
+
roughly corresponds to registers used in ib1 for Freedreno
14
+
- "rp_blit" - the register is used inside renderpass or blits
15
+
(ib2 for Freedreno)
16
+
17
+
It is expected that register with "cmd" usage may be written into only at
18
+
the start of the command buffer (ib1), while "rp_blit" usage indicates that register
19
+
is either overwritten by renderpass/blit (ib2) or not used if not overwritten
20
+
by a particular renderpass/blit.
21
+
-->
22
+
23
+
<!-- these might be same as a5xx -->
24
+
<enum name="a6xx_tile_mode">
25
+
<value name="TILE6_LINEAR" value="0"/>
26
+
<value name="TILE6_2" value="2"/>
27
+
<value name="TILE6_3" value="3"/>
28
+
</enum>
29
+
30
+
<enum name="a6xx_format">
31
+
<value value="0x02" name="FMT6_A8_UNORM"/>
32
+
<value value="0x03" name="FMT6_8_UNORM"/>
33
+
<value value="0x04" name="FMT6_8_SNORM"/>
34
+
<value value="0x05" name="FMT6_8_UINT"/>
35
+
<value value="0x06" name="FMT6_8_SINT"/>
36
+
37
+
<value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
38
+
<value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
39
+
<value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
40
+
<value value="0x0e" name="FMT6_5_6_5_UNORM"/>
41
+
42
+
<value value="0x0f" name="FMT6_8_8_UNORM"/>
43
+
<value value="0x10" name="FMT6_8_8_SNORM"/>
44
+
<value value="0x11" name="FMT6_8_8_UINT"/>
45
+
<value value="0x12" name="FMT6_8_8_SINT"/>
46
+
<value value="0x13" name="FMT6_L8_A8_UNORM"/>
47
+
48
+
<value value="0x15" name="FMT6_16_UNORM"/>
49
+
<value value="0x16" name="FMT6_16_SNORM"/>
50
+
<value value="0x17" name="FMT6_16_FLOAT"/>
51
+
<value value="0x18" name="FMT6_16_UINT"/>
52
+
<value value="0x19" name="FMT6_16_SINT"/>
53
+
54
+
<value value="0x21" name="FMT6_8_8_8_UNORM"/>
55
+
<value value="0x22" name="FMT6_8_8_8_SNORM"/>
56
+
<value value="0x23" name="FMT6_8_8_8_UINT"/>
57
+
<value value="0x24" name="FMT6_8_8_8_SINT"/>
58
+
59
+
<value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
60
+
<value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
61
+
<value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
62
+
<value value="0x33" name="FMT6_8_8_8_8_UINT"/>
63
+
<value value="0x34" name="FMT6_8_8_8_8_SINT"/>
64
+
65
+
<value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
66
+
67
+
<value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
68
+
<value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
69
+
<value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
70
+
<value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
71
+
<value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
72
+
73
+
<value value="0x42" name="FMT6_11_11_10_FLOAT"/>
74
+
75
+
<value value="0x43" name="FMT6_16_16_UNORM"/>
76
+
<value value="0x44" name="FMT6_16_16_SNORM"/>
77
+
<value value="0x45" name="FMT6_16_16_FLOAT"/>
78
+
<value value="0x46" name="FMT6_16_16_UINT"/>
79
+
<value value="0x47" name="FMT6_16_16_SINT"/>
80
+
81
+
<value value="0x48" name="FMT6_32_UNORM"/>
82
+
<value value="0x49" name="FMT6_32_SNORM"/>
83
+
<value value="0x4a" name="FMT6_32_FLOAT"/>
84
+
<value value="0x4b" name="FMT6_32_UINT"/>
85
+
<value value="0x4c" name="FMT6_32_SINT"/>
86
+
<value value="0x4d" name="FMT6_32_FIXED"/>
87
+
88
+
<value value="0x58" name="FMT6_16_16_16_UNORM"/>
89
+
<value value="0x59" name="FMT6_16_16_16_SNORM"/>
90
+
<value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
91
+
<value value="0x5b" name="FMT6_16_16_16_UINT"/>
92
+
<value value="0x5c" name="FMT6_16_16_16_SINT"/>
93
+
94
+
<value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
95
+
<value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
96
+
<value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
97
+
<value value="0x63" name="FMT6_16_16_16_16_UINT"/>
98
+
<value value="0x64" name="FMT6_16_16_16_16_SINT"/>
99
+
100
+
<value value="0x65" name="FMT6_32_32_UNORM"/>
101
+
<value value="0x66" name="FMT6_32_32_SNORM"/>
102
+
<value value="0x67" name="FMT6_32_32_FLOAT"/>
103
+
<value value="0x68" name="FMT6_32_32_UINT"/>
104
+
<value value="0x69" name="FMT6_32_32_SINT"/>
105
+
<value value="0x6a" name="FMT6_32_32_FIXED"/>
106
+
107
+
<value value="0x70" name="FMT6_32_32_32_UNORM"/>
108
+
<value value="0x71" name="FMT6_32_32_32_SNORM"/>
109
+
<value value="0x72" name="FMT6_32_32_32_UINT"/>
110
+
<value value="0x73" name="FMT6_32_32_32_SINT"/>
111
+
<value value="0x74" name="FMT6_32_32_32_FLOAT"/>
112
+
<value value="0x75" name="FMT6_32_32_32_FIXED"/>
113
+
114
+
<value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
115
+
<value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
116
+
<value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
117
+
<value value="0x83" name="FMT6_32_32_32_32_UINT"/>
118
+
<value value="0x84" name="FMT6_32_32_32_32_SINT"/>
119
+
<value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
120
+
121
+
<value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY -->
122
+
<value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV -->
123
+
<value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 -->
124
+
<value value="0x8f" name="FMT6_NV21"/>
125
+
<value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 -->
126
+
127
+
<value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
128
+
129
+
<!-- Note: tiling/UBWC for these may be different from equivalent formats
130
+
For example FMT6_NV12_Y is not compatible with FMT6_8_UNORM
131
+
-->
132
+
<value value="0x94" name="FMT6_NV12_Y"/>
133
+
<value value="0x95" name="FMT6_NV12_UV"/>
134
+
<value value="0x96" name="FMT6_NV12_VU"/>
135
+
<value value="0x97" name="FMT6_NV12_4R"/>
136
+
<value value="0x98" name="FMT6_NV12_4R_Y"/>
137
+
<value value="0x99" name="FMT6_NV12_4R_UV"/>
138
+
<value value="0x9a" name="FMT6_P010"/>
139
+
<value value="0x9b" name="FMT6_P010_Y"/>
140
+
<value value="0x9c" name="FMT6_P010_UV"/>
141
+
<value value="0x9d" name="FMT6_TP10"/>
142
+
<value value="0x9e" name="FMT6_TP10_Y"/>
143
+
<value value="0x9f" name="FMT6_TP10_UV"/>
144
+
145
+
<value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
146
+
147
+
<value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
148
+
<value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
149
+
<value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
150
+
<value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
151
+
<value value="0xaf" name="FMT6_ETC1"/>
152
+
<value value="0xb0" name="FMT6_ETC2_RGB8"/>
153
+
<value value="0xb1" name="FMT6_ETC2_RGBA8"/>
154
+
<value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
155
+
<value value="0xb3" name="FMT6_DXT1"/>
156
+
<value value="0xb4" name="FMT6_DXT3"/>
157
+
<value value="0xb5" name="FMT6_DXT5"/>
158
+
<value value="0xb7" name="FMT6_RGTC1_UNORM"/>
159
+
<value value="0xb8" name="FMT6_RGTC1_SNORM"/>
160
+
<value value="0xbb" name="FMT6_RGTC2_UNORM"/>
161
+
<value value="0xbc" name="FMT6_RGTC2_SNORM"/>
162
+
<value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
163
+
<value value="0xbf" name="FMT6_BPTC_FLOAT"/>
164
+
<value value="0xc0" name="FMT6_BPTC"/>
165
+
<value value="0xc1" name="FMT6_ASTC_4x4"/>
166
+
<value value="0xc2" name="FMT6_ASTC_5x4"/>
167
+
<value value="0xc3" name="FMT6_ASTC_5x5"/>
168
+
<value value="0xc4" name="FMT6_ASTC_6x5"/>
169
+
<value value="0xc5" name="FMT6_ASTC_6x6"/>
170
+
<value value="0xc6" name="FMT6_ASTC_8x5"/>
171
+
<value value="0xc7" name="FMT6_ASTC_8x6"/>
172
+
<value value="0xc8" name="FMT6_ASTC_8x8"/>
173
+
<value value="0xc9" name="FMT6_ASTC_10x5"/>
174
+
<value value="0xca" name="FMT6_ASTC_10x6"/>
175
+
<value value="0xcb" name="FMT6_ASTC_10x8"/>
176
+
<value value="0xcc" name="FMT6_ASTC_10x10"/>
177
+
<value value="0xcd" name="FMT6_ASTC_12x10"/>
178
+
<value value="0xce" name="FMT6_ASTC_12x12"/>
179
+
180
+
<!-- for sampling stencil (integer, 2nd channel), not available on a630 -->
181
+
<value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/>
182
+
183
+
<!-- Not a hw enum, used internally in driver -->
184
+
<value value="0xff" name="FMT6_NONE"/>
185
+
186
+
</enum>
187
+
188
+
<!-- probably same as a5xx -->
189
+
<enum name="a6xx_polygon_mode">
190
+
<value name="POLYMODE6_POINTS" value="1"/>
191
+
<value name="POLYMODE6_LINES" value="2"/>
192
+
<value name="POLYMODE6_TRIANGLES" value="3"/>
193
+
</enum>
194
+
195
+
<enum name="a6xx_depth_format">
196
+
<value name="DEPTH6_NONE" value="0"/>
197
+
<value name="DEPTH6_16" value="1"/>
198
+
<value name="DEPTH6_24_8" value="2"/>
199
+
<value name="DEPTH6_32" value="4"/>
200
+
</enum>
201
+
202
+
<bitset name="a6x_cp_protect" inline="yes">
203
+
<bitfield name="BASE_ADDR" low="0" high="17"/>
204
+
<bitfield name="MASK_LEN" low="18" high="30"/>
205
+
<bitfield name="READ" pos="31" type="boolean"/>
206
+
</bitset>
207
+
208
+
<enum name="a6xx_shader_id">
209
+
<value value="0x9" name="A6XX_TP0_TMO_DATA"/>
210
+
<value value="0xa" name="A6XX_TP0_SMO_DATA"/>
211
+
<value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
212
+
<value value="0x19" name="A6XX_TP1_TMO_DATA"/>
213
+
<value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
214
+
<value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
215
+
<value value="0x29" name="A6XX_SP_INST_DATA"/>
216
+
<value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
217
+
<value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
218
+
<value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
219
+
<value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
220
+
<value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
221
+
<value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
222
+
<value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
223
+
<value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
224
+
<value value="0x32" name="A6XX_SP_UAV_DATA"/>
225
+
<value value="0x33" name="A6XX_SP_INST_TAG"/>
226
+
<value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
227
+
<value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
228
+
<value value="0x36" name="A6XX_SP_SMO_TAG"/>
229
+
<value value="0x37" name="A6XX_SP_STATE_DATA"/>
230
+
<value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
231
+
<value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
232
+
<value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
233
+
<value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
234
+
<value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
235
+
<value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
236
+
<value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
237
+
<value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
238
+
<value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
239
+
<value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
240
+
<value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
241
+
<value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
242
+
<value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
243
+
<value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
244
+
<value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
245
+
<value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
246
+
<value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
247
+
<value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
248
+
<value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
249
+
<value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
250
+
<value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
251
+
<value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
252
+
<value value="0x70" name="A6XX_SP_LB_6_DATA"/>
253
+
<value value="0x71" name="A6XX_SP_LB_7_DATA"/>
254
+
<value value="0x73" name="A6XX_HLSQ_INST_RAM_1"/>
255
+
</enum>
256
+
257
+
<enum name="a7xx_statetype_id">
258
+
<value value="0" name="A7XX_TP0_NCTX_REG"/>
259
+
<value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/>
260
+
<value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/>
261
+
<value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/>
262
+
<value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/>
263
+
<value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/>
264
+
<value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/>
265
+
<value value="9" name="A7XX_TP0_TMO_DATA"/>
266
+
<value value="10" name="A7XX_TP0_SMO_DATA"/>
267
+
<value value="11" name="A7XX_TP0_MIPMAP_BASE_DATA"/>
268
+
<value value="32" name="A7XX_SP_NCTX_REG"/>
269
+
<value value="33" name="A7XX_SP_CTX0_3D_CVS_REG"/>
270
+
<value value="34" name="A7XX_SP_CTX0_3D_CPS_REG"/>
271
+
<value value="35" name="A7XX_SP_CTX1_3D_CVS_REG"/>
272
+
<value value="36" name="A7XX_SP_CTX1_3D_CPS_REG"/>
273
+
<value value="37" name="A7XX_SP_CTX2_3D_CPS_REG"/>
274
+
<value value="38" name="A7XX_SP_CTX3_3D_CPS_REG"/>
275
+
<value value="39" name="A7XX_SP_INST_DATA"/>
276
+
<value value="40" name="A7XX_SP_INST_DATA_1"/>
277
+
<value value="41" name="A7XX_SP_LB_0_DATA"/>
278
+
<value value="42" name="A7XX_SP_LB_1_DATA"/>
279
+
<value value="43" name="A7XX_SP_LB_2_DATA"/>
280
+
<value value="44" name="A7XX_SP_LB_3_DATA"/>
281
+
<value value="45" name="A7XX_SP_LB_4_DATA"/>
282
+
<value value="46" name="A7XX_SP_LB_5_DATA"/>
283
+
<value value="47" name="A7XX_SP_LB_6_DATA"/>
284
+
<value value="48" name="A7XX_SP_LB_7_DATA"/>
285
+
<value value="49" name="A7XX_SP_CB_RAM"/>
286
+
<value value="50" name="A7XX_SP_LB_13_DATA"/>
287
+
<value value="51" name="A7XX_SP_LB_14_DATA"/>
288
+
<value value="52" name="A7XX_SP_INST_TAG"/>
289
+
<value value="53" name="A7XX_SP_INST_DATA_2"/>
290
+
<value value="54" name="A7XX_SP_TMO_TAG"/>
291
+
<value value="55" name="A7XX_SP_SMO_TAG"/>
292
+
<value value="56" name="A7XX_SP_STATE_DATA"/>
293
+
<value value="57" name="A7XX_SP_HWAVE_RAM"/>
294
+
<value value="58" name="A7XX_SP_L0_INST_BUF"/>
295
+
<value value="59" name="A7XX_SP_LB_8_DATA"/>
296
+
<value value="60" name="A7XX_SP_LB_9_DATA"/>
297
+
<value value="61" name="A7XX_SP_LB_10_DATA"/>
298
+
<value value="62" name="A7XX_SP_LB_11_DATA"/>
299
+
<value value="63" name="A7XX_SP_LB_12_DATA"/>
300
+
<value value="64" name="A7XX_HLSQ_DATAPATH_DSTR_META"/>
301
+
<value value="67" name="A7XX_HLSQ_L2STC_TAG_RAM"/>
302
+
<value value="68" name="A7XX_HLSQ_L2STC_INFO_CMD"/>
303
+
<value value="69" name="A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/>
304
+
<value value="70" name="A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/>
305
+
<value value="71" name="A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/>
306
+
<value value="72" name="A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/>
307
+
<value value="73" name="A7XX_HLSQ_CHUNK_CVS_RAM"/>
308
+
<value value="74" name="A7XX_HLSQ_CHUNK_CPS_RAM"/>
309
+
<value value="75" name="A7XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
310
+
<value value="76" name="A7XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
311
+
<value value="77" name="A7XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
312
+
<value value="78" name="A7XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
313
+
<value value="79" name="A7XX_HLSQ_CVS_MISC_RAM"/>
314
+
<value value="80" name="A7XX_HLSQ_CPS_MISC_RAM"/>
315
+
<value value="81" name="A7XX_HLSQ_CPS_MISC_RAM_1"/>
316
+
<value value="82" name="A7XX_HLSQ_INST_RAM"/>
317
+
<value value="83" name="A7XX_HLSQ_GFX_CVS_CONST_RAM"/>
318
+
<value value="84" name="A7XX_HLSQ_GFX_CPS_CONST_RAM"/>
319
+
<value value="85" name="A7XX_HLSQ_CVS_MISC_RAM_TAG"/>
320
+
<value value="86" name="A7XX_HLSQ_CPS_MISC_RAM_TAG"/>
321
+
<value value="87" name="A7XX_HLSQ_INST_RAM_TAG"/>
322
+
<value value="88" name="A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
323
+
<value value="89" name="A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
324
+
<value value="90" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM"/>
325
+
<value value="91" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/>
326
+
<value value="92" name="A7XX_HLSQ_INST_RAM_1"/>
327
+
<value value="93" name="A7XX_HLSQ_STPROC_META"/>
328
+
<value value="94" name="A7XX_HLSQ_BV_BE_META"/>
329
+
<value value="95" name="A7XX_HLSQ_INST_RAM_2"/>
330
+
<value value="96" name="A7XX_HLSQ_DATAPATH_META"/>
331
+
<value value="97" name="A7XX_HLSQ_FRONTEND_META"/>
332
+
<value value="98" name="A7XX_HLSQ_INDIRECT_META"/>
333
+
<value value="99" name="A7XX_HLSQ_BACKEND_META"/>
334
+
</enum>
335
+
336
+
<enum name="a6xx_debugbus_id">
337
+
<value value="0x1" name="A6XX_DBGBUS_CP"/>
338
+
<value value="0x2" name="A6XX_DBGBUS_RBBM"/>
339
+
<value value="0x3" name="A6XX_DBGBUS_VBIF"/>
340
+
<value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
341
+
<value value="0x5" name="A6XX_DBGBUS_UCHE"/>
342
+
<value value="0x6" name="A6XX_DBGBUS_DPM"/>
343
+
<value value="0x7" name="A6XX_DBGBUS_TESS"/>
344
+
<value value="0x8" name="A6XX_DBGBUS_PC"/>
345
+
<value value="0x9" name="A6XX_DBGBUS_VFDP"/>
346
+
<value value="0xa" name="A6XX_DBGBUS_VPC"/>
347
+
<value value="0xb" name="A6XX_DBGBUS_TSE"/>
348
+
<value value="0xc" name="A6XX_DBGBUS_RAS"/>
349
+
<value value="0xd" name="A6XX_DBGBUS_VSC"/>
350
+
<value value="0xe" name="A6XX_DBGBUS_COM"/>
351
+
<value value="0x10" name="A6XX_DBGBUS_LRZ"/>
352
+
<value value="0x11" name="A6XX_DBGBUS_A2D"/>
353
+
<value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
354
+
<value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
355
+
<value value="0x14" name="A6XX_DBGBUS_RBP"/>
356
+
<value value="0x15" name="A6XX_DBGBUS_DCS"/>
357
+
<value value="0x16" name="A6XX_DBGBUS_DBGC"/>
358
+
<value value="0x17" name="A6XX_DBGBUS_CX"/>
359
+
<value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
360
+
<value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
361
+
<value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
362
+
<value value="0x1d" name="A6XX_DBGBUS_GPC"/>
363
+
<value value="0x1e" name="A6XX_DBGBUS_LARC"/>
364
+
<value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
365
+
<value value="0x20" name="A6XX_DBGBUS_RB_0"/>
366
+
<value value="0x21" name="A6XX_DBGBUS_RB_1"/>
367
+
<value value="0x22" name="A6XX_DBGBUS_RB_2"/>
368
+
<value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
369
+
<value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
370
+
<value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
371
+
<value value="0x2a" name="A6XX_DBGBUS_CCU_2"/>
372
+
<value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
373
+
<value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
374
+
<value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
375
+
<value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
376
+
<value value="0x3c" name="A6XX_DBGBUS_VFD_4"/>
377
+
<value value="0x3d" name="A6XX_DBGBUS_VFD_5"/>
378
+
<value value="0x40" name="A6XX_DBGBUS_SP_0"/>
379
+
<value value="0x41" name="A6XX_DBGBUS_SP_1"/>
380
+
<value value="0x42" name="A6XX_DBGBUS_SP_2"/>
381
+
<value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
382
+
<value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
383
+
<value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
384
+
<value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
385
+
<value value="0x4c" name="A6XX_DBGBUS_TPL1_4"/>
386
+
<value value="0x4d" name="A6XX_DBGBUS_TPL1_5"/>
387
+
<value value="0x58" name="A6XX_DBGBUS_SPTP_0"/>
388
+
<value value="0x59" name="A6XX_DBGBUS_SPTP_1"/>
389
+
<value value="0x5a" name="A6XX_DBGBUS_SPTP_2"/>
390
+
<value value="0x5b" name="A6XX_DBGBUS_SPTP_3"/>
391
+
<value value="0x5c" name="A6XX_DBGBUS_SPTP_4"/>
392
+
<value value="0x5d" name="A6XX_DBGBUS_SPTP_5"/>
393
+
</enum>
394
+
395
+
<enum name="a7xx_state_location">
396
+
<value value="0" name="A7XX_HLSQ_STATE"/>
397
+
<value value="1" name="A7XX_HLSQ_DP"/>
398
+
<value value="2" name="A7XX_SP_TOP"/>
399
+
<value value="3" name="A7XX_USPTP"/>
400
+
</enum>
401
+
402
+
<enum name="a7xx_pipe">
403
+
<value value="0" name="A7XX_PIPE_NONE"/>
404
+
<value value="1" name="A7XX_PIPE_BR"/>
405
+
<value value="2" name="A7XX_PIPE_BV"/>
406
+
<value value="3" name="A7XX_PIPE_LPAC"/>
407
+
</enum>
408
+
409
+
<enum name="a7xx_cluster">
410
+
<value value="0" name="A7XX_CLUSTER_NONE"/>
411
+
<value value="1" name="A7XX_CLUSTER_FE"/>
412
+
<value value="2" name="A7XX_CLUSTER_SP_VS"/>
413
+
<value value="3" name="A7XX_CLUSTER_PC_VS"/>
414
+
<value value="4" name="A7XX_CLUSTER_GRAS"/>
415
+
<value value="5" name="A7XX_CLUSTER_SP_PS"/>
416
+
<value value="6" name="A7XX_CLUSTER_VPC_PS"/>
417
+
<value value="7" name="A7XX_CLUSTER_PS"/>
418
+
</enum>
419
+
420
+
<enum name="a7xx_debugbus_id">
421
+
<value value="1" name="A7XX_DBGBUS_CP_0_0"/>
422
+
<value value="2" name="A7XX_DBGBUS_CP_0_1"/>
423
+
<value value="3" name="A7XX_DBGBUS_RBBM"/>
424
+
<value value="5" name="A7XX_DBGBUS_GBIF_GX"/>
425
+
<value value="6" name="A7XX_DBGBUS_GBIF_CX"/>
426
+
<value value="7" name="A7XX_DBGBUS_HLSQ"/>
427
+
<value value="9" name="A7XX_DBGBUS_UCHE_0"/>
428
+
<value value="10" name="A7XX_DBGBUS_UCHE_1"/>
429
+
<value value="13" name="A7XX_DBGBUS_TESS_BR"/>
430
+
<value value="14" name="A7XX_DBGBUS_TESS_BV"/>
431
+
<value value="17" name="A7XX_DBGBUS_PC_BR"/>
432
+
<value value="18" name="A7XX_DBGBUS_PC_BV"/>
433
+
<value value="21" name="A7XX_DBGBUS_VFDP_BR"/>
434
+
<value value="22" name="A7XX_DBGBUS_VFDP_BV"/>
435
+
<value value="25" name="A7XX_DBGBUS_VPC_BR"/>
436
+
<value value="26" name="A7XX_DBGBUS_VPC_BV"/>
437
+
<value value="29" name="A7XX_DBGBUS_TSE_BR"/>
438
+
<value value="30" name="A7XX_DBGBUS_TSE_BV"/>
439
+
<value value="33" name="A7XX_DBGBUS_RAS_BR"/>
440
+
<value value="34" name="A7XX_DBGBUS_RAS_BV"/>
441
+
<value value="37" name="A7XX_DBGBUS_VSC"/>
442
+
<value value="39" name="A7XX_DBGBUS_COM_0"/>
443
+
<value value="43" name="A7XX_DBGBUS_LRZ_BR"/>
444
+
<value value="44" name="A7XX_DBGBUS_LRZ_BV"/>
445
+
<value value="47" name="A7XX_DBGBUS_UFC_0"/>
446
+
<value value="48" name="A7XX_DBGBUS_UFC_1"/>
447
+
<value value="55" name="A7XX_DBGBUS_GMU_GX"/>
448
+
<value value="59" name="A7XX_DBGBUS_DBGC"/>
449
+
<value value="60" name="A7XX_DBGBUS_CX"/>
450
+
<value value="61" name="A7XX_DBGBUS_GMU_CX"/>
451
+
<value value="62" name="A7XX_DBGBUS_GPC_BR"/>
452
+
<value value="63" name="A7XX_DBGBUS_GPC_BV"/>
453
+
<value value="66" name="A7XX_DBGBUS_LARC"/>
454
+
<value value="68" name="A7XX_DBGBUS_HLSQ_SPTP"/>
455
+
<value value="70" name="A7XX_DBGBUS_RB_0"/>
456
+
<value value="71" name="A7XX_DBGBUS_RB_1"/>
457
+
<value value="72" name="A7XX_DBGBUS_RB_2"/>
458
+
<value value="73" name="A7XX_DBGBUS_RB_3"/>
459
+
<value value="74" name="A7XX_DBGBUS_RB_4"/>
460
+
<value value="75" name="A7XX_DBGBUS_RB_5"/>
461
+
<value value="102" name="A7XX_DBGBUS_UCHE_WRAPPER"/>
462
+
<value value="106" name="A7XX_DBGBUS_CCU_0"/>
463
+
<value value="107" name="A7XX_DBGBUS_CCU_1"/>
464
+
<value value="108" name="A7XX_DBGBUS_CCU_2"/>
465
+
<value value="109" name="A7XX_DBGBUS_CCU_3"/>
466
+
<value value="110" name="A7XX_DBGBUS_CCU_4"/>
467
+
<value value="111" name="A7XX_DBGBUS_CCU_5"/>
468
+
<value value="138" name="A7XX_DBGBUS_VFD_BR_0"/>
469
+
<value value="139" name="A7XX_DBGBUS_VFD_BR_1"/>
470
+
<value value="140" name="A7XX_DBGBUS_VFD_BR_2"/>
471
+
<value value="141" name="A7XX_DBGBUS_VFD_BR_3"/>
472
+
<value value="142" name="A7XX_DBGBUS_VFD_BR_4"/>
473
+
<value value="143" name="A7XX_DBGBUS_VFD_BR_5"/>
474
+
<value value="144" name="A7XX_DBGBUS_VFD_BR_6"/>
475
+
<value value="145" name="A7XX_DBGBUS_VFD_BR_7"/>
476
+
<value value="202" name="A7XX_DBGBUS_VFD_BV_0"/>
477
+
<value value="203" name="A7XX_DBGBUS_VFD_BV_1"/>
478
+
<value value="204" name="A7XX_DBGBUS_VFD_BV_2"/>
479
+
<value value="205" name="A7XX_DBGBUS_VFD_BV_3"/>
480
+
<value value="234" name="A7XX_DBGBUS_USP_0"/>
481
+
<value value="235" name="A7XX_DBGBUS_USP_1"/>
482
+
<value value="236" name="A7XX_DBGBUS_USP_2"/>
483
+
<value value="237" name="A7XX_DBGBUS_USP_3"/>
484
+
<value value="238" name="A7XX_DBGBUS_USP_4"/>
485
+
<value value="239" name="A7XX_DBGBUS_USP_5"/>
486
+
<value value="266" name="A7XX_DBGBUS_TP_0"/>
487
+
<value value="267" name="A7XX_DBGBUS_TP_1"/>
488
+
<value value="268" name="A7XX_DBGBUS_TP_2"/>
489
+
<value value="269" name="A7XX_DBGBUS_TP_3"/>
490
+
<value value="270" name="A7XX_DBGBUS_TP_4"/>
491
+
<value value="271" name="A7XX_DBGBUS_TP_5"/>
492
+
<value value="272" name="A7XX_DBGBUS_TP_6"/>
493
+
<value value="273" name="A7XX_DBGBUS_TP_7"/>
494
+
<value value="274" name="A7XX_DBGBUS_TP_8"/>
495
+
<value value="275" name="A7XX_DBGBUS_TP_9"/>
496
+
<value value="276" name="A7XX_DBGBUS_TP_10"/>
497
+
<value value="277" name="A7XX_DBGBUS_TP_11"/>
498
+
<value value="330" name="A7XX_DBGBUS_USPTP_0"/>
499
+
<value value="331" name="A7XX_DBGBUS_USPTP_1"/>
500
+
<value value="332" name="A7XX_DBGBUS_USPTP_2"/>
501
+
<value value="333" name="A7XX_DBGBUS_USPTP_3"/>
502
+
<value value="334" name="A7XX_DBGBUS_USPTP_4"/>
503
+
<value value="335" name="A7XX_DBGBUS_USPTP_5"/>
504
+
<value value="336" name="A7XX_DBGBUS_USPTP_6"/>
505
+
<value value="337" name="A7XX_DBGBUS_USPTP_7"/>
506
+
<value value="338" name="A7XX_DBGBUS_USPTP_8"/>
507
+
<value value="339" name="A7XX_DBGBUS_USPTP_9"/>
508
+
<value value="340" name="A7XX_DBGBUS_USPTP_10"/>
509
+
<value value="341" name="A7XX_DBGBUS_USPTP_11"/>
510
+
<value value="396" name="A7XX_DBGBUS_CCHE_0"/>
511
+
<value value="397" name="A7XX_DBGBUS_CCHE_1"/>
512
+
<value value="398" name="A7XX_DBGBUS_CCHE_2"/>
513
+
<value value="408" name="A7XX_DBGBUS_VPC_DSTR_0"/>
514
+
<value value="409" name="A7XX_DBGBUS_VPC_DSTR_1"/>
515
+
<value value="410" name="A7XX_DBGBUS_VPC_DSTR_2"/>
516
+
<value value="411" name="A7XX_DBGBUS_HLSQ_DP_STR_0"/>
517
+
<value value="412" name="A7XX_DBGBUS_HLSQ_DP_STR_1"/>
518
+
<value value="413" name="A7XX_DBGBUS_HLSQ_DP_STR_2"/>
519
+
<value value="414" name="A7XX_DBGBUS_HLSQ_DP_STR_3"/>
520
+
<value value="415" name="A7XX_DBGBUS_HLSQ_DP_STR_4"/>
521
+
<value value="416" name="A7XX_DBGBUS_HLSQ_DP_STR_5"/>
522
+
<value value="443" name="A7XX_DBGBUS_UFC_DSTR_0"/>
523
+
<value value="444" name="A7XX_DBGBUS_UFC_DSTR_1"/>
524
+
<value value="445" name="A7XX_DBGBUS_UFC_DSTR_2"/>
525
+
<value value="446" name="A7XX_DBGBUS_CGC_SUBCORE"/>
526
+
<value value="447" name="A7XX_DBGBUS_CGC_CORE"/>
527
+
</enum>
528
+
529
+
<enum name="a6xx_cp_perfcounter_select">
530
+
<value value="0" name="PERF_CP_ALWAYS_COUNT"/>
531
+
<value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
532
+
<value value="2" name="PERF_CP_BUSY_CYCLES"/>
533
+
<value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
534
+
<value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
535
+
<value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
536
+
<value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
537
+
<value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
538
+
<value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
539
+
<value value="9" name="PERF_CP_MODE_SWITCH"/>
540
+
<value value="10" name="PERF_CP_ZPASS_DONE"/>
541
+
<value value="11" name="PERF_CP_CONTEXT_DONE"/>
542
+
<value value="12" name="PERF_CP_CACHE_FLUSH"/>
543
+
<value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
544
+
<value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
545
+
<value value="15" name="PERF_CP_SQE_IDLE"/>
546
+
<value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
547
+
<value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
548
+
<value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
549
+
<value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
550
+
<value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
551
+
<value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
552
+
<value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
553
+
<value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
554
+
<value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
555
+
<value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
556
+
<value value="26" name="PERF_CP_SQE_T4_EXEC"/>
557
+
<value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
558
+
<value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
559
+
<value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
560
+
<value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
561
+
<value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
562
+
<value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
563
+
<value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
564
+
<value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
565
+
<value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
566
+
<value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
567
+
<value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
568
+
<value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
569
+
<value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
570
+
<value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
571
+
<value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
572
+
<value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
573
+
<value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
574
+
<value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
575
+
<value value="45" name="PERF_CP_PM4_DATA"/>
576
+
<value value="46" name="PERF_CP_PM4_HEADERS"/>
577
+
<value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
578
+
<value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
579
+
<value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
580
+
</enum>
581
+
582
+
<enum name="a6xx_rbbm_perfcounter_select">
583
+
<value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
584
+
<value value="1" name="PERF_RBBM_ALWAYS_ON"/>
585
+
<value value="2" name="PERF_RBBM_TSE_BUSY"/>
586
+
<value value="3" name="PERF_RBBM_RAS_BUSY"/>
587
+
<value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
588
+
<value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
589
+
<value value="6" name="PERF_RBBM_STATUS_MASKED"/>
590
+
<value value="7" name="PERF_RBBM_COM_BUSY"/>
591
+
<value value="8" name="PERF_RBBM_DCOM_BUSY"/>
592
+
<value value="9" name="PERF_RBBM_VBIF_BUSY"/>
593
+
<value value="10" name="PERF_RBBM_VSC_BUSY"/>
594
+
<value value="11" name="PERF_RBBM_TESS_BUSY"/>
595
+
<value value="12" name="PERF_RBBM_UCHE_BUSY"/>
596
+
<value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
597
+
</enum>
598
+
599
+
<enum name="a6xx_pc_perfcounter_select">
600
+
<value value="0" name="PERF_PC_BUSY_CYCLES"/>
601
+
<value value="1" name="PERF_PC_WORKING_CYCLES"/>
602
+
<value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
603
+
<value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
604
+
<value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
605
+
<value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
606
+
<value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
607
+
<value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
608
+
<value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
609
+
<value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
610
+
<value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
611
+
<value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
612
+
<value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
613
+
<value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
614
+
<value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
615
+
<value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
616
+
<value value="16" name="PERF_PC_INSTANCES"/>
617
+
<value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
618
+
<value value="18" name="PERF_PC_DEAD_PRIM"/>
619
+
<value value="19" name="PERF_PC_LIVE_PRIM"/>
620
+
<value value="20" name="PERF_PC_VERTEX_HITS"/>
621
+
<value value="21" name="PERF_PC_IA_VERTICES"/>
622
+
<value value="22" name="PERF_PC_IA_PRIMITIVES"/>
623
+
<value value="23" name="PERF_PC_GS_PRIMITIVES"/>
624
+
<value value="24" name="PERF_PC_HS_INVOCATIONS"/>
625
+
<value value="25" name="PERF_PC_DS_INVOCATIONS"/>
626
+
<value value="26" name="PERF_PC_VS_INVOCATIONS"/>
627
+
<value value="27" name="PERF_PC_GS_INVOCATIONS"/>
628
+
<value value="28" name="PERF_PC_DS_PRIMITIVES"/>
629
+
<value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
630
+
<value value="30" name="PERF_PC_3D_DRAWCALLS"/>
631
+
<value value="31" name="PERF_PC_2D_DRAWCALLS"/>
632
+
<value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
633
+
<value value="33" name="PERF_TESS_BUSY_CYCLES"/>
634
+
<value value="34" name="PERF_TESS_WORKING_CYCLES"/>
635
+
<value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
636
+
<value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
637
+
<value value="37" name="PERF_PC_TSE_TRANSACTION"/>
638
+
<value value="38" name="PERF_PC_TSE_VERTEX"/>
639
+
<value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
640
+
<value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
641
+
<value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
642
+
</enum>
643
+
644
+
<enum name="a6xx_vfd_perfcounter_select">
645
+
<value value="0" name="PERF_VFD_BUSY_CYCLES"/>
646
+
<value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
647
+
<value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
648
+
<value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
649
+
<value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
650
+
<value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
651
+
<value value="6" name="PERF_VFD_RBUFFER_FULL"/>
652
+
<value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
653
+
<value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
654
+
<value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
655
+
<value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
656
+
<value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
657
+
<value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
658
+
<value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
659
+
<value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
660
+
<value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
661
+
<value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
662
+
<value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
663
+
<value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
664
+
<value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
665
+
<value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
666
+
<value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
667
+
<value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
668
+
</enum>
669
+
670
+
<enum name="a6xx_hlsq_perfcounter_select">
671
+
<value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
672
+
<value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
673
+
<value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
674
+
<value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
675
+
<value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
676
+
<value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
677
+
<value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
678
+
<value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
679
+
<value value="8" name="PERF_HLSQ_QUADS"/>
680
+
<value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
681
+
<value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
682
+
<value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
683
+
<value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
684
+
<value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
685
+
<value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
686
+
<value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
687
+
<value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
688
+
<value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
689
+
<value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
690
+
<value value="19" name="PERF_HLSQ_PIXELS"/>
691
+
<value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
692
+
</enum>
693
+
694
+
<enum name="a6xx_vpc_perfcounter_select">
695
+
<value value="0" name="PERF_VPC_BUSY_CYCLES"/>
696
+
<value value="1" name="PERF_VPC_WORKING_CYCLES"/>
697
+
<value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
698
+
<value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
699
+
<value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
700
+
<value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
701
+
<value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
702
+
<value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
703
+
<value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
704
+
<value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
705
+
<value value="10" name="PERF_VPC_SP_COMPONENTS"/>
706
+
<value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
707
+
<value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
708
+
<value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
709
+
<value value="14" name="PERF_VPC_LM_TRANSACTION"/>
710
+
<value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
711
+
<value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
712
+
<value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
713
+
<value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
714
+
<value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
715
+
<value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
716
+
<value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
717
+
<value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
718
+
<value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
719
+
<value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
720
+
<value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
721
+
<value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
722
+
<value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
723
+
</enum>
724
+
725
+
<enum name="a6xx_tse_perfcounter_select">
726
+
<value value="0" name="PERF_TSE_BUSY_CYCLES"/>
727
+
<value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
728
+
<value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
729
+
<value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
730
+
<value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
731
+
<value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
732
+
<value value="6" name="PERF_TSE_INPUT_PRIM"/>
733
+
<value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
734
+
<value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
735
+
<value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
736
+
<value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
737
+
<value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
738
+
<value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
739
+
<value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
740
+
<value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
741
+
<value value="15" name="PERF_TSE_CINVOCATION"/>
742
+
<value value="16" name="PERF_TSE_CPRIMITIVES"/>
743
+
<value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
744
+
<value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
745
+
<value value="19" name="PERF_TSE_CLIP_PLANES"/>
746
+
</enum>
747
+
748
+
<enum name="a6xx_ras_perfcounter_select">
749
+
<value value="0" name="PERF_RAS_BUSY_CYCLES"/>
750
+
<value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
751
+
<value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
752
+
<value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
753
+
<value value="4" name="PERF_RAS_SUPER_TILES"/>
754
+
<value value="5" name="PERF_RAS_8X4_TILES"/>
755
+
<value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
756
+
<value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
757
+
<value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
758
+
<value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
759
+
<value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
760
+
<value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
761
+
<value value="12" name="PERF_RAS_BLOCKS"/>
762
+
</enum>
763
+
764
+
<enum name="a6xx_uche_perfcounter_select">
765
+
<value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
766
+
<value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
767
+
<value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
768
+
<value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
769
+
<value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
770
+
<value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
771
+
<value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
772
+
<value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
773
+
<value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
774
+
<value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
775
+
<value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
776
+
<value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
777
+
<value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
778
+
<value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
779
+
<value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
780
+
<value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
781
+
<value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
782
+
<value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
783
+
<value value="18" name="PERF_UCHE_EVICTS"/>
784
+
<value value="19" name="PERF_UCHE_BANK_REQ0"/>
785
+
<value value="20" name="PERF_UCHE_BANK_REQ1"/>
786
+
<value value="21" name="PERF_UCHE_BANK_REQ2"/>
787
+
<value value="22" name="PERF_UCHE_BANK_REQ3"/>
788
+
<value value="23" name="PERF_UCHE_BANK_REQ4"/>
789
+
<value value="24" name="PERF_UCHE_BANK_REQ5"/>
790
+
<value value="25" name="PERF_UCHE_BANK_REQ6"/>
791
+
<value value="26" name="PERF_UCHE_BANK_REQ7"/>
792
+
<value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
793
+
<value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
794
+
<value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
795
+
<value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
796
+
<value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
797
+
<value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
798
+
<value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
799
+
<value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
800
+
<value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
801
+
<value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
802
+
<value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
803
+
<value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
804
+
<value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
805
+
</enum>
806
+
807
+
<enum name="a6xx_tp_perfcounter_select">
808
+
<value value="0" name="PERF_TP_BUSY_CYCLES"/>
809
+
<value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
810
+
<value value="2" name="PERF_TP_LATENCY_CYCLES"/>
811
+
<value value="3" name="PERF_TP_LATENCY_TRANS"/>
812
+
<value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
813
+
<value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
814
+
<value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
815
+
<value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
816
+
<value value="8" name="PERF_TP_SP_TP_TRANS"/>
817
+
<value value="9" name="PERF_TP_TP_SP_TRANS"/>
818
+
<value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
819
+
<value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
820
+
<value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
821
+
<value value="13" name="PERF_TP_QUADS_RECEIVED"/>
822
+
<value value="14" name="PERF_TP_QUADS_OFFSET"/>
823
+
<value value="15" name="PERF_TP_QUADS_SHADOW"/>
824
+
<value value="16" name="PERF_TP_QUADS_ARRAY"/>
825
+
<value value="17" name="PERF_TP_QUADS_GRADIENT"/>
826
+
<value value="18" name="PERF_TP_QUADS_1D"/>
827
+
<value value="19" name="PERF_TP_QUADS_2D"/>
828
+
<value value="20" name="PERF_TP_QUADS_BUFFER"/>
829
+
<value value="21" name="PERF_TP_QUADS_3D"/>
830
+
<value value="22" name="PERF_TP_QUADS_CUBE"/>
831
+
<value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
832
+
<value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
833
+
<value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
834
+
<value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
835
+
<value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
836
+
<value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
837
+
<value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
838
+
<value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
839
+
<value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
840
+
<value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
841
+
<value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
842
+
<value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
843
+
<value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
844
+
<value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
845
+
<value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
846
+
<value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
847
+
<value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
848
+
<value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
849
+
<value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
850
+
<value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
851
+
<value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
852
+
<value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
853
+
<value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
854
+
<value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
855
+
<value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
856
+
<value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
857
+
<value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
858
+
<value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
859
+
<value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
860
+
<value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
861
+
<value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
862
+
<value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
863
+
<value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
864
+
<value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
865
+
</enum>
866
+
867
+
<enum name="a6xx_sp_perfcounter_select">
868
+
<value value="0" name="PERF_SP_BUSY_CYCLES"/>
869
+
<value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
870
+
<value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
871
+
<value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
872
+
<value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
873
+
<value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
874
+
<value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
875
+
<value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
876
+
<value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
877
+
<value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
878
+
<value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
879
+
<value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
880
+
<value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
881
+
<value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
882
+
<value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
883
+
<value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
884
+
<value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
885
+
<value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
886
+
<value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
887
+
<value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
888
+
<value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
889
+
<value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
890
+
<value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
891
+
<value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
892
+
<value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
893
+
<value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
894
+
<value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
895
+
<value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
896
+
<value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
897
+
<value value="29" name="PERF_SP_LM_ATOMICS"/>
898
+
<value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
899
+
<value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
900
+
<value value="32" name="PERF_SP_GM_ATOMICS"/>
901
+
<value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
902
+
<value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
903
+
<value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
904
+
<value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
905
+
<value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
906
+
<value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
907
+
<value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
908
+
<value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
909
+
<value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
910
+
<value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
911
+
<value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
912
+
<value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
913
+
<value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
914
+
<value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
915
+
<value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
916
+
<value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
917
+
<value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
918
+
<value value="50" name="PERF_SP_PIXELS_KILLED"/>
919
+
<value value="51" name="PERF_SP_ICL1_REQUESTS"/>
920
+
<value value="52" name="PERF_SP_ICL1_MISSES"/>
921
+
<value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
922
+
<value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
923
+
<value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
924
+
<value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
925
+
<value value="57" name="PERF_SP_GPR_READ"/>
926
+
<value value="58" name="PERF_SP_GPR_WRITE"/>
927
+
<value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
928
+
<value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
929
+
<value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
930
+
<value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
931
+
<value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
932
+
<value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
933
+
<value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
934
+
<value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
935
+
<value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
936
+
<value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
937
+
<value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
938
+
<value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
939
+
<value value="71" name="PERF_SP_WORKING_EU"/>
940
+
<value value="72" name="PERF_SP_ANY_EU_WORKING"/>
941
+
<value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
942
+
<value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
943
+
<value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
944
+
<value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
945
+
<value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
946
+
<value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
947
+
<value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
948
+
<value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
949
+
<value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
950
+
<value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
951
+
<value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
952
+
<value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
953
+
</enum>
954
+
955
+
<enum name="a6xx_rb_perfcounter_select">
956
+
<value value="0" name="PERF_RB_BUSY_CYCLES"/>
957
+
<value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
958
+
<value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
959
+
<value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
960
+
<value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
961
+
<value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
962
+
<value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
963
+
<value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
964
+
<value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
965
+
<value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
966
+
<value value="10" name="PERF_RB_Z_WORKLOAD"/>
967
+
<value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
968
+
<value value="12" name="PERF_RB_Z_READ"/>
969
+
<value value="13" name="PERF_RB_Z_WRITE"/>
970
+
<value value="14" name="PERF_RB_C_READ"/>
971
+
<value value="15" name="PERF_RB_C_WRITE"/>
972
+
<value value="16" name="PERF_RB_TOTAL_PASS"/>
973
+
<value value="17" name="PERF_RB_Z_PASS"/>
974
+
<value value="18" name="PERF_RB_Z_FAIL"/>
975
+
<value value="19" name="PERF_RB_S_FAIL"/>
976
+
<value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
977
+
<value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
978
+
<value value="22" name="PERF_RB_PS_INVOCATIONS"/>
979
+
<value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
980
+
<value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
981
+
<value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
982
+
<value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
983
+
<value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
984
+
<value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
985
+
<value value="29" name="PERF_RB_3D_PIXELS"/>
986
+
<value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
987
+
<value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
988
+
<value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
989
+
<value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
990
+
<value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
991
+
<value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
992
+
<value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
993
+
<value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
994
+
<value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
995
+
<value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
996
+
<value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
997
+
<value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
998
+
<value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
999
+
<value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
1000
+
<value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
1001
+
<value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
1002
+
<value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
1003
+
<value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
1004
+
</enum>
1005
+
1006
+
<enum name="a6xx_vsc_perfcounter_select">
1007
+
<value value="0" name="PERF_VSC_BUSY_CYCLES"/>
1008
+
<value value="1" name="PERF_VSC_WORKING_CYCLES"/>
1009
+
<value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
1010
+
<value value="3" name="PERF_VSC_EOT_NUM"/>
1011
+
<value value="4" name="PERF_VSC_INPUT_TILES"/>
1012
+
</enum>
1013
+
1014
+
<enum name="a6xx_ccu_perfcounter_select">
1015
+
<value value="0" name="PERF_CCU_BUSY_CYCLES"/>
1016
+
<value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
1017
+
<value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
1018
+
<value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
1019
+
<value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
1020
+
<value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
1021
+
<value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
1022
+
<value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
1023
+
<value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
1024
+
<value value="9" name="PERF_CCU_GMEM_READ"/>
1025
+
<value value="10" name="PERF_CCU_GMEM_WRITE"/>
1026
+
<value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
1027
+
<value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
1028
+
<value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
1029
+
<value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
1030
+
<value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
1031
+
<value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
1032
+
<value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
1033
+
<value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
1034
+
<value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
1035
+
<value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
1036
+
<value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
1037
+
<value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
1038
+
<value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
1039
+
<value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
1040
+
<value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
1041
+
<value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
1042
+
<value value="27" name="PERF_CCU_2D_RD_REQ"/>
1043
+
<value value="28" name="PERF_CCU_2D_WR_REQ"/>
1044
+
</enum>
1045
+
1046
+
<enum name="a6xx_lrz_perfcounter_select">
1047
+
<value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
1048
+
<value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
1049
+
<value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
1050
+
<value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
1051
+
<value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
1052
+
<value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
1053
+
<value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
1054
+
<value value="7" name="PERF_LRZ_LRZ_READ"/>
1055
+
<value value="8" name="PERF_LRZ_LRZ_WRITE"/>
1056
+
<value value="9" name="PERF_LRZ_READ_LATENCY"/>
1057
+
<value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
1058
+
<value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
1059
+
<value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
1060
+
<value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
1061
+
<value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
1062
+
<value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
1063
+
<value value="16" name="PERF_LRZ_TILE_KILLED"/>
1064
+
<value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
1065
+
<value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
1066
+
<value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
1067
+
<value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
1068
+
<value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
1069
+
<value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
1070
+
<value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
1071
+
<value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
1072
+
<value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
1073
+
<value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
1074
+
<value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
1075
+
</enum>
1076
+
1077
+
<enum name="a6xx_cmp_perfcounter_select">
1078
+
<value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
1079
+
<value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
1080
+
<value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
1081
+
<value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
1082
+
<value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
1083
+
<value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
1084
+
<value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
1085
+
<value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
1086
+
<value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
1087
+
<value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
1088
+
<value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
1089
+
<value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
1090
+
<value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
1091
+
<value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
1092
+
<value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
1093
+
<value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
1094
+
<value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
1095
+
<value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
1096
+
<value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
1097
+
<value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
1098
+
<value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
1099
+
<value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
1100
+
<value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
1101
+
<value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
1102
+
<value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
1103
+
<value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
1104
+
<value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
1105
+
<value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
1106
+
<value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
1107
+
<value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
1108
+
<value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
1109
+
<value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
1110
+
<value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
1111
+
<value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
1112
+
<value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
1113
+
<value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
1114
+
<value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
1115
+
<value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
1116
+
<value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
1117
+
<value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
1118
+
</enum>
1119
+
1120
+
<!--
1121
+
Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
1122
+
component type/size, so I think it relates to internal format used for
1123
+
blending? The one exception is that 16b unorm and 32b float use the
1124
+
same value... maybe 16b unorm is uncommon enough that it was just easier
1125
+
to upconvert to 32b float internally?
1126
+
1127
+
8b unorm: 10 (sometimes 0, is the high bit part of something else?)
1128
+
16b unorm: 4
1129
+
1130
+
32b int: 7
1131
+
16b int: 6
1132
+
8b int: 5
1133
+
1134
+
32b float: 4
1135
+
16b float: 3
1136
+
-->
1137
+
<enum name="a6xx_2d_ifmt">
1138
+
<value value="0x10" name="R2D_UNORM8"/>
1139
+
<value value="0x7" name="R2D_INT32"/>
1140
+
<value value="0x6" name="R2D_INT16"/>
1141
+
<value value="0x5" name="R2D_INT8"/>
1142
+
<value value="0x4" name="R2D_FLOAT32"/>
1143
+
<value value="0x3" name="R2D_FLOAT16"/>
1144
+
<value value="0x1" name="R2D_UNORM8_SRGB"/>
1145
+
<value value="0x0" name="R2D_RAW"/>
1146
+
</enum>
1147
+
1148
+
<enum name="a6xx_ztest_mode">
1149
+
<doc>Allow early z-test and early-lrz (if applicable)</doc>
1150
+
<value value="0x0" name="A6XX_EARLY_Z"/>
1151
+
<doc>Disable early z-test and early-lrz test (if applicable)</doc>
1152
+
<value value="0x1" name="A6XX_LATE_Z"/>
1153
+
<doc>
1154
+
A special mode that allows early-lrz test but disables
1155
+
early-z test. Which might sound a bit funny, since
1156
+
lrz-test happens before z-test. But as long as a couple
1157
+
conditions are maintained this allows using lrz-test in
1158
+
cases where fragment shader has kill/discard:
1159
+
1160
+
1) Disable lrz-write in cases where it is uncertain during
1161
+
binning pass that a fragment will pass. Ie. if frag
1162
+
shader has-kill, writes-z, or alpha/stencil test is
1163
+
enabled. (For correctness, lrz-write must be disabled
1164
+
when blend is enabled.) This is analogous to how a
1165
+
z-prepass works.
1166
+
1167
+
2) Disable lrz-write and test if a depth-test direction
1168
+
reversal is detected. Due to condition (1), the contents
1169
+
of the lrz buffer are a conservative estimation of the
1170
+
depth buffer during the draw pass. Meaning that geometry
1171
+
that we know for certain will not be visible will not pass
1172
+
lrz-test. But geometry which may be (or contributes to
1173
+
blend) will pass the lrz-test.
1174
+
1175
+
This allows us to keep early-lrz-test in cases where the frag
1176
+
shader does not write-z (ie. we know the z-value before FS)
1177
+
and does not have side-effects (image/ssbo writes, etc), but
1178
+
does have kill/discard. Which turns out to be a common
1179
+
enough case that it is useful to keep early-lrz test against
1180
+
the conservative lrz buffer to discard fragments that we
1181
+
know will definitely not be visible.
1182
+
</doc>
1183
+
<value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/>
1184
+
<doc>Not a real hw value, used internally by mesa</doc>
1185
+
<value value="0x3" name="A6XX_INVALID_ZTEST"/>
1186
+
</enum>
1187
+
1188
+
<enum name="a6xx_tess_spacing">
1189
+
<value value="0x0" name="TESS_EQUAL"/>
1190
+
<value value="0x2" name="TESS_FRACTIONAL_ODD"/>
1191
+
<value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
1192
+
</enum>
1193
+
<enum name="a6xx_tess_output">
1194
+
<value value="0x0" name="TESS_POINTS"/>
1195
+
<value value="0x1" name="TESS_LINES"/>
1196
+
<value value="0x2" name="TESS_CW_TRIS"/>
1197
+
<value value="0x3" name="TESS_CCW_TRIS"/>
1198
+
</enum>
1199
+
1200
+
<domain name="A6XX" width="32" prefix="variant" varset="chip">
1201
+
<bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip">
1202
+
<bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
1203
+
<bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>
1204
+
<bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/>
1205
+
<bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/>
1206
+
<bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/>
1207
+
<bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
1208
+
<bitfield name="CP_SW" pos="8" type="boolean"/>
1209
+
<bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
1210
+
<bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
1211
+
<bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
1212
+
<bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
1213
+
<bitfield name="CP_IB2" pos="13" type="boolean"/>
1214
+
<bitfield name="CP_IB1" pos="14" type="boolean"/>
1215
+
<bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/>
1216
+
<!-- Same as above but different name??: -->
1217
+
<bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX-"/>
1218
+
<bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX-"/>
1219
+
<bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
1220
+
<bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
1221
+
<bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
1222
+
<bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX-"/>
1223
+
<bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
1224
+
<bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/>
1225
+
<bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
1226
+
<bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
1227
+
<bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
1228
+
<bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
1229
+
<bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/>
1230
+
<bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
1231
+
<bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
1232
+
</bitset>
1233
+
1234
+
<!--
1235
+
Note the _LPAC bits probably *actually* first appeared in a660, but the
1236
+
_BV bits are new in a7xx
1237
+
-->
1238
+
<bitset name="A6XX_CP_INT" varset="chip">
1239
+
<bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
1240
+
<bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/>
1241
+
<bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
1242
+
<bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>
1243
+
<bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
1244
+
<bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/>
1245
+
<bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/>
1246
+
<bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX-"/>
1247
+
<bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX-"/>
1248
+
<bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX-"/>
1249
+
<bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX-"/>
1250
+
<bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX-"/>
1251
+
<bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX-"/>
1252
+
<bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX-"/>
1253
+
<bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX-"/>
1254
+
<bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX-"/>
1255
+
<bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/>
1256
+
</bitset>
1257
+
1258
+
<reg64 offset="0x0800" name="CP_RB_BASE"/>
1259
+
<reg32 offset="0x0802" name="CP_RB_CNTL"/>
1260
+
<reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
1261
+
<reg32 offset="0x0806" name="CP_RB_RPTR"/>
1262
+
<reg32 offset="0x0807" name="CP_RB_WPTR"/>
1263
+
<reg32 offset="0x0808" name="CP_SQE_CNTL"/>
1264
+
<reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
1265
+
<bitfield name="IFPC" pos="0" type="boolean"/>
1266
+
</reg32>
1267
+
<reg32 offset="0x0821" name="CP_HW_FAULT"/>
1268
+
<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT"/>
1269
+
<reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
1270
+
<reg32 offset="0x0825" name="CP_STATUS_1"/>
1271
+
<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
1272
+
<reg32 offset="0x0840" name="CP_MISC_CNTL"/>
1273
+
<reg32 offset="0x0844" name="CP_APRIV_CNTL">
1274
+
<!-- Crashdumper writes -->
1275
+
<bitfield pos="6" name="CDWRITE" type="boolean"/>
1276
+
<!-- Crashdumper reads -->
1277
+
<bitfield pos="5" name="CDREAD" type="boolean"/>
1278
+
1279
+
<!-- 4 is unknown -->
1280
+
1281
+
<!-- RPTR shadow writes -->
1282
+
<bitfield pos="3" name="RBRPWB" type="boolean"/>
1283
+
<!-- Memory accesses from PM4 packets in the ringbuffer -->
1284
+
<bitfield pos="2" name="RBPRIVLEVEL" type="boolean"/>
1285
+
<!-- Ringbuffer reads -->
1286
+
<bitfield pos="1" name="RBFETCH" type="boolean"/>
1287
+
<!-- Instruction cache fetches -->
1288
+
<bitfield pos="0" name="ICACHE" type="boolean"/>
1289
+
</reg32>
1290
+
<!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: -->
1291
+
<reg32 offset="0x08C0" name="CP_PREEMPT_THRESHOLD"/>
1292
+
<!-- all the threshold values seem to be in units of quad-dwords: -->
1293
+
<reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
1294
+
<doc>
1295
+
b0..7 identifies where MRB data starts (and RB data ends)
1296
+
b8.15 identifies where VSD data starts (and MRB data ends)
1297
+
b16..23 identifies where IB1 data starts (and RB data ends)
1298
+
b24..31 identifies where IB2 data starts (and IB1 data ends)
1299
+
</doc>
1300
+
<bitfield name="MRB_START" low="0" high="7" shr="2"/>
1301
+
<bitfield name="VSD_START" low="8" high="15" shr="2"/>
1302
+
<bitfield name="IB1_START" low="16" high="23" shr="2"/>
1303
+
<bitfield name="IB2_START" low="24" high="31" shr="2"/>
1304
+
</reg32>
1305
+
<reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
1306
+
<doc>
1307
+
low bits identify where CP_SET_DRAW_STATE stateobj
1308
+
processing starts (and IB2 data ends). I'm guessing
1309
+
b8 is part of this since (from downstream kgsl):
1310
+
1311
+
/* ROQ sizes are twice as big on a640/a680 than on a630 */
1312
+
if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
1313
+
kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
1314
+
kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
1315
+
} ...
1316
+
</doc>
1317
+
<bitfield name="SDS_START" low="0" high="8" shr="2"/>
1318
+
<!-- total ROQ size: -->
1319
+
<bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
1320
+
</reg32>
1321
+
<reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
1322
+
<reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
1323
+
<reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1324
+
<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
1325
+
<reg32 offset="0x084F" name="CP_PROTECT_CNTL">
1326
+
<bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/>
1327
+
<bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/>
1328
+
<bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/>
1329
+
</reg32>
1330
+
1331
+
<array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
1332
+
<reg32 offset="0x0" name="REG" type="uint"/>
1333
+
</array>
1334
+
<array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
1335
+
<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
1336
+
</array>
1337
+
1338
+
<reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
1339
+
<reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/>
1340
+
<reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>
1341
+
<reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>
1342
+
<reg64 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/>
1343
+
<reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/>
1344
+
<array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>
1345
+
<array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/>
1346
+
<reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/>
1347
+
<reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1348
+
<reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1349
+
<reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1350
+
<reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1351
+
<reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1352
+
<reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1353
+
<reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1354
+
<reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1355
+
<reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1356
+
<reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1357
+
<reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1358
+
<reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1359
+
<reg64 offset="0x0928" name="CP_IB1_BASE"/>
1360
+
<reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1361
+
<reg64 offset="0x092B" name="CP_IB2_BASE"/>
1362
+
<reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1363
+
<!-- SDS == CP_SET_DRAW_STATE: -->
1364
+
<reg64 offset="0x092e" name="CP_SDS_BASE"/>
1365
+
<reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/>
1366
+
<!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
1367
+
<reg64 offset="0x0931" name="CP_MRB_BASE"/>
1368
+
<reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/>
1369
+
<!--
1370
+
VSD == Visibility Stream Decode
1371
+
This is used by CP to read the draw stream and skip empty draws
1372
+
-->
1373
+
<reg64 offset="0x0934" name="CP_VSD_BASE"/>
1374
+
1375
+
<bitset name="a6xx_roq_stat" inline="yes">
1376
+
<bitfield name="RPTR" low="0" high="9"/>
1377
+
<bitfield name="WPTR" low="16" high="25"/>
1378
+
</bitset>
1379
+
<reg32 offset="0x0939" name="CP_ROQ_RB_STAT" type="a6xx_roq_stat"/>
1380
+
<reg32 offset="0x093a" name="CP_ROQ_IB1_STAT" type="a6xx_roq_stat"/>
1381
+
<reg32 offset="0x093b" name="CP_ROQ_IB2_STAT" type="a6xx_roq_stat"/>
1382
+
<reg32 offset="0x093c" name="CP_ROQ_SDS_STAT" type="a6xx_roq_stat"/>
1383
+
<reg32 offset="0x093d" name="CP_ROQ_MRB_STAT" type="a6xx_roq_stat"/>
1384
+
<reg32 offset="0x093e" name="CP_ROQ_VSD_STAT" type="a6xx_roq_stat"/>
1385
+
1386
+
<reg32 offset="0x0943" name="CP_IB1_DWORDS"/>
1387
+
<reg32 offset="0x0944" name="CP_IB2_DWORDS"/>
1388
+
<reg32 offset="0x0945" name="CP_SDS_DWORDS"/>
1389
+
<reg32 offset="0x0946" name="CP_MRB_DWORDS"/>
1390
+
<reg32 offset="0x0947" name="CP_VSD_DWORDS"/>
1391
+
1392
+
<reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB">
1393
+
<doc>number of remaining dwords incl current dword being consumed?</doc>
1394
+
<bitfield name="REM" low="16" high="31"/>
1395
+
</reg32>
1396
+
<reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1">
1397
+
<doc>number of remaining dwords incl current dword being consumed?</doc>
1398
+
<bitfield name="REM" low="16" high="31"/>
1399
+
</reg32>
1400
+
<reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2">
1401
+
<doc>number of remaining dwords incl current dword being consumed?</doc>
1402
+
<bitfield name="REM" low="16" high="31"/>
1403
+
</reg32>
1404
+
<reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS">
1405
+
<doc>number of remaining dwords incl current dword being consumed?</doc>
1406
+
<bitfield name="REM" low="16" high="31"/>
1407
+
</reg32>
1408
+
<reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB">
1409
+
<doc>number of dwords that have already been read but haven't been consumed by $addr</doc>
1410
+
<bitfield name="REM" low="16" high="31"/>
1411
+
</reg32>
1412
+
<reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD">
1413
+
<doc>number of remaining dwords incl current dword being consumed?</doc>
1414
+
<bitfield name="REM" low="16" high="31"/>
1415
+
</reg32>
1416
+
1417
+
<bitset name="a7xx_aperture_cntl" inline="yes">
1418
+
<bitfield name="PIPE" low="12" high="13" type="a7xx_pipe"/>
1419
+
<bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/>
1420
+
<bitfield name="CONTEXT" low="4" high="5"/>
1421
+
</bitset>
1422
+
<reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/>
1423
+
<reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1424
+
<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/>
1425
+
<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/>
1426
+
<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/>
1427
+
<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/>
1428
+
1429
+
<reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/>
1430
+
<reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/>
1431
+
<reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/>
1432
+
<reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/>
1433
+
<reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/>
1434
+
<reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/>
1435
+
<reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/>
1436
+
<reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/>
1437
+
<reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/>
1438
+
<reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/>
1439
+
<reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/>
1440
+
<reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/>
1441
+
<reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/>
1442
+
1443
+
<reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR" variants="A7XX-"/>
1444
+
<reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA" variants="A7XX-"/>
1445
+
<reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/>
1446
+
<reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/>
1447
+
1448
+
<reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/>
1449
+
<reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/>
1450
+
<reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/>
1451
+
<reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/>
1452
+
<reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/>
1453
+
<reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/>
1454
+
<reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/>
1455
+
1456
+
<reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/>
1457
+
<reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
1458
+
<reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/>
1459
+
<reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/>
1460
+
<reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/>
1461
+
<reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL"/>
1462
+
<reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>
1463
+
<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1464
+
<reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/>
1465
+
<reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
1466
+
<reg32 offset="0x0210" name="RBBM_STATUS">
1467
+
<bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/>
1468
+
<bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/>
1469
+
<bitfield pos="21" name="HLSQ_BUSY" type="boolean"/>
1470
+
<bitfield pos="20" name="VSC_BUSY" type="boolean"/>
1471
+
<bitfield pos="19" name="TPL1_BUSY" type="boolean"/>
1472
+
<bitfield pos="18" name="SP_BUSY" type="boolean"/>
1473
+
<bitfield pos="17" name="UCHE_BUSY" type="boolean"/>
1474
+
<bitfield pos="16" name="VPC_BUSY" type="boolean"/>
1475
+
<bitfield pos="15" name="VFD_BUSY" type="boolean"/>
1476
+
<bitfield pos="14" name="TESS_BUSY" type="boolean"/>
1477
+
<bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/>
1478
+
<bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/>
1479
+
<bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/>
1480
+
<bitfield pos="10" name="LRZ_BUSY" type="boolean"/>
1481
+
<bitfield pos="9" name="A2D_BUSY" type="boolean"/>
1482
+
<bitfield pos="8" name="CCU_BUSY" type="boolean"/>
1483
+
<bitfield pos="7" name="RB_BUSY" type="boolean"/>
1484
+
<bitfield pos="6" name="RAS_BUSY" type="boolean"/>
1485
+
<bitfield pos="5" name="TSE_BUSY" type="boolean"/>
1486
+
<bitfield pos="4" name="VBIF_BUSY" type="boolean"/>
1487
+
<bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/>
1488
+
<bitfield pos="2" name="CP_BUSY" type="boolean"/>
1489
+
<bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/>
1490
+
<bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>
1491
+
</reg32>
1492
+
<reg32 offset="0x0211" name="RBBM_STATUS1"/>
1493
+
<reg32 offset="0x0212" name="RBBM_STATUS2"/>
1494
+
<reg32 offset="0x0213" name="RBBM_STATUS3">
1495
+
<bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
1496
+
</reg32>
1497
+
<reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1498
+
1499
+
<reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/>
1500
+
<reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/>
1501
+
<reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/>
1502
+
<reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/>
1503
+
<reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/>
1504
+
<reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/>
1505
+
1506
+
<array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/>
1507
+
<array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/>
1508
+
<array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/>
1509
+
<array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/>
1510
+
<array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/>
1511
+
<array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A6XX"/>
1512
+
<array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A6XX"/>
1513
+
<array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A6XX"/>
1514
+
<array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A6XX"/>
1515
+
<array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A6XX"/>
1516
+
<array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A6XX"/>
1517
+
<array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A6XX"/>
1518
+
<array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A6XX"/>
1519
+
<array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A6XX"/>
1520
+
<array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/>
1521
+
<array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/>
1522
+
1523
+
<array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/>
1524
+
<array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/>
1525
+
<array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/>
1526
+
<array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/>
1527
+
<array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/>
1528
+
<array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/>
1529
+
<array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/>
1530
+
<array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/>
1531
+
<array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/>
1532
+
<array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/>
1533
+
<array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/>
1534
+
<array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/>
1535
+
<array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/>
1536
+
<array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/>
1537
+
<array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/>
1538
+
<array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/>
1539
+
<array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/>
1540
+
<array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/>
1541
+
<array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/>
1542
+
<array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/>
1543
+
<array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/>
1544
+
<array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/>
1545
+
<array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/>
1546
+
<array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/>
1547
+
<array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/>
1548
+
<array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/>
1549
+
<array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/>
1550
+
<array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/>
1551
+
1552
+
<reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1553
+
<reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1554
+
<reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1555
+
<reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1556
+
<reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1557
+
<reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1558
+
<reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1559
+
<array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>
1560
+
<reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1561
+
<reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/>
1562
+
<reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/>
1563
+
<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1564
+
<reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL" variants="A7XX-"/>
1565
+
<reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/>
1566
+
1567
+
<!---
1568
+
This block of registers aren't tied to perf counters. They
1569
+
count various geometry stats, for example number of
1570
+
vertices in, number of primnitives assembled etc.
1571
+
-->
1572
+
1573
+
<reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in -->
1574
+
<reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
1575
+
<reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out -->
1576
+
<reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
1577
+
<reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in -->
1578
+
<reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
1579
+
<reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out -->
1580
+
<reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
1581
+
<reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in -->
1582
+
<reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
1583
+
<reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out -->
1584
+
<reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
1585
+
<reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in -->
1586
+
<reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
1587
+
<reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out -->
1588
+
<reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
1589
+
<reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out -->
1590
+
<reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
1591
+
<reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in -->
1592
+
<reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
1593
+
<reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
1594
+
<reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
1595
+
1596
+
<reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1597
+
<reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/>
1598
+
<reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1599
+
<reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1600
+
<reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1601
+
<reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/>
1602
+
<reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1603
+
<reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
1604
+
<reg32 offset="0x00016" name="RBBM_GBIF_HALT"/>
1605
+
<reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK"/>
1606
+
<reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
1607
+
<bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
1608
+
</reg32>
1609
+
1610
+
<reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/>
1611
+
<reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/>
1612
+
<reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1613
+
<reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>
1614
+
<reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK"/>
1615
+
<reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/>
1616
+
<reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1617
+
<reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1618
+
<reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1619
+
<reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1620
+
<reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1621
+
<reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/>
1622
+
<reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1623
+
<reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1624
+
<reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1625
+
<reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1626
+
<reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1627
+
<reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1628
+
<reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1629
+
<reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1630
+
<reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1631
+
<reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1632
+
<reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1633
+
<reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1634
+
<reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1635
+
<reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1636
+
<reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1637
+
<reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1638
+
<reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1639
+
<reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1640
+
<reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1641
+
<reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1642
+
<reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1643
+
<reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1644
+
<reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1645
+
<reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1646
+
<reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1647
+
<reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1648
+
<reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1649
+
<reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1650
+
<reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1651
+
<reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1652
+
<reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1653
+
<reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1654
+
<reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1655
+
<reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1656
+
<reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1657
+
<reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1658
+
<reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1659
+
<reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1660
+
<reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1661
+
<reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1662
+
<reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1663
+
<reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1664
+
<reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1665
+
<reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1666
+
<reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1667
+
<reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1668
+
<reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1669
+
<reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1670
+
<reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1671
+
<reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1672
+
<reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1673
+
<reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1674
+
<reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1675
+
<reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1676
+
<reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1677
+
<reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1678
+
<reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1679
+
<reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1680
+
<reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1681
+
<reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1682
+
<reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1683
+
<reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1684
+
<reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1685
+
<reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1686
+
<reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1687
+
<reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1688
+
<reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1689
+
<reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1690
+
<reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1691
+
<reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1692
+
<reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1693
+
<reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1694
+
<reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1695
+
<reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1696
+
<reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1697
+
<reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1698
+
<reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1699
+
<reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1700
+
<reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1701
+
<reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1702
+
<reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1703
+
<reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1704
+
<reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1705
+
<reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1706
+
<reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1707
+
<reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1708
+
<reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1709
+
<reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1710
+
<reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1711
+
<reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1712
+
<reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1713
+
<reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1714
+
<reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1715
+
<reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1716
+
<reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1717
+
<reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1718
+
<reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1719
+
<reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1720
+
<reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1721
+
<reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1722
+
<reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1723
+
<reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1724
+
<reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1725
+
<reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1726
+
<reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1727
+
<reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1728
+
<reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/>
1729
+
<reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/>
1730
+
<reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/>
1731
+
<reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/>
1732
+
<reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/>
1733
+
<reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/>
1734
+
<reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-">
1735
+
<bitfield name="TXDONE" pos="0" type="boolean"/>
1736
+
</reg32>
1737
+
<reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE"/>
1738
+
<reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE"/>
1739
+
<reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE"/>
1740
+
<reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB"/>
1741
+
<reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB"/>
1742
+
<reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB"/>
1743
+
<reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC"/>
1744
+
<reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC"/>
1745
+
<reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC"/>
1746
+
<reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/>
1747
+
<reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL"/>
1748
+
1749
+
<reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1750
+
<reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1751
+
<reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1752
+
<reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1753
+
<bitfield high="7" low="0" name="PING_INDEX"/>
1754
+
<bitfield high="15" low="8" name="PING_BLK_SEL"/>
1755
+
</reg32>
1756
+
<reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1757
+
<bitfield high="5" low="0" name="TRACEEN"/>
1758
+
<bitfield high="14" low="12" name="GRANU"/>
1759
+
<bitfield high="31" low="28" name="SEGT"/>
1760
+
</reg32>
1761
+
<reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1762
+
<bitfield high="27" low="24" name="ENABLE"/>
1763
+
</reg32>
1764
+
<reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1765
+
<reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1766
+
<reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1767
+
<reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1768
+
<reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1769
+
<reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1770
+
<reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1771
+
<reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1772
+
<reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1773
+
<bitfield high="3" low="0" name="BYTEL0"/>
1774
+
<bitfield high="7" low="4" name="BYTEL1"/>
1775
+
<bitfield high="11" low="8" name="BYTEL2"/>
1776
+
<bitfield high="15" low="12" name="BYTEL3"/>
1777
+
<bitfield high="19" low="16" name="BYTEL4"/>
1778
+
<bitfield high="23" low="20" name="BYTEL5"/>
1779
+
<bitfield high="27" low="24" name="BYTEL6"/>
1780
+
<bitfield high="31" low="28" name="BYTEL7"/>
1781
+
</reg32>
1782
+
<reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1783
+
<bitfield high="3" low="0" name="BYTEL8"/>
1784
+
<bitfield high="7" low="4" name="BYTEL9"/>
1785
+
<bitfield high="11" low="8" name="BYTEL10"/>
1786
+
<bitfield high="15" low="12" name="BYTEL11"/>
1787
+
<bitfield high="19" low="16" name="BYTEL12"/>
1788
+
<bitfield high="23" low="20" name="BYTEL13"/>
1789
+
<bitfield high="27" low="24" name="BYTEL14"/>
1790
+
<bitfield high="31" low="28" name="BYTEL15"/>
1791
+
</reg32>
1792
+
<reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1793
+
<reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1794
+
<array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/>
1795
+
<reg32 offset="0x0CD8" name="VSC_UNKNOWN_0CD8" variants="A7XX">
1796
+
<doc>
1797
+
Set to true when binning, isn't changed afterwards
1798
+
</doc>
1799
+
<bitfield name="BINNING" pos="0" type="boolean"/>
1800
+
</reg32>
1801
+
<reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1802
+
<reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1803
+
<reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1804
+
<reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1805
+
<reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX"/>
1806
+
<reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE"/>
1807
+
<reg64 offset="0x0E09" name="UCHE_TRAP_BASE"/>
1808
+
<reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN"/>
1809
+
<reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX"/>
1810
+
<reg32 offset="0x0E17" name="UCHE_CACHE_WAYS" usage="cmd"/>
1811
+
<reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1812
+
<reg32 offset="0x0E19" name="UCHE_CLIENT_PF" usage="cmd">
1813
+
<bitfield high="7" low="0" name="PERFSEL"/>
1814
+
</reg32>
1815
+
<array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
1816
+
<reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/>
1817
+
<reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>
1818
+
1819
+
<reg32 offset="0x3000" name="VBIF_VERSION"/>
1820
+
<reg32 offset="0x3001" name="VBIF_CLKON">
1821
+
<bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/>
1822
+
</reg32>
1823
+
<reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1824
+
<reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1825
+
<reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1826
+
<reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1827
+
<reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1828
+
<reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1829
+
<bitfield low="0" high="3" name="DATA_SEL"/>
1830
+
</reg32>
1831
+
<reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1832
+
<reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1833
+
<bitfield low="0" high="8" name="DATA_SEL"/>
1834
+
</reg32>
1835
+
<reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1836
+
<reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1837
+
<reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1838
+
<reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1839
+
<reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1840
+
<reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1841
+
<reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1842
+
<reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1843
+
<reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1844
+
<reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1845
+
<reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1846
+
<reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1847
+
<reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1848
+
<reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1849
+
<reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1850
+
<reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1851
+
<reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1852
+
<reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1853
+
<reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1854
+
<reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1855
+
<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1856
+
<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1857
+
1858
+
<reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
1859
+
<reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
1860
+
<reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
1861
+
<reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
1862
+
<reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
1863
+
<reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
1864
+
<reg32 offset="0x3c45" name="GBIF_HALT"/>
1865
+
<reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
1866
+
<reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
1867
+
<reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/>
1868
+
<reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
1869
+
<reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
1870
+
<reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
1871
+
<reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
1872
+
<reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
1873
+
<reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
1874
+
<reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
1875
+
<reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
1876
+
<reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
1877
+
<reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
1878
+
<reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
1879
+
<reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
1880
+
<reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
1881
+
<reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
1882
+
<reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
1883
+
<reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
1884
+
1885
+
<reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/>
1886
+
<reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit">
1887
+
<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1888
+
<bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
1889
+
</reg32>
1890
+
<reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress" usage="cmd"/>
1891
+
<reg32 offset="0x0c06" name="VSC_BIN_COUNT" usage="rp_blit">
1892
+
<bitfield name="NX" low="1" high="10" type="uint"/>
1893
+
<bitfield name="NY" low="11" high="20" type="uint"/>
1894
+
</reg32>
1895
+
<array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32" usage="rp_blit">
1896
+
<reg32 offset="0x0" name="REG">
1897
+
<doc>
1898
+
Configures the mapping between VSC_PIPE buffer and
1899
+
bin, X/Y specify the bin index in the horiz/vert
1900
+
direction (0,0 is upper left, 0,1 is leftmost bin
1901
+
on second row, and so on). W/H specify the number
1902
+
of bins assigned to this VSC_PIPE in the horiz/vert
1903
+
dimension.
1904
+
</doc>
1905
+
<bitfield name="X" low="0" high="9" type="uint"/>
1906
+
<bitfield name="Y" low="10" high="19" type="uint"/>
1907
+
<bitfield name="W" low="20" high="25" type="uint"/>
1908
+
<bitfield name="H" low="26" high="31" type="uint"/>
1909
+
</reg32>
1910
+
</array>
1911
+
<!--
1912
+
HW binning primitive & draw streams, which enable draws and primitives
1913
+
within a draw to be skipped in the main tile pass. See:
1914
+
https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
1915
+
1916
+
Compared to a5xx and earlier, we just program the address of the first
1917
+
stream and hw adds (pipe_num * VSC_*_STRM_PITCH)
1918
+
1919
+
LIMIT is set to PITCH - 64, to make room for a bit of overflow
1920
+
-->
1921
+
<reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress" usage="cmd"/>
1922
+
<reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH" usage="cmd"/>
1923
+
<reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT" usage="cmd"/>
1924
+
<reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress" usage="cmd"/>
1925
+
<reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH" usage="cmd"/>
1926
+
<reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT" usage="cmd"/>
1927
+
1928
+
<array offset="0x0c38" name="VSC_STATE" stride="1" length="32" usage="rp_blit">
1929
+
<doc>
1930
+
Seems to be a bitmap of which tiles mapped to the VSC
1931
+
pipe contain geometry.
1932
+
1933
+
I suppose we can connect a maximum of 32 tiles to a
1934
+
single VSC pipe.
1935
+
</doc>
1936
+
<reg32 offset="0x0" name="REG"/>
1937
+
</array>
1938
+
1939
+
<array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit">
1940
+
<doc>
1941
+
Has the size of data written to corresponding VSC_PRIM_STRM
1942
+
buffer.
1943
+
</doc>
1944
+
<reg32 offset="0x0" name="REG"/>
1945
+
</array>
1946
+
1947
+
<array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit">
1948
+
<doc>
1949
+
Has the size of data written to corresponding VSC pipe, ie.
1950
+
same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI
1951
+
</doc>
1952
+
<reg32 offset="0x0" name="REG"/>
1953
+
</array>
1954
+
1955
+
<reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/>
1956
+
1957
+
<reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/>
1958
+
<reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/>
1959
+
<!-- always 0x03200000 ? -->
1960
+
<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" usage="cmd"/>
1961
+
1962
+
<!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
1963
+
<bitset name="a6xx_reg_xy" inline="yes">
1964
+
<bitfield name="X" low="0" high="13" type="uint"/>
1965
+
<bitfield name="Y" low="16" high="29" type="uint"/>
1966
+
</bitset>
1967
+
1968
+
<reg32 offset="0x8000" name="GRAS_CL_CNTL" usage="rp_blit">
1969
+
<bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
1970
+
<bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
1971
+
<bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
1972
+
<bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
1973
+
<!-- controls near z clip behavior (set for vulkan) -->
1974
+
<bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
1975
+
<!-- guess based on a3xx and meaning of bits 8 and 9
1976
+
if the guess is right then this is related to point sprite clipping -->
1977
+
<bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
1978
+
<bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
1979
+
<bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
1980
+
</reg32>
1981
+
1982
+
<bitset name="a6xx_gras_xs_cl_cntl" inline="yes">
1983
+
<bitfield name="CLIP_MASK" low="0" high="7"/>
1984
+
<bitfield name="CULL_MASK" low="8" high="15"/>
1985
+
</bitset>
1986
+
<reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>
1987
+
<reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>
1988
+
<reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>
1989
+
<reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint" usage="rp_blit"/>
1990
+
1991
+
<reg32 offset="0x8005" name="GRAS_CNTL" usage="rp_blit">
1992
+
<!-- see also RB_RENDER_CONTROL0 -->
1993
+
<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
1994
+
<bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
1995
+
<bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
1996
+
<bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
1997
+
<bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
1998
+
<bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
1999
+
<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
2000
+
<bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/>
2001
+
<bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/>
2002
+
</reg32>
2003
+
<reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" usage="rp_blit">
2004
+
<bitfield name="HORZ" low="0" high="8" type="uint"/>
2005
+
<bitfield name="VERT" low="10" high="18" type="uint"/>
2006
+
</reg32>
2007
+
2008
+
<!-- Something connected to depth-stencil attachment size -->
2009
+
<reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/>
2010
+
2011
+
<reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/>
2012
+
2013
+
<reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/>
2014
+
<reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/>
2015
+
<reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/>
2016
+
<reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/>
2017
+
2018
+
<!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> -->
2019
+
2020
+
<!-- 0x8006-0x800f invalid -->
2021
+
<array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16" usage="rp_blit">
2022
+
<reg32 offset="0" name="XOFFSET" type="float"/>
2023
+
<reg32 offset="1" name="XSCALE" type="float"/>
2024
+
<reg32 offset="2" name="YOFFSET" type="float"/>
2025
+
<reg32 offset="3" name="YSCALE" type="float"/>
2026
+
<reg32 offset="4" name="ZOFFSET" type="float"/>
2027
+
<reg32 offset="5" name="ZSCALE" type="float"/>
2028
+
</array>
2029
+
<array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16" usage="rp_blit">
2030
+
<reg32 offset="0" name="MIN" type="float"/>
2031
+
<reg32 offset="1" name="MAX" type="float"/>
2032
+
</array>
2033
+
2034
+
<reg32 offset="0x8090" name="GRAS_SU_CNTL" usage="rp_blit">
2035
+
<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
2036
+
<bitfield name="CULL_BACK" pos="1" type="boolean"/>
2037
+
<bitfield name="FRONT_CW" pos="2" type="boolean"/>
2038
+
<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
2039
+
<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
2040
+
<bitfield name="UNK12" pos="12"/>
2041
+
<bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>
2042
+
<bitfield name="UNK15" low="15" high="16"/>
2043
+
<!--
2044
+
On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have
2045
+
the ability to add the view index to either the RT array
2046
+
index or the viewport index, and it seems that
2047
+
MULTIVIEW_ENABLE doesn't do anything, instead we need to
2048
+
set at least one of RENDERTARGETINDEXINCR or
2049
+
VIEWPORTINDEXINCR to enable multiview. The blob still
2050
+
sets MULTIVIEW_ENABLE regardless.
2051
+
TODO: what about gen2 (a640)?
2052
+
-->
2053
+
<bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/>
2054
+
<bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/>
2055
+
<bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/>
2056
+
<bitfield name="UNK20" low="20" high="22"/>
2057
+
</reg32>
2058
+
<reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" usage="rp_blit">
2059
+
<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
2060
+
<bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
2061
+
</reg32>
2062
+
<reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" usage="rp_blit"/>
2063
+
<!-- 0x8093 invalid -->
2064
+
<reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" usage="rp_blit">
2065
+
<bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
2066
+
</reg32>
2067
+
<reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" usage="rp_blit"/>
2068
+
<reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" usage="rp_blit"/>
2069
+
<reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" usage="rp_blit"/>
2070
+
<!-- duplicates RB_DEPTH_BUFFER_INFO: -->
2071
+
<reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" usage="rp_blit">
2072
+
<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2073
+
<bitfield name="UNK3" pos="3"/>
2074
+
</reg32>
2075
+
2076
+
<reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" usage="cmd">
2077
+
<bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
2078
+
<bitfield name="SHIFTAMOUNT" low="1" high="2"/>
2079
+
<bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/>
2080
+
<bitfield name="UNK4" low="4" high="5"/>
2081
+
</reg32>
2082
+
<reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL">
2083
+
<bitfield name="UNK0" pos="0" type="boolean"/>
2084
+
<bitfield name="LINELENGTHEN" pos="1" type="boolean"/>
2085
+
</reg32>
2086
+
2087
+
<bitset name="a6xx_gras_layer_cntl" inline="yes">
2088
+
<bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
2089
+
<bitfield name="WRITES_VIEW" pos="1" type="boolean"/>
2090
+
</bitset>
2091
+
<reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>
2092
+
<reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>
2093
+
<reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>
2094
+
<!-- 0x809e/0x809f invalid -->
2095
+
2096
+
<enum name="a6xx_sequenced_thread_dist">
2097
+
<value value="0x0" name="DIST_SCREEN_COORD"/>
2098
+
<value value="0x1" name="DIST_ALL_TO_RB0"/>
2099
+
</enum>
2100
+
2101
+
<enum name="a6xx_single_prim_mode">
2102
+
<value value="0x0" name="NO_FLUSH"/>
2103
+
<doc>
2104
+
In addition to FLUSH_PER_OVERLAP, guarantee that UCHE
2105
+
and CCU don't get out of sync when fetching the previous
2106
+
value for the current pixel. With NO_FLUSH, there's the
2107
+
possibility that the flags for the current pixel are
2108
+
flushed before the data or vice-versa, leading to
2109
+
texture fetches via UCHE getting out of sync values.
2110
+
This mode should eliminate that. It's used in bypass
2111
+
mode for coherent blending
2112
+
(GL_KHR_blend_equation_advanced_coherent) as well as
2113
+
non-coherent blending.
2114
+
</doc>
2115
+
<value value="0x1" name="FLUSH_PER_OVERLAP_AND_OVERWRITE"/>
2116
+
<doc>
2117
+
Invalidate UCHE and wait for any pending work to finish
2118
+
if there was possibly an overlapping primitive prior to
2119
+
the current one. This is similar to a combination of
2120
+
GRAS_SC_CONTROL::INJECT_L2_INVALIDATE_EVENT and
2121
+
WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for
2122
+
coherent blending
2123
+
(GL_KHR_blend_equation_advanced_coherent).
2124
+
</doc>
2125
+
<value value="0x3" name="FLUSH_PER_OVERLAP"/>
2126
+
</enum>
2127
+
2128
+
<!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE -->
2129
+
<enum name="a6xx_raster_mode">
2130
+
<value value="0x0" name="TYPE_TILED"/>
2131
+
<value value="0x1" name="TYPE_WRITER"/>
2132
+
</enum>
2133
+
2134
+
<!-- I'm guessing this is the same as a3xx -->
2135
+
<enum name="a6xx_raster_direction">
2136
+
<value value="0x0" name="LR_TB"/>
2137
+
<value value="0x1" name="RL_TB"/>
2138
+
<value value="0x2" name="LR_BT"/>
2139
+
<value value="0x3" name="RB_BT"/>
2140
+
</enum>
2141
+
2142
+
<reg32 offset="0x80a0" name="GRAS_SC_CNTL" usage="rp_blit">
2143
+
<bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/>
2144
+
<bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/>
2145
+
<bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/>
2146
+
<bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/>
2147
+
<bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/>
2148
+
<!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set -->
2149
+
<bitfield name="UNK9" pos="9" type="boolean"/>
2150
+
<bitfield name="ROTATION" low="10" high="11" type="uint"/>
2151
+
<bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/>
2152
+
</reg32>
2153
+
2154
+
<enum name="a6xx_render_mode">
2155
+
<value value="0x0" name="RENDERING_PASS"/>
2156
+
<value value="0x1" name="BINNING_PASS"/>
2157
+
</enum>
2158
+
2159
+
<enum name="a6xx_buffers_location">
2160
+
<value value="0" name="BUFFERS_IN_GMEM"/>
2161
+
<value value="3" name="BUFFERS_IN_SYSMEM"/>
2162
+
</enum>
2163
+
2164
+
<reg32 offset="0x80a1" name="GRAS_BIN_CONTROL" usage="rp_blit">
2165
+
<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
2166
+
<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
2167
+
<bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
2168
+
<bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
2169
+
<bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location" variants="A6XX"/>
2170
+
<bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
2171
+
<bitfield name="UNK27" pos="27"/>
2172
+
</reg32>
2173
+
2174
+
<reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL" usage="rp_blit">
2175
+
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2176
+
<bitfield name="UNK2" pos="2"/>
2177
+
<bitfield name="UNK3" pos="3"/>
2178
+
</reg32>
2179
+
<reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL" usage="rp_blit">
2180
+
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2181
+
<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2182
+
</reg32>
2183
+
2184
+
<bitset name="a6xx_sample_config" inline="yes">
2185
+
<bitfield name="UNK0" pos="0"/>
2186
+
<bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
2187
+
</bitset>
2188
+
2189
+
<bitset name="a6xx_sample_locations" inline="yes">
2190
+
<bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
2191
+
<bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
2192
+
<bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
2193
+
<bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
2194
+
<bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
2195
+
<bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
2196
+
<bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
2197
+
<bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
2198
+
</bitset>
2199
+
2200
+
<reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>
2201
+
<reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>
2202
+
<reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>
2203
+
2204
+
<reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/>
2205
+
2206
+
<!-- 0x80a7-0x80ae invalid -->
2207
+
<reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0" usage="cmd"/>
2208
+
2209
+
<bitset name="a6xx_scissor_xy" inline="yes">
2210
+
<bitfield name="X" low="0" high="15" type="uint"/>
2211
+
<bitfield name="Y" low="16" high="31" type="uint"/>
2212
+
</bitset>
2213
+
<array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" usage="rp_blit">
2214
+
<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
2215
+
<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
2216
+
</array>
2217
+
<array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" usage="rp_blit">
2218
+
<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
2219
+
<reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
2220
+
</array>
2221
+
2222
+
<reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/>
2223
+
<reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/>
2224
+
2225
+
<!-- 0x80f4 - 0x80fa are used for VK_KHR_fragment_shading_rate -->
2226
+
<reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-" usage="cmd"/>
2227
+
<reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-" usage="cmd"/>
2228
+
<reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-" usage="cmd"/>
2229
+
<reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-" usage="cmd"/>
2230
+
<reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-" usage="cmd"/>
2231
+
<reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-" usage="cmd"/>
2232
+
2233
+
<enum name="a6xx_lrz_dir_status">
2234
+
<value value="0x1" name="LRZ_DIR_LE"/>
2235
+
<value value="0x2" name="LRZ_DIR_GE"/>
2236
+
<value value="0x3" name="LRZ_DIR_INVALID"/>
2237
+
</enum>
2238
+
2239
+
<reg32 offset="0x8100" name="GRAS_LRZ_CNTL" usage="rp_blit">
2240
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
2241
+
<doc>LRZ write also disabled for blend/etc.</doc>
2242
+
<bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
2243
+
<doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
2244
+
<bitfield name="GREATER" pos="2" type="boolean"/>
2245
+
<doc>
2246
+
Clears the LRZ block being touched to:
2247
+
- 0.0 if GREATER
2248
+
- 1.0 if LESS
2249
+
</doc>
2250
+
<bitfield name="FC_ENABLE" pos="3" type="boolean"/>
2251
+
<!-- set when depth-test + depth-write enabled -->
2252
+
<bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
2253
+
<bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/>
2254
+
<bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/>
2255
+
<doc>
2256
+
If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into
2257
+
buffer, in case of mismatched direction writes 0 (disables LRZ).
2258
+
</doc>
2259
+
<bitfield name="DIR_WRITE" pos="8" type="boolean"/>
2260
+
<doc>
2261
+
Disable LRZ based on previous direction and the current one.
2262
+
If DIR_WRITE is not enabled - there is no write to direction buffer.
2263
+
</doc>
2264
+
<bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean"/>
2265
+
<bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/>
2266
+
</reg32>
2267
+
2268
+
<enum name="a6xx_fragcoord_sample_mode">
2269
+
<value value="0" name="FRAGCOORD_CENTER"/>
2270
+
<value value="3" name="FRAGCOORD_SAMPLE"/>
2271
+
</enum>
2272
+
2273
+
<reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2" usage="rp_blit">
2274
+
<bitfield name="SAMPLEID" pos="0" type="boolean"/>
2275
+
<bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/>
2276
+
</reg32>
2277
+
2278
+
<reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUF_INFO_0" usage="rp_blit">
2279
+
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2280
+
</reg32>
2281
+
<reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit"/>
2282
+
<reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" usage="rp_blit">
2283
+
<!-- TODO: fix the shr fields -->
2284
+
<bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
2285
+
<bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/>
2286
+
</reg32>
2287
+
2288
+
<!--
2289
+
The LRZ "fast clear" buffer is initialized to zero's by blob, and
2290
+
read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set. It appears
2291
+
to store 1b/block. It appears that '0' means block has original
2292
+
depth clear value, and '1' means that the corresponding block in
2293
+
LRZ has been modified. Ignoring alignment/padding, the size is
2294
+
given by the formula:
2295
+
2296
+
// calculate LRZ size from depth size:
2297
+
if (nr_samples == 4) {
2298
+
width *= 2;
2299
+
height *= 2;
2300
+
} else if (nr_samples == 2) {
2301
+
height *= 2;
2302
+
}
2303
+
2304
+
lrz_width = div_round_up(width, 8);
2305
+
lrz_heigh = div_round_up(height, 8);
2306
+
2307
+
// calculate # of blocks:
2308
+
nblocksx = div_round_up(lrz_width, 16);
2309
+
nblocksy = div_round_up(lrz_height, 4);
2310
+
2311
+
// fast-clear buffer is 1bit/block:
2312
+
fc_sz = div_round_up(nblocksx * nblocksy, 8);
2313
+
2314
+
In practice the blob seems to switch off FC_ENABLE once the size
2315
+
increases beyond 1 page. Not sure if that is an actual limit or
2316
+
not.
2317
+
-->
2318
+
<reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp_blit"/>
2319
+
<!-- 0x8108 invalid -->
2320
+
<reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL" usage="rp_blit">
2321
+
<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2322
+
</reg32>
2323
+
<!--
2324
+
LRZ buffer represents a single array layer + mip level, and there is
2325
+
a single buffer per depth image. Thus to reuse LRZ between renderpasses
2326
+
it is necessary to track the depth view used in the past renderpass, which
2327
+
GRAS_LRZ_DEPTH_VIEW is for.
2328
+
GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_DEPTH_VIEW is equal to
2329
+
the value stored in the LRZ buffer, if not - LRZ is disabled.
2330
+
-->
2331
+
<reg32 offset="0x810a" name="GRAS_LRZ_DEPTH_VIEW" usage="cmd">
2332
+
<bitfield name="BASE_LAYER" low="0" high="10" type="uint"/>
2333
+
<bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/>
2334
+
<bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/>
2335
+
</reg32>
2336
+
2337
+
<reg32 offset="0x810b" name="GRAS_UNKNOWN_810B" variants="A7XX-" usage="cmd"/>
2338
+
2339
+
<!-- 0x810c-0x810f invalid -->
2340
+
2341
+
<reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/>
2342
+
2343
+
<!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR -->
2344
+
<reg32 offset="0x8111" name="GRAS_LRZ_CLEAR_DEPTH_F32" type="float" variants="A7XX-"/>
2345
+
2346
+
<reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"/>
2347
+
2348
+
<!-- Always written together and always equal 09510840 00000a62 -->
2349
+
<reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/>
2350
+
<reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/>
2351
+
2352
+
<!-- 0x8112-0x83ff invalid -->
2353
+
2354
+
<enum name="a6xx_rotation">
2355
+
<value value="0x0" name="ROTATE_0"/>
2356
+
<value value="0x1" name="ROTATE_90"/>
2357
+
<value value="0x2" name="ROTATE_180"/>
2358
+
<value value="0x3" name="ROTATE_270"/>
2359
+
<value value="0x4" name="ROTATE_HFLIP"/>
2360
+
<value value="0x5" name="ROTATE_VFLIP"/>
2361
+
</enum>
2362
+
2363
+
<bitset name="a6xx_2d_blit_cntl" inline="yes">
2364
+
<bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
2365
+
<bitfield name="OVERWRITEEN" pos="3" type="boolean"/>
2366
+
<bitfield name="UNK4" low="4" high="6"/>
2367
+
<bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
2368
+
<bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
2369
+
<bitfield name="SCISSOR" pos="16" type="boolean"/>
2370
+
<bitfield name="UNK17" low="17" high="18"/>
2371
+
<!-- required when blitting D24S8/D24X8 -->
2372
+
<bitfield name="D24S8" pos="19" type="boolean"/>
2373
+
<!-- some sort of channel mask, disabled channels are set to zero ? -->
2374
+
<bitfield name="MASK" low="20" high="23"/>
2375
+
<bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
2376
+
<bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/>
2377
+
<bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/>
2378
+
</bitset>
2379
+
2380
+
<reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/>
2381
+
<!-- note: the low 8 bits for src coords are valid, probably fixed point
2382
+
it would be a bit weird though, since we subtract 1 from BR coords
2383
+
apparently signed, gallium driver uses negative coords and it works?
2384
+
-->
2385
+
<reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int" usage="rp_blit"/>
2386
+
<reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int" usage="rp_blit"/>
2387
+
<reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int" usage="rp_blit"/>
2388
+
<reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int" usage="rp_blit"/>
2389
+
<reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy" usage="rp_blit"/>
2390
+
<reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy" usage="rp_blit"/>
2391
+
<reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>
2392
+
<reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>
2393
+
<reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/>
2394
+
<reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/>
2395
+
<reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/>
2396
+
<!-- 0x840c-0x85ff invalid -->
2397
+
2398
+
<!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
2399
+
<reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="cmd">
2400
+
<bitfield name="UNK7" pos="7" type="boolean"/>
2401
+
<bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/>
2402
+
</reg32>
2403
+
<reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
2404
+
<reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX-"/>
2405
+
<array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>
2406
+
<array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>
2407
+
<array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/>
2408
+
2409
+
<!-- note 0x8620-0x87ff are not all invalid
2410
+
(in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)
2411
+
-->
2412
+
2413
+
<!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
2414
+
<reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A6XX" usage="rp_blit">
2415
+
<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
2416
+
<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
2417
+
<bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
2418
+
<bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
2419
+
<bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/>
2420
+
<bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
2421
+
</reg32>
2422
+
2423
+
<reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A7XX-" usage="rp_blit">
2424
+
<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
2425
+
<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
2426
+
<bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
2427
+
<bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
2428
+
<bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
2429
+
</reg32>
2430
+
2431
+
<reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit">
2432
+
<bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/>
2433
+
<bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>
2434
+
<!-- set during binning pass: -->
2435
+
<bitfield name="BINNING" pos="7" type="boolean"/>
2436
+
<bitfield name="UNK8" low="8" high="10"/>
2437
+
<bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>
2438
+
<bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
2439
+
<bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>
2440
+
<bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>
2441
+
<!-- bit seems to be set whenever depth buffer enabled: -->
2442
+
<bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
2443
+
<!-- bitmask of MRTs using UBWC flag buffer: -->
2444
+
<bitfield name="FLAG_MRTS" low="16" high="23"/>
2445
+
</reg32>
2446
+
<reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
2447
+
<bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>
2448
+
<!-- set during binning pass: -->
2449
+
<bitfield name="BINNING" pos="7" type="boolean"/>
2450
+
<bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>
2451
+
<bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
2452
+
<bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>
2453
+
<bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>
2454
+
</reg32>
2455
+
<reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
2456
+
<bitfield name="BINNING" pos="7" type="boolean"/>
2457
+
</reg32>
2458
+
2459
+
<reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit">
2460
+
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2461
+
<bitfield name="UNK2" pos="2"/>
2462
+
<bitfield name="UNK3" pos="3"/>
2463
+
</reg32>
2464
+
<reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL" usage="rp_blit">
2465
+
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2466
+
<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2467
+
</reg32>
2468
+
2469
+
<reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>
2470
+
<reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>
2471
+
<reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>
2472
+
<!-- 0x8807-0x8808 invalid -->
2473
+
<!--
2474
+
note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
2475
+
name comes from kernel and is probably right)
2476
+
-->
2477
+
<reg32 offset="0x8809" name="RB_RENDER_CONTROL0" usage="rp_blit">
2478
+
<!-- see also GRAS_CNTL -->
2479
+
<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
2480
+
<bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
2481
+
<bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
2482
+
<bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
2483
+
<bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
2484
+
<bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
2485
+
<bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
2486
+
<bitfield name="UNK10" pos="10" type="boolean"/>
2487
+
</reg32>
2488
+
<reg32 offset="0x880a" name="RB_RENDER_CONTROL1" usage="rp_blit">
2489
+
<!-- enable bits for various FS sysvalue regs: -->
2490
+
<bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
2491
+
<bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/>
2492
+
<bitfield name="FACENESS" pos="2" type="boolean"/>
2493
+
<bitfield name="SAMPLEID" pos="3" type="boolean"/>
2494
+
<bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/>
2495
+
<bitfield name="CENTERRHW" pos="6" type="boolean"/>
2496
+
<bitfield name="LINELENGTHEN" pos="7" type="boolean"/>
2497
+
<bitfield name="FOVEATION" pos="8" type="boolean"/>
2498
+
</reg32>
2499
+
2500
+
<reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0" usage="rp_blit">
2501
+
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
2502
+
<bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
2503
+
<bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
2504
+
<bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/>
2505
+
</reg32>
2506
+
<reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1" usage="rp_blit">
2507
+
<bitfield name="MRT" low="0" high="3" type="uint"/>
2508
+
</reg32>
2509
+
<reg32 offset="0x880d" name="RB_RENDER_COMPONENTS" usage="rp_blit">
2510
+
<bitfield name="RT0" low="0" high="3"/>
2511
+
<bitfield name="RT1" low="4" high="7"/>
2512
+
<bitfield name="RT2" low="8" high="11"/>
2513
+
<bitfield name="RT3" low="12" high="15"/>
2514
+
<bitfield name="RT4" low="16" high="19"/>
2515
+
<bitfield name="RT5" low="20" high="23"/>
2516
+
<bitfield name="RT6" low="24" high="27"/>
2517
+
<bitfield name="RT7" low="28" high="31"/>
2518
+
</reg32>
2519
+
<reg32 offset="0x880e" name="RB_DITHER_CNTL" usage="cmd">
2520
+
<bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/>
2521
+
<bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/>
2522
+
<bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/>
2523
+
<bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/>
2524
+
<bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/>
2525
+
<bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
2526
+
<bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/>
2527
+
<bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
2528
+
</reg32>
2529
+
<reg32 offset="0x880f" name="RB_SRGB_CNTL" usage="rp_blit">
2530
+
<!-- Same as SP_SRGB_CNTL -->
2531
+
<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2532
+
<bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2533
+
<bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2534
+
<bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2535
+
<bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2536
+
<bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2537
+
<bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2538
+
<bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2539
+
</reg32>
2540
+
2541
+
<reg32 offset="0x8810" name="RB_SAMPLE_CNTL" usage="rp_blit">
2542
+
<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2543
+
</reg32>
2544
+
<reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6" usage="cmd"/>
2545
+
<reg32 offset="0x8812" name="RB_UNKNOWN_8812" variants="A7XX-" usage="rp_blit"/>
2546
+
<!-- 0x8813-0x8817 invalid -->
2547
+
<!-- always 0x0 ? -->
2548
+
<reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6" usage="cmd"/>
2549
+
<!-- 0x8819-0x881e all 32 bits -->
2550
+
<reg32 offset="0x8819" name="RB_UNKNOWN_8819" usage="cmd"/>
2551
+
<reg32 offset="0x881a" name="RB_UNKNOWN_881A" usage="cmd"/>
2552
+
<reg32 offset="0x881b" name="RB_UNKNOWN_881B" usage="cmd"/>
2553
+
<reg32 offset="0x881c" name="RB_UNKNOWN_881C" usage="cmd"/>
2554
+
<reg32 offset="0x881d" name="RB_UNKNOWN_881D" usage="cmd"/>
2555
+
<reg32 offset="0x881e" name="RB_UNKNOWN_881E" usage="cmd"/>
2556
+
<!-- 0x881f invalid -->
2557
+
<array offset="0x8820" name="RB_MRT" stride="8" length="8" usage="rp_blit">
2558
+
<reg32 offset="0x0" name="CONTROL">
2559
+
<bitfield name="BLEND" pos="0" type="boolean"/>
2560
+
<bitfield name="BLEND2" pos="1" type="boolean"/>
2561
+
<bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2562
+
<bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2563
+
<bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2564
+
</reg32>
2565
+
<reg32 offset="0x1" name="BLEND_CONTROL">
2566
+
<bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2567
+
<bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2568
+
<bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2569
+
<bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2570
+
<bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2571
+
<bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2572
+
</reg32>
2573
+
<reg32 offset="0x2" name="BUF_INFO" variants="A6XX">
2574
+
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2575
+
<bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2576
+
<bitfield name="UNK10" pos="10"/>
2577
+
<bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2578
+
</reg32>
2579
+
<reg32 offset="0x2" name="BUF_INFO" variants="A7XX-">
2580
+
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2581
+
<bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2582
+
<bitfield name="UNK10" pos="10"/>
2583
+
<bitfield name="LOSSLESSCOMPEN" pos="11" type="boolean"/>
2584
+
<bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2585
+
</reg32>
2586
+
<!--
2587
+
at least in gmem, things seem to be aligned to pitch of 64..
2588
+
maybe an artifact of tiled format used in gmem?
2589
+
-->
2590
+
<reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/>
2591
+
<reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/>
2592
+
<!--
2593
+
Compared to a5xx and before, we configure both a GMEM base and
2594
+
external base. Not sure if this is to facilitate GMEM save/
2595
+
restore for context switch, or just to simplify state setup to
2596
+
not have to care about GMEM vs BYPASS mode.
2597
+
-->
2598
+
<!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
2599
+
<reg64 offset="0x5" name="BASE" type="waddress" align="1"/>
2600
+
2601
+
<reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/>
2602
+
</array>
2603
+
2604
+
<reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float" usage="rp_blit"/>
2605
+
<reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float" usage="rp_blit"/>
2606
+
<reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float" usage="rp_blit"/>
2607
+
<reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float" usage="rp_blit"/>
2608
+
<reg32 offset="0x8864" name="RB_ALPHA_CONTROL" usage="cmd">
2609
+
<bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2610
+
<bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2611
+
<bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2612
+
</reg32>
2613
+
<reg32 offset="0x8865" name="RB_BLEND_CNTL" usage="rp_blit">
2614
+
<!-- per-mrt enable bit -->
2615
+
<bitfield name="ENABLE_BLEND" low="0" high="7"/>
2616
+
<bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2617
+
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
2618
+
<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2619
+
<bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>
2620
+
<bitfield name="SAMPLE_MASK" low="16" high="31"/>
2621
+
</reg32>
2622
+
<!-- 0x8866-0x886f invalid -->
2623
+
<reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" usage="rp_blit">
2624
+
<bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
2625
+
</reg32>
2626
+
2627
+
<reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="rp_blit">
2628
+
<bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
2629
+
<bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2630
+
<bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2631
+
<bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
2632
+
<doc>
2633
+
Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
2634
+
also set when Z_BOUNDS_ENABLE is set
2635
+
</doc>
2636
+
<bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/>
2637
+
<bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
2638
+
</reg32>
2639
+
<reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" usage="rp_blit">
2640
+
<bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
2641
+
</reg32>
2642
+
<!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2643
+
<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" usage="rp_blit">
2644
+
<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2645
+
<bitfield name="UNK3" low="3" high="4"/>
2646
+
</reg32>
2647
+
<!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO -->
2648
+
<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
2649
+
<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2650
+
<bitfield name="UNK3" low="3" high="4"/>
2651
+
<bitfield name="TILEMODE" low="5" high="6" type="a6xx_tile_mode"/>
2652
+
<bitfield name="LOSSLESSCOMPEN" pos="7" type="boolean"/>
2653
+
</reg32>
2654
+
2655
+
<reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint" usage="rp_blit"/>
2656
+
<reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint" usage="rp_blit"/>
2657
+
<reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
2658
+
<reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>
2659
+
2660
+
<reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float" usage="rp_blit"/>
2661
+
<reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float" usage="rp_blit"/>
2662
+
<!-- 0x887a-0x887f invalid -->
2663
+
<reg32 offset="0x8880" name="RB_STENCIL_CONTROL" usage="rp_blit">
2664
+
<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2665
+
<bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2666
+
<!--
2667
+
set for stencil operations that require read from stencil
2668
+
buffer, but not for example for stencil clear (which does
2669
+
not require read).. so guessing this is analogous to
2670
+
READ_DEST_ENABLE for color buffer..
2671
+
-->
2672
+
<bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2673
+
<bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2674
+
<bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2675
+
<bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2676
+
<bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2677
+
<bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2678
+
<bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2679
+
<bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2680
+
<bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2681
+
</reg32>
2682
+
<reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" usage="rp_blit">
2683
+
<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2684
+
</reg32>
2685
+
<reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A6XX" usage="rp_blit">
2686
+
<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2687
+
<bitfield name="UNK1" pos="1" type="boolean"/>
2688
+
</reg32>
2689
+
<reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A7XX-" usage="rp_blit">
2690
+
<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2691
+
<bitfield name="UNK1" pos="1" type="boolean"/>
2692
+
<bitfield name="TILEMODE" low="2" high="3" type="a6xx_tile_mode"/>
2693
+
</reg32>
2694
+
<reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint" usage="rp_blit"/>
2695
+
<reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint" usage="rp_blit"/>
2696
+
<reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
2697
+
<reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>
2698
+
<reg32 offset="0x8887" name="RB_STENCILREF" usage="rp_blit">
2699
+
<bitfield name="REF" low="0" high="7"/>
2700
+
<bitfield name="BFREF" low="8" high="15"/>
2701
+
</reg32>
2702
+
<reg32 offset="0x8888" name="RB_STENCILMASK" usage="rp_blit">
2703
+
<bitfield name="MASK" low="0" high="7"/>
2704
+
<bitfield name="BFMASK" low="8" high="15"/>
2705
+
</reg32>
2706
+
<reg32 offset="0x8889" name="RB_STENCILWRMASK" usage="rp_blit">
2707
+
<bitfield name="WRMASK" low="0" high="7"/>
2708
+
<bitfield name="BFWRMASK" low="8" high="15"/>
2709
+
</reg32>
2710
+
<!-- 0x888a-0x888f invalid -->
2711
+
<reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/>
2712
+
<reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL" usage="cmd">
2713
+
<bitfield name="DISABLE" pos="0" type="boolean"/>
2714
+
<bitfield name="COPY" pos="1" type="boolean"/>
2715
+
</reg32>
2716
+
<!-- 0x8892-0x8897 invalid -->
2717
+
<reg32 offset="0x8898" name="RB_LRZ_CNTL" usage="rp_blit">
2718
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
2719
+
</reg32>
2720
+
<reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/>
2721
+
<!-- 0x8899-0x88bf invalid -->
2722
+
<!-- clamps depth value for depth test/write -->
2723
+
<reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float" usage="rp_blit"/>
2724
+
<reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float" usage="rp_blit"/>
2725
+
<!-- 0x88c2-0x88cf invalid-->
2726
+
<reg32 offset="0x88d0" name="RB_UNKNOWN_88D0" usage="rp_blit">
2727
+
<bitfield name="UNK0" low="0" high="12"/>
2728
+
<bitfield name="UNK16" low="16" high="26"/>
2729
+
</reg32>
2730
+
<reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/>
2731
+
<reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/>
2732
+
<!-- weird to duplicate other regs from same block?? -->
2733
+
<reg32 offset="0x88d3" name="RB_BIN_CONTROL2" usage="rp_blit">
2734
+
<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
2735
+
<bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
2736
+
</reg32>
2737
+
<reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy" usage="rp_blit"/>
2738
+
<reg32 offset="0x88d5" name="RB_BLIT_GMEM_MSAA_CNTL" usage="rp_blit">
2739
+
<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2740
+
</reg32>
2741
+
<reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>
2742
+
<!-- s/DST_FORMAT/DST_INFO/ probably: -->
2743
+
<reg32 offset="0x88d7" name="RB_BLIT_DST_INFO" usage="rp_blit">
2744
+
<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
2745
+
<bitfield name="FLAGS" pos="2" type="boolean"/>
2746
+
<bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2747
+
<bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
2748
+
<bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
2749
+
<bitfield name="UNK15" pos="15" type="boolean"/>
2750
+
</reg32>
2751
+
<reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64" usage="rp_blit"/>
2752
+
<reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/>
2753
+
<!-- array-pitch is size of layer -->
2754
+
<reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/>
2755
+
<reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64" usage="rp_blit"/>
2756
+
<reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH" usage="rp_blit">
2757
+
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2758
+
<bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
2759
+
</reg32>
2760
+
2761
+
<reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0" usage="rp_blit"/>
2762
+
<reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1" usage="rp_blit"/>
2763
+
<reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2" usage="rp_blit"/>
2764
+
<reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3" usage="rp_blit"/>
2765
+
2766
+
<!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2767
+
<reg32 offset="0x88e3" name="RB_BLIT_INFO" usage="rp_blit">
2768
+
<bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color restore? -->
2769
+
<bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2770
+
<bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->
2771
+
<bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2772
+
<doc>
2773
+
For clearing depth/stencil
2774
+
1 - depth
2775
+
2 - stencil
2776
+
3 - depth+stencil
2777
+
For clearing color buffer:
2778
+
then probably a component mask, I always see 0xf
2779
+
</doc>
2780
+
<bitfield name="CLEAR_MASK" low="4" high="7"/>
2781
+
<!-- set when this is the last resolve on a650+ -->
2782
+
<bitfield name="LAST" low="8" high="9"/>
2783
+
<!--
2784
+
a618 GLES: color render target number being resolved for RM6_RESOLVE, 0x8 for depth, 0x9 for separate stencil.
2785
+
a618 VK: 0x8 for depth RM6_RESOLVE, 0x9 for separate stencil, 0 otherwise.
2786
+
2787
+
We believe this is related to concurrent resolves
2788
+
-->
2789
+
<bitfield name="BUFFER_ID" low="12" high="15"/>
2790
+
</reg32>
2791
+
<reg32 offset="0x88e4" name="RB_UNKNOWN_88E4" variants="A7XX-" usage="rp_blit">
2792
+
<!-- Value conditioned based on predicate, changed before blits -->
2793
+
<bitfield name="UNK0" pos="0" type="boolean"/>
2794
+
</reg32>
2795
+
2796
+
<enum name="a6xx_ccu_cache_size">
2797
+
<value value="0x0" name="CCU_CACHE_SIZE_FULL"/>
2798
+
<value value="0x1" name="CCU_CACHE_SIZE_HALF"/>
2799
+
<value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/>
2800
+
<value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/>
2801
+
</enum>
2802
+
<reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="cmd">
2803
+
<bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/>
2804
+
<bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/>
2805
+
<bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>
2806
+
<!-- GMEM offset of CCU depth cache -->
2807
+
<bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
2808
+
<bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/>
2809
+
<!-- GMEM offset of CCU color cache
2810
+
for GMEM rendering, we set it to GMEM size minus the minimum
2811
+
CCU color cache size. CCU color cache will be needed in some
2812
+
resolve cases, and in those cases we need to reserve the end
2813
+
of GMEM for color cache.
2814
+
-->
2815
+
<bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
2816
+
</reg32>
2817
+
<!-- 0x88e6-0x88ef invalid -->
2818
+
<!-- always 0x0 ? -->
2819
+
<reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" usage="cmd"/>
2820
+
<!-- could be for separate stencil? (or may not be a flag buffer at all) -->
2821
+
<reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/>
2822
+
<reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH">
2823
+
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2824
+
<bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/>
2825
+
</reg32>
2826
+
<reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
2827
+
<!-- Connected to VK_EXT_fragment_density_map? -->
2828
+
<reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/>
2829
+
<!-- 0x88f6-0x88ff invalid -->
2830
+
<reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
2831
+
<reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="rp_blit">
2832
+
<bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
2833
+
<!-- TODO: actually part of array pitch -->
2834
+
<bitfield name="UNK8" low="8" high="10"/>
2835
+
<bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
2836
+
</reg32>
2837
+
<array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8" usage="rp_blit">
2838
+
<reg64 offset="0" name="ADDR" type="waddress" align="64"/>
2839
+
<reg32 offset="2" name="PITCH">
2840
+
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2841
+
<bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/>
2842
+
</reg32>
2843
+
</array>
2844
+
<!-- 0x891b-0x8926 invalid -->
2845
+
<reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16" usage="cmd" variants="A6XX"/>
2846
+
<!-- 0x8929-0x89ff invalid -->
2847
+
2848
+
<!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
2849
+
2850
+
<!--
2851
+
These show up in a6xx gen3+ but so far haven't found an example of
2852
+
blob writing non-zero:
2853
+
-->
2854
+
<reg32 offset="0x8a00" name="RB_UNKNOWN_8A00" variants="A6XX" usage="rp_blit"/>
2855
+
<reg32 offset="0x8a10" name="RB_UNKNOWN_8A10" variants="A6XX" usage="rp_blit"/>
2856
+
<reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="rp_blit"/>
2857
+
<reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="rp_blit"/>
2858
+
2859
+
<reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/>
2860
+
<reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31" usage="rp_blit"/>
2861
+
2862
+
<bitset name="a6xx_2d_surf_info" inline="yes">
2863
+
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2864
+
<bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2865
+
<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2866
+
<bitfield name="FLAGS" pos="12" type="boolean"/>
2867
+
<bitfield name="SRGB" pos="13" type="boolean"/>
2868
+
<!-- the rest is only for src -->
2869
+
<bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
2870
+
<bitfield name="FILTER" pos="16" type="boolean"/>
2871
+
<bitfield name="UNK17" pos="17" type="boolean"/>
2872
+
<bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
2873
+
<bitfield name="UNK19" pos="19" type="boolean"/>
2874
+
<bitfield name="UNK20" pos="20" type="boolean"/>
2875
+
<bitfield name="UNK21" pos="21" type="boolean"/>
2876
+
<bitfield name="UNK22" pos="22" type="boolean"/>
2877
+
<bitfield name="UNK23" low="23" high="26"/>
2878
+
<bitfield name="UNK28" pos="28" type="boolean"/>
2879
+
</bitset>
2880
+
2881
+
<!-- 0x8c02-0x8c16 invalid -->
2882
+
<!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) -->
2883
+
<reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info" usage="rp_blit"/>
2884
+
<reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64" usage="rp_blit"/>
2885
+
<reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/>
2886
+
<!-- this is a guess but seems likely (for NV12/IYUV): -->
2887
+
<reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64" usage="rp_blit"/>
2888
+
<reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/>
2889
+
<reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64" usage="rp_blit"/>
2890
+
2891
+
<reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64" usage="rp_blit"/>
2892
+
<reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/>
2893
+
<!-- this is a guess but seems likely (for NV12 with UBWC): -->
2894
+
<reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64" usage="rp_blit"/>
2895
+
<reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/>
2896
+
2897
+
<!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
2898
+
<!-- unlike a5xx, these are per channel values rather than packed -->
2899
+
<reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0" usage="rp_blit"/>
2900
+
<reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1" usage="rp_blit"/>
2901
+
<reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2" usage="rp_blit"/>
2902
+
<reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3" usage="rp_blit"/>
2903
+
<!-- 0x8c34-0x8dff invalid -->
2904
+
2905
+
<!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
2906
+
<reg32 offset="0x8e01" name="RB_UNKNOWN_8E01" usage="cmd"/>
2907
+
<!-- 0x8e00-0x8e03 invalid -->
2908
+
<reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff -->
2909
+
<reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
2910
+
<!-- 0x02080000 in GMEM, zero otherwise? -->
2911
+
<reg32 offset="0x8e06" name="RB_UNKNOWN_8E06" variants="A7XX-" usage="cmd"/>
2912
+
2913
+
<reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A6XX">
2914
+
<bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/>
2915
+
<!-- concurrent resolves are apparently a 2-bit enum on a650+ -->
2916
+
<bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/>
2917
+
<bitfield name="DEPTH_OFFSET_HI" pos="7" type="hex"/>
2918
+
<bitfield name="COLOR_OFFSET_HI" pos="9" type="hex"/>
2919
+
<bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>
2920
+
<!-- GMEM offset of CCU depth cache -->
2921
+
<bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
2922
+
<bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/>
2923
+
<!-- GMEM offset of CCU color cache
2924
+
for GMEM rendering, we set it to GMEM size minus the minimum
2925
+
CCU color cache size. CCU color cache will be needed in some
2926
+
resolve cases, and in those cases we need to reserve the end
2927
+
of GMEM for color cache.
2928
+
-->
2929
+
<bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
2930
+
<!--TODO: valid mask 0xfffffc1f -->
2931
+
</reg32>
2932
+
<reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-">
2933
+
<bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/>
2934
+
<bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/>
2935
+
<!-- rest of the bits were moved to RB_CCU_CNTL2 -->
2936
+
</reg32>
2937
+
<reg32 offset="0x8e08" name="RB_NC_MODE_CNTL">
2938
+
<bitfield name="MODE" pos="0" type="boolean"/>
2939
+
<bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
2940
+
<bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
2941
+
<bitfield name="AMSBC" pos="4" type="boolean"/>
2942
+
<bitfield name="UPPER_BIT" pos="10" type="uint"/>
2943
+
<bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/>
2944
+
<bitfield name="UNK12" low="12" high="13"/>
2945
+
</reg32>
2946
+
<reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX-" usage="cmd"/>
2947
+
<!-- 0x8e09-0x8e0f invalid -->
2948
+
<array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/>
2949
+
<array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/>
2950
+
<!-- 0x8e1d-0x8e1f invalid -->
2951
+
<!-- 0x8e20-0x8e25 more perfcntr sel? -->
2952
+
<!-- 0x8e26-0x8e27 invalid -->
2953
+
<reg32 offset="0x8e28" name="RB_UNKNOWN_8E28" low="0" high="10"/>
2954
+
<!-- 0x8e29-0x8e2b invalid -->
2955
+
<array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
2956
+
<array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/>
2957
+
<reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
2958
+
<reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
2959
+
<!-- 0x8e3e-0x8e4f invalid -->
2960
+
<!-- GMEM save/restore for preemption: -->
2961
+
<reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/>
2962
+
<!-- address for GMEM save/restore? -->
2963
+
<reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/>
2964
+
<!-- 0x8e53-0x8e7f invalid -->
2965
+
<reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/>
2966
+
<!-- 0x8e80-0x8e83 are valid -->
2967
+
<!-- 0x8e84-0x90ff invalid -->
2968
+
2969
+
<!-- 0x9000-0x90ff invalid -->
2970
+
2971
+
<reg32 offset="0x9100" name="VPC_GS_PARAM" variants="A6XX" usage="rp_blit">
2972
+
<bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/>
2973
+
</reg32>
2974
+
2975
+
<bitset name="a6xx_vpc_xs_clip_cntl" inline="yes">
2976
+
<bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
2977
+
<!-- there can be up to 8 total clip/cull distance outputs,
2978
+
but apparenly VPC can only deal with vec4, so when there are
2979
+
more than 4 outputs a second location needs to be programmed
2980
+
-->
2981
+
<bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/>
2982
+
<bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/>
2983
+
</bitset>
2984
+
<reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
2985
+
<reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
2986
+
<reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
2987
+
2988
+
<reg32 offset="0x9311" name="VPC_VS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
2989
+
<reg32 offset="0x9312" name="VPC_GS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
2990
+
<reg32 offset="0x9313" name="VPC_DS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
2991
+
2992
+
<bitset name="a6xx_vpc_xs_layer_cntl" inline="yes">
2993
+
<bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
2994
+
<bitfield name="VIEWLOC" low="8" high="15" type="uint"/>
2995
+
<bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/>
2996
+
</bitset>
2997
+
2998
+
<reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
2999
+
<reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
3000
+
<reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
3001
+
3002
+
<reg32 offset="0x9314" name="VPC_VS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
3003
+
<reg32 offset="0x9315" name="VPC_GS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
3004
+
<reg32 offset="0x9316" name="VPC_DS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
3005
+
3006
+
<reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit">
3007
+
<!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused -->
3008
+
<bitfield name="RASTER_DISCARD" pos="0" type="boolean"/>
3009
+
<bitfield name="UNK2" pos="2" type="boolean"/>
3010
+
</reg32>
3011
+
<reg32 offset="0x9108" name="VPC_POLYGON_MODE" usage="rp_blit">
3012
+
<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
3013
+
</reg32>
3014
+
3015
+
<bitset name="a6xx_primitive_cntl_0" inline="yes">
3016
+
<bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
3017
+
<bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
3018
+
<bitfield name="D3D_VERTEX_ORDERING" pos="2" type="boolean">
3019
+
<doc>
3020
+
Swaps TESS_CW_TRIS/TESS_CCW_TRIS, and also makes
3021
+
triangle fans and triangle strips use the D3D
3022
+
order instead of the OpenGL order.
3023
+
</doc>
3024
+
</bitfield>
3025
+
<bitfield name="UNK3" pos="3" type="boolean"/>
3026
+
</bitset>
3027
+
3028
+
<bitset name="a6xx_primitive_cntl_5" inline="yes">
3029
+
<doc>
3030
+
geometry shader
3031
+
</doc>
3032
+
<!-- TODO: first 16 bits are valid so something is wrong or missing here -->
3033
+
<bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
3034
+
<bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
3035
+
<bitfield name="LINELENGTHEN" pos="15" type="boolean"/>
3036
+
<bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
3037
+
<bitfield name="UNK18" pos="18"/>
3038
+
</bitset>
3039
+
3040
+
<bitset name="a6xx_multiview_cntl" inline="yes">
3041
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
3042
+
<bitfield name="DISABLEMULTIPOS" pos="1" type="boolean">
3043
+
<doc>
3044
+
Multi-position output lets the last geometry
3045
+
stage shader write multiple copies of
3046
+
gl_Position. If disabled then the VS is run once
3047
+
for each view, and ViewID is passed as a
3048
+
register to the VS.
3049
+
</doc>
3050
+
</bitfield>
3051
+
<bitfield name="VIEWS" low="2" high="6" type="uint"/>
3052
+
</bitset>
3053
+
3054
+
<reg32 offset="0x9109" name="VPC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" variants="A7XX-" usage="rp_blit"/>
3055
+
<reg32 offset="0x910a" name="VPC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" variants="A7XX-" usage="rp_blit"/>
3056
+
<reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/>
3057
+
<reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage="rp_blit"/>
3058
+
3059
+
<enum name="a6xx_varying_interp_mode">
3060
+
<value value="0" name="INTERP_SMOOTH"/>
3061
+
<value value="1" name="INTERP_FLAT"/>
3062
+
<value value="2" name="INTERP_ZERO"/>
3063
+
<value value="3" name="INTERP_ONE"/>
3064
+
</enum>
3065
+
3066
+
<enum name="a6xx_varying_ps_repl_mode">
3067
+
<value value="0" name="PS_REPL_NONE"/>
3068
+
<value value="1" name="PS_REPL_S"/>
3069
+
<value value="2" name="PS_REPL_T"/>
3070
+
<value value="3" name="PS_REPL_ONE_MINUS_T"/>
3071
+
</enum>
3072
+
3073
+
<!-- 0x9109-0x91ff invalid -->
3074
+
<array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8" usage="rp_blit">
3075
+
<doc>Packed array of a6xx_varying_interp_mode</doc>
3076
+
<reg32 offset="0x0" name="MODE"/>
3077
+
</array>
3078
+
<array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8" usage="rp_blit">
3079
+
<doc>Packed array of a6xx_varying_ps_repl_mode</doc>
3080
+
<reg32 offset="0x0" name="MODE"/>
3081
+
</array>
3082
+
3083
+
<!-- always 0x0 -->
3084
+
<reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/>
3085
+
<reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/>
3086
+
3087
+
<array offset="0x9212" name="VPC_VAR" stride="1" length="4" usage="rp_blit">
3088
+
<!-- one bit per varying component: -->
3089
+
<reg32 offset="0" name="DISABLE"/>
3090
+
</array>
3091
+
3092
+
<reg32 offset="0x9216" name="VPC_SO_CNTL" usage="rp_blit">
3093
+
<!--
3094
+
Choose which DWORD to write to. There is an array of
3095
+
(4 * 64) DWORD's, dumped in the devcoredump at
3096
+
HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a
3097
+
(VPC location, stream) pair like so:
3098
+
3099
+
location 0, stream 0
3100
+
location 2, stream 0
3101
+
...
3102
+
location 126, stream 0
3103
+
location 0, stream 1
3104
+
location 2, stream 1
3105
+
...
3106
+
location 126, stream 1
3107
+
location 0, stream 2
3108
+
...
3109
+
3110
+
When EmitStreamVertex(N) happens, the HW goes to DWORD
3111
+
64 * N and then "executes" the next 64 DWORD's.
3112
+
3113
+
This field is auto-incremented when VPC_SO_PROG is
3114
+
written to.
3115
+
-->
3116
+
<bitfield name="ADDR" low="0" high="7" type="hex"/>
3117
+
<!-- clear all A_EN and B_EN bits for all DWORD's -->
3118
+
<bitfield name="RESET" pos="16" type="boolean"/>
3119
+
</reg32>
3120
+
<!-- special register, write multiple times to load SO program (not readable) -->
3121
+
<reg32 offset="0x9217" name="VPC_SO_PROG" usage="rp_blit">
3122
+
<bitfield name="A_BUF" low="0" high="1" type="uint"/>
3123
+
<bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
3124
+
<bitfield name="A_EN" pos="11" type="boolean"/>
3125
+
<bitfield name="B_BUF" low="12" high="13" type="uint"/>
3126
+
<bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
3127
+
<bitfield name="B_EN" pos="23" type="boolean"/>
3128
+
</reg32>
3129
+
3130
+
<reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32" usage="cmd"/>
3131
+
3132
+
<array offset="0x921a" name="VPC_SO" stride="7" length="4" usage="cmd">
3133
+
<reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
3134
+
<reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
3135
+
<reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/>
3136
+
<reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
3137
+
<reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>
3138
+
</array>
3139
+
3140
+
<reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT" usage="cmd">
3141
+
<bitfield name="INVERT" pos="0" type="boolean"/>
3142
+
</reg32>
3143
+
<!-- 0x9237-0x92ff invalid -->
3144
+
<!-- always 0x0 ? -->
3145
+
<reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2" usage="cmd"/>
3146
+
3147
+
<bitset name="a6xx_vpc_xs_pack" inline="yes">
3148
+
<doc>
3149
+
num of varyings plus four for gl_Position (plus one if gl_PointSize)
3150
+
plus # of transform-feedback (streamout) varyings if using the
3151
+
hw streamout (rather than stg instructions in shader)
3152
+
</doc>
3153
+
<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
3154
+
<bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
3155
+
<bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
3156
+
<bitfield name="EXTRAPOS" low="24" high="27" type="uint">
3157
+
<doc>
3158
+
The number of extra copies of POSITION, i.e.
3159
+
number of views minus one when multi-position
3160
+
output is enabled, otherwise 0.
3161
+
</doc>
3162
+
</bitfield>
3163
+
</bitset>
3164
+
<reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>
3165
+
<reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>
3166
+
<reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>
3167
+
3168
+
<reg32 offset="0x9304" name="VPC_CNTL_0" usage="rp_blit">
3169
+
<bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
3170
+
<!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
3171
+
<bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>
3172
+
<bitfield name="VARYING" pos="16" type="boolean"/>
3173
+
<bitfield name="VIEWIDLOC" low="24" high="31" type="uint">
3174
+
<doc>
3175
+
This VPC location will be overwritten with
3176
+
ViewID when multiview is enabled. It's used when
3177
+
fragment shaders read ViewID. It's only
3178
+
strictly required for multi-position output,
3179
+
where the same VS invocation is used for all the
3180
+
views at once, but it can be used when multi-pos
3181
+
output is disabled too, to avoid having to pass
3182
+
ViewID through the VS.
3183
+
</doc>
3184
+
</bitfield>
3185
+
</reg32>
3186
+
3187
+
<reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL" usage="rp_blit">
3188
+
<!--
3189
+
It's offset by 1, and 0 means "disabled"
3190
+
-->
3191
+
<bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/>
3192
+
<bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/>
3193
+
<bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/>
3194
+
<bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/>
3195
+
<bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
3196
+
</reg32>
3197
+
<reg32 offset="0x9306" name="VPC_SO_DISABLE" usage="rp_blit">
3198
+
<bitfield name="DISABLE" pos="0" type="boolean"/>
3199
+
</reg32>
3200
+
<reg32 offset="0x9307" name="VPC_POLYGON_MODE2" variants="A7XX-" usage="rp_blit">
3201
+
<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
3202
+
</reg32>
3203
+
<reg32 offset="0x9308" name="VPC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
3204
+
<bitfield name="SIZE_GMEM" low="0" high="31"/>
3205
+
</reg32>
3206
+
<reg32 offset="0x9309" name="VPC_ATTR_BUF_BASE_GMEM" variants="A7XX-" usage="rp_blit">
3207
+
<bitfield name="BASE_GMEM" low="0" high="31"/>
3208
+
</reg32>
3209
+
<reg32 offset="0x9b09" name="PC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
3210
+
<bitfield name="SIZE_GMEM" low="0" high="31"/>
3211
+
</reg32>
3212
+
3213
+
<!-- 0x9307-0x95ff invalid -->
3214
+
3215
+
<!-- TODO: 0x9600-0x97ff range -->
3216
+
<reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->
3217
+
<reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd"/>
3218
+
<reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0" usage="cmd"/> <!-- always 0x0 ? -->
3219
+
<reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
3220
+
<array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6" variants="A6XX"/>
3221
+
<array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX-"/>
3222
+
<!-- 0x960a-0x9623 invalid -->
3223
+
<!-- TODO: regs from 0x9624-0x963a -->
3224
+
<!-- 0x963b-0x97ff invalid -->
3225
+
3226
+
<reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint" usage="rp_blit"/>
3227
+
3228
+
<!-- always 0x0 ? -->
3229
+
<reg32 offset="0x9801" name="PC_HS_INPUT_SIZE" usage="rp_blit">
3230
+
<bitfield name="SIZE" low="0" high="10" type="uint"/>
3231
+
<bitfield name="UNK13" pos="13"/>
3232
+
</reg32>
3233
+
3234
+
<reg32 offset="0x9802" name="PC_TESS_CNTL" usage="rp_blit">
3235
+
<bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
3236
+
<bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
3237
+
</reg32>
3238
+
3239
+
<reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" usage="rp_blit"/>
3240
+
<reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" usage="rp_blit"/>
3241
+
3242
+
<reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
3243
+
3244
+
<reg32 offset="0x9806" name="PC_PS_CNTL" usage="rp_blit">
3245
+
<bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/>
3246
+
</reg32>
3247
+
3248
+
<!-- New in a6xx gen3+ -->
3249
+
<reg32 offset="0x9808" name="PC_SO_STREAM_CNTL" usage="rp_blit">
3250
+
<bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
3251
+
</reg32>
3252
+
3253
+
<reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL">
3254
+
<bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
3255
+
</reg32>
3256
+
<!-- 0x980b-0x983f invalid -->
3257
+
3258
+
<!-- 0x9840 - 0x9842 are not readable -->
3259
+
<reg32 offset="0x9840" name="PC_DRAW_CMD">
3260
+
<bitfield name="STATE_ID" low="0" high="7"/>
3261
+
</reg32>
3262
+
3263
+
<reg32 offset="0x9841" name="PC_DISPATCH_CMD">
3264
+
<bitfield name="STATE_ID" low="0" high="7"/>
3265
+
</reg32>
3266
+
3267
+
<reg32 offset="0x9842" name="PC_EVENT_CMD">
3268
+
<!-- I think only the low bit is actually used? -->
3269
+
<bitfield name="STATE_ID" low="16" high="23"/>
3270
+
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
3271
+
</reg32>
3272
+
3273
+
<!--
3274
+
0x9880 written in a lot of places by SQE, same value gets written
3275
+
to control reg 0x12a. Set by CP_SET_MARKER, so lets name it after
3276
+
that
3277
+
-->
3278
+
<reg32 offset="0x9880" name="PC_MARKER"/>
3279
+
3280
+
<!-- 0x9843-0x997f invalid -->
3281
+
3282
+
<reg32 offset="0x9981" name="PC_POLYGON_MODE" variants="A6XX" usage="rp_blit">
3283
+
<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
3284
+
</reg32>
3285
+
<reg32 offset="0x9809" name="PC_POLYGON_MODE" variants="A7XX-" usage="rp_blit">
3286
+
<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
3287
+
</reg32>
3288
+
3289
+
<reg32 offset="0x9980" name="PC_RASTER_CNTL" variants="A6XX" usage="rp_blit">
3290
+
<!-- which stream to send to GRAS -->
3291
+
<bitfield name="STREAM" low="0" high="1" type="uint"/>
3292
+
<!-- discard primitives before rasterization -->
3293
+
<bitfield name="DISCARD" pos="2" type="boolean"/>
3294
+
</reg32>
3295
+
<!-- VPC_RASTER_CNTL -->
3296
+
<reg32 offset="0x9107" name="PC_RASTER_CNTL" variants="A7XX-" usage="rp_blit">
3297
+
<!-- which stream to send to GRAS -->
3298
+
<bitfield name="STREAM" low="0" high="1" type="uint"/>
3299
+
<!-- discard primitives before rasterization -->
3300
+
<bitfield name="DISCARD" pos="2" type="boolean"/>
3301
+
</reg32>
3302
+
<reg32 offset="0x9317" name="PC_RASTER_CNTL_V2" variants="A7XX-" usage="rp_blit">
3303
+
<!-- which stream to send to GRAS -->
3304
+
<bitfield name="STREAM" low="0" high="1" type="uint"/>
3305
+
<!-- discard primitives before rasterization -->
3306
+
<bitfield name="DISCARD" pos="2" type="boolean"/>
3307
+
</reg32>
3308
+
3309
+
<!-- 0x9982-0x9aff invalid -->
3310
+
3311
+
<reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" usage="rp_blit"/>
3312
+
3313
+
<bitset name="a6xx_xs_out_cntl" inline="yes">
3314
+
<doc>
3315
+
num of varyings plus four for gl_Position (plus one if gl_PointSize)
3316
+
plus # of transform-feedback (streamout) varyings if using the
3317
+
hw streamout (rather than stg instructions in shader)
3318
+
</doc>
3319
+
<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
3320
+
<bitfield name="PSIZE" pos="8" type="boolean"/>
3321
+
<bitfield name="LAYER" pos="9" type="boolean"/>
3322
+
<bitfield name="VIEW" pos="10" type="boolean"/>
3323
+
<!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
3324
+
<bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
3325
+
<bitfield name="CLIP_MASK" low="16" high="23" type="uint"/>
3326
+
<bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/>
3327
+
</bitset>
3328
+
3329
+
<reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
3330
+
<reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
3331
+
<!-- since HS can't output anything, only PRIMITIVE_ID is valid -->
3332
+
<reg32 offset="0x9b03" name="PC_HS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
3333
+
<reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
3334
+
3335
+
<reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" usage="rp_blit"/>
3336
+
3337
+
<reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit">
3338
+
<doc>
3339
+
size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
3340
+
</doc>
3341
+
<bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/>
3342
+
</reg32>
3343
+
3344
+
<reg32 offset="0x9b07" name="PC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/>
3345
+
<!-- mask of enabled views, doesn't exist on A630 -->
3346
+
<reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15" usage="rp_blit"/>
3347
+
<!-- 0x9b09-0x9bff invalid -->
3348
+
<reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
3349
+
<!-- special register (but note first 8 bits can be written/read) -->
3350
+
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
3351
+
<bitfield name="STATE_ID" low="8" high="15"/>
3352
+
</reg32>
3353
+
<!-- 0x9c01-0x9dff invalid -->
3354
+
<!-- TODO: 0x9e00-0xa000 range incomplete -->
3355
+
<reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
3356
+
<reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
3357
+
<reg64 offset="0x9e04" name="PC_DRAW_INDX_BASE"/>
3358
+
<reg32 offset="0x9e06" name="PC_DRAW_FIRST_INDX" type="uint"/>
3359
+
<reg32 offset="0x9e07" name="PC_DRAW_MAX_INDICES" type="uint"/>
3360
+
<reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" variants="A6XX" type="waddress" align="32" usage="cmd"/>
3361
+
<reg64 offset="0x9810" name="PC_TESSFACTOR_ADDR" variants="A7XX-" type="waddress" align="32" usage="cmd"/>
3362
+
3363
+
<reg32 offset="0x9e0b" name="PC_DRAW_INITIATOR" type="vgt_draw_initiator_a4xx">
3364
+
<doc>
3365
+
Possibly not really "initiating" the draw but the layout is similar
3366
+
to VGT_DRAW_INITIATOR on older gens
3367
+
</doc>
3368
+
</reg32>
3369
+
<reg32 offset="0x9e0c" name="PC_DRAW_NUM_INSTANCES" type="uint"/>
3370
+
<reg32 offset="0x9e0d" name="PC_DRAW_NUM_INDICES" type="uint"/>
3371
+
3372
+
<!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
3373
+
<reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
3374
+
<bitfield name="UNK0" low="0" high="15"/>
3375
+
<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
3376
+
<bitfield name="VSC_N" low="22" high="26" type="uint"/>
3377
+
</reg32>
3378
+
<reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/>
3379
+
<reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/>
3380
+
3381
+
<reg32 offset="0x9e1c" name="PC_VISIBILITY_OVERRIDE">
3382
+
<doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc>
3383
+
<bitfield name="OVERRIDE" pos="0" type="boolean"/>
3384
+
</reg32>
3385
+
3386
+
<reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/>
3387
+
3388
+
<array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8" variants="A6XX"/>
3389
+
<array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/>
3390
+
3391
+
<!-- always 0x0 -->
3392
+
<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72" usage="cmd"/>
3393
+
3394
+
<reg32 offset="0xa000" name="VFD_CONTROL_0" usage="rp_blit">
3395
+
<bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
3396
+
<bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
3397
+
</reg32>
3398
+
<reg32 offset="0xa001" name="VFD_CONTROL_1" usage="rp_blit">
3399
+
<bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
3400
+
<bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
3401
+
<bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
3402
+
<!-- only used for VS in non-multi-position-output case -->
3403
+
<bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/>
3404
+
</reg32>
3405
+
<reg32 offset="0xa002" name="VFD_CONTROL_2" usage="rp_blit">
3406
+
<bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid">
3407
+
<doc>
3408
+
This is the ID of the current patch within the
3409
+
subdraw, used to calculate the offset of the
3410
+
patch within the HS->DS buffers. When a draw is
3411
+
split into multiple subdraws then this differs
3412
+
from gl_PrimitiveID on the second, third, etc.
3413
+
subdraws.
3414
+
</doc>
3415
+
</bitfield>
3416
+
<bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
3417
+
</reg32>
3418
+
<reg32 offset="0xa003" name="VFD_CONTROL_3" usage="rp_blit">
3419
+
<bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/>
3420
+
<bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/>
3421
+
<bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
3422
+
<bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
3423
+
</reg32>
3424
+
<reg32 offset="0xa004" name="VFD_CONTROL_4" usage="rp_blit">
3425
+
<bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>
3426
+
</reg32>
3427
+
<reg32 offset="0xa005" name="VFD_CONTROL_5" usage="rp_blit">
3428
+
<bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
3429
+
<bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/>
3430
+
</reg32>
3431
+
<reg32 offset="0xa006" name="VFD_CONTROL_6" usage="rp_blit">
3432
+
<!--
3433
+
True if gl_PrimitiveID is read via the FS
3434
+
-->
3435
+
<bitfield name="PRIMID4PSEN" pos="0" type="boolean"/>
3436
+
</reg32>
3437
+
3438
+
<reg32 offset="0xa007" name="VFD_MODE_CNTL" usage="cmd">
3439
+
<bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/>
3440
+
</reg32>
3441
+
3442
+
<reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/>
3443
+
<reg32 offset="0xa009" name="VFD_ADD_OFFSET" usage="cmd">
3444
+
<!-- add VFD_INDEX_OFFSET to REGID4VTX -->
3445
+
<bitfield name="VERTEX" pos="0" type="boolean"/>
3446
+
<!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
3447
+
<bitfield name="INSTANCE" pos="1" type="boolean"/>
3448
+
</reg32>
3449
+
3450
+
<reg32 offset="0xa00e" name="VFD_INDEX_OFFSET" usage="rp_blit"/>
3451
+
<reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET" usage="rp_blit"/>
3452
+
<array offset="0xa010" name="VFD_FETCH" stride="4" length="32" usage="rp_blit">
3453
+
<reg64 offset="0x0" name="BASE" type="address" align="1"/>
3454
+
<reg32 offset="0x2" name="SIZE" type="uint"/>
3455
+
<reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/>
3456
+
</array>
3457
+
<array offset="0xa090" name="VFD_DECODE" stride="2" length="32" usage="rp_blit">
3458
+
<reg32 offset="0x0" name="INSTR">
3459
+
<!-- IDX and byte OFFSET into VFD_FETCH -->
3460
+
<bitfield name="IDX" low="0" high="4" type="uint"/>
3461
+
<bitfield name="OFFSET" low="5" high="16"/>
3462
+
<bitfield name="INSTANCED" pos="17" type="boolean"/>
3463
+
<bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
3464
+
<bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
3465
+
<bitfield name="UNK30" pos="30" type="boolean"/>
3466
+
<bitfield name="FLOAT" pos="31" type="boolean"/>
3467
+
</reg32>
3468
+
<reg32 offset="0x1" name="STEP_RATE" type="uint"/>
3469
+
</array>
3470
+
<array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32" usage="rp_blit">
3471
+
<reg32 offset="0x0" name="INSTR">
3472
+
<bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
3473
+
<bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
3474
+
</reg32>
3475
+
</array>
3476
+
3477
+
<reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
3478
+
3479
+
<reg32 offset="0xa600" name="VFD_UNKNOWN_A600" variants="A7XX-" usage="cmd"/>
3480
+
3481
+
<reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
3482
+
<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/>
3483
+
<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/>
3484
+
3485
+
<!--
3486
+
Note: this seems to always be paired with another bit in another
3487
+
block.
3488
+
-->
3489
+
<enum name="a6xx_threadsize">
3490
+
<value value="0" name="THREAD64"/>
3491
+
<value value="1" name="THREAD128"/>
3492
+
</enum>
3493
+
3494
+
<bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
3495
+
<!-- if set to SINGLE, only use 1 concurrent wave on each SP -->
3496
+
<bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
3497
+
<!--
3498
+
When b31 set we just see FULLREGFOOTPRINT set. The pattern of
3499
+
used registers is a bit odd too:
3500
+
- used (half): 0-15 68-179 (cnt=128, max=179)
3501
+
- used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
3502
+
whereas we usually see a (mostly) contiguous range of regs used. But if
3503
+
I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
3504
+
then:
3505
+
- used (merged): 0-191 (cnt=192, max=191)
3506
+
So I think if b31 is set, then the half precision registers overlap
3507
+
the full precision registers. (Which seems like a pretty sensible
3508
+
feature, actually I'm not sure when you *wouldn't* want to use that,
3509
+
since it gives register allocation more flexibility)
3510
+
-->
3511
+
<bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
3512
+
<bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
3513
+
<!-- could it be a low bit of branchstack? -->
3514
+
<bitfield name="UNK13" pos="13" type="boolean"/>
3515
+
<!-- seems to be nesting level for flow control:.. -->
3516
+
<bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
3517
+
</bitset>
3518
+
3519
+
<bitset name="a6xx_sp_xs_config" inline="yes">
3520
+
<!--
3521
+
Each of these are set if the given resource type is used
3522
+
with the Vulkan/bindless binding model.
3523
+
-->
3524
+
<bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
3525
+
<bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
3526
+
<bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
3527
+
<bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
3528
+
3529
+
<bitfield name="ENABLED" pos="8" type="boolean"/>
3530
+
<!--
3531
+
number of textures and samplers.. these might be swapped, with GL I
3532
+
always see the same value for both.
3533
+
-->
3534
+
<bitfield name="NTEX" low="9" high="16" type="uint"/>
3535
+
<bitfield name="NSAMP" low="17" high="21" type="uint"/>
3536
+
<bitfield name="NIBO" low="22" high="28" type="uint"/>
3537
+
</bitset>
3538
+
3539
+
<bitset name="a6xx_sp_xs_prim_cntl" inline="yes">
3540
+
<!-- # of VS outputs including pos/psize -->
3541
+
<bitfield name="OUT" low="0" high="5" type="uint"/>
3542
+
<!-- FLAGS_REGID only for GS -->
3543
+
<bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
3544
+
</bitset>
3545
+
3546
+
<reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
3547
+
<!--
3548
+
This field actually controls all geometry stages. TCS, TES, and
3549
+
GS must have the same mergedregs setting as VS.
3550
+
-->
3551
+
<bitfield name="MERGEDREGS" pos="20" type="boolean"/>
3552
+
<!--
3553
+
Creates a separate preamble-only thread?
3554
+
3555
+
Early preamble has the following limitations:
3556
+
- Only shared, a1, and consts regs could be used
3557
+
(accessing other regs would result in GPU fault);
3558
+
- No cat5/cat6, only stc/ldc variants are working;
3559
+
- Values writen to shared regs are not accessible by the rest
3560
+
of the shader;
3561
+
- Instructions before shps are also considered to be a part of
3562
+
early preamble;
3563
+
3564
+
Note, for all shaders from d3d11 games blob produced preambles
3565
+
compatible with early preamble mode.
3566
+
-->
3567
+
<bitfield name="EARLYPREAMBLE" pos="21" type="boolean"/>
3568
+
</reg32>
3569
+
<!-- bitmask of true/false conditions for VS brac.N instructions,
3570
+
bit N corresponds to brac.N -->
3571
+
<reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex"/>
3572
+
<!-- # of VS outputs including pos/psize -->
3573
+
<reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>
3574
+
<array offset="0xa803" name="SP_VS_OUT" stride="1" length="16" usage="rp_blit">
3575
+
<reg32 offset="0x0" name="REG">
3576
+
<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
3577
+
<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
3578
+
<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
3579
+
<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
3580
+
</reg32>
3581
+
</array>
3582
+
<!--
3583
+
Starting with a5xx, position/psize outputs from shader end up in the
3584
+
SP_VS_OUT map, with highest OUTLOCn position. (Generally they are
3585
+
the last entries too, except when gl_PointCoord is used, blob inserts
3586
+
an extra varying after, but with a lower OUTLOC position. If present,
3587
+
psize is last, preceded by position.
3588
+
-->
3589
+
<array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8" usage="rp_blit">
3590
+
<reg32 offset="0x0" name="REG">
3591
+
<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
3592
+
<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
3593
+
<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
3594
+
<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
3595
+
</reg32>
3596
+
</array>
3597
+
3598
+
<bitset name="a6xx_sp_xs_pvt_mem_param" inline="yes">
3599
+
<bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">
3600
+
<doc>The size of memory that ldp/stp can address.</doc>
3601
+
</bitfield>
3602
+
<bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31">
3603
+
<doc>
3604
+
Seems to be the same as a3xx. The maximum stack
3605
+
size in units of 4 calls, so a call depth of 7
3606
+
would result in a value of 2.
3607
+
TODO: What's the actual size per call, i.e. the
3608
+
size of the PC? a3xx docs say it's 16 bits
3609
+
there, but the length register now takes 28 bits
3610
+
so it's probably been bumped to 32 bits.
3611
+
</doc>
3612
+
</bitfield>
3613
+
</bitset>
3614
+
3615
+
<bitset name="a6xx_sp_xs_pvt_mem_size" inline="yes">
3616
+
<bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/>
3617
+
<bitfield name="PERWAVEMEMLAYOUT" pos="31" type="boolean">
3618
+
<doc>
3619
+
There are four indices used to compute the
3620
+
private memory location for an access:
3621
+
3622
+
- stp/ldp offset
3623
+
- fiber id
3624
+
- wavefront id (a swizzled version of what "getwid" returns)
3625
+
- SP ID (the same as what "getspid" returns)
3626
+
3627
+
The stride for the SP ID is always set by
3628
+
TOTALPVTMEMSIZE. In the per-wave layout, the
3629
+
indices are used in this order:
3630
+
3631
+
- offset % 4 (offset within dword)
3632
+
- fiber id
3633
+
- offset / 4
3634
+
- wavefront id
3635
+
- SP ID
3636
+
3637
+
and the stride for the wavefront ID is
3638
+
MEMSIZEPERITEM, multiplied by 128 (fibers per
3639
+
wavefront). In the per-fiber layout, the indices
3640
+
are used in this order:
3641
+
3642
+
- offset
3643
+
- fiber id % 4
3644
+
- wavefront id
3645
+
- fiber id / 4
3646
+
- SP ID
3647
+
3648
+
and the stride for the fiber id/wavefront id
3649
+
combo is MEMSIZEPERITEM.
3650
+
3651
+
Note: Accesses of more than 1 dword do not work
3652
+
with per-fiber layout. The blob will fall back
3653
+
to per-wave instead.
3654
+
</doc>
3655
+
</bitfield>
3656
+
</bitset>
3657
+
3658
+
<bitset name="a6xx_sp_xs_pvt_mem_hw_stack_offset" inline="yes">
3659
+
<doc>
3660
+
This seems to be be the equivalent of HWSTACKOFFSET in
3661
+
a3xx. The ldp/stp offset formula above isn't affected by
3662
+
HWSTACKSIZEPERTHREAD at all, so the HW return address
3663
+
stack seems to be after all the normal per-SP private
3664
+
memory.
3665
+
</doc>
3666
+
<bitfield name="OFFSET" low="0" high="18" shr="11"/>
3667
+
</bitset>
3668
+
3669
+
<reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
3670
+
<reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32" usage="rp_blit"/>
3671
+
<reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
3672
+
<reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
3673
+
<reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
3674
+
<reg32 offset="0xa822" name="SP_VS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
3675
+
<reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
3676
+
<reg32 offset="0xa824" name="SP_VS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
3677
+
<reg32 offset="0xa825" name="SP_VS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
3678
+
<reg32 offset="0xa82d" name="SP_VS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
3679
+
3680
+
<reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
3681
+
<!-- There is no mergedregs bit, that comes from the VS. -->
3682
+
<bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>
3683
+
</reg32>
3684
+
<!--
3685
+
Total size of local storage in dwords divided by the wave size.
3686
+
The maximum value is 64. With the wave size being always 64 for HS,
3687
+
the maximum size of local storage should be:
3688
+
64 (wavesize) * 64 (SP_HS_WAVE_INPUT_SIZE) * 4 = 16k
3689
+
-->
3690
+
<reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint" usage="rp_blit"/>
3691
+
<reg32 offset="0xa832" name="SP_HS_BRANCH_COND" type="hex" usage="rp_blit"/>
3692
+
3693
+
<!-- TODO: exact same layout as 0xa81b-0xa825 -->
3694
+
<reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
3695
+
<reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32" usage="rp_blit"/>
3696
+
<reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
3697
+
<reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
3698
+
<reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
3699
+
<reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
3700
+
<reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
3701
+
<reg32 offset="0xa83c" name="SP_HS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
3702
+
<reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
3703
+
<reg32 offset="0xa82f" name="SP_HS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
3704
+
3705
+
<reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
3706
+
<!-- There is no mergedregs bit, that comes from the VS. -->
3707
+
<bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>
3708
+
</reg32>
3709
+
<reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/>
3710
+
3711
+
<!-- TODO: exact same layout as 0xa802-0xa81a -->
3712
+
<reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>
3713
+
<array offset="0xa843" name="SP_DS_OUT" stride="1" length="16" usage="rp_blit">
3714
+
<reg32 offset="0x0" name="REG">
3715
+
<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
3716
+
<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
3717
+
<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
3718
+
<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
3719
+
</reg32>
3720
+
</array>
3721
+
<array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8" usage="rp_blit">
3722
+
<reg32 offset="0x0" name="REG">
3723
+
<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
3724
+
<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
3725
+
<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
3726
+
<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
3727
+
</reg32>
3728
+
</array>
3729
+
3730
+
<!-- TODO: exact same layout as 0xa81b-0xa825 -->
3731
+
<reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
3732
+
<reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32" usage="rp_blit"/>
3733
+
<reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
3734
+
<reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
3735
+
<reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
3736
+
<reg32 offset="0xa862" name="SP_DS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
3737
+
<reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
3738
+
<reg32 offset="0xa864" name="SP_DS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
3739
+
<reg32 offset="0xa865" name="SP_DS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
3740
+
<reg32 offset="0xa868" name="SP_DS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
3741
+
3742
+
<reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
3743
+
<!-- There is no mergedregs bit, that comes from the VS. -->
3744
+
<bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>
3745
+
</reg32>
3746
+
<reg32 offset="0xa871" name="SP_GS_PRIM_SIZE" low="0" high="7" type="uint" usage="rp_blit">
3747
+
<doc>
3748
+
Normally the size of the output of the last stage in
3749
+
dwords. It should be programmed as follows:
3750
+
3751
+
size less than 63 - size
3752
+
size of 63 (?) or 64 - 63
3753
+
size greater than 64 - 64
3754
+
3755
+
What to program when the size is 61-63 is a guess, but
3756
+
both the blob and ir3 align the size to 4 dword's so it
3757
+
doesn't matter in practice.
3758
+
</doc>
3759
+
</reg32>
3760
+
<reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex" usage="rp_blit"/>
3761
+
3762
+
<!-- TODO: exact same layout as 0xa802-0xa81a -->
3763
+
<reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>
3764
+
<array offset="0xa874" name="SP_GS_OUT" stride="1" length="16" usage="rp_blit">
3765
+
<reg32 offset="0x0" name="REG">
3766
+
<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
3767
+
<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
3768
+
<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
3769
+
<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
3770
+
</reg32>
3771
+
</array>
3772
+
3773
+
<array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8" usage="rp_blit">
3774
+
<reg32 offset="0x0" name="REG">
3775
+
<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
3776
+
<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
3777
+
<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
3778
+
<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
3779
+
</reg32>
3780
+
</array>
3781
+
3782
+
<!-- TODO: exact same layout as 0xa81b-0xa825 -->
3783
+
<reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
3784
+
<reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32" usage="rp_blit"/>
3785
+
<reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
3786
+
<reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
3787
+
<reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
3788
+
<reg32 offset="0xa893" name="SP_GS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
3789
+
<reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
3790
+
<reg32 offset="0xa895" name="SP_GS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
3791
+
<reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
3792
+
<reg32 offset="0xa899" name="SP_GS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
3793
+
3794
+
<reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16" usage="cmd"/>
3795
+
<reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16" usage="cmd"/>
3796
+
<reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16" usage="cmd"/>
3797
+
<reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16" usage="cmd"/>
3798
+
<reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64" usage="cmd"/>
3799
+
<reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64" usage="cmd"/>
3800
+
<reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64" usage="cmd"/>
3801
+
<reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64" usage="cmd"/>
3802
+
3803
+
<!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 -->
3804
+
3805
+
<reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
3806
+
<bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
3807
+
<bitfield name="UNK21" pos="21" type="boolean"/>
3808
+
<bitfield name="VARYING" pos="22" type="boolean"/>
3809
+
<bitfield name="LODPIXMASK" pos="23" type="boolean">
3810
+
<doc>
3811
+
Enable ALL helper invocations in a quad. Necessary for
3812
+
fine derivatives and quad subgroup ops.
3813
+
</doc>
3814
+
</bitfield>
3815
+
<!-- note: vk blob uses bit24 -->
3816
+
<bitfield name="UNK24" pos="24" type="boolean"/>
3817
+
<bitfield name="UNK25" pos="25" type="boolean"/>
3818
+
<bitfield name="PIXLODENABLE" pos="26" type="boolean">
3819
+
<doc>
3820
+
Enable helper invocations. Enables 3 out of 4 fragments,
3821
+
because the coarse derivatives only use half of the quad
3822
+
and so one pixel's value is always unused.
3823
+
</doc>
3824
+
</bitfield>
3825
+
<bitfield name="UNK27" pos="27" type="boolean"/>
3826
+
<bitfield name="EARLYPREAMBLE" pos="28" type="boolean"/>
3827
+
<bitfield name="MERGEDREGS" pos="31" type="boolean"/>
3828
+
</reg32>
3829
+
<reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex"/>
3830
+
<reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
3831
+
<reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32" usage="rp_blit"/>
3832
+
<reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
3833
+
<reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
3834
+
<reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
3835
+
3836
+
<reg32 offset="0xa989" name="SP_BLEND_CNTL" usage="rp_blit">
3837
+
<!-- per-mrt enable bit -->
3838
+
<bitfield name="ENABLE_BLEND" low="0" high="7"/>
3839
+
<bitfield name="UNK8" pos="8" type="boolean"/>
3840
+
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
3841
+
<bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
3842
+
</reg32>
3843
+
<reg32 offset="0xa98a" name="SP_SRGB_CNTL" usage="rp_blit">
3844
+
<!-- Same as RB_SRGB_CNTL -->
3845
+
<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
3846
+
<bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
3847
+
<bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
3848
+
<bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
3849
+
<bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
3850
+
<bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
3851
+
<bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
3852
+
<bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
3853
+
</reg32>
3854
+
<reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS" usage="rp_blit">
3855
+
<bitfield name="RT0" low="0" high="3"/>
3856
+
<bitfield name="RT1" low="4" high="7"/>
3857
+
<bitfield name="RT2" low="8" high="11"/>
3858
+
<bitfield name="RT3" low="12" high="15"/>
3859
+
<bitfield name="RT4" low="16" high="19"/>
3860
+
<bitfield name="RT5" low="20" high="23"/>
3861
+
<bitfield name="RT6" low="24" high="27"/>
3862
+
<bitfield name="RT7" low="28" high="31"/>
3863
+
</reg32>
3864
+
<reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0" usage="rp_blit">
3865
+
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
3866
+
<bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
3867
+
<bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
3868
+
<bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/>
3869
+
</reg32>
3870
+
<reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1" usage="rp_blit">
3871
+
<bitfield name="MRT" low="0" high="3" type="uint"/>
3872
+
</reg32>
3873
+
3874
+
<array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8" usage="rp_blit">
3875
+
<doc>per MRT</doc>
3876
+
<reg32 offset="0x0" name="REG">
3877
+
<bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
3878
+
<bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
3879
+
</reg32>
3880
+
</array>
3881
+
3882
+
<array offset="0xa996" name="SP_FS_MRT" stride="1" length="8" usage="rp_blit">
3883
+
<reg32 offset="0" name="REG">
3884
+
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3885
+
<bitfield name="COLOR_SINT" pos="8" type="boolean"/>
3886
+
<bitfield name="COLOR_UINT" pos="9" type="boolean"/>
3887
+
<bitfield name="UNK10" pos="10" type="boolean"/>
3888
+
</reg32>
3889
+
</array>
3890
+
3891
+
<reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL" usage="rp_blit">
3892
+
<bitfield name="COUNT" low="0" high="2" type="uint"/>
3893
+
<bitfield name="IJ_WRITE_DISABLE" pos="3" type="boolean"/>
3894
+
<doc>
3895
+
Similar to "(eq)" flag but disables helper invocations
3896
+
after the texture prefetch.
3897
+
</doc>
3898
+
<bitfield name="ENDOFQUAD" pos="4" type="boolean" />
3899
+
<doc>
3900
+
Bypass writing to regs and overwrite output with color from
3901
+
CONSTSLOTID const regs.
3902
+
</doc>
3903
+
<bitfield name="WRITE_COLOR_TO_OUTPUT" pos="5" type="boolean"/>
3904
+
<bitfield name="CONSTSLOTID" low="6" high="14" type="uint"/>
3905
+
<!-- Blob never uses it -->
3906
+
<bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/>
3907
+
</reg32>
3908
+
<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A6XX" usage="rp_blit">
3909
+
<reg32 offset="0" name="CMD" variants="A6XX">
3910
+
<bitfield name="SRC" low="0" high="6" type="uint"/>
3911
+
<bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
3912
+
<bitfield name="TEX_ID" low="11" high="15" type="uint"/>
3913
+
<bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
3914
+
<bitfield name="WRMASK" low="22" high="25" type="hex"/>
3915
+
<bitfield name="HALF" pos="26" type="boolean"/>
3916
+
<doc>Results in color being zero</doc>
3917
+
<bitfield name="UNK27" pos="27" type="boolean"/>
3918
+
<bitfield name="BINDLESS" pos="28" type="boolean"/>
3919
+
<bitfield name="CMD" low="29" high="31" type="a6xx_tex_prefetch_cmd"/>
3920
+
</reg32>
3921
+
</array>
3922
+
<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A7XX-" usage="rp_blit">
3923
+
<reg32 offset="0" name="CMD" variants="A7XX-">
3924
+
<bitfield name="SRC" low="0" high="6" type="uint"/>
3925
+
<bitfield name="SAMP_ID" low="7" high="9" type="uint"/>
3926
+
<bitfield name="TEX_ID" low="10" high="12" type="uint"/>
3927
+
<bitfield name="DST" low="13" high="18" type="a3xx_regid"/>
3928
+
<bitfield name="WRMASK" low="19" high="22" type="hex"/>
3929
+
<bitfield name="HALF" pos="23" type="boolean"/>
3930
+
<bitfield name="BINDLESS" pos="25" type="boolean"/>
3931
+
<bitfield name="CMD" low="26" high="29" type="a6xx_tex_prefetch_cmd"/>
3932
+
</reg32>
3933
+
</array>
3934
+
<array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4" usage="rp_blit">
3935
+
<reg32 offset="0" name="CMD">
3936
+
<bitfield name="SAMP_ID" low="0" high="15" type="uint"/>
3937
+
<bitfield name="TEX_ID" low="16" high="31" type="uint"/>
3938
+
</reg32>
3939
+
</array>
3940
+
<reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
3941
+
<reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? -->
3942
+
<reg32 offset="0xa9a9" name="SP_FS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
3943
+
3944
+
<!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->
3945
+
3946
+
3947
+
3948
+
3949
+
<reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="cmd">
3950
+
<bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
3951
+
<!-- seems to make SP use less concurrent threads when possible? -->
3952
+
<bitfield name="UNK21" pos="21" type="boolean"/>
3953
+
<!-- has a small impact on performance, not clear what it does -->
3954
+
<bitfield name="UNK22" pos="22" type="boolean"/>
3955
+
<bitfield name="EARLYPREAMBLE" pos="23" type="boolean"/>
3956
+
<bitfield name="MERGEDREGS" pos="31" type="boolean"/>
3957
+
</reg32>
3958
+
3959
+
<!-- set for compute shaders -->
3960
+
<reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" usage="cmd">
3961
+
<bitfield name="SHARED_SIZE" low="0" high="4" type="uint">
3962
+
<doc>
3963
+
If 0 - all 32k of shared storage is enabled, otherwise
3964
+
(SHARED_SIZE + 1) * 1k is enabled.
3965
+
The ldl/stl offset seems to be rewritten to 0 when it is beyond
3966
+
this limit. This is different from ldlw/stlw, which wraps at
3967
+
64k (and has 36k of storage on A640 - reads between 36k-64k
3968
+
always return 0)
3969
+
</doc>
3970
+
</bitfield>
3971
+
<bitfield name="UNK5" pos="5" type="boolean"/>
3972
+
<!-- always 1 ? -->
3973
+
<bitfield name="UNK6" pos="6" type="boolean"/>
3974
+
</reg32>
3975
+
<reg32 offset="0xa9b2" name="SP_CS_BRANCH_COND" type="hex" usage="cmd"/>
3976
+
<reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="cmd"/>
3977
+
<reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32" usage="cmd"/>
3978
+
<reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="cmd"/>
3979
+
<reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32" usage="cmd"/>
3980
+
<reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="cmd"/>
3981
+
<reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" low="0" high="7" type="uint" usage="cmd"/>
3982
+
<reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/>
3983
+
<reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" low="0" high="27" type="uint" usage="cmd"/>
3984
+
<reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="cmd"/>
3985
+
<reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/>
3986
+
<reg32 offset="0xa9c5" name="SP_CS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
3987
+
3988
+
<!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 -->
3989
+
<reg32 offset="0xa9c2" name="SP_CS_CNTL_0" usage="cmd">
3990
+
<bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
3991
+
<bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
3992
+
<bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
3993
+
<bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
3994
+
</reg32>
3995
+
<!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 -->
3996
+
<reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A6XX" usage="cmd">
3997
+
<!-- gl_LocalInvocationIndex -->
3998
+
<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
3999
+
<!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
4000
+
one of those 6 "SP cores" -->
4001
+
<bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>
4002
+
<!-- Must match SP_CS_CTRL -->
4003
+
<bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
4004
+
<!-- 1 thread per wave (ignored if bit9 set) -->
4005
+
<bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>
4006
+
</reg32>
4007
+
4008
+
<reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A7XX-" usage="cmd">
4009
+
<!-- gl_LocalInvocationIndex -->
4010
+
<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
4011
+
<!-- Must match SP_CS_CTRL -->
4012
+
<bitfield name="THREADSIZE" pos="8" type="a6xx_threadsize"/>
4013
+
<!-- 1 thread per wave (would hang if THREAD128 is also set) -->
4014
+
<bitfield name="THREADSIZE_SCALAR" pos="9" type="boolean"/>
4015
+
4016
+
<!-- Affects getone. If enabled, getone sometimes executed 1? less times
4017
+
than there are subgroups.
4018
+
-->
4019
+
<bitfield name="UNK15" pos="15" type="boolean"/>
4020
+
</reg32>
4021
+
4022
+
<!-- TODO: two 64kb aligned addresses at a9d0/a9d2 -->
4023
+
4024
+
<reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16" usage="rp_blit"/>
4025
+
<reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16" usage="cmd"/>
4026
+
<reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64" usage="rp_blit"/>
4027
+
<reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64" usage="cmd"/>
4028
+
4029
+
<enum name="a6xx_bindless_descriptor_size">
4030
+
<doc>
4031
+
This can alternatively be interpreted as a pitch shift, ie, the
4032
+
descriptor size is 2 << N dwords
4033
+
</doc>
4034
+
<value value="1" name="BINDLESS_DESCRIPTOR_16B"/>
4035
+
<value value="3" name="BINDLESS_DESCRIPTOR_64B"/>
4036
+
</enum>
4037
+
4038
+
<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd">
4039
+
<reg64 offset="0" name="DESCRIPTOR" variants="A6XX">
4040
+
<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
4041
+
<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
4042
+
</reg64>
4043
+
</array>
4044
+
<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="cmd">
4045
+
<reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
4046
+
<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
4047
+
<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
4048
+
</reg64>
4049
+
</array>
4050
+
4051
+
<!--
4052
+
IBO state for compute shader:
4053
+
-->
4054
+
<reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/>
4055
+
<reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/>
4056
+
4057
+
<!-- Correlated with avgs/uvgs usage in FS -->
4058
+
<reg32 offset="0xaa01" name="SP_FS_VGPR_CONFIG" type="uint" variants="A7XX-" usage="cmd"/>
4059
+
4060
+
<reg32 offset="0xaa02" name="SP_PS_ALIASED_COMPONENTS_CONTROL" variants="A7XX-" usage="cmd">
4061
+
<bitfield name="ENABLED" pos="0" type="boolean"/>
4062
+
</reg32>
4063
+
<reg32 offset="0xaa03" name="SP_PS_ALIASED_COMPONENTS" variants="A7XX-" usage="cmd">
4064
+
<doc>
4065
+
Specify for which components the output color should be read
4066
+
from alias, e.g. for:
4067
+
4068
+
alias.1.b32.0 r3.x, c8.x
4069
+
alias.1.b32.0 r2.x, c4.x
4070
+
alias.1.b32.0 r1.x, c4.x
4071
+
alias.1.b32.0 r0.x, c0.x
4072
+
4073
+
the SP_PS_ALIASED_COMPONENTS would be 0x00001111
4074
+
</doc>
4075
+
4076
+
<bitfield name="RT0" low="0" high="3"/>
4077
+
<bitfield name="RT1" low="4" high="7"/>
4078
+
<bitfield name="RT2" low="8" high="11"/>
4079
+
<bitfield name="RT3" low="12" high="15"/>
4080
+
<bitfield name="RT4" low="16" high="19"/>
4081
+
<bitfield name="RT5" low="20" high="23"/>
4082
+
<bitfield name="RT6" low="24" high="27"/>
4083
+
<bitfield name="RT7" low="28" high="31"/>
4084
+
</reg32>
4085
+
4086
+
<reg32 offset="0xaaf2" name="SP_UNKNOWN_AAF2" type="uint" usage="cmd"/>
4087
+
4088
+
<!--
4089
+
This enum is probably similar in purpose to SNORMMODE on a3xx,
4090
+
minus the snorm stuff, i.e. it controls what happens with an
4091
+
out-of-bounds isam/isamm. GL and Vulkan robustness require us to
4092
+
return 0 on out-of-bound textureFetch().
4093
+
-->
4094
+
<enum name="a6xx_isam_mode">
4095
+
<value value="0x1" name="ISAMMODE_CL"/>
4096
+
<value value="0x2" name="ISAMMODE_GL"/>
4097
+
</enum>
4098
+
4099
+
<reg32 offset="0xab00" name="SP_MODE_CONTROL" usage="rp_blit">
4100
+
<!--
4101
+
When set, half register loads from the constant file will
4102
+
load a 32-bit value (so hc0.y loads the same value as c0.y)
4103
+
and implicitly convert it to 16b (f2f16, or u2u16, based on
4104
+
operand type). When unset, half register loads from the
4105
+
constant file will load 16 bits from the packed constant
4106
+
file (so hc0.y loads the top 16 bits of the value of c0.x)
4107
+
-->
4108
+
<bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>
4109
+
<bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/>
4110
+
<bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->
4111
+
</reg32>
4112
+
4113
+
<reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/>
4114
+
<reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/>
4115
+
4116
+
<reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
4117
+
<reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
4118
+
4119
+
<array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit">
4120
+
<reg64 offset="0" name="DESCRIPTOR" variants="A6XX">
4121
+
<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
4122
+
<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
4123
+
</reg64>
4124
+
</array>
4125
+
<array offset="0xab0a" name="SP_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_blit">
4126
+
<reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
4127
+
<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
4128
+
<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
4129
+
</reg64>
4130
+
</array>
4131
+
4132
+
<!--
4133
+
Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
4134
+
instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders.
4135
+
-->
4136
+
<reg64 offset="0xab1a" name="SP_IBO" type="address" align="16" usage="cmd"/>
4137
+
<reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint" usage="cmd"/>
4138
+
4139
+
<reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/>
4140
+
4141
+
<bitset name="a6xx_sp_2d_dst_format" inline="yes">
4142
+
<bitfield name="NORM" pos="0" type="boolean"/>
4143
+
<bitfield name="SINT" pos="1" type="boolean"/>
4144
+
<bitfield name="UINT" pos="2" type="boolean"/>
4145
+
<!-- looks like HW only cares about the base type of this format,
4146
+
which matches the ifmt? -->
4147
+
<bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
4148
+
<!-- set when ifmt is R2D_UNORM8_SRGB -->
4149
+
<bitfield name="SRGB" pos="11" type="boolean"/>
4150
+
<!-- some sort of channel mask, not sure what it is for -->
4151
+
<bitfield name="MASK" low="12" high="15"/>
4152
+
</bitset>
4153
+
4154
+
<reg32 offset="0xacc0" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A6XX" usage="rp_blit"/>
4155
+
<reg32 offset="0xa9bf" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A7XX-" usage="rp_blit"/>
4156
+
4157
+
<reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="cmd"/>
4158
+
<reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
4159
+
<reg32 offset="0xae02" name="SP_NC_MODE_CNTL">
4160
+
<!-- TODO: valid bits 0x3c3f, see kernel -->
4161
+
</reg32>
4162
+
<reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="cmd"/>
4163
+
<reg32 offset="0xae04" name="SP_FLOAT_CNTL" usage="cmd">
4164
+
<bitfield name="F16_NO_INF" pos="3" type="boolean"/>
4165
+
</reg32>
4166
+
4167
+
<reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/>
4168
+
<reg32 offset="0xae08" name="SP_UNKNOWN_AE08" variants="A7XX-" usage="cmd"/>
4169
+
<reg32 offset="0xae09" name="SP_UNKNOWN_AE09" variants="A7XX-" usage="cmd"/>
4170
+
<reg32 offset="0xae0a" name="SP_UNKNOWN_AE0A" variants="A7XX-" usage="cmd"/>
4171
+
4172
+
<reg32 offset="0xae0f" name="SP_PERFCTR_ENABLE" usage="cmd">
4173
+
<!-- some perfcntrs are affected by a per-stage enable bit
4174
+
(PERF_SP_ALU_WORKING_CYCLES for example)
4175
+
TODO: verify position of HS/DS/GS bits -->
4176
+
<bitfield name="VS" pos="0" type="boolean"/>
4177
+
<bitfield name="HS" pos="1" type="boolean"/>
4178
+
<bitfield name="DS" pos="2" type="boolean"/>
4179
+
<bitfield name="GS" pos="3" type="boolean"/>
4180
+
<bitfield name="FS" pos="4" type="boolean"/>
4181
+
<bitfield name="CS" pos="5" type="boolean"/>
4182
+
</reg32>
4183
+
<array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/>
4184
+
<array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/>
4185
+
<reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/>
4186
+
<reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/>
4187
+
<reg32 offset="0xae6c" name="SP_UNKNOWN_AE6C" variants="A7XX-" usage="cmd"/>
4188
+
<reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-">
4189
+
<bitfield name="LOCATION" low="18" high="19" type="a7xx_state_location"/>
4190
+
<bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/>
4191
+
<bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/>
4192
+
<bitfield name="USPTP" low="4" high="7"/>
4193
+
<bitfield name="SPTP" low="0" high="3"/>
4194
+
</reg32>
4195
+
<reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/>
4196
+
<reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="cmd"/>
4197
+
<array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/>
4198
+
<!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
4199
+
<!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
4200
+
<reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
4201
+
4202
+
<!--
4203
+
The downstream kernel calls the debug cluster of registers
4204
+
"a6xx_sp_ps_tp_cluster" but this actually specifies the border
4205
+
color base for compute shaders.
4206
+
-->
4207
+
<reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/>
4208
+
<reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2" usage="cmd"/>
4209
+
<reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23" usage="cmd"/>
4210
+
4211
+
<reg32 offset="0xb190" name="SP_UNKNOWN_B190"/>
4212
+
<reg32 offset="0xb191" name="SP_UNKNOWN_B191"/>
4213
+
4214
+
<!-- could be all the stuff below here is actually TPL1?? -->
4215
+
4216
+
<reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL" usage="rp_blit">
4217
+
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
4218
+
<bitfield name="UNK2" low="2" high="3"/>
4219
+
</reg32>
4220
+
<reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL" usage="rp_blit">
4221
+
<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
4222
+
<bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
4223
+
</reg32>
4224
+
4225
+
<!-- looks to work in the same way as a5xx: -->
4226
+
<reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/>
4227
+
<reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>
4228
+
<reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>
4229
+
<reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>
4230
+
<reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/>
4231
+
<reg32 offset="0xb309" name="SP_TP_MODE_CNTL" usage="cmd">
4232
+
<bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/>
4233
+
<bitfield name="UNK3" low="2" high="7"/>
4234
+
</reg32>
4235
+
<reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/>
4236
+
4237
+
<!--
4238
+
Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
4239
+
badly named or the functionality moved in a6xx. But downstream kernel
4240
+
calls this "a6xx_sp_ps_tp_2d_cluster"
4241
+
-->
4242
+
<reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info" variants="A6XX" usage="rp_blit"/>
4243
+
<reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE" variants="A6XX" usage="rp_blit">
4244
+
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
4245
+
<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
4246
+
</reg32>
4247
+
<reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A6XX" usage="rp_blit"/>
4248
+
<reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH" variants="A6XX" usage="rp_blit">
4249
+
<bitfield name="UNK0" low="0" high="8"/>
4250
+
<bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>
4251
+
</reg32>
4252
+
4253
+
<reg32 offset="0xb2c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info" variants="A7XX-" usage="rp_blit"/>
4254
+
<reg32 offset="0xb2c1" name="SP_PS_2D_SRC_SIZE" variants="A7XX">
4255
+
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
4256
+
<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
4257
+
</reg32>
4258
+
<reg64 offset="0xb2c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A7XX-" usage="rp_blit"/>
4259
+
<reg32 offset="0xb2c4" name="SP_PS_2D_SRC_PITCH" variants="A7XX">
4260
+
<bitfield name="UNK0" low="0" high="8"/>
4261
+
<bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>
4262
+
</reg32>
4263
+
4264
+
<!-- planes for NV12, etc. (TODO: not tested) -->
4265
+
<reg64 offset="0xb4c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A6XX"/>
4266
+
<reg32 offset="0xb4c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A6XX"/>
4267
+
<reg64 offset="0xb4c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A6XX"/>
4268
+
4269
+
<reg64 offset="0xb2c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A7XX-"/>
4270
+
<reg32 offset="0xb2c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A7XX-"/>
4271
+
<reg64 offset="0xb2c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A7XX-"/>
4272
+
4273
+
<reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A6XX" usage="rp_blit"/>
4274
+
<reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A6XX" usage="rp_blit"/>
4275
+
4276
+
<reg64 offset="0xb2ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A7XX-" usage="rp_blit"/>
4277
+
<reg32 offset="0xb2cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/>
4278
+
4279
+
<reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX"/>
4280
+
<reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX"/>
4281
+
<reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A6XX"/>
4282
+
<reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A6XX"/>
4283
+
<reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A6XX" usage="rp_blit"/>
4284
+
4285
+
<reg32 offset="0xb2cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A7XX"/>
4286
+
<reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/>
4287
+
<reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/>
4288
+
<reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/>
4289
+
<reg32 offset="0xb2d1" name="SP_PS_2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/>
4290
+
<reg32 offset="0xb2d2" name="SP_PS_UNKNOWN_B2D2" variants="A7XX-" usage="rp_blit"/>
4291
+
<reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"/>
4292
+
4293
+
<!-- always 0x100000 or 0x1000000? -->
4294
+
<reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/>
4295
+
<reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
4296
+
<reg32 offset="0xb602" name="TPL1_UNKNOWN_B602" low="0" high="7" type="uint" usage="cmd"/>
4297
+
<reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL">
4298
+
<bitfield name="MODE" pos="0" type="boolean"/>
4299
+
<bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
4300
+
<bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
4301
+
<bitfield name="UPPER_BIT" pos="4" type="uint"/>
4302
+
<bitfield name="UNK6" low="6" high="7"/>
4303
+
</reg32>
4304
+
<reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? -->
4305
+
4306
+
<reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A6XX"/>
4307
+
<reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A6XX"/>
4308
+
<reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A6XX"/>
4309
+
<reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A6XX"/>
4310
+
<reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A6XX"/>
4311
+
4312
+
<reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A7XX" usage="cmd"/>
4313
+
<reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A7XX" usage="cmd"/>
4314
+
<reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A7XX" usage="cmd"/>
4315
+
<reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A7XX" usage="cmd"/>
4316
+
<reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A7XX" usage="cmd"/>
4317
+
4318
+
<array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12"/>
4319
+
4320
+
<!-- TODO: 4 more perfcntr sel at 0xb620 ? -->
4321
+
4322
+
<bitset name="a6xx_hlsq_xs_cntl" inline="yes">
4323
+
<bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
4324
+
<bitfield name="ENABLED" pos="8" type="boolean"/>
4325
+
<bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/>
4326
+
</bitset>
4327
+
4328
+
<reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
4329
+
<reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
4330
+
<reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
4331
+
<reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
4332
+
4333
+
<reg32 offset="0xa827" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
4334
+
<reg32 offset="0xa83f" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
4335
+
<reg32 offset="0xa867" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
4336
+
<reg32 offset="0xa898" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
4337
+
4338
+
<reg32 offset="0xa9aa" name="HLSQ_FS_UNKNOWN_A9AA" variants="A7XX-" usage="rp_blit">
4339
+
<!-- Tentatively named, appears to disable consts being loaded via CP_LOAD_STATE6_FRAG -->
4340
+
<bitfield name="CONSTS_LOAD_DISABLE" pos="0" type="boolean"/>
4341
+
</reg32>
4342
+
4343
+
<!-- Always 0 -->
4344
+
<reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/>
4345
+
4346
+
<!-- Used in VK_KHR_fragment_shading_rate -->
4347
+
<reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/>
4348
+
4349
+
<reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit">
4350
+
<bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/>
4351
+
<!-- UNK8 is set on a730/a740 -->
4352
+
<bitfield name="UNK8" pos="8" type="boolean"/>
4353
+
<!-- UNK9 is set on a750 -->
4354
+
<bitfield name="UNK9" pos="9" type="boolean"/>
4355
+
</reg32>
4356
+
4357
+
<reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/>
4358
+
<reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR" align="16" type="address"/>
4359
+
<reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/>
4360
+
4361
+
4362
+
<bitset name="a6xx_hlsq_fs_cntl_0" inline="yes">
4363
+
<!-- must match SP_FS_CTRL -->
4364
+
<bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/>
4365
+
<bitfield name="VARYINGS" pos="1" type="boolean"/>
4366
+
<bitfield name="UNK2" low="2" high="11"/>
4367
+
</bitset>
4368
+
<bitset name="a6xx_hlsq_control_3_reg" inline="yes">
4369
+
<!-- register loaded with position (bary.f) -->
4370
+
<bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
4371
+
<bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
4372
+
<bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
4373
+
<bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
4374
+
</bitset>
4375
+
<bitset name="a6xx_hlsq_control_4_reg" inline="yes">
4376
+
<bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
4377
+
<bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
4378
+
<bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
4379
+
<bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
4380
+
</bitset>
4381
+
<bitset name="a6xx_hlsq_control_5_reg" inline="yes">
4382
+
<bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/>
4383
+
<bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/>
4384
+
</bitset>
4385
+
4386
+
<reg32 offset="0xb980" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A6XX" usage="rp_blit"/>
4387
+
<reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob -->
4388
+
<reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A6XX" usage="rp_blit">
4389
+
<!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the
4390
+
A3xx field, except that it's not necessary to set it to anything but the maximum, since
4391
+
the hardware will simply emit smaller waves when it runs out of space. -->
4392
+
<bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
4393
+
</reg32>
4394
+
<reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG" variants="A6XX" usage="rp_blit">
4395
+
<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
4396
+
<!-- SAMPLEID is loaded into a half-precision register: -->
4397
+
<bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
4398
+
<bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
4399
+
<bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
4400
+
</reg32>
4401
+
<reg32 offset="0xb984" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A6XX" usage="rp_blit"/>
4402
+
<reg32 offset="0xb985" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A6XX" usage="rp_blit"/>
4403
+
<reg32 offset="0xb986" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A6XX" usage="rp_blit"/>
4404
+
<reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="cmd"/>
4405
+
<reg32 offset="0xa9c6" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A7XX-" usage="rp_blit"/>
4406
+
<reg32 offset="0xa9c7" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A7XX-" usage="rp_blit">
4407
+
<bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
4408
+
</reg32>
4409
+
<reg32 offset="0xa9c8" name="HLSQ_CONTROL_2_REG" variants="A7XX-" usage="rp_blit">
4410
+
<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
4411
+
<!-- SAMPLEID is loaded into a half-precision register: -->
4412
+
<bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
4413
+
<bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
4414
+
<bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
4415
+
</reg32>
4416
+
<reg32 offset="0xa9c9" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A7XX-" usage="rp_blit"/>
4417
+
<reg32 offset="0xa9ca" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A7XX-" usage="rp_blit"/>
4418
+
<reg32 offset="0xa9cb" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A7XX-" usage="rp_blit"/>
4419
+
<reg32 offset="0xa9cd" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="cmd"/>
4420
+
4421
+
<!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
4422
+
<reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0" variants="A6XX" usage="rp_blit">
4423
+
<bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
4424
+
<!-- localsize is value minus one: -->
4425
+
<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
4426
+
<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
4427
+
<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
4428
+
</reg32>
4429
+
<reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1" variants="A6XX" usage="rp_blit">
4430
+
<bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
4431
+
</reg32>
4432
+
<reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2" variants="A6XX" usage="rp_blit">
4433
+
<bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
4434
+
</reg32>
4435
+
<reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3" variants="A6XX" usage="rp_blit">
4436
+
<bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
4437
+
</reg32>
4438
+
<reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4" variants="A6XX" usage="rp_blit">
4439
+
<bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
4440
+
</reg32>
4441
+
<reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5" variants="A6XX" usage="rp_blit">
4442
+
<bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
4443
+
</reg32>
4444
+
<reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6" variants="A6XX" usage="rp_blit">
4445
+
<bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
4446
+
</reg32>
4447
+
<reg32 offset="0xb997" name="HLSQ_CS_CNTL_0" variants="A6XX" usage="rp_blit">
4448
+
<!-- these are all vec3. first 3 need to be high regs
4449
+
WGSIZECONSTID is the local size (from HLSQ_CS_NDRANGE_0)
4450
+
WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID
4451
+
-->
4452
+
<bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
4453
+
<bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
4454
+
<bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
4455
+
<bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
4456
+
</reg32>
4457
+
<reg32 offset="0xb998" name="HLSQ_CS_CNTL_1" variants="A6XX" usage="rp_blit">
4458
+
<!-- gl_LocalInvocationIndex -->
4459
+
<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
4460
+
<!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
4461
+
one of those 6 "SP cores" -->
4462
+
<bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>
4463
+
<!-- Must match SP_CS_CTRL -->
4464
+
<bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
4465
+
<!-- 1 thread per wave (ignored if bit9 set) -->
4466
+
<bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>
4467
+
</reg32>
4468
+
<!--note: vulkan blob doesn't use these -->
4469
+
<reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X" variants="A6XX" usage="rp_blit"/>
4470
+
<reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A6XX" usage="rp_blit"/>
4471
+
<reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A6XX" usage="rp_blit"/>
4472
+
4473
+
<!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
4474
+
<reg32 offset="0xa9d4" name="HLSQ_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit">
4475
+
<bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
4476
+
<!-- localsize is value minus one: -->
4477
+
<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
4478
+
<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
4479
+
<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
4480
+
</reg32>
4481
+
<reg32 offset="0xa9d5" name="HLSQ_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit">
4482
+
<bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
4483
+
</reg32>
4484
+
<reg32 offset="0xa9d6" name="HLSQ_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit">
4485
+
<bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
4486
+
</reg32>
4487
+
<reg32 offset="0xa9d7" name="HLSQ_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit">
4488
+
<bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
4489
+
</reg32>
4490
+
<reg32 offset="0xa9d8" name="HLSQ_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit">
4491
+
<bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
4492
+
</reg32>
4493
+
<reg32 offset="0xa9d9" name="HLSQ_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit">
4494
+
<bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
4495
+
</reg32>
4496
+
<reg32 offset="0xa9da" name="HLSQ_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit">
4497
+
<bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
4498
+
</reg32>
4499
+
<!--note: vulkan blob doesn't use these -->
4500
+
<reg32 offset="0xa9dc" name="HLSQ_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/>
4501
+
<reg32 offset="0xa9dd" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/>
4502
+
<reg32 offset="0xa9de" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/>
4503
+
4504
+
<enum name="a7xx_cs_yalign">
4505
+
<value name="CS_YALIGN_1" value="8"/>
4506
+
<value name="CS_YALIGN_2" value="4"/>
4507
+
<value name="CS_YALIGN_4" value="2"/>
4508
+
<value name="CS_YALIGN_8" value="1"/>
4509
+
</enum>
4510
+
4511
+
<reg32 offset="0xa9db" name="HLSQ_CS_CNTL_1" variants="A7XX-" usage="rp_blit">
4512
+
<!-- gl_LocalInvocationIndex -->
4513
+
<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
4514
+
<!-- Must match SP_CS_CTRL -->
4515
+
<bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
4516
+
<bitfield name="UNK11" pos="11" type="boolean"/>
4517
+
<bitfield name="UNK22" pos="22" type="boolean"/>
4518
+
<bitfield name="UNK26" pos="26" type="boolean"/>
4519
+
<bitfield name="YALIGN" low="27" high="30" type="a7xx_cs_yalign"/>
4520
+
</reg32>
4521
+
4522
+
<reg32 offset="0xa9df" name="HLSQ_CS_LOCAL_SIZE" variants="A7XX-" usage="cmd">
4523
+
<!-- localsize is value minus one: -->
4524
+
<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
4525
+
<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
4526
+
<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
4527
+
</reg32>
4528
+
4529
+
<reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/>
4530
+
<reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR" align="16" type="address"/>
4531
+
<reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/>
4532
+
4533
+
<!-- mirror of SP_CS_BINDLESS_BASE -->
4534
+
<array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit">
4535
+
<reg64 offset="0" name="DESCRIPTOR">
4536
+
<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
4537
+
<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
4538
+
</reg64>
4539
+
</array>
4540
+
4541
+
<!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? -->
4542
+
<reg32 offset="0xb9d0" name="HLSQ_CS_UNKNOWN_B9D0" variants="A6XX" usage="cmd">
4543
+
<bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/>
4544
+
<bitfield name="UNK5" pos="5" type="boolean"/>
4545
+
<!-- always 1 ? -->
4546
+
<bitfield name="UNK6" pos="6" type="boolean"/>
4547
+
</reg32>
4548
+
4549
+
<reg32 offset="0xbb00" name="HLSQ_DRAW_CMD">
4550
+
<bitfield name="STATE_ID" low="0" high="7"/>
4551
+
</reg32>
4552
+
4553
+
<reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD">
4554
+
<bitfield name="STATE_ID" low="0" high="7"/>
4555
+
</reg32>
4556
+
4557
+
<reg32 offset="0xbb02" name="HLSQ_EVENT_CMD">
4558
+
<!-- I think only the low bit is actually used? -->
4559
+
<bitfield name="STATE_ID" low="16" high="23"/>
4560
+
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
4561
+
</reg32>
4562
+
4563
+
<reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD" variants="A6XX" usage="cmd">
4564
+
<doc>
4565
+
This register clears pending loads queued up by
4566
+
CP_LOAD_STATE6. Each bit resets a particular kind(s) of
4567
+
CP_LOAD_STATE6.
4568
+
</doc>
4569
+
4570
+
<!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
4571
+
<bitfield name="VS_STATE" pos="0" type="boolean"/>
4572
+
<bitfield name="HS_STATE" pos="1" type="boolean"/>
4573
+
<bitfield name="DS_STATE" pos="2" type="boolean"/>
4574
+
<bitfield name="GS_STATE" pos="3" type="boolean"/>
4575
+
<bitfield name="FS_STATE" pos="4" type="boolean"/>
4576
+
<bitfield name="CS_STATE" pos="5" type="boolean"/>
4577
+
4578
+
<bitfield name="CS_IBO" pos="6" type="boolean"/>
4579
+
<bitfield name="GFX_IBO" pos="7" type="boolean"/>
4580
+
4581
+
<!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->
4582
+
<bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/>
4583
+
<bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/>
4584
+
4585
+
<!-- SS6_BINDLESS: one bit per bindless base -->
4586
+
<bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/>
4587
+
<bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/>
4588
+
</reg32>
4589
+
4590
+
<reg32 offset="0xab1f" name="HLSQ_INVALIDATE_CMD" variants="A7XX-" usage="cmd">
4591
+
<doc>
4592
+
This register clears pending loads queued up by
4593
+
CP_LOAD_STATE6. Each bit resets a particular kind(s) of
4594
+
CP_LOAD_STATE6.
4595
+
</doc>
4596
+
4597
+
<!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
4598
+
<bitfield name="VS_STATE" pos="0" type="boolean"/>
4599
+
<bitfield name="HS_STATE" pos="1" type="boolean"/>
4600
+
<bitfield name="DS_STATE" pos="2" type="boolean"/>
4601
+
<bitfield name="GS_STATE" pos="3" type="boolean"/>
4602
+
<bitfield name="FS_STATE" pos="4" type="boolean"/>
4603
+
<bitfield name="CS_STATE" pos="5" type="boolean"/>
4604
+
4605
+
<bitfield name="CS_IBO" pos="6" type="boolean"/>
4606
+
<bitfield name="GFX_IBO" pos="7" type="boolean"/>
4607
+
4608
+
<!-- SS6_BINDLESS: one bit per bindless base -->
4609
+
<bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/>
4610
+
<bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/>
4611
+
</reg32>
4612
+
4613
+
<reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
4614
+
<reg32 offset="0xab03" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
4615
+
4616
+
<array offset="0xab40" name="HLSQ_SHARED_CONSTS_IMM" stride="1" length="64" variants="A7XX-"/>
4617
+
4618
+
<reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd">
4619
+
<doc>
4620
+
Shared constants are intended to be used for Vulkan push
4621
+
constants. When enabled, 8 vec4's are reserved in the FS
4622
+
const pool and 16 in the geometry const pool although
4623
+
only 8 are actually used (why?) and they are mapped to
4624
+
c504-c511 in each stage. Both VS and FS shared consts
4625
+
are written using ST6_CONSTANTS/SB6_IBO, so that both
4626
+
the geometry and FS shared consts can be written at once
4627
+
by using CP_LOAD_STATE6 rather than
4628
+
CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition
4629
+
DST_OFF and NUM_UNIT are in units of dwords instead of
4630
+
vec4's.
4631
+
4632
+
There is also a separate shared constant pool for CS,
4633
+
which is loaded through CP_LOAD_STATE6_FRAG with
4634
+
ST6_UBO/ST6_IBO. However the only real difference for CS
4635
+
is the dword units.
4636
+
</doc>
4637
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
4638
+
</reg32>
4639
+
4640
+
<!-- mirror of SP_BINDLESS_BASE -->
4641
+
<array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd">
4642
+
<reg64 offset="0" name="DESCRIPTOR">
4643
+
<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
4644
+
<bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
4645
+
</reg64>
4646
+
</array>
4647
+
4648
+
<reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD">
4649
+
<bitfield name="STATE_ID" low="8" high="15"/>
4650
+
<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
4651
+
</reg32>
4652
+
4653
+
<reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="cmd"/> <!-- all bits valid except bit 29 -->
4654
+
<reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="cmd"/>
4655
+
<reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="cmd"/>
4656
+
<reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
4657
+
<reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/>
4658
+
<array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/>
4659
+
4660
+
<!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
4661
+
<reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
4662
+
4663
+
<reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/>
4664
+
4665
+
<!-- Don't know if these are SP, always 0 -->
4666
+
<reg64 offset="0x0ce2" name="SP_UNKNOWN_0CE2" variants="A7XX-" usage="cmd"/>
4667
+
<reg64 offset="0x0ce4" name="SP_UNKNOWN_0CE4" variants="A7XX-" usage="cmd"/>
4668
+
<reg64 offset="0x0ce6" name="SP_UNKNOWN_0CE6" variants="A7XX-" usage="cmd"/>
4669
+
4670
+
<!--
4671
+
These special registers signal the beginning/end of an event
4672
+
sequence. The sequence used internally for an event looks like:
4673
+
- write EVENT_CMD pipe register
4674
+
- write CP_EVENT_START
4675
+
- write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD
4676
+
- write PC_EVENT_CMD with event or PC_DRAW_CMD
4677
+
- write HLSQ_EVENT_CMD(CONTEXT_DONE)
4678
+
- write PC_EVENT_CMD(CONTEXT_DONE)
4679
+
- write CP_EVENT_END
4680
+
Writing to CP_EVENT_END seems to actually trigger the context roll
4681
+
-->
4682
+
<reg32 offset="0xd600" name="CP_EVENT_START">
4683
+
<bitfield name="STATE_ID" low="0" high="7"/>
4684
+
</reg32>
4685
+
<reg32 offset="0xd601" name="CP_EVENT_END">
4686
+
<bitfield name="STATE_ID" low="0" high="7"/>
4687
+
</reg32>
4688
+
<reg32 offset="0xd700" name="CP_2D_EVENT_START">
4689
+
<bitfield name="STATE_ID" low="0" high="7"/>
4690
+
</reg32>
4691
+
<reg32 offset="0xd701" name="CP_2D_EVENT_END">
4692
+
<bitfield name="STATE_ID" low="0" high="7"/>
4693
+
</reg32>
4694
+
</domain>
4695
+
4696
+
<!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
4697
+
<domain name="A6XX_TEX_SAMP" width="32">
4698
+
<doc>Texture sampler dwords</doc>
4699
+
<enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
4700
+
<value name="A6XX_TEX_NEAREST" value="0"/>
4701
+
<value name="A6XX_TEX_LINEAR" value="1"/>
4702
+
<value name="A6XX_TEX_ANISO" value="2"/>
4703
+
<value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
4704
+
</enum>
4705
+
<enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
4706
+
<value name="A6XX_TEX_REPEAT" value="0"/>
4707
+
<value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
4708
+
<value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
4709
+
<value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
4710
+
<value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
4711
+
</enum>
4712
+
<enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
4713
+
<value name="A6XX_TEX_ANISO_1" value="0"/>
4714
+
<value name="A6XX_TEX_ANISO_2" value="1"/>
4715
+
<value name="A6XX_TEX_ANISO_4" value="2"/>
4716
+
<value name="A6XX_TEX_ANISO_8" value="3"/>
4717
+
<value name="A6XX_TEX_ANISO_16" value="4"/>
4718
+
</enum>
4719
+
<enum name="a6xx_reduction_mode">
4720
+
<value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
4721
+
<value name="A6XX_REDUCTION_MODE_MIN" value="1"/>
4722
+
<value name="A6XX_REDUCTION_MODE_MAX" value="2"/>
4723
+
</enum>
4724
+
4725
+
<reg32 offset="0" name="0">
4726
+
<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
4727
+
<bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
4728
+
<bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
4729
+
<bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
4730
+
<bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
4731
+
<bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
4732
+
<bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
4733
+
<bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
4734
+
</reg32>
4735
+
<reg32 offset="1" name="1">
4736
+
<bitfield name="CLAMPENABLE" pos="0" type="boolean">
4737
+
<doc>
4738
+
clamp result to [0, 1] if the format is unorm or
4739
+
[-1, 1] if the format is snorm, *after*
4740
+
filtering. Has no effect for other formats.
4741
+
</doc>
4742
+
</bitfield>
4743
+
<bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
4744
+
<bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
4745
+
<bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
4746
+
<bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
4747
+
<bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
4748
+
<bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
4749
+
</reg32>
4750
+
<reg32 offset="2" name="2">
4751
+
<bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
4752
+
<bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/>
4753
+
<bitfield name="BCOLOR" low="7" high="31"/>
4754
+
</reg32>
4755
+
<reg32 offset="3" name="3"/>
4756
+
</domain>
4757
+
4758
+
<domain name="A6XX_TEX_CONST" width="32">
4759
+
<doc>Texture constant dwords</doc>
4760
+
<enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
4761
+
<value name="A6XX_TEX_X" value="0"/>
4762
+
<value name="A6XX_TEX_Y" value="1"/>
4763
+
<value name="A6XX_TEX_Z" value="2"/>
4764
+
<value name="A6XX_TEX_W" value="3"/>
4765
+
<value name="A6XX_TEX_ZERO" value="4"/>
4766
+
<value name="A6XX_TEX_ONE" value="5"/>
4767
+
</enum>
4768
+
<enum name="a6xx_tex_type"> <!-- same as a4xx? -->
4769
+
<value name="A6XX_TEX_1D" value="0"/>
4770
+
<value name="A6XX_TEX_2D" value="1"/>
4771
+
<value name="A6XX_TEX_CUBE" value="2"/>
4772
+
<value name="A6XX_TEX_3D" value="3"/>
4773
+
<value name="A6XX_TEX_BUFFER" value="4"/>
4774
+
</enum>
4775
+
<reg32 offset="0" name="0">
4776
+
<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
4777
+
<bitfield name="SRGB" pos="2" type="boolean"/>
4778
+
<bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
4779
+
<bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
4780
+
<bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
4781
+
<bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
4782
+
<bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
4783
+
<!-- overlaps with MIPLVLS -->
4784
+
<bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/>
4785
+
<bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/>
4786
+
<bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
4787
+
<bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
4788
+
<!--
4789
+
Why is the swap needed in addition to SWIZ_*? The swap
4790
+
is performed before border color replacement, while the
4791
+
swizzle is applied after after it.
4792
+
-->
4793
+
<bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
4794
+
</reg32>
4795
+
<reg32 offset="1" name="1">
4796
+
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
4797
+
<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
4798
+
</reg32>
4799
+
<reg32 offset="2" name="2">
4800
+
<!--
4801
+
These fields overlap PITCH, and are used instead of
4802
+
PITCH/PITCHALIGN when TYPE is A6XX_TEX_BUFFER.
4803
+
-->
4804
+
<doc> probably for D3D structured UAVs, normally set to 1 </doc>
4805
+
<bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/>
4806
+
<bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/>
4807
+
4808
+
<!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
4809
+
<bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
4810
+
<doc>Pitch in bytes (so actually stride)</doc>
4811
+
<bitfield name="PITCH" low="7" high="28" type="uint"/>
4812
+
<bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/>
4813
+
</reg32>
4814
+
<reg32 offset="3" name="3">
4815
+
<!--
4816
+
ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
4817
+
for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
4818
+
layer size at the point that it stops being reduced moving to
4819
+
higher (smaller) mipmap levels
4820
+
-->
4821
+
<bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/>
4822
+
<bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
4823
+
<!--
4824
+
by default levels with w < 16 are linear
4825
+
TILE_ALL makes all levels have tiling
4826
+
seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
4827
+
-->
4828
+
<bitfield name="TILE_ALL" pos="27" type="boolean"/>
4829
+
<bitfield name="FLAG" pos="28" type="boolean"/>
4830
+
</reg32>
4831
+
<!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
4832
+
the address of the non-flag base buffer is determined automatically,
4833
+
and must follow the flag buffer
4834
+
-->
4835
+
<reg32 offset="4" name="4">
4836
+
<bitfield name="BASE_LO" low="5" high="31" shr="5"/>
4837
+
</reg32>
4838
+
<reg32 offset="5" name="5">
4839
+
<bitfield name="BASE_HI" low="0" high="16"/>
4840
+
<bitfield name="DEPTH" low="17" high="29" type="uint"/>
4841
+
</reg32>
4842
+
<reg32 offset="6" name="6">
4843
+
<!-- overlaps with PLANE_PITCH -->
4844
+
<bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/>
4845
+
<!-- pitch for plane 2 / plane 3 -->
4846
+
<bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>
4847
+
</reg32>
4848
+
<!-- 7/8 is plane 2 address for planar formats -->
4849
+
<reg32 offset="7" name="7">
4850
+
<bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
4851
+
</reg32>
4852
+
<reg32 offset="8" name="8">
4853
+
<bitfield name="FLAG_HI" low="0" high="16"/>
4854
+
</reg32>
4855
+
<!-- 9/10 is plane 3 address for planar formats -->
4856
+
<reg32 offset="9" name="9">
4857
+
<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
4858
+
</reg32>
4859
+
<reg32 offset="10" name="10">
4860
+
<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
4861
+
<!-- log2 size of the first level, required for mipmapping -->
4862
+
<bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
4863
+
<bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
4864
+
</reg32>
4865
+
<reg32 offset="11" name="11"/>
4866
+
<reg32 offset="12" name="12"/>
4867
+
<reg32 offset="13" name="13"/>
4868
+
<reg32 offset="14" name="14"/>
4869
+
<reg32 offset="15" name="15"/>
4870
+
</domain>
4871
+
4872
+
<domain name="A6XX_UBO" width="32">
4873
+
<reg32 offset="0" name="0">
4874
+
<bitfield name="BASE_LO" low="0" high="31"/>
4875
+
</reg32>
4876
+
<reg32 offset="1" name="1">
4877
+
<bitfield name="BASE_HI" low="0" high="16"/>
4878
+
<bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
4879
+
</reg32>
4880
+
</domain>
4881
+
4882
+
<domain name="A6XX_PDC" width="32">
4883
+
<reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
4884
+
<reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
4885
+
<reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
4886
+
<reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
4887
+
<reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
4888
+
<reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
4889
+
<reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
4890
+
<reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
4891
+
<reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
4892
+
<reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
4893
+
<reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
4894
+
<reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
4895
+
<reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
4896
+
<reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
4897
+
<reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
4898
+
<reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
4899
+
<reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
4900
+
<reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
4901
+
<reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
4902
+
<reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
4903
+
<reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
4904
+
<reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
4905
+
<reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
4906
+
<reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
4907
+
<reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
4908
+
<reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
4909
+
</domain>
4910
+
4911
+
<domain name="A6XX_PDC_GPU_SEQ" width="32">
4912
+
<reg32 offset="0x0" name="MEM_0"/>
4913
+
</domain>
4914
+
4915
+
<domain name="A6XX_CX_DBGC" width="32">
4916
+
<reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
4917
+
<bitfield high="7" low="0" name="PING_INDEX"/>
4918
+
<bitfield high="15" low="8" name="PING_BLK_SEL"/>
4919
+
</reg32>
4920
+
<reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
4921
+
<reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
4922
+
<reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
4923
+
<reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
4924
+
<bitfield high="5" low="0" name="TRACEEN"/>
4925
+
<bitfield high="14" low="12" name="GRANU"/>
4926
+
<bitfield high="31" low="28" name="SEGT"/>
4927
+
</reg32>
4928
+
<reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
4929
+
<bitfield high="27" low="24" name="ENABLE"/>
4930
+
</reg32>
4931
+
<reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
4932
+
<reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
4933
+
<reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
4934
+
<reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
4935
+
<reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
4936
+
<reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
4937
+
<reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
4938
+
<reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
4939
+
<reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
4940
+
<bitfield high="3" low="0" name="BYTEL0"/>
4941
+
<bitfield high="7" low="4" name="BYTEL1"/>
4942
+
<bitfield high="11" low="8" name="BYTEL2"/>
4943
+
<bitfield high="15" low="12" name="BYTEL3"/>
4944
+
<bitfield high="19" low="16" name="BYTEL4"/>
4945
+
<bitfield high="23" low="20" name="BYTEL5"/>
4946
+
<bitfield high="27" low="24" name="BYTEL6"/>
4947
+
<bitfield high="31" low="28" name="BYTEL7"/>
4948
+
</reg32>
4949
+
<reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
4950
+
<bitfield high="3" low="0" name="BYTEL8"/>
4951
+
<bitfield high="7" low="4" name="BYTEL9"/>
4952
+
<bitfield high="11" low="8" name="BYTEL10"/>
4953
+
<bitfield high="15" low="12" name="BYTEL11"/>
4954
+
<bitfield high="19" low="16" name="BYTEL12"/>
4955
+
<bitfield high="23" low="20" name="BYTEL13"/>
4956
+
<bitfield high="27" low="24" name="BYTEL14"/>
4957
+
<bitfield high="31" low="28" name="BYTEL15"/>
4958
+
</reg32>
4959
+
4960
+
<reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
4961
+
<reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
4962
+
</domain>
4963
+
4964
+
<domain name="A6XX_CX_MISC" width="32" prefix="variant" varset="chip">
4965
+
<reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
4966
+
<reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
4967
+
<reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/>
4968
+
</domain>
4969
+
4970
+
</database>
+228
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
+228
drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
<import file="adreno/adreno_common.xml"/>
7
+
8
+
<domain name="A6XX" width="32" prefix="variant" varset="chip">
9
+
10
+
<bitset name="A6XX_GMU_GPU_IDLE_STATUS">
11
+
<bitfield name="BUSY_IGN_AHB" pos="23"/>
12
+
<bitfield name="CX_GX_CPU_BUSY_IGN_AHB" pos="30"/>
13
+
</bitset>
14
+
15
+
<bitset name="A6XX_GMU_OOB">
16
+
<bitfield name="BOOT_SLUMBER_SET_MASK" pos="22"/>
17
+
<bitfield name="BOOT_SLUMBER_CHECK_MASK" pos="30"/>
18
+
<bitfield name="BOOT_SLUMBER_CLEAR_MASK" pos="30"/>
19
+
<bitfield name="DCVS_SET_MASK" pos="23"/>
20
+
<bitfield name="DCVS_CHECK_MASK" pos="31"/>
21
+
<bitfield name="DCVS_CLEAR_MASK" pos="31"/>
22
+
<bitfield name="GPU_SET_MASK" pos="18"/>
23
+
<bitfield name="GPU_CHECK_MASK" pos="26"/>
24
+
<bitfield name="GPU_CLEAR_MASK" pos="26"/>
25
+
<bitfield name="PERFCNTR_SET_MASK" pos="17"/>
26
+
<bitfield name="PERFCNTR_CHECK_MASK" pos="25"/>
27
+
<bitfield name="PERFCNTR_CLEAR_MASK" pos="25"/>
28
+
</bitset>
29
+
30
+
<bitset name="A6XX_HFI_IRQ">
31
+
<bitfield name="MSGQ_MASK" pos="0" />
32
+
<bitfield name="DSGQ_MASK" pos="1"/>
33
+
<bitfield name="BLOCKED_MSG_MASK" pos="2"/>
34
+
<bitfield name="CM3_FAULT_MASK" pos="23"/>
35
+
<bitfield name="GMU_ERR_MASK" low="16" high="22"/>
36
+
<bitfield name="OOB_MASK" low="24" high="31"/>
37
+
</bitset>
38
+
39
+
<bitset name="A6XX_HFI_H2F">
40
+
<bitfield name="IRQ_MASK_BIT" pos="0" />
41
+
</bitset>
42
+
43
+
<reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
44
+
<reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
45
+
<reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
46
+
<reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
47
+
<reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
48
+
<reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
49
+
<reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
50
+
<reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
51
+
<reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
52
+
<reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
53
+
<reg32 offset="0x23fe" name="GMU_DCVS_BW_SETTING"/>
54
+
<reg32 offset="0x23ff" name="GMU_DCVS_RETURN"/>
55
+
<reg32 offset="0x4c00" name="GMU_ICACHE_CONFIG"/>
56
+
<reg32 offset="0x4c01" name="GMU_DCACHE_CONFIG"/>
57
+
<reg32 offset="0x4c0f" name="GMU_SYS_BUS_CONFIG"/>
58
+
<reg32 offset="0x5000" name="GMU_CM3_SYSRESET"/>
59
+
<reg32 offset="0x5001" name="GMU_CM3_BOOT_CONFIG"/>
60
+
<reg32 offset="0x501a" name="GMU_CM3_FW_BUSY"/>
61
+
<reg32 offset="0x501c" name="GMU_CM3_FW_INIT_RESULT"/>
62
+
<reg32 offset="0x502d" name="GMU_CM3_CFG"/>
63
+
<reg32 offset="0x5040" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/>
64
+
<reg32 offset="0x5041" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/>
65
+
<reg32 offset="0x5042" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/>
66
+
<reg32 offset="0x5044" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/>
67
+
<reg32 offset="0x5045" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/>
68
+
<reg32 offset="0x5046" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/>
69
+
<reg32 offset="0x5047" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/>
70
+
<reg32 offset="0x5048" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/>
71
+
<reg32 offset="0x5049" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/>
72
+
<reg32 offset="0x504a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/>
73
+
<reg32 offset="0x504b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/>
74
+
<reg32 offset="0x504c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/>
75
+
<reg32 offset="0x504d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/>
76
+
<reg32 offset="0x504e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/>
77
+
<reg32 offset="0x504f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/>
78
+
<reg32 offset="0x50c0" name="GMU_PWR_COL_INTER_FRAME_CTRL">
79
+
<bitfield name="IFPC_ENABLE" pos="0" type="boolean"/>
80
+
<bitfield name="HM_POWER_COLLAPSE_ENABLE" pos="1" type="boolean"/>
81
+
<bitfield name="SPTPRAC_POWER_CONTROL_ENABLE" pos="2" type="boolean"/>
82
+
<bitfield name="NUM_PASS_SKIPS" low="10" high="13"/>
83
+
<bitfield name="MIN_PASS_LENGTH" low="14" high="31"/>
84
+
</reg32>
85
+
<reg32 offset="0x50c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/>
86
+
<reg32 offset="0x50c2" name="GMU_PWR_COL_SPTPRAC_HYST"/>
87
+
<reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS">
88
+
<bitfield name="SPTPRAC_GDSC_POWERING_OFF" pos="0" type="boolean"/>
89
+
<bitfield name="SPTPRAC_GDSC_POWERING_ON" pos="1" type="boolean"/>
90
+
<bitfield name="SPTPRAC_GDSC_POWER_OFF" pos="2" type="boolean"/>
91
+
<bitfield name="SPTPRAC_GDSC_POWER_ON" pos="3" type="boolean"/>
92
+
<bitfield name="SP_CLOCK_OFF" pos="4" type="boolean"/>
93
+
<bitfield name="GMU_UP_POWER_STATE" pos="5" type="boolean"/>
94
+
<bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/>
95
+
<bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/>
96
+
</reg32>
97
+
<reg32 offset="0x50e4" name="GMU_GPU_NAP_CTRL">
98
+
<bitfield name="HW_NAP_ENABLE" pos="0"/>
99
+
<bitfield name="SID" low="4" high="8"/>
100
+
</reg32>
101
+
<reg32 offset="0x50e8" name="GMU_RPMH_CTRL">
102
+
<bitfield name="RPMH_INTERFACE_ENABLE" pos="0" type="boolean"/>
103
+
<bitfield name="LLC_VOTE_ENABLE" pos="4" type="boolean"/>
104
+
<bitfield name="DDR_VOTE_ENABLE" pos="8" type="boolean"/>
105
+
<bitfield name="MX_VOTE_ENABLE" pos="9" type="boolean"/>
106
+
<bitfield name="CX_VOTE_ENABLE" pos="10" type="boolean"/>
107
+
<bitfield name="GFX_VOTE_ENABLE" pos="11" type="boolean"/>
108
+
<bitfield name="DDR_MIN_VOTE_ENABLE" pos="12" type="boolean"/>
109
+
<bitfield name="MX_MIN_VOTE_ENABLE" pos="13" type="boolean"/>
110
+
<bitfield name="CX_MIN_VOTE_ENABLE" pos="14" type="boolean"/>
111
+
<bitfield name="GFX_MIN_VOTE_ENABLE" pos="15" type="boolean"/>
112
+
</reg32>
113
+
<reg32 offset="0x50e9" name="GMU_RPMH_HYST_CTRL"/>
114
+
<reg32 offset="0x50ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/>
115
+
<reg32 offset="0x50f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/>
116
+
<reg32 offset="0x50f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF"/>
117
+
<reg32 offset="0x5100" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
118
+
<reg32 offset="0x5101" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
119
+
<reg32 offset="0x51f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
120
+
<reg32 offset="0x5157" name="GMU_LLM_GLM_SLEEP_CTRL"/>
121
+
<reg32 offset="0x5158" name="GMU_LLM_GLM_SLEEP_STATUS"/>
122
+
<reg32 offset="0x5088" name="GMU_ALWAYS_ON_COUNTER_L"/>
123
+
<reg32 offset="0x5089" name="GMU_ALWAYS_ON_COUNTER_H"/>
124
+
<reg32 offset="0x50c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/>
125
+
<reg32 offset="0x5180" name="GMU_HFI_CTRL_STATUS"/>
126
+
<reg32 offset="0x5181" name="GMU_HFI_VERSION_INFO"/>
127
+
<reg32 offset="0x5182" name="GMU_HFI_SFR_ADDR"/>
128
+
<reg32 offset="0x5183" name="GMU_HFI_MMAP_ADDR"/>
129
+
<reg32 offset="0x5184" name="GMU_HFI_QTBL_INFO"/>
130
+
<reg32 offset="0x5185" name="GMU_HFI_QTBL_ADDR"/>
131
+
<reg32 offset="0x5186" name="GMU_HFI_CTRL_INIT"/>
132
+
<reg32 offset="0x5190" name="GMU_GMU2HOST_INTR_SET"/>
133
+
<reg32 offset="0x5191" name="GMU_GMU2HOST_INTR_CLR"/>
134
+
<reg32 offset="0x5192" name="GMU_GMU2HOST_INTR_INFO">
135
+
<bitfield name="MSGQ" pos="0" type="boolean"/>
136
+
<bitfield name="CM3_FAULT" pos="23" type="boolean"/>
137
+
</reg32>
138
+
<reg32 offset="0x5193" name="GMU_GMU2HOST_INTR_MASK"/>
139
+
<reg32 offset="0x5194" name="GMU_HOST2GMU_INTR_SET"/>
140
+
<reg32 offset="0x5195" name="GMU_HOST2GMU_INTR_CLR"/>
141
+
<reg32 offset="0x5196" name="GMU_HOST2GMU_INTR_RAW_INFO"/>
142
+
<reg32 offset="0x5197" name="GMU_HOST2GMU_INTR_EN_0"/>
143
+
<reg32 offset="0x5198" name="GMU_HOST2GMU_INTR_EN_1"/>
144
+
<reg32 offset="0x5199" name="GMU_HOST2GMU_INTR_EN_2"/>
145
+
<reg32 offset="0x519a" name="GMU_HOST2GMU_INTR_EN_3"/>
146
+
<reg32 offset="0x519b" name="GMU_HOST2GMU_INTR_INFO_0"/>
147
+
<reg32 offset="0x519c" name="GMU_HOST2GMU_INTR_INFO_1"/>
148
+
<reg32 offset="0x519d" name="GMU_HOST2GMU_INTR_INFO_2"/>
149
+
<reg32 offset="0x519e" name="GMU_HOST2GMU_INTR_INFO_3"/>
150
+
<reg32 offset="0x51c5" name="GMU_GENERAL_0"/>
151
+
<reg32 offset="0x51c6" name="GMU_GENERAL_1"/>
152
+
<reg32 offset="0x51cb" name="GMU_GENERAL_6"/>
153
+
<reg32 offset="0x51cc" name="GMU_GENERAL_7"/>
154
+
<reg32 offset="0x51cd" name="GMU_GENERAL_8" variants="A7XX"/>
155
+
<reg32 offset="0x51ce" name="GMU_GENERAL_9" variants="A7XX"/>
156
+
<reg32 offset="0x51cf" name="GMU_GENERAL_10" variants="A7XX"/>
157
+
<reg32 offset="0x515d" name="GMU_ISENSE_CTRL"/>
158
+
<reg32 offset="0x8920" name="GPU_CS_ENABLE_REG"/>
159
+
<reg32 offset="0x515d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/>
160
+
<reg32 offset="0x8578" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/>
161
+
<reg32 offset="0x8558" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/>
162
+
<reg32 offset="0x8580" name="GPU_CS_A_SENSOR_CTRL_0"/>
163
+
<reg32 offset="0x27ada" name="GPU_CS_A_SENSOR_CTRL_2"/>
164
+
<reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
165
+
<reg32 offset="0x8957" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
166
+
<reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
167
+
<reg32 offset="0x881d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
168
+
<reg32 offset="0x881f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
169
+
<reg32 offset="0x8821" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
170
+
<reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
171
+
<reg32 offset="0x896d" name="GPU_CS_AMP_PERIOD_CTRL"/>
172
+
<reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
173
+
<reg32 offset="0x514d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/>
174
+
<reg32 offset="0x9303" name="GMU_AO_INTERRUPT_EN"/>
175
+
<reg32 offset="0x9304" name="GMU_AO_HOST_INTERRUPT_CLR"/>
176
+
<reg32 offset="0x9305" name="GMU_AO_HOST_INTERRUPT_STATUS">
177
+
<bitfield name="WDOG_BITE" pos="0" type="boolean"/>
178
+
<bitfield name="RSCC_COMP" pos="1" type="boolean"/>
179
+
<bitfield name="VDROOP" pos="2" type="boolean"/>
180
+
<bitfield name="FENCE_ERR" pos="3" type="boolean"/>
181
+
<bitfield name="DBD_WAKEUP" pos="4" type="boolean"/>
182
+
<bitfield name="HOST_AHB_BUS_ERROR" pos="5" type="boolean"/>
183
+
</reg32>
184
+
<reg32 offset="0x9306" name="GMU_AO_HOST_INTERRUPT_MASK"/>
185
+
<reg32 offset="0x9309" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/>
186
+
<reg32 offset="0x930a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/>
187
+
<reg32 offset="0x930b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/>
188
+
<reg32 offset="0x930c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS">
189
+
<bitfield name = "GPUBUSYIGNAHB" pos="23" type="boolean"/>
190
+
</reg32>
191
+
<reg32 offset="0x930d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/>
192
+
<reg32 offset="0x930e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/>
193
+
<reg32 offset="0x9310" name="GMU_AO_AHB_FENCE_CTRL"/>
194
+
<reg32 offset="0x9313" name="GMU_AHB_FENCE_STATUS"/>
195
+
<reg32 offset="0x9314" name="GMU_AHB_FENCE_STATUS_CLR"/>
196
+
<reg32 offset="0x9315" name="GMU_RBBM_INT_UNMASKED_STATUS"/>
197
+
<reg32 offset="0x9316" name="GMU_AO_SPARE_CNTL"/>
198
+
<reg32 offset="0x9307" name="GMU_RSCC_CONTROL_REQ"/>
199
+
<reg32 offset="0x9308" name="GMU_RSCC_CONTROL_ACK"/>
200
+
<reg32 offset="0x9311" name="GMU_AHB_FENCE_RANGE_0"/>
201
+
<reg32 offset="0x9312" name="GMU_AHB_FENCE_RANGE_1"/>
202
+
<reg32 offset="0x9c03" name="GPU_CC_GX_GDSCR"/>
203
+
<reg32 offset="0x9d42" name="GPU_CC_GX_DOMAIN_MISC"/>
204
+
<reg32 offset="0xc001" name="GPU_CPR_FSM_CTL"/>
205
+
206
+
<!-- starts at offset 0x8c00 on most gpus -->
207
+
<reg32 offset="0x0004" name="GPU_RSCC_RSC_STATUS0_DRV0"/>
208
+
<reg32 offset="0x0008" name="RSCC_PDC_SEQ_START_ADDR"/>
209
+
<reg32 offset="0x0009" name="RSCC_PDC_MATCH_VALUE_LO"/>
210
+
<reg32 offset="0x000a" name="RSCC_PDC_MATCH_VALUE_HI"/>
211
+
<reg32 offset="0x000b" name="RSCC_PDC_SLAVE_ID_DRV0"/>
212
+
<reg32 offset="0x000d" name="RSCC_HIDDEN_TCS_CMD0_ADDR"/>
213
+
<reg32 offset="0x000e" name="RSCC_HIDDEN_TCS_CMD0_DATA"/>
214
+
<reg32 offset="0x0082" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0"/>
215
+
<reg32 offset="0x0083" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0"/>
216
+
<reg32 offset="0x0089" name="RSCC_TIMESTAMP_UNIT1_EN_DRV0"/>
217
+
<reg32 offset="0x008c" name="RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0"/>
218
+
<reg32 offset="0x0100" name="RSCC_OVERRIDE_START_ADDR"/>
219
+
<reg32 offset="0x0101" name="RSCC_SEQ_BUSY_DRV0"/>
220
+
<reg32 offset="0x0154" name="RSCC_SEQ_MEM_0_DRV0_A740" variants="A7XX"/>
221
+
<reg32 offset="0x0180" name="RSCC_SEQ_MEM_0_DRV0"/>
222
+
<reg32 offset="0x0346" name="RSCC_TCS0_DRV0_STATUS"/>
223
+
<reg32 offset="0x03ee" name="RSCC_TCS1_DRV0_STATUS"/>
224
+
<reg32 offset="0x0496" name="RSCC_TCS2_DRV0_STATUS"/>
225
+
<reg32 offset="0x053e" name="RSCC_TCS3_DRV0_STATUS"/>
226
+
</domain>
227
+
228
+
</database>