Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM fixes from Paolo Bonzini:
"Bug fixes (ARM, s390, x86)"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: async_pf: avoid async pf injection when in guest mode
KVM: cpuid: Fix read/write out-of-bounds vulnerability in cpuid emulation
arm: KVM: Allow unaligned accesses at HYP
arm64: KVM: Allow unaligned accesses at EL2
arm64: KVM: Preserve RES1 bits in SCTLR_EL2
KVM: arm/arm64: Handle possible NULL stage2 pud when ageing pages
KVM: nVMX: Fix exception injection
kvm: async_pf: fix rcu_irq_enter() with irqs enabled
KVM: arm/arm64: vgic-v3: Fix nr_pre_bits bitfield extraction
KVM: s390: fix ais handling vs cpu model
KVM: arm/arm64: Fix isues with GICv2 on GICv3 migration
+153
-59
+2
-3
arch/arm/kvm/init.S
+2
-3
arch/arm/kvm/init.S
···
104
104
@ - Write permission implies XN: disabled
105
105
@ - Instruction cache: enabled
106
106
@ - Data/Unified cache: enabled
107
-
@ - Memory alignment checks: enabled
108
107
@ - MMU: enabled (this code must be run from an identity mapping)
109
108
mrc p15, 4, r0, c1, c0, 0 @ HSCR
110
109
ldr r2, =HSCTLR_MASK
···
111
112
mrc p15, 0, r1, c1, c0, 0 @ SCTLR
112
113
ldr r2, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)
113
114
and r1, r1, r2
114
-
ARM( ldr r2, =(HSCTLR_M | HSCTLR_A) )
115
-
THUMB( ldr r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE) )
115
+
ARM( ldr r2, =(HSCTLR_M) )
116
+
THUMB( ldr r2, =(HSCTLR_M | HSCTLR_TE) )
116
117
orr r1, r1, r2
117
118
orr r0, r0, r1
118
119
mcr p15, 4, r0, c1, c0, 0 @ HSCR
+4
arch/arm64/include/asm/sysreg.h
+4
arch/arm64/include/asm/sysreg.h
···
286
286
#define SCTLR_ELx_A (1 << 1)
287
287
#define SCTLR_ELx_M 1
288
288
289
+
#define SCTLR_EL2_RES1 ((1 << 4) | (1 << 5) | (1 << 11) | (1 << 16) | \
290
+
(1 << 16) | (1 << 18) | (1 << 22) | (1 << 23) | \
291
+
(1 << 28) | (1 << 29))
292
+
289
293
#define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
290
294
SCTLR_ELx_SA | SCTLR_ELx_I)
291
295
+7
-4
arch/arm64/kvm/hyp-init.S
+7
-4
arch/arm64/kvm/hyp-init.S
···
106
106
tlbi alle2
107
107
dsb sy
108
108
109
-
mrs x4, sctlr_el2
110
-
and x4, x4, #SCTLR_ELx_EE // preserve endianness of EL2
111
-
ldr x5, =SCTLR_ELx_FLAGS
112
-
orr x4, x4, x5
109
+
/*
110
+
* Preserve all the RES1 bits while setting the default flags,
111
+
* as well as the EE bit on BE. Drop the A flag since the compiler
112
+
* is allowed to generate unaligned accesses.
113
+
*/
114
+
ldr x4, =(SCTLR_EL2_RES1 | (SCTLR_ELx_FLAGS & ~SCTLR_ELx_A))
115
+
CPU_BE( orr x4, x4, #SCTLR_ELx_EE)
113
116
msr sctlr_el2, x4
114
117
isb
115
118
+5
-5
arch/arm64/kvm/vgic-sys-reg-v3.c
+5
-5
arch/arm64/kvm/vgic-sys-reg-v3.c
···
65
65
* Here set VMCR.CTLR in ICC_CTLR_EL1 layout.
66
66
* The vgic_set_vmcr() will convert to ICH_VMCR layout.
67
67
*/
68
-
vmcr.ctlr = val & ICC_CTLR_EL1_CBPR_MASK;
69
-
vmcr.ctlr |= val & ICC_CTLR_EL1_EOImode_MASK;
68
+
vmcr.cbpr = (val & ICC_CTLR_EL1_CBPR_MASK) >> ICC_CTLR_EL1_CBPR_SHIFT;
69
+
vmcr.eoim = (val & ICC_CTLR_EL1_EOImode_MASK) >> ICC_CTLR_EL1_EOImode_SHIFT;
70
70
vgic_set_vmcr(vcpu, &vmcr);
71
71
} else {
72
72
val = 0;
···
83
83
* The VMCR.CTLR value is in ICC_CTLR_EL1 layout.
84
84
* Extract it directly using ICC_CTLR_EL1 reg definitions.
85
85
*/
86
-
val |= vmcr.ctlr & ICC_CTLR_EL1_CBPR_MASK;
87
-
val |= vmcr.ctlr & ICC_CTLR_EL1_EOImode_MASK;
86
+
val |= (vmcr.cbpr << ICC_CTLR_EL1_CBPR_SHIFT) & ICC_CTLR_EL1_CBPR_MASK;
87
+
val |= (vmcr.eoim << ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
88
88
89
89
p->regval = val;
90
90
}
···
135
135
p->regval = 0;
136
136
137
137
vgic_get_vmcr(vcpu, &vmcr);
138
-
if (!((vmcr.ctlr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT)) {
138
+
if (!vmcr.cbpr) {
139
139
if (p->is_write) {
140
140
vmcr.abpr = (p->regval & ICC_BPR1_EL1_MASK) >>
141
141
ICC_BPR1_EL1_SHIFT;
-1
arch/s390/include/asm/kvm_host.h
-1
arch/s390/include/asm/kvm_host.h
+2
-2
arch/s390/kvm/interrupt.c
+2
-2
arch/s390/kvm/interrupt.c
···
2160
2160
struct kvm_s390_ais_req req;
2161
2161
int ret = 0;
2162
2162
2163
-
if (!fi->ais_enabled)
2163
+
if (!test_kvm_facility(kvm, 72))
2164
2164
return -ENOTSUPP;
2165
2165
2166
2166
if (copy_from_user(&req, (void __user *)attr->addr, sizeof(req)))
···
2204
2204
};
2205
2205
int ret = 0;
2206
2206
2207
-
if (!fi->ais_enabled || !adapter->suppressible)
2207
+
if (!test_kvm_facility(kvm, 72) || !adapter->suppressible)
2208
2208
return kvm_s390_inject_vm(kvm, &s390int);
2209
2209
2210
2210
mutex_lock(&fi->ais_lock);
-2
arch/s390/kvm/kvm-s390.c
-2
arch/s390/kvm/kvm-s390.c
···
558
558
} else {
559
559
set_kvm_facility(kvm->arch.model.fac_mask, 72);
560
560
set_kvm_facility(kvm->arch.model.fac_list, 72);
561
-
kvm->arch.float_int.ais_enabled = 1;
562
561
r = 0;
563
562
}
564
563
mutex_unlock(&kvm->lock);
···
1532
1533
mutex_init(&kvm->arch.float_int.ais_lock);
1533
1534
kvm->arch.float_int.simm = 0;
1534
1535
kvm->arch.float_int.nimm = 0;
1535
-
kvm->arch.float_int.ais_enabled = 0;
1536
1536
spin_lock_init(&kvm->arch.float_int.lock);
1537
1537
for (i = 0; i < FIRQ_LIST_COUNT; i++)
1538
1538
INIT_LIST_HEAD(&kvm->arch.float_int.lists[i]);
+1
-1
arch/x86/kernel/kvm.c
+1
-1
arch/x86/kernel/kvm.c
+11
-9
arch/x86/kvm/cpuid.c
+11
-9
arch/x86/kvm/cpuid.c
···
780
780
static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
781
781
{
782
782
struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
783
-
int j, nent = vcpu->arch.cpuid_nent;
783
+
struct kvm_cpuid_entry2 *ej;
784
+
int j = i;
785
+
int nent = vcpu->arch.cpuid_nent;
784
786
785
787
e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
786
788
/* when no next entry is found, the current entry[i] is reselected */
787
-
for (j = i + 1; ; j = (j + 1) % nent) {
788
-
struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
789
-
if (ej->function == e->function) {
790
-
ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
791
-
return j;
792
-
}
793
-
}
794
-
return 0; /* silence gcc, even though control never reaches here */
789
+
do {
790
+
j = (j + 1) % nent;
791
+
ej = &vcpu->arch.cpuid_entries[j];
792
+
} while (ej->function != e->function);
793
+
794
+
ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
795
+
796
+
return j;
795
797
}
796
798
797
799
/* find an entry with matching function, matching index (if needed), and that
+5
-2
arch/x86/kvm/mmu.c
+5
-2
arch/x86/kvm/mmu.c
···
3698
3698
return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3699
3699
}
3700
3700
3701
-
static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3701
+
bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
3702
3702
{
3703
3703
if (unlikely(!lapic_in_kernel(vcpu) ||
3704
3704
kvm_event_needs_reinjection(vcpu)))
3705
+
return false;
3706
+
3707
+
if (is_guest_mode(vcpu))
3705
3708
return false;
3706
3709
3707
3710
return kvm_x86_ops->interrupt_allowed(vcpu);
···
3722
3719
if (!async)
3723
3720
return false; /* *pfn has correct page already */
3724
3721
3725
-
if (!prefault && can_do_async_pf(vcpu)) {
3722
+
if (!prefault && kvm_can_do_async_pf(vcpu)) {
3726
3723
trace_kvm_try_async_get_page(gva, gfn);
3727
3724
if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3728
3725
trace_kvm_async_pf_doublefault(gva, gfn);
+1
arch/x86/kvm/mmu.h
+1
arch/x86/kvm/mmu.h
···
76
76
void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu);
77
77
void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
78
78
bool accessed_dirty);
79
+
bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
79
80
80
81
static inline unsigned int kvm_mmu_available_pages(struct kvm *kvm)
81
82
{
+1
-1
arch/x86/kvm/vmx.c
+1
-1
arch/x86/kvm/vmx.c
···
2425
2425
if (!(vmcs12->exception_bitmap & (1u << nr)))
2426
2426
return 0;
2427
2427
2428
-
nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2428
+
nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
2429
2429
vmcs_read32(VM_EXIT_INTR_INFO),
2430
2430
vmcs_readl(EXIT_QUALIFICATION));
2431
2431
return 1;
+1
-2
arch/x86/kvm/x86.c
+1
-2
arch/x86/kvm/x86.c
···
8607
8607
if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8608
8608
return true;
8609
8609
else
8610
-
return !kvm_event_needs_reinjection(vcpu) &&
8611
-
kvm_x86_ops->interrupt_allowed(vcpu);
8610
+
return kvm_can_do_async_pf(vcpu);
8612
8611
}
8613
8612
8614
8613
void kvm_arch_start_assignment(struct kvm *kvm)
+4
include/linux/irqchip/arm-gic-v3.h
+4
include/linux/irqchip/arm-gic-v3.h
···
417
417
#define ICH_HCR_EN (1 << 0)
418
418
#define ICH_HCR_UIE (1 << 1)
419
419
420
+
#define ICH_VMCR_ACK_CTL_SHIFT 2
421
+
#define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT)
422
+
#define ICH_VMCR_FIQ_EN_SHIFT 3
423
+
#define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT)
420
424
#define ICH_VMCR_CBPR_SHIFT 4
421
425
#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
422
426
#define ICH_VMCR_EOIM_SHIFT 9
+25
-3
include/linux/irqchip/arm-gic.h
+25
-3
include/linux/irqchip/arm-gic.h
···
25
25
#define GICC_ENABLE 0x1
26
26
#define GICC_INT_PRI_THRESHOLD 0xf0
27
27
28
-
#define GIC_CPU_CTRL_EOImodeNS (1 << 9)
28
+
#define GIC_CPU_CTRL_EnableGrp0_SHIFT 0
29
+
#define GIC_CPU_CTRL_EnableGrp0 (1 << GIC_CPU_CTRL_EnableGrp0_SHIFT)
30
+
#define GIC_CPU_CTRL_EnableGrp1_SHIFT 1
31
+
#define GIC_CPU_CTRL_EnableGrp1 (1 << GIC_CPU_CTRL_EnableGrp1_SHIFT)
32
+
#define GIC_CPU_CTRL_AckCtl_SHIFT 2
33
+
#define GIC_CPU_CTRL_AckCtl (1 << GIC_CPU_CTRL_AckCtl_SHIFT)
34
+
#define GIC_CPU_CTRL_FIQEn_SHIFT 3
35
+
#define GIC_CPU_CTRL_FIQEn (1 << GIC_CPU_CTRL_FIQEn_SHIFT)
36
+
#define GIC_CPU_CTRL_CBPR_SHIFT 4
37
+
#define GIC_CPU_CTRL_CBPR (1 << GIC_CPU_CTRL_CBPR_SHIFT)
38
+
#define GIC_CPU_CTRL_EOImodeNS_SHIFT 9
39
+
#define GIC_CPU_CTRL_EOImodeNS (1 << GIC_CPU_CTRL_EOImodeNS_SHIFT)
29
40
30
41
#define GICC_IAR_INT_ID_MASK 0x3ff
31
42
#define GICC_INT_SPURIOUS 1023
···
95
84
#define GICH_LR_EOI (1 << 19)
96
85
#define GICH_LR_HW (1 << 31)
97
86
98
-
#define GICH_VMCR_CTRL_SHIFT 0
99
-
#define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT)
87
+
#define GICH_VMCR_ENABLE_GRP0_SHIFT 0
88
+
#define GICH_VMCR_ENABLE_GRP0_MASK (1 << GICH_VMCR_ENABLE_GRP0_SHIFT)
89
+
#define GICH_VMCR_ENABLE_GRP1_SHIFT 1
90
+
#define GICH_VMCR_ENABLE_GRP1_MASK (1 << GICH_VMCR_ENABLE_GRP1_SHIFT)
91
+
#define GICH_VMCR_ACK_CTL_SHIFT 2
92
+
#define GICH_VMCR_ACK_CTL_MASK (1 << GICH_VMCR_ACK_CTL_SHIFT)
93
+
#define GICH_VMCR_FIQ_EN_SHIFT 3
94
+
#define GICH_VMCR_FIQ_EN_MASK (1 << GICH_VMCR_FIQ_EN_SHIFT)
95
+
#define GICH_VMCR_CBPR_SHIFT 4
96
+
#define GICH_VMCR_CBPR_MASK (1 << GICH_VMCR_CBPR_SHIFT)
97
+
#define GICH_VMCR_EOI_MODE_SHIFT 9
98
+
#define GICH_VMCR_EOI_MODE_MASK (1 << GICH_VMCR_EOI_MODE_SHIFT)
99
+
100
100
#define GICH_VMCR_PRIMASK_SHIFT 27
101
101
#define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT)
102
102
#define GICH_VMCR_BINPOINT_SHIFT 21
+1
-1
virt/kvm/arm/hyp/vgic-v3-sr.c
+1
-1
virt/kvm/arm/hyp/vgic-v3-sr.c
+3
virt/kvm/arm/mmu.c
+3
virt/kvm/arm/mmu.c
+14
-2
virt/kvm/arm/vgic/vgic-mmio-v2.c
+14
-2
virt/kvm/arm/vgic/vgic-mmio-v2.c
···
226
226
227
227
switch (addr & 0xff) {
228
228
case GIC_CPU_CTRL:
229
-
val = vmcr.ctlr;
229
+
val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT;
230
+
val |= vmcr.grpen1 << GIC_CPU_CTRL_EnableGrp1_SHIFT;
231
+
val |= vmcr.ackctl << GIC_CPU_CTRL_AckCtl_SHIFT;
232
+
val |= vmcr.fiqen << GIC_CPU_CTRL_FIQEn_SHIFT;
233
+
val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT;
234
+
val |= vmcr.eoim << GIC_CPU_CTRL_EOImodeNS_SHIFT;
235
+
230
236
break;
231
237
case GIC_CPU_PRIMASK:
232
238
/*
···
273
267
274
268
switch (addr & 0xff) {
275
269
case GIC_CPU_CTRL:
276
-
vmcr.ctlr = val;
270
+
vmcr.grpen0 = !!(val & GIC_CPU_CTRL_EnableGrp0);
271
+
vmcr.grpen1 = !!(val & GIC_CPU_CTRL_EnableGrp1);
272
+
vmcr.ackctl = !!(val & GIC_CPU_CTRL_AckCtl);
273
+
vmcr.fiqen = !!(val & GIC_CPU_CTRL_FIQEn);
274
+
vmcr.cbpr = !!(val & GIC_CPU_CTRL_CBPR);
275
+
vmcr.eoim = !!(val & GIC_CPU_CTRL_EOImodeNS);
276
+
277
277
break;
278
278
case GIC_CPU_PRIMASK:
279
279
/*
+25
-3
virt/kvm/arm/vgic/vgic-v2.c
+25
-3
virt/kvm/arm/vgic/vgic-v2.c
···
177
177
struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
178
178
u32 vmcr;
179
179
180
-
vmcr = (vmcrp->ctlr << GICH_VMCR_CTRL_SHIFT) & GICH_VMCR_CTRL_MASK;
180
+
vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
181
+
GICH_VMCR_ENABLE_GRP0_MASK;
182
+
vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
183
+
GICH_VMCR_ENABLE_GRP1_MASK;
184
+
vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
185
+
GICH_VMCR_ACK_CTL_MASK;
186
+
vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
187
+
GICH_VMCR_FIQ_EN_MASK;
188
+
vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
189
+
GICH_VMCR_CBPR_MASK;
190
+
vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
191
+
GICH_VMCR_EOI_MODE_MASK;
181
192
vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
182
193
GICH_VMCR_ALIAS_BINPOINT_MASK;
183
194
vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
···
206
195
207
196
vmcr = cpu_if->vgic_vmcr;
208
197
209
-
vmcrp->ctlr = (vmcr & GICH_VMCR_CTRL_MASK) >>
210
-
GICH_VMCR_CTRL_SHIFT;
198
+
vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
199
+
GICH_VMCR_ENABLE_GRP0_SHIFT;
200
+
vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
201
+
GICH_VMCR_ENABLE_GRP1_SHIFT;
202
+
vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
203
+
GICH_VMCR_ACK_CTL_SHIFT;
204
+
vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
205
+
GICH_VMCR_FIQ_EN_SHIFT;
206
+
vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
207
+
GICH_VMCR_CBPR_SHIFT;
208
+
vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
209
+
GICH_VMCR_EOI_MODE_SHIFT;
210
+
211
211
vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
212
212
GICH_VMCR_ALIAS_BINPOINT_SHIFT;
213
213
vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
+33
-14
virt/kvm/arm/vgic/vgic-v3.c
+33
-14
virt/kvm/arm/vgic/vgic-v3.c
···
159
159
void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
160
160
{
161
161
struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
162
+
u32 model = vcpu->kvm->arch.vgic.vgic_model;
162
163
u32 vmcr;
163
164
164
-
/*
165
-
* Ignore the FIQen bit, because GIC emulation always implies
166
-
* SRE=1 which means the vFIQEn bit is also RES1.
167
-
*/
168
-
vmcr = ((vmcrp->ctlr >> ICC_CTLR_EL1_EOImode_SHIFT) <<
169
-
ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
170
-
vmcr |= (vmcrp->ctlr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
165
+
if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
166
+
vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) &
167
+
ICH_VMCR_ACK_CTL_MASK;
168
+
vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) &
169
+
ICH_VMCR_FIQ_EN_MASK;
170
+
} else {
171
+
/*
172
+
* When emulating GICv3 on GICv3 with SRE=1 on the
173
+
* VFIQEn bit is RES1 and the VAckCtl bit is RES0.
174
+
*/
175
+
vmcr = ICH_VMCR_FIQ_EN_MASK;
176
+
}
177
+
178
+
vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK;
179
+
vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK;
171
180
vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK;
172
181
vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK;
173
182
vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK;
···
189
180
void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
190
181
{
191
182
struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
183
+
u32 model = vcpu->kvm->arch.vgic.vgic_model;
192
184
u32 vmcr;
193
185
194
186
vmcr = cpu_if->vgic_vmcr;
195
187
196
-
/*
197
-
* Ignore the FIQen bit, because GIC emulation always implies
198
-
* SRE=1 which means the vFIQEn bit is also RES1.
199
-
*/
200
-
vmcrp->ctlr = ((vmcr >> ICH_VMCR_EOIM_SHIFT) <<
201
-
ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
202
-
vmcrp->ctlr |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
188
+
if (model == KVM_DEV_TYPE_ARM_VGIC_V2) {
189
+
vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >>
190
+
ICH_VMCR_ACK_CTL_SHIFT;
191
+
vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >>
192
+
ICH_VMCR_FIQ_EN_SHIFT;
193
+
} else {
194
+
/*
195
+
* When emulating GICv3 on GICv3 with SRE=1 on the
196
+
* VFIQEn bit is RES1 and the VAckCtl bit is RES0.
197
+
*/
198
+
vmcrp->fiqen = 1;
199
+
vmcrp->ackctl = 0;
200
+
}
201
+
202
+
vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT;
203
+
vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT;
203
204
vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT;
204
205
vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT;
205
206
vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT;
+8
-4
virt/kvm/arm/vgic/vgic.h
+8
-4
virt/kvm/arm/vgic/vgic.h
···
111
111
* registers regardless of the hardware backed GIC used.
112
112
*/
113
113
struct vgic_vmcr {
114
-
u32 ctlr;
114
+
u32 grpen0;
115
+
u32 grpen1;
116
+
117
+
u32 ackctl;
118
+
u32 fiqen;
119
+
u32 cbpr;
120
+
u32 eoim;
121
+
115
122
u32 abpr;
116
123
u32 bpr;
117
124
u32 pmr; /* Priority mask field in the GICC_PMR and
118
125
* ICC_PMR_EL1 priority field format */
119
-
/* Below member variable are valid only for GICv3 */
120
-
u32 grpen0;
121
-
u32 grpen1;
122
126
};
123
127
124
128
struct vgic_reg_attr {