Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'icc-6.11-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
Georgi writes:
interconnect changes for 6.11
This pull request contains the interconnect changes for the 6.11-rc1 merge
window. It contains just driver changes with the following highlights:
Driver changes:
- New driver for MediaTek MT8183/8195 platforms
- New driver for MSM8953 platforms
- New QoS support for RPMh-based platforms with SC7280 being the
first one to benefit from it.
- Fix incorrect master-id value in qcm2290 driver
- Add missing MODULE_DESCRIPTION in a few drivers
Signed-off-by: Georgi Djakov <djakov@kernel.org>
* tag 'icc-6.11-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
interconnect: qcom: Fix DT backwards compatibility for QoS
interconnect: qcom: Add MSM8953 driver
dt-bindings: interconnect: qcom: Add Qualcomm MSM8953 NoC
interconnect: qcom: qcm2290: Fix mas_snoc_bimc RPM master ID
interconnect: qcom: sc7280: enable QoS configuration
interconnect: qcom: icc-rpmh: Add QoS configuration support
dt-bindings: interconnect: add clock property to enable QOS on SC7280
interconnect: mediatek: remove unneeded semicolon
interconnect: qcom: add missing MODULE_DESCRIPTION() macros
interconnect: imx: add missing MODULE_DESCRIPTION() macros
interconnect: mediatek: Add MediaTek MT8183/8195 EMI Interconnect driver
dt-bindings: interconnect: Add MediaTek EMI Interconnect bindings
+2821
-1
+51
Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml
+51
Documentation/devicetree/bindings/interconnect/mediatek,mt8183-emi.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/mediatek,mt8183-emi.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: MediaTek External Memory Interface (EMI) Interconnect
8
+
9
+
maintainers:
10
+
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11
+
12
+
description: |
13
+
EMI interconnect providers support system bandwidth requirements through
14
+
Dynamic Voltage Frequency Scaling Resource Collector (DVFSRC) hardware.
15
+
The provider is able to communicate with the DVFSRC through Secure Monitor
16
+
Call (SMC).
17
+
18
+
ICC provider ICC Nodes
19
+
---- ----
20
+
_________ |CPU | |--- |VPU |
21
+
_____ | |----- ---- | ----
22
+
| |->| DRAM | ---- | ----
23
+
|DRAM |->|scheduler|----- |GPU | |--- |DISP|
24
+
| |->| (EMI) | ---- | ----
25
+
|_____|->|_________|---. ----- | ----
26
+
/|\ `-|MMSYS|--|--- |VDEC|
27
+
| ----- | ----
28
+
| | ----
29
+
| change DRAM freq |--- |VENC|
30
+
-------- | ----
31
+
SMC --> | DVFSRC | | ----
32
+
-------- |--- |IMG |
33
+
| ----
34
+
| ----
35
+
|--- |CAM |
36
+
----
37
+
38
+
properties:
39
+
compatible:
40
+
enum:
41
+
- mediatek,mt8183-emi
42
+
- mediatek,mt8195-emi
43
+
44
+
'#interconnect-cells':
45
+
const: 1
46
+
47
+
required:
48
+
- compatible
49
+
- '#interconnect-cells'
50
+
51
+
unevaluatedProperties: false
+101
Documentation/devicetree/bindings/interconnect/qcom,msm8953.yaml
+101
Documentation/devicetree/bindings/interconnect/qcom,msm8953.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interconnect/qcom,msm8953.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm MSM8953 Network-On-Chip interconnect
8
+
9
+
maintainers:
10
+
- Barnabas Czeman <barnabas.czeman@mainlining.org>
11
+
12
+
description: |
13
+
The Qualcomm MSM8953 interconnect providers support adjusting the
14
+
bandwidth requirements between the various NoC fabrics.
15
+
16
+
See also:
17
+
- dt-bindings/interconnect/qcom,msm8953.h
18
+
19
+
properties:
20
+
compatible:
21
+
enum:
22
+
- qcom,msm8953-bimc
23
+
- qcom,msm8953-pcnoc
24
+
- qcom,msm8953-snoc
25
+
26
+
reg:
27
+
maxItems: 1
28
+
29
+
clocks:
30
+
maxItems: 1
31
+
32
+
clock-names:
33
+
maxItems: 1
34
+
35
+
'#interconnect-cells':
36
+
const: 2
37
+
38
+
patternProperties:
39
+
'^interconnect-[a-z0-9\-]+$':
40
+
type: object
41
+
$ref: qcom,rpm-common.yaml#
42
+
unevaluatedProperties: false
43
+
description:
44
+
The interconnect providers do not have a separate QoS register space,
45
+
but share parent's space.
46
+
47
+
properties:
48
+
compatible:
49
+
const: qcom,msm8953-snoc-mm
50
+
51
+
required:
52
+
- compatible
53
+
- '#interconnect-cells'
54
+
55
+
required:
56
+
- compatible
57
+
- reg
58
+
- '#interconnect-cells'
59
+
60
+
allOf:
61
+
- $ref: qcom,rpm-common.yaml#
62
+
- if:
63
+
properties:
64
+
compatible:
65
+
const: qcom,msm8953-pcnoc
66
+
67
+
then:
68
+
properties:
69
+
clocks:
70
+
items:
71
+
- description: PCNOC USB3 AXI Clock.
72
+
73
+
clock-names:
74
+
const: pcnoc_usb3_axi
75
+
76
+
required:
77
+
- clocks
78
+
- clock-names
79
+
else:
80
+
properties:
81
+
clocks: false
82
+
clock-names: false
83
+
84
+
additionalProperties: false
85
+
86
+
examples:
87
+
- |
88
+
#include <dt-bindings/clock/qcom,gcc-msm8953.h>
89
+
90
+
snoc: interconnect@580000 {
91
+
compatible = "qcom,msm8953-snoc";
92
+
reg = <0x580000 0x16080>;
93
+
94
+
#interconnect-cells = <2>;
95
+
96
+
snoc_mm: interconnect-snoc {
97
+
compatible = "qcom,msm8953-snoc-mm";
98
+
99
+
#interconnect-cells = <2>;
100
+
};
101
+
};
+53
Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
+53
Documentation/devicetree/bindings/interconnect/qcom,sc7280-rpmh.yaml
···
35
35
reg:
36
36
maxItems: 1
37
37
38
+
clocks:
39
+
minItems: 1
40
+
maxItems: 2
41
+
38
42
required:
39
43
- compatible
40
44
···
57
53
required:
58
54
- reg
59
55
56
+
- if:
57
+
properties:
58
+
compatible:
59
+
contains:
60
+
enum:
61
+
- qcom,sc7280-aggre1-noc
62
+
then:
63
+
properties:
64
+
clocks:
65
+
items:
66
+
- description: aggre UFS PHY AXI clock
67
+
- description: aggre USB3 PRIM AXI clock
68
+
69
+
- if:
70
+
properties:
71
+
compatible:
72
+
contains:
73
+
enum:
74
+
- qcom,sc7280-aggre2-noc
75
+
then:
76
+
properties:
77
+
clocks:
78
+
items:
79
+
- description: RPMH CC IPA clock
80
+
81
+
- if:
82
+
properties:
83
+
compatible:
84
+
contains:
85
+
enum:
86
+
- qcom,sc7280-aggre1-noc
87
+
- qcom,sc7280-aggre2-noc
88
+
then:
89
+
required:
90
+
- clocks
91
+
else:
92
+
properties:
93
+
clocks: false
94
+
60
95
unevaluatedProperties: false
61
96
62
97
examples:
63
98
- |
99
+
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
64
100
interconnect {
65
101
compatible = "qcom,sc7280-clk-virt";
66
102
#interconnect-cells = <2>;
···
112
68
compatible = "qcom,sc7280-gem-noc";
113
69
#interconnect-cells = <2>;
114
70
qcom,bcm-voters = <&apps_bcm_voter>;
71
+
};
72
+
73
+
interconnect@16e0000 {
74
+
reg = <0x016e0000 0x1c080>;
75
+
compatible = "qcom,sc7280-aggre1-noc";
76
+
#interconnect-cells = <2>;
77
+
qcom,bcm-voters = <&apps_bcm_voter>;
78
+
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
79
+
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
115
80
};
+1
drivers/interconnect/Kconfig
+1
drivers/interconnect/Kconfig
+1
drivers/interconnect/Makefile
+1
drivers/interconnect/Makefile
+1
drivers/interconnect/imx/imx.c
+1
drivers/interconnect/imx/imx.c
+1
drivers/interconnect/imx/imx8mm.c
+1
drivers/interconnect/imx/imx8mm.c
+1
drivers/interconnect/imx/imx8mn.c
+1
drivers/interconnect/imx/imx8mn.c
+1
drivers/interconnect/imx/imx8mp.c
+1
drivers/interconnect/imx/imx8mp.c
+1
drivers/interconnect/imx/imx8mq.c
+1
drivers/interconnect/imx/imx8mq.c
+29
drivers/interconnect/mediatek/Kconfig
+29
drivers/interconnect/mediatek/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
config INTERCONNECT_MTK
4
+
bool "MediaTek interconnect drivers"
5
+
depends on ARCH_MEDIATEK || COMPILE_TEST
6
+
help
7
+
Support for MediaTek's bus interconnect hardware.
8
+
9
+
config INTERCONNECT_MTK_DVFSRC_EMI
10
+
tristate "MediaTek DVFSRC EMI interconnect driver"
11
+
depends on INTERCONNECT_MTK && MTK_DVFSRC
12
+
help
13
+
This is a driver for the MediaTek External Memory Interface
14
+
interconnect on SoCs equipped with the integrated Dynamic
15
+
Voltage Frequency Scaling Resource Collector (DVFSRC) MCU
16
+
17
+
config INTERCONNECT_MTK_MT8183
18
+
tristate "MediaTek MT8183 interconnect driver"
19
+
depends on INTERCONNECT_MTK_DVFSRC_EMI
20
+
help
21
+
This is a driver for the MediaTek bus interconnect on MT8183-based
22
+
platforms.
23
+
24
+
config INTERCONNECT_MTK_MT8195
25
+
tristate "MediaTek MT8195 interconnect driver"
26
+
depends on INTERCONNECT_MTK_DVFSRC_EMI
27
+
help
28
+
This is a driver for the MediaTek bus interconnect on MT8195-based
29
+
platforms.
+5
drivers/interconnect/mediatek/Makefile
+5
drivers/interconnect/mediatek/Makefile
+153
drivers/interconnect/mediatek/icc-emi.c
+153
drivers/interconnect/mediatek/icc-emi.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* MediaTek External Memory Interface (EMI) Interconnect driver
4
+
*
5
+
* Copyright (c) 2021 MediaTek Inc.
6
+
* Copyright (c) 2024 Collabora Ltd.
7
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
8
+
*/
9
+
10
+
#include <linux/interconnect.h>
11
+
#include <linux/interconnect-provider.h>
12
+
#include <linux/module.h>
13
+
#include <linux/of.h>
14
+
#include <linux/of_platform.h>
15
+
#include <linux/platform_device.h>
16
+
#include <linux/soc/mediatek/dvfsrc.h>
17
+
18
+
#include "icc-emi.h"
19
+
20
+
static int mtk_emi_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
21
+
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
22
+
{
23
+
struct mtk_icc_node *in = node->data;
24
+
25
+
*agg_avg += avg_bw;
26
+
*agg_peak = max_t(u32, *agg_peak, peak_bw);
27
+
28
+
in->sum_avg = *agg_avg;
29
+
in->max_peak = *agg_peak;
30
+
31
+
return 0;
32
+
}
33
+
34
+
static int mtk_emi_icc_set(struct icc_node *src, struct icc_node *dst)
35
+
{
36
+
struct mtk_icc_node *node = dst->data;
37
+
struct device *dev;
38
+
int ret;
39
+
40
+
if (unlikely(!src->provider))
41
+
return -EINVAL;
42
+
43
+
dev = src->provider->dev;
44
+
45
+
switch (node->ep) {
46
+
case 0:
47
+
break;
48
+
case 1:
49
+
ret = mtk_dvfsrc_send_request(dev, MTK_DVFSRC_CMD_PEAK_BW, node->max_peak);
50
+
if (ret) {
51
+
dev_err(dev, "Cannot send peak bw request: %d\n", ret);
52
+
return ret;
53
+
}
54
+
55
+
ret = mtk_dvfsrc_send_request(dev, MTK_DVFSRC_CMD_BW, node->sum_avg);
56
+
if (ret) {
57
+
dev_err(dev, "Cannot send bw request: %d\n", ret);
58
+
return ret;
59
+
}
60
+
break;
61
+
case 2:
62
+
ret = mtk_dvfsrc_send_request(dev, MTK_DVFSRC_CMD_HRT_BW, node->sum_avg);
63
+
if (ret) {
64
+
dev_err(dev, "Cannot send HRT bw request: %d\n", ret);
65
+
return ret;
66
+
}
67
+
break;
68
+
default:
69
+
dev_err(src->provider->dev, "Unknown endpoint %u\n", node->ep);
70
+
return -EINVAL;
71
+
}
72
+
73
+
return 0;
74
+
}
75
+
76
+
int mtk_emi_icc_probe(struct platform_device *pdev)
77
+
{
78
+
const struct mtk_icc_desc *desc;
79
+
struct device *dev = &pdev->dev;
80
+
struct icc_node *node;
81
+
struct icc_onecell_data *data;
82
+
struct icc_provider *provider;
83
+
struct mtk_icc_node **mnodes;
84
+
int i, j, ret;
85
+
86
+
desc = of_device_get_match_data(dev);
87
+
if (!desc)
88
+
return -EINVAL;
89
+
90
+
mnodes = desc->nodes;
91
+
92
+
provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
93
+
if (!provider)
94
+
return -ENOMEM;
95
+
96
+
data = devm_kzalloc(dev, struct_size(data, nodes, desc->num_nodes), GFP_KERNEL);
97
+
if (!data)
98
+
return -ENOMEM;
99
+
100
+
provider->dev = pdev->dev.parent;
101
+
provider->set = mtk_emi_icc_set;
102
+
provider->aggregate = mtk_emi_icc_aggregate;
103
+
provider->xlate = of_icc_xlate_onecell;
104
+
INIT_LIST_HEAD(&provider->nodes);
105
+
provider->data = data;
106
+
107
+
for (i = 0; i < desc->num_nodes; i++) {
108
+
if (!mnodes[i])
109
+
continue;
110
+
111
+
node = icc_node_create(mnodes[i]->id);
112
+
if (IS_ERR(node)) {
113
+
ret = PTR_ERR(node);
114
+
goto err;
115
+
}
116
+
117
+
node->name = mnodes[i]->name;
118
+
node->data = mnodes[i];
119
+
icc_node_add(node, provider);
120
+
121
+
for (j = 0; j < mnodes[i]->num_links; j++)
122
+
icc_link_create(node, mnodes[i]->links[j]);
123
+
124
+
data->nodes[i] = node;
125
+
}
126
+
data->num_nodes = desc->num_nodes;
127
+
128
+
ret = icc_provider_register(provider);
129
+
if (ret)
130
+
goto err;
131
+
132
+
platform_set_drvdata(pdev, provider);
133
+
134
+
return 0;
135
+
err:
136
+
icc_nodes_remove(provider);
137
+
return ret;
138
+
}
139
+
EXPORT_SYMBOL_GPL(mtk_emi_icc_probe);
140
+
141
+
void mtk_emi_icc_remove(struct platform_device *pdev)
142
+
{
143
+
struct icc_provider *provider = platform_get_drvdata(pdev);
144
+
145
+
icc_provider_deregister(provider);
146
+
icc_nodes_remove(provider);
147
+
}
148
+
EXPORT_SYMBOL_GPL(mtk_emi_icc_remove);
149
+
150
+
MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
151
+
MODULE_AUTHOR("Henry Chen <henryc.chen@mediatek.com>");
152
+
MODULE_DESCRIPTION("MediaTek External Memory Interface interconnect driver");
153
+
MODULE_LICENSE("GPL");
+40
drivers/interconnect/mediatek/icc-emi.h
+40
drivers/interconnect/mediatek/icc-emi.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Copyright (c) 2024 Collabora Ltd.
5
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6
+
*/
7
+
8
+
#ifndef __DRIVERS_INTERCONNECT_MEDIATEK_ICC_EMI_H
9
+
#define __DRIVERS_INTERCONNECT_MEDIATEK_ICC_EMI_H
10
+
11
+
/**
12
+
* struct mtk_icc_node - Mediatek EMI Interconnect Node
13
+
* @name: The interconnect node name which is shown in debugfs
14
+
* @ep: Type of this endpoint
15
+
* @id: Unique node identifier
16
+
* @sum_avg: Current sum aggregate value of all average bw requests in kBps
17
+
* @max_peak: Current max aggregate value of all peak bw requests in kBps
18
+
* @num_links: The total number of @links
19
+
* @links: Array of @id linked to this node
20
+
*/
21
+
struct mtk_icc_node {
22
+
unsigned char *name;
23
+
int ep;
24
+
u16 id;
25
+
u64 sum_avg;
26
+
u64 max_peak;
27
+
28
+
u16 num_links;
29
+
u16 links[] __counted_by(num_links);
30
+
};
31
+
32
+
struct mtk_icc_desc {
33
+
struct mtk_icc_node **nodes;
34
+
size_t num_nodes;
35
+
};
36
+
37
+
int mtk_emi_icc_probe(struct platform_device *pdev);
38
+
void mtk_emi_icc_remove(struct platform_device *pdev);
39
+
40
+
#endif /* __DRIVERS_INTERCONNECT_MEDIATEK_ICC_EMI_H */
+143
drivers/interconnect/mediatek/mt8183.c
+143
drivers/interconnect/mediatek/mt8183.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Copyright (c) 2024 Collabora Ltd.
5
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6
+
*/
7
+
8
+
#include <linux/device.h>
9
+
#include <linux/interconnect.h>
10
+
#include <linux/interconnect-provider.h>
11
+
#include <linux/mod_devicetable.h>
12
+
#include <linux/module.h>
13
+
#include <linux/platform_device.h>
14
+
#include <dt-bindings/interconnect/mediatek,mt8183.h>
15
+
16
+
#include "icc-emi.h"
17
+
18
+
static struct mtk_icc_node ddr_emi = {
19
+
.name = "ddr-emi",
20
+
.id = SLAVE_DDR_EMI,
21
+
.ep = 1,
22
+
};
23
+
24
+
static struct mtk_icc_node mcusys = {
25
+
.name = "mcusys",
26
+
.id = MASTER_MCUSYS,
27
+
.ep = 0,
28
+
.num_links = 1,
29
+
.links = { SLAVE_DDR_EMI }
30
+
};
31
+
32
+
static struct mtk_icc_node gpu = {
33
+
.name = "gpu",
34
+
.id = MASTER_MFG,
35
+
.ep = 0,
36
+
.num_links = 1,
37
+
.links = { SLAVE_DDR_EMI }
38
+
};
39
+
40
+
static struct mtk_icc_node mmsys = {
41
+
.name = "mmsys",
42
+
.id = MASTER_MMSYS,
43
+
.ep = 0,
44
+
.num_links = 1,
45
+
.links = { SLAVE_DDR_EMI }
46
+
};
47
+
48
+
static struct mtk_icc_node mm_vpu = {
49
+
.name = "mm-vpu",
50
+
.id = MASTER_MM_VPU,
51
+
.ep = 0,
52
+
.num_links = 1,
53
+
.links = { MASTER_MMSYS }
54
+
};
55
+
56
+
static struct mtk_icc_node mm_disp = {
57
+
.name = "mm-disp",
58
+
.id = MASTER_MM_DISP,
59
+
.ep = 0,
60
+
.num_links = 1,
61
+
.links = { MASTER_MMSYS }
62
+
};
63
+
64
+
static struct mtk_icc_node mm_vdec = {
65
+
.name = "mm-vdec",
66
+
.id = MASTER_MM_VDEC,
67
+
.ep = 0,
68
+
.num_links = 1,
69
+
.links = { MASTER_MMSYS }
70
+
};
71
+
72
+
static struct mtk_icc_node mm_venc = {
73
+
.name = "mm-venc",
74
+
.id = MASTER_MM_VENC,
75
+
.ep = 0,
76
+
.num_links = 1,
77
+
.links = { MASTER_MMSYS }
78
+
};
79
+
80
+
static struct mtk_icc_node mm_cam = {
81
+
.name = "mm-cam",
82
+
.id = MASTER_MM_CAM,
83
+
.ep = 0,
84
+
.num_links = 1,
85
+
.links = { MASTER_MMSYS }
86
+
};
87
+
88
+
static struct mtk_icc_node mm_img = {
89
+
.name = "mm-img",
90
+
.id = MASTER_MM_IMG,
91
+
.ep = 0,
92
+
.num_links = 1,
93
+
.links = { MASTER_MMSYS }
94
+
};
95
+
96
+
static struct mtk_icc_node mm_mdp = {
97
+
.name = "mm-mdp",
98
+
.id = MASTER_MM_MDP,
99
+
.ep = 0,
100
+
.num_links = 1,
101
+
.links = { MASTER_MMSYS }
102
+
};
103
+
104
+
static struct mtk_icc_node *mt8183_emi_icc_nodes[] = {
105
+
[SLAVE_DDR_EMI] = &ddr_emi,
106
+
[MASTER_MCUSYS] = &mcusys,
107
+
[MASTER_MFG] = &gpu,
108
+
[MASTER_MMSYS] = &mmsys,
109
+
[MASTER_MM_VPU] = &mm_vpu,
110
+
[MASTER_MM_DISP] = &mm_disp,
111
+
[MASTER_MM_VDEC] = &mm_vdec,
112
+
[MASTER_MM_VENC] = &mm_venc,
113
+
[MASTER_MM_CAM] = &mm_cam,
114
+
[MASTER_MM_IMG] = &mm_img,
115
+
[MASTER_MM_MDP] = &mm_mdp
116
+
};
117
+
118
+
static const struct mtk_icc_desc mt8183_emi_icc = {
119
+
.nodes = mt8183_emi_icc_nodes,
120
+
.num_nodes = ARRAY_SIZE(mt8183_emi_icc_nodes),
121
+
};
122
+
123
+
static const struct of_device_id mtk_mt8183_emi_icc_of_match[] = {
124
+
{ .compatible = "mediatek,mt8183-emi", .data = &mt8183_emi_icc },
125
+
{ /* sentinel */ },
126
+
};
127
+
MODULE_DEVICE_TABLE(of, mtk_mt8183_emi_icc_of_match);
128
+
129
+
static struct platform_driver mtk_emi_icc_mt8183_driver = {
130
+
.driver = {
131
+
.name = "emi-icc-mt8183",
132
+
.of_match_table = mtk_mt8183_emi_icc_of_match,
133
+
.sync_state = icc_sync_state,
134
+
},
135
+
.probe = mtk_emi_icc_probe,
136
+
.remove_new = mtk_emi_icc_remove,
137
+
138
+
};
139
+
module_platform_driver(mtk_emi_icc_mt8183_driver);
140
+
141
+
MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
142
+
MODULE_DESCRIPTION("MediaTek MT8183 EMI ICC driver");
143
+
MODULE_LICENSE("GPL");
+339
drivers/interconnect/mediatek/mt8195.c
+339
drivers/interconnect/mediatek/mt8195.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Copyright (c) 2024 Collabora Ltd.
5
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6
+
*/
7
+
8
+
#include <linux/device.h>
9
+
#include <linux/interconnect.h>
10
+
#include <linux/interconnect-provider.h>
11
+
#include <linux/mod_devicetable.h>
12
+
#include <linux/module.h>
13
+
#include <linux/platform_device.h>
14
+
#include <dt-bindings/interconnect/mediatek,mt8195.h>
15
+
16
+
#include "icc-emi.h"
17
+
18
+
static struct mtk_icc_node ddr_emi = {
19
+
.name = "ddr-emi",
20
+
.id = SLAVE_DDR_EMI,
21
+
.ep = 1,
22
+
};
23
+
24
+
static struct mtk_icc_node mcusys = {
25
+
.name = "mcusys",
26
+
.id = MASTER_MCUSYS,
27
+
.ep = 0,
28
+
.num_links = 1,
29
+
.links = { SLAVE_DDR_EMI }
30
+
};
31
+
32
+
static struct mtk_icc_node gpu = {
33
+
.name = "gpu",
34
+
.id = MASTER_GPUSYS,
35
+
.ep = 0,
36
+
.num_links = 1,
37
+
.links = { SLAVE_DDR_EMI }
38
+
};
39
+
40
+
static struct mtk_icc_node mmsys = {
41
+
.name = "mmsys",
42
+
.id = MASTER_MMSYS,
43
+
.ep = 0,
44
+
.num_links = 1,
45
+
.links = { SLAVE_DDR_EMI }
46
+
};
47
+
48
+
static struct mtk_icc_node mm_vpu = {
49
+
.name = "mm-vpu",
50
+
.id = MASTER_MM_VPU,
51
+
.ep = 0,
52
+
.num_links = 1,
53
+
.links = { MASTER_MMSYS }
54
+
};
55
+
56
+
static struct mtk_icc_node mm_disp = {
57
+
.name = "mm-disp",
58
+
.id = MASTER_MM_DISP,
59
+
.ep = 0,
60
+
.num_links = 1,
61
+
.links = { MASTER_MMSYS }
62
+
};
63
+
64
+
static struct mtk_icc_node mm_vdec = {
65
+
.name = "mm-vdec",
66
+
.id = MASTER_MM_VDEC,
67
+
.ep = 0,
68
+
.num_links = 1,
69
+
.links = { MASTER_MMSYS }
70
+
};
71
+
72
+
static struct mtk_icc_node mm_venc = {
73
+
.name = "mm-venc",
74
+
.id = MASTER_MM_VENC,
75
+
.ep = 0,
76
+
.num_links = 1,
77
+
.links = { MASTER_MMSYS }
78
+
};
79
+
80
+
static struct mtk_icc_node mm_cam = {
81
+
.name = "mm-cam",
82
+
.id = MASTER_MM_CAM,
83
+
.ep = 0,
84
+
.num_links = 1,
85
+
.links = { MASTER_MMSYS }
86
+
};
87
+
88
+
static struct mtk_icc_node mm_img = {
89
+
.name = "mm-img",
90
+
.id = MASTER_MM_IMG,
91
+
.ep = 0,
92
+
.num_links = 1,
93
+
.links = { MASTER_MMSYS }
94
+
};
95
+
96
+
static struct mtk_icc_node mm_mdp = {
97
+
.name = "mm-mdp",
98
+
.id = MASTER_MM_MDP,
99
+
.ep = 0,
100
+
.num_links = 1,
101
+
.links = { MASTER_MMSYS }
102
+
};
103
+
104
+
static struct mtk_icc_node vpusys = {
105
+
.name = "vpusys",
106
+
.id = MASTER_VPUSYS,
107
+
.ep = 0,
108
+
.num_links = 1,
109
+
.links = { SLAVE_DDR_EMI }
110
+
};
111
+
112
+
static struct mtk_icc_node vpu_port0 = {
113
+
.name = "vpu-port0",
114
+
.id = MASTER_VPU_0,
115
+
.ep = 0,
116
+
.num_links = 1,
117
+
.links = { MASTER_VPUSYS }
118
+
};
119
+
120
+
static struct mtk_icc_node vpu_port1 = {
121
+
.name = "vpu-port1",
122
+
.id = MASTER_VPU_1,
123
+
.ep = 0,
124
+
.num_links = 1,
125
+
.links = { MASTER_VPUSYS }
126
+
};
127
+
128
+
static struct mtk_icc_node mdlasys = {
129
+
.name = "mdlasys",
130
+
.id = MASTER_MDLASYS,
131
+
.ep = 0,
132
+
.num_links = 1,
133
+
.links = { SLAVE_DDR_EMI }
134
+
};
135
+
136
+
static struct mtk_icc_node mdla_port0 = {
137
+
.name = "mdla-port0",
138
+
.id = MASTER_MDLA_0,
139
+
.ep = 0,
140
+
.num_links = 1,
141
+
.links = { MASTER_MDLASYS }
142
+
};
143
+
144
+
static struct mtk_icc_node ufs = {
145
+
.name = "ufs",
146
+
.id = MASTER_UFS,
147
+
.ep = 0,
148
+
.num_links = 1,
149
+
.links = { SLAVE_DDR_EMI }
150
+
};
151
+
152
+
static struct mtk_icc_node pcie0 = {
153
+
.name = "pcie0",
154
+
.id = MASTER_PCIE_0,
155
+
.ep = 0,
156
+
.num_links = 1,
157
+
.links = { SLAVE_DDR_EMI }
158
+
};
159
+
160
+
static struct mtk_icc_node pcie1 = {
161
+
.name = "pcie1",
162
+
.id = MASTER_PCIE_1,
163
+
.ep = 0,
164
+
.num_links = 1,
165
+
.links = { SLAVE_DDR_EMI }
166
+
};
167
+
168
+
static struct mtk_icc_node usb = {
169
+
.name = "usb",
170
+
.id = MASTER_USB,
171
+
.ep = 0,
172
+
.num_links = 1,
173
+
.links = { SLAVE_DDR_EMI }
174
+
};
175
+
176
+
static struct mtk_icc_node wifi = {
177
+
.name = "wifi",
178
+
.id = MASTER_WIFI,
179
+
.ep = 0,
180
+
.num_links = 1,
181
+
.links = { SLAVE_DDR_EMI }
182
+
};
183
+
184
+
static struct mtk_icc_node bt = {
185
+
.name = "bt",
186
+
.id = MASTER_BT,
187
+
.ep = 0,
188
+
.num_links = 1,
189
+
.links = { SLAVE_DDR_EMI }
190
+
};
191
+
192
+
static struct mtk_icc_node netsys = {
193
+
.name = "netsys",
194
+
.id = MASTER_NETSYS,
195
+
.ep = 0,
196
+
.num_links = 1,
197
+
.links = { SLAVE_DDR_EMI }
198
+
};
199
+
200
+
static struct mtk_icc_node dbgif = {
201
+
.name = "dbgif",
202
+
.id = MASTER_DBGIF,
203
+
.ep = 0,
204
+
.num_links = 1,
205
+
.links = { SLAVE_DDR_EMI }
206
+
};
207
+
208
+
static struct mtk_icc_node hrt_ddr_emi = {
209
+
.name = "hrt-ddr-emi",
210
+
.id = SLAVE_HRT_DDR_EMI,
211
+
.ep = 2,
212
+
};
213
+
214
+
static struct mtk_icc_node hrt_mmsys = {
215
+
.name = "hrt-mmsys",
216
+
.id = MASTER_HRT_MMSYS,
217
+
.ep = 0,
218
+
.num_links = 1,
219
+
.links = { SLAVE_HRT_DDR_EMI }
220
+
};
221
+
222
+
static struct mtk_icc_node hrt_mm_disp = {
223
+
.name = "hrt-mm-disp",
224
+
.id = MASTER_HRT_MM_DISP,
225
+
.ep = 0,
226
+
.num_links = 1,
227
+
.links = { MASTER_HRT_MMSYS }
228
+
};
229
+
230
+
static struct mtk_icc_node hrt_mm_vdec = {
231
+
.name = "hrt-mm-vdec",
232
+
.id = MASTER_HRT_MM_VDEC,
233
+
.ep = 0,
234
+
.num_links = 1,
235
+
.links = { MASTER_HRT_MMSYS }
236
+
};
237
+
238
+
static struct mtk_icc_node hrt_mm_venc = {
239
+
.name = "hrt-mm-venc",
240
+
.id = MASTER_HRT_MM_VENC,
241
+
.ep = 0,
242
+
.num_links = 1,
243
+
.links = { MASTER_HRT_MMSYS }
244
+
};
245
+
246
+
static struct mtk_icc_node hrt_mm_cam = {
247
+
.name = "hrt-mm-cam",
248
+
.id = MASTER_HRT_MM_CAM,
249
+
.ep = 0,
250
+
.num_links = 1,
251
+
.links = { MASTER_HRT_MMSYS }
252
+
};
253
+
254
+
static struct mtk_icc_node hrt_mm_img = {
255
+
.name = "hrt-mm-img",
256
+
.id = MASTER_HRT_MM_IMG,
257
+
.ep = 0,
258
+
.num_links = 1,
259
+
.links = { MASTER_HRT_MMSYS }
260
+
};
261
+
262
+
static struct mtk_icc_node hrt_mm_mdp = {
263
+
.name = "hrt-mm-mdp",
264
+
.id = MASTER_HRT_MM_MDP,
265
+
.ep = 0,
266
+
.num_links = 1,
267
+
.links = { MASTER_HRT_MMSYS }
268
+
};
269
+
270
+
static struct mtk_icc_node hrt_dbgif = {
271
+
.name = "hrt-dbgif",
272
+
.id = MASTER_HRT_DBGIF,
273
+
.ep = 0,
274
+
.num_links = 1,
275
+
.links = { SLAVE_HRT_DDR_EMI }
276
+
};
277
+
278
+
static struct mtk_icc_node *mt8195_emi_icc_nodes[] = {
279
+
[SLAVE_DDR_EMI] = &ddr_emi,
280
+
[MASTER_MCUSYS] = &mcusys,
281
+
[MASTER_GPUSYS] = &gpu,
282
+
[MASTER_MMSYS] = &mmsys,
283
+
[MASTER_MM_VPU] = &mm_vpu,
284
+
[MASTER_MM_DISP] = &mm_disp,
285
+
[MASTER_MM_VDEC] = &mm_vdec,
286
+
[MASTER_MM_VENC] = &mm_venc,
287
+
[MASTER_MM_CAM] = &mm_cam,
288
+
[MASTER_MM_IMG] = &mm_img,
289
+
[MASTER_MM_MDP] = &mm_mdp,
290
+
[MASTER_VPUSYS] = &vpusys,
291
+
[MASTER_VPU_0] = &vpu_port0,
292
+
[MASTER_VPU_1] = &vpu_port1,
293
+
[MASTER_MDLASYS] = &mdlasys,
294
+
[MASTER_MDLA_0] = &mdla_port0,
295
+
[MASTER_UFS] = &ufs,
296
+
[MASTER_PCIE_0] = &pcie0,
297
+
[MASTER_PCIE_1] = &pcie1,
298
+
[MASTER_USB] = &usb,
299
+
[MASTER_WIFI] = &wifi,
300
+
[MASTER_BT] = &bt,
301
+
[MASTER_NETSYS] = &netsys,
302
+
[MASTER_DBGIF] = &dbgif,
303
+
[SLAVE_HRT_DDR_EMI] = &hrt_ddr_emi,
304
+
[MASTER_HRT_MMSYS] = &hrt_mmsys,
305
+
[MASTER_HRT_MM_DISP] = &hrt_mm_disp,
306
+
[MASTER_HRT_MM_VDEC] = &hrt_mm_vdec,
307
+
[MASTER_HRT_MM_VENC] = &hrt_mm_venc,
308
+
[MASTER_HRT_MM_CAM] = &hrt_mm_cam,
309
+
[MASTER_HRT_MM_IMG] = &hrt_mm_img,
310
+
[MASTER_HRT_MM_MDP] = &hrt_mm_mdp,
311
+
[MASTER_HRT_DBGIF] = &hrt_dbgif
312
+
};
313
+
314
+
static struct mtk_icc_desc mt8195_emi_icc = {
315
+
.nodes = mt8195_emi_icc_nodes,
316
+
.num_nodes = ARRAY_SIZE(mt8195_emi_icc_nodes),
317
+
};
318
+
319
+
static const struct of_device_id mtk_mt8195_emi_icc_of_match[] = {
320
+
{ .compatible = "mediatek,mt8195-emi", .data = &mt8195_emi_icc },
321
+
{ /* sentinel */ },
322
+
};
323
+
MODULE_DEVICE_TABLE(of, mtk_mt8195_emi_icc_of_match);
324
+
325
+
static struct platform_driver mtk_emi_icc_mt8195_driver = {
326
+
.driver = {
327
+
.name = "emi-icc-mt8195",
328
+
.of_match_table = mtk_mt8195_emi_icc_of_match,
329
+
.sync_state = icc_sync_state,
330
+
},
331
+
.probe = mtk_emi_icc_probe,
332
+
.remove_new = mtk_emi_icc_remove,
333
+
334
+
};
335
+
module_platform_driver(mtk_emi_icc_mt8195_driver);
336
+
337
+
MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
338
+
MODULE_DESCRIPTION("MediaTek MT8195 EMI ICC driver");
339
+
MODULE_LICENSE("GPL");
+9
drivers/interconnect/qcom/Kconfig
+9
drivers/interconnect/qcom/Kconfig
···
35
35
This is a driver for the Qualcomm Network-on-Chip on msm8939-based
36
36
platforms.
37
37
38
+
config INTERCONNECT_QCOM_MSM8953
39
+
tristate "Qualcomm MSM8953 interconnect driver"
40
+
depends on INTERCONNECT_QCOM
41
+
depends on QCOM_SMD_RPM
42
+
select INTERCONNECT_QCOM_SMD_RPM
43
+
help
44
+
This is a driver for the Qualcomm Network-on-Chip on msm8953-based
45
+
platforms.
46
+
38
47
config INTERCONNECT_QCOM_MSM8974
39
48
tristate "Qualcomm MSM8974 interconnect driver"
40
49
depends on INTERCONNECT_QCOM
+2
drivers/interconnect/qcom/Makefile
+2
drivers/interconnect/qcom/Makefile
···
7
7
qnoc-msm8909-objs := msm8909.o
8
8
qnoc-msm8916-objs := msm8916.o
9
9
qnoc-msm8939-objs := msm8939.o
10
+
qnoc-msm8953-objs := msm8953.o
10
11
qnoc-msm8974-objs := msm8974.o
11
12
qnoc-msm8996-objs := msm8996.o
12
13
icc-osm-l3-objs := osm-l3.o
···
42
41
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) += qnoc-msm8909.o
43
42
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
44
43
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) += qnoc-msm8939.o
44
+
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8953) += qnoc-msm8953.o
45
45
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o
46
46
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o
47
47
obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
+1
drivers/interconnect/qcom/icc-common.c
+1
drivers/interconnect/qcom/icc-common.c
+94
drivers/interconnect/qcom/icc-rpmh.c
+94
drivers/interconnect/qcom/icc-rpmh.c
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
/*
3
3
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
4
5
*/
5
6
7
+
#include <linux/bitfield.h>
8
+
#include <linux/clk.h>
6
9
#include <linux/interconnect.h>
7
10
#include <linux/interconnect-provider.h>
8
11
#include <linux/module.h>
···
16
13
#include "bcm-voter.h"
17
14
#include "icc-common.h"
18
15
#include "icc-rpmh.h"
16
+
17
+
/* QNOC QoS */
18
+
#define QOSGEN_MAINCTL_LO(p, qp) (0x8 + (p->port_offsets[qp]))
19
+
#define QOS_SLV_URG_MSG_EN_MASK GENMASK(3, 3)
20
+
#define QOS_DFLT_PRIO_MASK GENMASK(6, 4)
21
+
#define QOS_DISABLE_MASK GENMASK(24, 24)
22
+
23
+
/**
24
+
* qcom_icc_set_qos - initialize static QoS configurations
25
+
* @qp: qcom icc provider to which @node belongs
26
+
* @node: qcom icc node to operate on
27
+
*/
28
+
static void qcom_icc_set_qos(struct qcom_icc_provider *qp,
29
+
struct qcom_icc_node *node)
30
+
{
31
+
const struct qcom_icc_qosbox *qos = node->qosbox;
32
+
int port;
33
+
34
+
for (port = 0; port < qos->num_ports; port++) {
35
+
regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port),
36
+
QOS_DISABLE_MASK,
37
+
FIELD_PREP(QOS_DISABLE_MASK, qos->prio_fwd_disable));
38
+
39
+
regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port),
40
+
QOS_DFLT_PRIO_MASK,
41
+
FIELD_PREP(QOS_DFLT_PRIO_MASK, qos->prio));
42
+
43
+
regmap_update_bits(qp->regmap, QOSGEN_MAINCTL_LO(qos, port),
44
+
QOS_SLV_URG_MSG_EN_MASK,
45
+
FIELD_PREP(QOS_SLV_URG_MSG_EN_MASK, qos->urg_fwd));
46
+
}
47
+
}
19
48
20
49
/**
21
50
* qcom_icc_pre_aggregate - cleans up stale values from prior icc_set
···
194
159
}
195
160
EXPORT_SYMBOL_GPL(qcom_icc_bcm_init);
196
161
162
+
/**
163
+
* qcom_icc_rpmh_configure_qos - configure QoS parameters
164
+
* @qp: qcom icc provider associated with QoS endpoint nodes
165
+
*
166
+
* Return: 0 on success, or an error code otherwise
167
+
*/
168
+
static int qcom_icc_rpmh_configure_qos(struct qcom_icc_provider *qp)
169
+
{
170
+
struct qcom_icc_node *qnode;
171
+
size_t i;
172
+
int ret;
173
+
174
+
ret = clk_bulk_prepare_enable(qp->num_clks, qp->clks);
175
+
if (ret)
176
+
return ret;
177
+
178
+
for (i = 0; i < qp->num_nodes; i++) {
179
+
qnode = qp->nodes[i];
180
+
if (!qnode)
181
+
continue;
182
+
183
+
if (qnode->qosbox)
184
+
qcom_icc_set_qos(qp, qnode);
185
+
}
186
+
187
+
clk_bulk_disable_unprepare(qp->num_clks, qp->clks);
188
+
189
+
return ret;
190
+
}
191
+
197
192
int qcom_icc_rpmh_probe(struct platform_device *pdev)
198
193
{
199
194
const struct qcom_icc_desc *desc;
···
264
199
265
200
qp->dev = dev;
266
201
qp->bcms = desc->bcms;
202
+
qp->nodes = desc->nodes;
267
203
qp->num_bcms = desc->num_bcms;
204
+
qp->num_nodes = desc->num_nodes;
268
205
269
206
qp->voter = of_bcm_voter_get(qp->dev, NULL);
270
207
if (IS_ERR(qp->voter))
···
296
229
data->nodes[i] = node;
297
230
}
298
231
232
+
if (desc->config) {
233
+
struct resource *res;
234
+
void __iomem *base;
235
+
236
+
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
237
+
if (IS_ERR(base))
238
+
goto skip_qos_config;
239
+
240
+
qp->regmap = devm_regmap_init_mmio(dev, base, desc->config);
241
+
if (IS_ERR(qp->regmap)) {
242
+
dev_info(dev, "Skipping QoS, regmap failed; %ld\n", PTR_ERR(qp->regmap));
243
+
goto skip_qos_config;
244
+
}
245
+
246
+
qp->num_clks = devm_clk_bulk_get_all(qp->dev, &qp->clks);
247
+
if (qp->num_clks < 0 || (!qp->num_clks && desc->qos_clks_required)) {
248
+
dev_info(dev, "Skipping QoS, failed to get clk: %d\n", qp->num_clks);
249
+
goto skip_qos_config;
250
+
}
251
+
252
+
ret = qcom_icc_rpmh_configure_qos(qp);
253
+
if (ret)
254
+
dev_info(dev, "Failed to program QoS: %d\n", ret);
255
+
}
256
+
257
+
skip_qos_config:
299
258
ret = icc_provider_register(provider);
300
259
if (ret)
301
260
goto err_remove_nodes;
···
355
262
}
356
263
EXPORT_SYMBOL_GPL(qcom_icc_rpmh_remove);
357
264
265
+
MODULE_DESCRIPTION("Qualcomm RPMh interconnect driver");
358
266
MODULE_LICENSE("GPL v2");
+36
drivers/interconnect/qcom/icc-rpmh.h
+36
drivers/interconnect/qcom/icc-rpmh.h
···
1
1
/* SPDX-License-Identifier: GPL-2.0 */
2
2
/*
3
3
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
4
5
*/
5
6
6
7
#ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__
7
8
#define __DRIVERS_INTERCONNECT_QCOM_ICC_RPMH_H__
8
9
9
10
#include <dt-bindings/interconnect/qcom,icc.h>
11
+
#include <linux/regmap.h>
10
12
11
13
#define to_qcom_provider(_provider) \
12
14
container_of(_provider, struct qcom_icc_provider, provider)
···
20
18
* @bcms: list of bcms that maps to the provider
21
19
* @num_bcms: number of @bcms
22
20
* @voter: bcm voter targeted by this provider
21
+
* @nodes: list of icc nodes that maps to the provider
22
+
* @num_nodes: number of @nodes
23
+
* @regmap: used for QoS, register access
24
+
* @clks : clks required for register access
25
+
* @num_clks: number of @clks
23
26
*/
24
27
struct qcom_icc_provider {
25
28
struct icc_provider provider;
···
32
25
struct qcom_icc_bcm * const *bcms;
33
26
size_t num_bcms;
34
27
struct bcm_voter *voter;
28
+
struct qcom_icc_node * const *nodes;
29
+
size_t num_nodes;
30
+
struct regmap *regmap;
31
+
struct clk_bulk_data *clks;
32
+
int num_clks;
35
33
};
36
34
37
35
/**
···
51
39
__le16 width;
52
40
u8 vcd;
53
41
u8 reserved;
42
+
};
43
+
44
+
#define MAX_PORTS 2
45
+
46
+
/**
47
+
* struct qcom_icc_qosbox - Qualcomm specific QoS config
48
+
* @prio: priority value assigned to requests on the node
49
+
* @urg_fwd: whether to forward the urgency promotion issued by master
50
+
* (endpoint), or discard
51
+
* @prio_fwd_disable: whether to forward the priority driven by master, or
52
+
* override by @prio
53
+
* @num_ports: number of @ports
54
+
* @port_offsets: qos register offsets
55
+
*/
56
+
struct qcom_icc_qosbox {
57
+
const u32 prio;
58
+
const bool urg_fwd;
59
+
const bool prio_fwd_disable;
60
+
const u32 num_ports;
61
+
const u32 port_offsets[MAX_PORTS];
54
62
};
55
63
56
64
#define MAX_LINKS 128
···
90
58
* @max_peak: current max aggregate value of all peak bw requests
91
59
* @bcms: list of bcms associated with this logical node
92
60
* @num_bcms: num of @bcms
61
+
* @qosbox: QoS config data associated with node
93
62
*/
94
63
struct qcom_icc_node {
95
64
const char *name;
···
103
70
u64 max_peak[QCOM_ICC_NUM_BUCKETS];
104
71
struct qcom_icc_bcm *bcms[MAX_BCM_PER_NODE];
105
72
size_t num_bcms;
73
+
const struct qcom_icc_qosbox *qosbox;
106
74
};
107
75
108
76
/**
···
148
114
};
149
115
150
116
struct qcom_icc_desc {
117
+
const struct regmap_config *config;
151
118
struct qcom_icc_node * const *nodes;
152
119
size_t num_nodes;
153
120
struct qcom_icc_bcm * const *bcms;
154
121
size_t num_bcms;
122
+
bool qos_clks_required;
155
123
};
156
124
157
125
int qcom_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
+1321
drivers/interconnect/qcom/msm8953.c
+1321
drivers/interconnect/qcom/msm8953.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
3
+
#include <linux/clk.h>
4
+
#include <linux/interconnect-provider.h>
5
+
#include <linux/mod_devicetable.h>
6
+
#include <linux/module.h>
7
+
#include <linux/of_device.h>
8
+
#include <linux/platform_device.h>
9
+
#include <linux/regmap.h>
10
+
11
+
#include <dt-bindings/interconnect/qcom,msm8953.h>
12
+
13
+
#include "icc-rpm.h"
14
+
15
+
enum {
16
+
MSM8953_MASTER_AMPSS_M0 = 1,
17
+
MSM8953_MASTER_GRAPHICS_3D,
18
+
MSM8953_SNOC_BIMC_0_MAS,
19
+
MSM8953_SNOC_BIMC_2_MAS,
20
+
MSM8953_SNOC_BIMC_1_MAS,
21
+
MSM8953_MASTER_TCU_0,
22
+
MSM8953_SLAVE_EBI_CH0,
23
+
MSM8953_BIMC_SNOC_SLV,
24
+
MSM8953_MASTER_SPDM,
25
+
MSM8953_MASTER_BLSP_1,
26
+
MSM8953_MASTER_BLSP_2,
27
+
MSM8953_MASTER_USB3,
28
+
MSM8953_MASTER_CRYPTO_CORE0,
29
+
MSM8953_MASTER_SDCC_1,
30
+
MSM8953_MASTER_SDCC_2,
31
+
MSM8953_SNOC_PNOC_MAS,
32
+
MSM8953_PNOC_M_0,
33
+
MSM8953_PNOC_M_1,
34
+
MSM8953_PNOC_INT_1,
35
+
MSM8953_PNOC_INT_2,
36
+
MSM8953_PNOC_SLV_0,
37
+
MSM8953_PNOC_SLV_1,
38
+
MSM8953_PNOC_SLV_2,
39
+
MSM8953_PNOC_SLV_3,
40
+
MSM8953_PNOC_SLV_4,
41
+
MSM8953_PNOC_SLV_6,
42
+
MSM8953_PNOC_SLV_7,
43
+
MSM8953_PNOC_SLV_8,
44
+
MSM8953_PNOC_SLV_9,
45
+
MSM8953_SLAVE_SPDM_WRAPPER,
46
+
MSM8953_SLAVE_PDM,
47
+
MSM8953_SLAVE_TCSR,
48
+
MSM8953_SLAVE_SNOC_CFG,
49
+
MSM8953_SLAVE_TLMM,
50
+
MSM8953_SLAVE_MESSAGE_RAM,
51
+
MSM8953_SLAVE_BLSP_1,
52
+
MSM8953_SLAVE_BLSP_2,
53
+
MSM8953_SLAVE_PRNG,
54
+
MSM8953_SLAVE_CAMERA_CFG,
55
+
MSM8953_SLAVE_DISPLAY_CFG,
56
+
MSM8953_SLAVE_VENUS_CFG,
57
+
MSM8953_SLAVE_GRAPHICS_3D_CFG,
58
+
MSM8953_SLAVE_SDCC_1,
59
+
MSM8953_SLAVE_SDCC_2,
60
+
MSM8953_SLAVE_CRYPTO_0_CFG,
61
+
MSM8953_SLAVE_PMIC_ARB,
62
+
MSM8953_SLAVE_USB3,
63
+
MSM8953_SLAVE_IPA_CFG,
64
+
MSM8953_SLAVE_TCU,
65
+
MSM8953_PNOC_SNOC_SLV,
66
+
MSM8953_MASTER_QDSS_BAM,
67
+
MSM8953_BIMC_SNOC_MAS,
68
+
MSM8953_PNOC_SNOC_MAS,
69
+
MSM8953_MASTER_IPA,
70
+
MSM8953_MASTER_QDSS_ETR,
71
+
MSM8953_SNOC_QDSS_INT,
72
+
MSM8953_SNOC_INT_0,
73
+
MSM8953_SNOC_INT_1,
74
+
MSM8953_SNOC_INT_2,
75
+
MSM8953_SLAVE_APPSS,
76
+
MSM8953_SLAVE_WCSS,
77
+
MSM8953_SNOC_BIMC_1_SLV,
78
+
MSM8953_SLAVE_OCIMEM,
79
+
MSM8953_SNOC_PNOC_SLV,
80
+
MSM8953_SLAVE_QDSS_STM,
81
+
MSM8953_SLAVE_OCMEM_64,
82
+
MSM8953_SLAVE_LPASS,
83
+
MSM8953_MASTER_JPEG,
84
+
MSM8953_MASTER_MDP_PORT0,
85
+
MSM8953_MASTER_VIDEO_P0,
86
+
MSM8953_MASTER_VFE,
87
+
MSM8953_MASTER_VFE1,
88
+
MSM8953_MASTER_CPP,
89
+
MSM8953_SNOC_BIMC_0_SLV,
90
+
MSM8953_SNOC_BIMC_2_SLV,
91
+
MSM8953_SLAVE_CATS_128,
92
+
};
93
+
94
+
static const u16 mas_apps_proc_links[] = {
95
+
MSM8953_SLAVE_EBI_CH0,
96
+
MSM8953_BIMC_SNOC_SLV
97
+
};
98
+
99
+
static struct qcom_icc_node mas_apps_proc = {
100
+
.name = "mas_apps_proc",
101
+
.id = MSM8953_MASTER_AMPSS_M0,
102
+
.buswidth = 8,
103
+
.qos.ap_owned = true,
104
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
105
+
.qos.prio_level = 0,
106
+
.qos.areq_prio = 0,
107
+
.qos.qos_port = 0,
108
+
.num_links = ARRAY_SIZE(mas_apps_proc_links),
109
+
.links = mas_apps_proc_links,
110
+
};
111
+
112
+
static const u16 mas_oxili_links[] = {
113
+
MSM8953_SLAVE_EBI_CH0,
114
+
MSM8953_BIMC_SNOC_SLV
115
+
};
116
+
117
+
static struct qcom_icc_node mas_oxili = {
118
+
.name = "mas_oxili",
119
+
.id = MSM8953_MASTER_GRAPHICS_3D,
120
+
.buswidth = 8,
121
+
.qos.ap_owned = true,
122
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
123
+
.qos.prio_level = 0,
124
+
.qos.areq_prio = 0,
125
+
.qos.qos_port = 2,
126
+
.num_links = ARRAY_SIZE(mas_oxili_links),
127
+
.links = mas_oxili_links,
128
+
};
129
+
130
+
static const u16 mas_snoc_bimc_0_links[] = {
131
+
MSM8953_SLAVE_EBI_CH0,
132
+
MSM8953_BIMC_SNOC_SLV
133
+
};
134
+
135
+
static struct qcom_icc_node mas_snoc_bimc_0 = {
136
+
.name = "mas_snoc_bimc_0",
137
+
.id = MSM8953_SNOC_BIMC_0_MAS,
138
+
.buswidth = 8,
139
+
.qos.ap_owned = true,
140
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
141
+
.qos.prio_level = 0,
142
+
.qos.areq_prio = 0,
143
+
.qos.qos_port = 3,
144
+
.num_links = ARRAY_SIZE(mas_snoc_bimc_0_links),
145
+
.links = mas_snoc_bimc_0_links,
146
+
};
147
+
148
+
static const u16 mas_snoc_bimc_2_links[] = {
149
+
MSM8953_SLAVE_EBI_CH0,
150
+
MSM8953_BIMC_SNOC_SLV
151
+
};
152
+
153
+
static struct qcom_icc_node mas_snoc_bimc_2 = {
154
+
.name = "mas_snoc_bimc_2",
155
+
.id = MSM8953_SNOC_BIMC_2_MAS,
156
+
.buswidth = 8,
157
+
.qos.ap_owned = true,
158
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
159
+
.qos.prio_level = 0,
160
+
.qos.areq_prio = 0,
161
+
.qos.qos_port = 4,
162
+
.num_links = ARRAY_SIZE(mas_snoc_bimc_2_links),
163
+
.links = mas_snoc_bimc_2_links,
164
+
};
165
+
166
+
static const u16 mas_snoc_bimc_1_links[] = {
167
+
MSM8953_SLAVE_EBI_CH0
168
+
};
169
+
170
+
static struct qcom_icc_node mas_snoc_bimc_1 = {
171
+
.name = "mas_snoc_bimc_1",
172
+
.id = MSM8953_SNOC_BIMC_1_MAS,
173
+
.buswidth = 8,
174
+
.mas_rpm_id = 76,
175
+
.slv_rpm_id = -1,
176
+
.num_links = ARRAY_SIZE(mas_snoc_bimc_1_links),
177
+
.links = mas_snoc_bimc_1_links,
178
+
};
179
+
180
+
static const u16 mas_tcu_0_links[] = {
181
+
MSM8953_SLAVE_EBI_CH0,
182
+
MSM8953_BIMC_SNOC_SLV
183
+
};
184
+
185
+
static struct qcom_icc_node mas_tcu_0 = {
186
+
.name = "mas_tcu_0",
187
+
.id = MSM8953_MASTER_TCU_0,
188
+
.buswidth = 8,
189
+
.qos.ap_owned = true,
190
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
191
+
.qos.prio_level = 2,
192
+
.qos.areq_prio = 2,
193
+
.qos.qos_port = 6,
194
+
.num_links = ARRAY_SIZE(mas_tcu_0_links),
195
+
.links = mas_tcu_0_links,
196
+
};
197
+
198
+
static struct qcom_icc_node slv_ebi = {
199
+
.name = "slv_ebi",
200
+
.id = MSM8953_SLAVE_EBI_CH0,
201
+
.buswidth = 8,
202
+
.mas_rpm_id = -1,
203
+
.slv_rpm_id = 0,
204
+
};
205
+
206
+
static const u16 slv_bimc_snoc_links[] = {
207
+
MSM8953_BIMC_SNOC_MAS
208
+
};
209
+
210
+
static struct qcom_icc_node slv_bimc_snoc = {
211
+
.name = "slv_bimc_snoc",
212
+
.id = MSM8953_BIMC_SNOC_SLV,
213
+
.buswidth = 8,
214
+
.mas_rpm_id = -1,
215
+
.slv_rpm_id = 2,
216
+
.num_links = ARRAY_SIZE(slv_bimc_snoc_links),
217
+
.links = slv_bimc_snoc_links,
218
+
};
219
+
220
+
static const u16 mas_spdm_links[] = {
221
+
MSM8953_PNOC_M_0
222
+
};
223
+
224
+
static struct qcom_icc_node mas_spdm = {
225
+
.name = "mas_spdm",
226
+
.id = MSM8953_MASTER_SPDM,
227
+
.buswidth = 4,
228
+
.qos.ap_owned = true,
229
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
230
+
.qos.prio_level = 0,
231
+
.qos.areq_prio = 0,
232
+
.qos.qos_port = -1,
233
+
.num_links = ARRAY_SIZE(mas_spdm_links),
234
+
.links = mas_spdm_links,
235
+
};
236
+
237
+
static const u16 mas_blsp_1_links[] = {
238
+
MSM8953_PNOC_M_1
239
+
};
240
+
241
+
static struct qcom_icc_node mas_blsp_1 = {
242
+
.name = "mas_blsp_1",
243
+
.id = MSM8953_MASTER_BLSP_1,
244
+
.buswidth = 4,
245
+
.mas_rpm_id = 41,
246
+
.slv_rpm_id = -1,
247
+
.num_links = ARRAY_SIZE(mas_blsp_1_links),
248
+
.links = mas_blsp_1_links,
249
+
};
250
+
251
+
static const u16 mas_blsp_2_links[] = {
252
+
MSM8953_PNOC_M_1
253
+
};
254
+
255
+
static struct qcom_icc_node mas_blsp_2 = {
256
+
.name = "mas_blsp_2",
257
+
.id = MSM8953_MASTER_BLSP_2,
258
+
.buswidth = 4,
259
+
.mas_rpm_id = 39,
260
+
.slv_rpm_id = -1,
261
+
.num_links = ARRAY_SIZE(mas_blsp_2_links),
262
+
.links = mas_blsp_2_links,
263
+
};
264
+
265
+
static const u16 mas_usb3_links[] = {
266
+
MSM8953_PNOC_INT_1
267
+
};
268
+
269
+
static struct qcom_icc_node mas_usb3 = {
270
+
.name = "mas_usb3",
271
+
.id = MSM8953_MASTER_USB3,
272
+
.buswidth = 8,
273
+
.qos.ap_owned = true,
274
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
275
+
.qos.prio_level = 1,
276
+
.qos.areq_prio = 1,
277
+
.qos.qos_port = 11,
278
+
.num_links = ARRAY_SIZE(mas_usb3_links),
279
+
.links = mas_usb3_links,
280
+
};
281
+
282
+
static const u16 mas_crypto_links[] = {
283
+
MSM8953_PNOC_INT_1
284
+
};
285
+
286
+
static struct qcom_icc_node mas_crypto = {
287
+
.name = "mas_crypto",
288
+
.id = MSM8953_MASTER_CRYPTO_CORE0,
289
+
.buswidth = 8,
290
+
.qos.ap_owned = true,
291
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
292
+
.qos.prio_level = 1,
293
+
.qos.areq_prio = 1,
294
+
.qos.qos_port = 0,
295
+
.num_links = ARRAY_SIZE(mas_crypto_links),
296
+
.links = mas_crypto_links,
297
+
};
298
+
299
+
static const u16 mas_sdcc_1_links[] = {
300
+
MSM8953_PNOC_INT_1
301
+
};
302
+
303
+
static struct qcom_icc_node mas_sdcc_1 = {
304
+
.name = "mas_sdcc_1",
305
+
.id = MSM8953_MASTER_SDCC_1,
306
+
.buswidth = 8,
307
+
.mas_rpm_id = 33,
308
+
.slv_rpm_id = -1,
309
+
.num_links = ARRAY_SIZE(mas_sdcc_1_links),
310
+
.links = mas_sdcc_1_links,
311
+
};
312
+
313
+
static const u16 mas_sdcc_2_links[] = {
314
+
MSM8953_PNOC_INT_1
315
+
};
316
+
317
+
static struct qcom_icc_node mas_sdcc_2 = {
318
+
.name = "mas_sdcc_2",
319
+
.id = MSM8953_MASTER_SDCC_2,
320
+
.buswidth = 8,
321
+
.mas_rpm_id = 35,
322
+
.slv_rpm_id = -1,
323
+
.num_links = ARRAY_SIZE(mas_sdcc_2_links),
324
+
.links = mas_sdcc_2_links,
325
+
};
326
+
327
+
static const u16 mas_snoc_pcnoc_links[] = {
328
+
MSM8953_PNOC_INT_2
329
+
};
330
+
331
+
static struct qcom_icc_node mas_snoc_pcnoc = {
332
+
.name = "mas_snoc_pcnoc",
333
+
.id = MSM8953_SNOC_PNOC_MAS,
334
+
.buswidth = 8,
335
+
.mas_rpm_id = 77,
336
+
.slv_rpm_id = -1,
337
+
.num_links = ARRAY_SIZE(mas_snoc_pcnoc_links),
338
+
.links = mas_snoc_pcnoc_links,
339
+
};
340
+
341
+
static const u16 pcnoc_m_0_links[] = {
342
+
MSM8953_PNOC_INT_1
343
+
};
344
+
345
+
static struct qcom_icc_node pcnoc_m_0 = {
346
+
.name = "pcnoc_m_0",
347
+
.id = MSM8953_PNOC_M_0,
348
+
.buswidth = 4,
349
+
.qos.ap_owned = true,
350
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
351
+
.qos.prio_level = 1,
352
+
.qos.areq_prio = 1,
353
+
.qos.qos_port = 5,
354
+
.num_links = ARRAY_SIZE(pcnoc_m_0_links),
355
+
.links = pcnoc_m_0_links,
356
+
};
357
+
358
+
static const u16 pcnoc_m_1_links[] = {
359
+
MSM8953_PNOC_INT_1
360
+
};
361
+
362
+
static struct qcom_icc_node pcnoc_m_1 = {
363
+
.name = "pcnoc_m_1",
364
+
.id = MSM8953_PNOC_M_1,
365
+
.buswidth = 4,
366
+
.mas_rpm_id = 88,
367
+
.slv_rpm_id = 117,
368
+
.num_links = ARRAY_SIZE(pcnoc_m_1_links),
369
+
.links = pcnoc_m_1_links,
370
+
};
371
+
372
+
static const u16 pcnoc_int_1_links[] = {
373
+
MSM8953_PNOC_INT_2,
374
+
MSM8953_PNOC_SNOC_SLV
375
+
};
376
+
377
+
static struct qcom_icc_node pcnoc_int_1 = {
378
+
.name = "pcnoc_int_1",
379
+
.id = MSM8953_PNOC_INT_1,
380
+
.buswidth = 8,
381
+
.mas_rpm_id = 86,
382
+
.slv_rpm_id = 115,
383
+
.num_links = ARRAY_SIZE(pcnoc_int_1_links),
384
+
.links = pcnoc_int_1_links,
385
+
};
386
+
387
+
static const u16 pcnoc_int_2_links[] = {
388
+
MSM8953_PNOC_SLV_1,
389
+
MSM8953_PNOC_SLV_2,
390
+
MSM8953_PNOC_SLV_0,
391
+
MSM8953_PNOC_SLV_4,
392
+
MSM8953_PNOC_SLV_6,
393
+
MSM8953_PNOC_SLV_7,
394
+
MSM8953_PNOC_SLV_8,
395
+
MSM8953_PNOC_SLV_9,
396
+
MSM8953_SLAVE_TCU,
397
+
MSM8953_SLAVE_GRAPHICS_3D_CFG,
398
+
MSM8953_PNOC_SLV_3
399
+
};
400
+
401
+
static struct qcom_icc_node pcnoc_int_2 = {
402
+
.name = "pcnoc_int_2",
403
+
.id = MSM8953_PNOC_INT_2,
404
+
.buswidth = 8,
405
+
.mas_rpm_id = 124,
406
+
.slv_rpm_id = 184,
407
+
.num_links = ARRAY_SIZE(pcnoc_int_2_links),
408
+
.links = pcnoc_int_2_links,
409
+
};
410
+
411
+
static const u16 pcnoc_s_0_links[] = {
412
+
MSM8953_SLAVE_PDM,
413
+
MSM8953_SLAVE_SPDM_WRAPPER
414
+
};
415
+
416
+
static struct qcom_icc_node pcnoc_s_0 = {
417
+
.name = "pcnoc_s_0",
418
+
.id = MSM8953_PNOC_SLV_0,
419
+
.buswidth = 4,
420
+
.mas_rpm_id = 89,
421
+
.slv_rpm_id = 118,
422
+
.num_links = ARRAY_SIZE(pcnoc_s_0_links),
423
+
.links = pcnoc_s_0_links,
424
+
};
425
+
426
+
static const u16 pcnoc_s_1_links[] = {
427
+
MSM8953_SLAVE_TCSR
428
+
};
429
+
430
+
static struct qcom_icc_node pcnoc_s_1 = {
431
+
.name = "pcnoc_s_1",
432
+
.id = MSM8953_PNOC_SLV_1,
433
+
.buswidth = 4,
434
+
.mas_rpm_id = 90,
435
+
.slv_rpm_id = 119,
436
+
.num_links = ARRAY_SIZE(pcnoc_s_1_links),
437
+
.links = pcnoc_s_1_links,
438
+
};
439
+
440
+
static const u16 pcnoc_s_2_links[] = {
441
+
MSM8953_SLAVE_SNOC_CFG
442
+
};
443
+
444
+
static struct qcom_icc_node pcnoc_s_2 = {
445
+
.name = "pcnoc_s_2",
446
+
.id = MSM8953_PNOC_SLV_2,
447
+
.buswidth = 4,
448
+
.mas_rpm_id = 91,
449
+
.slv_rpm_id = 120,
450
+
.num_links = ARRAY_SIZE(pcnoc_s_2_links),
451
+
.links = pcnoc_s_2_links,
452
+
};
453
+
454
+
static const u16 pcnoc_s_3_links[] = {
455
+
MSM8953_SLAVE_TLMM,
456
+
MSM8953_SLAVE_PRNG,
457
+
MSM8953_SLAVE_BLSP_1,
458
+
MSM8953_SLAVE_BLSP_2,
459
+
MSM8953_SLAVE_MESSAGE_RAM
460
+
};
461
+
462
+
static struct qcom_icc_node pcnoc_s_3 = {
463
+
.name = "pcnoc_s_3",
464
+
.id = MSM8953_PNOC_SLV_3,
465
+
.buswidth = 4,
466
+
.mas_rpm_id = 92,
467
+
.slv_rpm_id = 121,
468
+
.num_links = ARRAY_SIZE(pcnoc_s_3_links),
469
+
.links = pcnoc_s_3_links,
470
+
};
471
+
472
+
static const u16 pcnoc_s_4_links[] = {
473
+
MSM8953_SLAVE_CAMERA_CFG,
474
+
MSM8953_SLAVE_DISPLAY_CFG,
475
+
MSM8953_SLAVE_VENUS_CFG
476
+
};
477
+
478
+
static struct qcom_icc_node pcnoc_s_4 = {
479
+
.name = "pcnoc_s_4",
480
+
.id = MSM8953_PNOC_SLV_4,
481
+
.buswidth = 4,
482
+
.qos.ap_owned = true,
483
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
484
+
.qos.prio_level = 0,
485
+
.qos.areq_prio = 0,
486
+
.qos.qos_port = -1,
487
+
.num_links = ARRAY_SIZE(pcnoc_s_4_links),
488
+
.links = pcnoc_s_4_links,
489
+
};
490
+
491
+
static const u16 pcnoc_s_6_links[] = {
492
+
MSM8953_SLAVE_CRYPTO_0_CFG,
493
+
MSM8953_SLAVE_SDCC_2,
494
+
MSM8953_SLAVE_SDCC_1
495
+
};
496
+
497
+
static struct qcom_icc_node pcnoc_s_6 = {
498
+
.name = "pcnoc_s_6",
499
+
.id = MSM8953_PNOC_SLV_6,
500
+
.buswidth = 4,
501
+
.mas_rpm_id = 94,
502
+
.slv_rpm_id = 123,
503
+
.num_links = ARRAY_SIZE(pcnoc_s_6_links),
504
+
.links = pcnoc_s_6_links,
505
+
};
506
+
507
+
static const u16 pcnoc_s_7_links[] = {
508
+
MSM8953_SLAVE_PMIC_ARB
509
+
};
510
+
511
+
static struct qcom_icc_node pcnoc_s_7 = {
512
+
.name = "pcnoc_s_7",
513
+
.id = MSM8953_PNOC_SLV_7,
514
+
.buswidth = 4,
515
+
.mas_rpm_id = 95,
516
+
.slv_rpm_id = 124,
517
+
.num_links = ARRAY_SIZE(pcnoc_s_7_links),
518
+
.links = pcnoc_s_7_links,
519
+
};
520
+
521
+
static const u16 pcnoc_s_8_links[] = {
522
+
MSM8953_SLAVE_USB3
523
+
};
524
+
525
+
static struct qcom_icc_node pcnoc_s_8 = {
526
+
.name = "pcnoc_s_8",
527
+
.id = MSM8953_PNOC_SLV_8,
528
+
.buswidth = 4,
529
+
.qos.ap_owned = true,
530
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
531
+
.qos.prio_level = 0,
532
+
.qos.areq_prio = 0,
533
+
.qos.qos_port = -1,
534
+
.num_links = ARRAY_SIZE(pcnoc_s_8_links),
535
+
.links = pcnoc_s_8_links,
536
+
};
537
+
538
+
static const u16 pcnoc_s_9_links[] = {
539
+
MSM8953_SLAVE_IPA_CFG
540
+
};
541
+
542
+
static struct qcom_icc_node pcnoc_s_9 = {
543
+
.name = "pcnoc_s_9",
544
+
.id = MSM8953_PNOC_SLV_9,
545
+
.buswidth = 4,
546
+
.qos.ap_owned = true,
547
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
548
+
.qos.prio_level = 0,
549
+
.qos.areq_prio = 0,
550
+
.qos.qos_port = -1,
551
+
.num_links = ARRAY_SIZE(pcnoc_s_9_links),
552
+
.links = pcnoc_s_9_links,
553
+
};
554
+
555
+
static struct qcom_icc_node slv_spdm = {
556
+
.name = "slv_spdm",
557
+
.id = MSM8953_SLAVE_SPDM_WRAPPER,
558
+
.buswidth = 4,
559
+
.qos.ap_owned = true,
560
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
561
+
.qos.prio_level = 0,
562
+
.qos.areq_prio = 0,
563
+
.qos.qos_port = -1,
564
+
};
565
+
566
+
static struct qcom_icc_node slv_pdm = {
567
+
.name = "slv_pdm",
568
+
.id = MSM8953_SLAVE_PDM,
569
+
.buswidth = 4,
570
+
.mas_rpm_id = -1,
571
+
.slv_rpm_id = 41,
572
+
};
573
+
574
+
static struct qcom_icc_node slv_tcsr = {
575
+
.name = "slv_tcsr",
576
+
.id = MSM8953_SLAVE_TCSR,
577
+
.buswidth = 4,
578
+
.mas_rpm_id = -1,
579
+
.slv_rpm_id = 50,
580
+
};
581
+
582
+
static struct qcom_icc_node slv_snoc_cfg = {
583
+
.name = "slv_snoc_cfg",
584
+
.id = MSM8953_SLAVE_SNOC_CFG,
585
+
.buswidth = 4,
586
+
.mas_rpm_id = -1,
587
+
.slv_rpm_id = 70,
588
+
};
589
+
590
+
static struct qcom_icc_node slv_tlmm = {
591
+
.name = "slv_tlmm",
592
+
.id = MSM8953_SLAVE_TLMM,
593
+
.buswidth = 4,
594
+
.mas_rpm_id = -1,
595
+
.slv_rpm_id = 51,
596
+
};
597
+
598
+
static struct qcom_icc_node slv_message_ram = {
599
+
.name = "slv_message_ram",
600
+
.id = MSM8953_SLAVE_MESSAGE_RAM,
601
+
.buswidth = 4,
602
+
.mas_rpm_id = -1,
603
+
.slv_rpm_id = 55,
604
+
};
605
+
606
+
static struct qcom_icc_node slv_blsp_1 = {
607
+
.name = "slv_blsp_1",
608
+
.id = MSM8953_SLAVE_BLSP_1,
609
+
.buswidth = 4,
610
+
.mas_rpm_id = -1,
611
+
.slv_rpm_id = 39,
612
+
};
613
+
614
+
static struct qcom_icc_node slv_blsp_2 = {
615
+
.name = "slv_blsp_2",
616
+
.id = MSM8953_SLAVE_BLSP_2,
617
+
.buswidth = 4,
618
+
.mas_rpm_id = -1,
619
+
.slv_rpm_id = 37,
620
+
};
621
+
622
+
static struct qcom_icc_node slv_prng = {
623
+
.name = "slv_prng",
624
+
.id = MSM8953_SLAVE_PRNG,
625
+
.buswidth = 4,
626
+
.mas_rpm_id = -1,
627
+
.slv_rpm_id = 44,
628
+
};
629
+
630
+
static struct qcom_icc_node slv_camera_ss_cfg = {
631
+
.name = "slv_camera_ss_cfg",
632
+
.id = MSM8953_SLAVE_CAMERA_CFG,
633
+
.buswidth = 4,
634
+
.qos.ap_owned = true,
635
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
636
+
.qos.prio_level = 0,
637
+
.qos.areq_prio = 0,
638
+
.qos.qos_port = -1,
639
+
};
640
+
641
+
static struct qcom_icc_node slv_disp_ss_cfg = {
642
+
.name = "slv_disp_ss_cfg",
643
+
.id = MSM8953_SLAVE_DISPLAY_CFG,
644
+
.buswidth = 4,
645
+
.qos.ap_owned = true,
646
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
647
+
.qos.prio_level = 0,
648
+
.qos.areq_prio = 0,
649
+
.qos.qos_port = -1,
650
+
};
651
+
652
+
static struct qcom_icc_node slv_venus_cfg = {
653
+
.name = "slv_venus_cfg",
654
+
.id = MSM8953_SLAVE_VENUS_CFG,
655
+
.buswidth = 4,
656
+
.qos.ap_owned = true,
657
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
658
+
.qos.prio_level = 0,
659
+
.qos.areq_prio = 0,
660
+
.qos.qos_port = -1,
661
+
};
662
+
663
+
static struct qcom_icc_node slv_gpu_cfg = {
664
+
.name = "slv_gpu_cfg",
665
+
.id = MSM8953_SLAVE_GRAPHICS_3D_CFG,
666
+
.buswidth = 8,
667
+
.qos.ap_owned = true,
668
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
669
+
.qos.prio_level = 0,
670
+
.qos.areq_prio = 0,
671
+
.qos.qos_port = -1,
672
+
};
673
+
674
+
static struct qcom_icc_node slv_sdcc_1 = {
675
+
.name = "slv_sdcc_1",
676
+
.id = MSM8953_SLAVE_SDCC_1,
677
+
.buswidth = 4,
678
+
.mas_rpm_id = -1,
679
+
.slv_rpm_id = 31,
680
+
};
681
+
682
+
static struct qcom_icc_node slv_sdcc_2 = {
683
+
.name = "slv_sdcc_2",
684
+
.id = MSM8953_SLAVE_SDCC_2,
685
+
.buswidth = 4,
686
+
.mas_rpm_id = -1,
687
+
.slv_rpm_id = 33,
688
+
};
689
+
690
+
static struct qcom_icc_node slv_crypto_0_cfg = {
691
+
.name = "slv_crypto_0_cfg",
692
+
.id = MSM8953_SLAVE_CRYPTO_0_CFG,
693
+
.buswidth = 4,
694
+
.qos.ap_owned = true,
695
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
696
+
.qos.prio_level = 0,
697
+
.qos.areq_prio = 0,
698
+
.qos.qos_port = -1,
699
+
};
700
+
701
+
static struct qcom_icc_node slv_pmic_arb = {
702
+
.name = "slv_pmic_arb",
703
+
.id = MSM8953_SLAVE_PMIC_ARB,
704
+
.buswidth = 4,
705
+
.mas_rpm_id = -1,
706
+
.slv_rpm_id = 59,
707
+
};
708
+
709
+
static struct qcom_icc_node slv_usb3 = {
710
+
.name = "slv_usb3",
711
+
.id = MSM8953_SLAVE_USB3,
712
+
.buswidth = 4,
713
+
.qos.ap_owned = true,
714
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
715
+
.qos.prio_level = 0,
716
+
.qos.areq_prio = 0,
717
+
.qos.qos_port = -1,
718
+
};
719
+
720
+
static struct qcom_icc_node slv_ipa_cfg = {
721
+
.name = "slv_ipa_cfg",
722
+
.id = MSM8953_SLAVE_IPA_CFG,
723
+
.buswidth = 4,
724
+
.qos.ap_owned = true,
725
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
726
+
.qos.prio_level = 0,
727
+
.qos.areq_prio = 0,
728
+
.qos.qos_port = -1,
729
+
};
730
+
731
+
static struct qcom_icc_node slv_tcu = {
732
+
.name = "slv_tcu",
733
+
.id = MSM8953_SLAVE_TCU,
734
+
.buswidth = 8,
735
+
.qos.ap_owned = true,
736
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
737
+
.qos.prio_level = 0,
738
+
.qos.areq_prio = 0,
739
+
.qos.qos_port = -1,
740
+
};
741
+
742
+
static const u16 slv_pcnoc_snoc_links[] = {
743
+
MSM8953_PNOC_SNOC_MAS
744
+
};
745
+
746
+
static struct qcom_icc_node slv_pcnoc_snoc = {
747
+
.name = "slv_pcnoc_snoc",
748
+
.id = MSM8953_PNOC_SNOC_SLV,
749
+
.buswidth = 8,
750
+
.mas_rpm_id = -1,
751
+
.slv_rpm_id = 45,
752
+
.num_links = ARRAY_SIZE(slv_pcnoc_snoc_links),
753
+
.links = slv_pcnoc_snoc_links,
754
+
};
755
+
756
+
static const u16 mas_qdss_bam_links[] = {
757
+
MSM8953_SNOC_QDSS_INT
758
+
};
759
+
760
+
static struct qcom_icc_node mas_qdss_bam = {
761
+
.name = "mas_qdss_bam",
762
+
.id = MSM8953_MASTER_QDSS_BAM,
763
+
.buswidth = 4,
764
+
.qos.ap_owned = true,
765
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
766
+
.qos.prio_level = 1,
767
+
.qos.areq_prio = 1,
768
+
.qos.qos_port = 11,
769
+
.num_links = ARRAY_SIZE(mas_qdss_bam_links),
770
+
.links = mas_qdss_bam_links,
771
+
};
772
+
773
+
static const u16 mas_bimc_snoc_links[] = {
774
+
MSM8953_SNOC_INT_0,
775
+
MSM8953_SNOC_INT_1,
776
+
MSM8953_SNOC_INT_2
777
+
};
778
+
779
+
static struct qcom_icc_node mas_bimc_snoc = {
780
+
.name = "mas_bimc_snoc",
781
+
.id = MSM8953_BIMC_SNOC_MAS,
782
+
.buswidth = 8,
783
+
.mas_rpm_id = 21,
784
+
.slv_rpm_id = -1,
785
+
.num_links = ARRAY_SIZE(mas_bimc_snoc_links),
786
+
.links = mas_bimc_snoc_links,
787
+
};
788
+
789
+
static const u16 mas_pcnoc_snoc_links[] = {
790
+
MSM8953_SNOC_INT_0,
791
+
MSM8953_SNOC_INT_1,
792
+
MSM8953_SNOC_BIMC_1_SLV
793
+
};
794
+
795
+
static struct qcom_icc_node mas_pcnoc_snoc = {
796
+
.name = "mas_pcnoc_snoc",
797
+
.id = MSM8953_PNOC_SNOC_MAS,
798
+
.buswidth = 8,
799
+
.mas_rpm_id = 29,
800
+
.slv_rpm_id = -1,
801
+
.num_links = ARRAY_SIZE(mas_pcnoc_snoc_links),
802
+
.links = mas_pcnoc_snoc_links,
803
+
};
804
+
805
+
static const u16 mas_ipa_links[] = {
806
+
MSM8953_SNOC_INT_0,
807
+
MSM8953_SNOC_INT_1,
808
+
MSM8953_SNOC_BIMC_1_SLV
809
+
};
810
+
811
+
static struct qcom_icc_node mas_ipa = {
812
+
.name = "mas_ipa",
813
+
.id = MSM8953_MASTER_IPA,
814
+
.buswidth = 8,
815
+
.qos.ap_owned = true,
816
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
817
+
.qos.prio_level = 0,
818
+
.qos.areq_prio = 0,
819
+
.qos.qos_port = 14,
820
+
.num_links = ARRAY_SIZE(mas_ipa_links),
821
+
.links = mas_ipa_links,
822
+
};
823
+
824
+
static const u16 mas_qdss_etr_links[] = {
825
+
MSM8953_SNOC_QDSS_INT
826
+
};
827
+
828
+
static struct qcom_icc_node mas_qdss_etr = {
829
+
.name = "mas_qdss_etr",
830
+
.id = MSM8953_MASTER_QDSS_ETR,
831
+
.buswidth = 8,
832
+
.qos.ap_owned = true,
833
+
.qos.qos_mode = NOC_QOS_MODE_FIXED,
834
+
.qos.prio_level = 1,
835
+
.qos.areq_prio = 1,
836
+
.qos.qos_port = 10,
837
+
.num_links = ARRAY_SIZE(mas_qdss_etr_links),
838
+
.links = mas_qdss_etr_links,
839
+
};
840
+
841
+
static const u16 qdss_int_links[] = {
842
+
MSM8953_SNOC_INT_1,
843
+
MSM8953_SNOC_BIMC_1_SLV
844
+
};
845
+
846
+
static struct qcom_icc_node qdss_int = {
847
+
.name = "qdss_int",
848
+
.id = MSM8953_SNOC_QDSS_INT,
849
+
.buswidth = 8,
850
+
.qos.ap_owned = true,
851
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
852
+
.qos.prio_level = 0,
853
+
.qos.areq_prio = 0,
854
+
.qos.qos_port = -1,
855
+
.num_links = ARRAY_SIZE(qdss_int_links),
856
+
.links = qdss_int_links,
857
+
};
858
+
859
+
static const u16 snoc_int_0_links[] = {
860
+
MSM8953_SLAVE_LPASS,
861
+
MSM8953_SLAVE_WCSS,
862
+
MSM8953_SLAVE_APPSS
863
+
};
864
+
865
+
static struct qcom_icc_node snoc_int_0 = {
866
+
.name = "snoc_int_0",
867
+
.id = MSM8953_SNOC_INT_0,
868
+
.buswidth = 8,
869
+
.qos.ap_owned = true,
870
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
871
+
.qos.prio_level = 0,
872
+
.qos.areq_prio = 0,
873
+
.qos.qos_port = -1,
874
+
.num_links = ARRAY_SIZE(snoc_int_0_links),
875
+
.links = snoc_int_0_links,
876
+
};
877
+
878
+
static const u16 snoc_int_1_links[] = {
879
+
MSM8953_SLAVE_QDSS_STM,
880
+
MSM8953_SLAVE_OCIMEM,
881
+
MSM8953_SNOC_PNOC_SLV
882
+
};
883
+
884
+
static struct qcom_icc_node snoc_int_1 = {
885
+
.name = "snoc_int_1",
886
+
.id = MSM8953_SNOC_INT_1,
887
+
.buswidth = 8,
888
+
.mas_rpm_id = 100,
889
+
.slv_rpm_id = 131,
890
+
.num_links = ARRAY_SIZE(snoc_int_1_links),
891
+
.links = snoc_int_1_links,
892
+
};
893
+
894
+
static const u16 snoc_int_2_links[] = {
895
+
MSM8953_SLAVE_CATS_128,
896
+
MSM8953_SLAVE_OCMEM_64
897
+
};
898
+
899
+
static struct qcom_icc_node snoc_int_2 = {
900
+
.name = "snoc_int_2",
901
+
.id = MSM8953_SNOC_INT_2,
902
+
.buswidth = 8,
903
+
.qos.ap_owned = true,
904
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
905
+
.qos.prio_level = 0,
906
+
.qos.areq_prio = 0,
907
+
.qos.qos_port = -1,
908
+
.num_links = ARRAY_SIZE(snoc_int_2_links),
909
+
.links = snoc_int_2_links,
910
+
};
911
+
912
+
static struct qcom_icc_node slv_kpss_ahb = {
913
+
.name = "slv_kpss_ahb",
914
+
.id = MSM8953_SLAVE_APPSS,
915
+
.buswidth = 4,
916
+
.qos.ap_owned = true,
917
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
918
+
.qos.prio_level = 0,
919
+
.qos.areq_prio = 0,
920
+
.qos.qos_port = -1,
921
+
};
922
+
923
+
static struct qcom_icc_node slv_wcss = {
924
+
.name = "slv_wcss",
925
+
.id = MSM8953_SLAVE_WCSS,
926
+
.buswidth = 4,
927
+
.qos.ap_owned = true,
928
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
929
+
.qos.prio_level = 0,
930
+
.qos.areq_prio = 0,
931
+
.qos.qos_port = -1,
932
+
};
933
+
934
+
static const u16 slv_snoc_bimc_1_links[] = {
935
+
MSM8953_SNOC_BIMC_1_MAS
936
+
};
937
+
938
+
static struct qcom_icc_node slv_snoc_bimc_1 = {
939
+
.name = "slv_snoc_bimc_1",
940
+
.id = MSM8953_SNOC_BIMC_1_SLV,
941
+
.buswidth = 8,
942
+
.mas_rpm_id = -1,
943
+
.slv_rpm_id = 104,
944
+
.num_links = ARRAY_SIZE(slv_snoc_bimc_1_links),
945
+
.links = slv_snoc_bimc_1_links,
946
+
};
947
+
948
+
static struct qcom_icc_node slv_imem = {
949
+
.name = "slv_imem",
950
+
.id = MSM8953_SLAVE_OCIMEM,
951
+
.buswidth = 8,
952
+
.mas_rpm_id = -1,
953
+
.slv_rpm_id = 26,
954
+
};
955
+
956
+
static const u16 slv_snoc_pcnoc_links[] = {
957
+
MSM8953_SNOC_PNOC_MAS
958
+
};
959
+
960
+
static struct qcom_icc_node slv_snoc_pcnoc = {
961
+
.name = "slv_snoc_pcnoc",
962
+
.id = MSM8953_SNOC_PNOC_SLV,
963
+
.buswidth = 8,
964
+
.mas_rpm_id = -1,
965
+
.slv_rpm_id = 28,
966
+
.num_links = ARRAY_SIZE(slv_snoc_pcnoc_links),
967
+
.links = slv_snoc_pcnoc_links,
968
+
};
969
+
970
+
static struct qcom_icc_node slv_qdss_stm = {
971
+
.name = "slv_qdss_stm",
972
+
.id = MSM8953_SLAVE_QDSS_STM,
973
+
.buswidth = 4,
974
+
.mas_rpm_id = -1,
975
+
.slv_rpm_id = 30,
976
+
};
977
+
978
+
static struct qcom_icc_node slv_cats_1 = {
979
+
.name = "slv_cats_1",
980
+
.id = MSM8953_SLAVE_OCMEM_64,
981
+
.buswidth = 8,
982
+
.qos.ap_owned = true,
983
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
984
+
.qos.prio_level = 0,
985
+
.qos.areq_prio = 0,
986
+
.qos.qos_port = -1,
987
+
};
988
+
989
+
static struct qcom_icc_node slv_lpass = {
990
+
.name = "slv_lpass",
991
+
.id = MSM8953_SLAVE_LPASS,
992
+
.buswidth = 4,
993
+
.qos.ap_owned = true,
994
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
995
+
.qos.prio_level = 0,
996
+
.qos.areq_prio = 0,
997
+
.qos.qos_port = -1,
998
+
};
999
+
1000
+
static const u16 mas_jpeg_links[] = {
1001
+
MSM8953_SNOC_BIMC_2_SLV
1002
+
};
1003
+
1004
+
static struct qcom_icc_node mas_jpeg = {
1005
+
.name = "mas_jpeg",
1006
+
.id = MSM8953_MASTER_JPEG,
1007
+
.buswidth = 16,
1008
+
.qos.ap_owned = true,
1009
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
1010
+
.qos.prio_level = 0,
1011
+
.qos.areq_prio = 0,
1012
+
.qos.qos_port = 6,
1013
+
.num_links = ARRAY_SIZE(mas_jpeg_links),
1014
+
.links = mas_jpeg_links,
1015
+
};
1016
+
1017
+
static const u16 mas_mdp_links[] = {
1018
+
MSM8953_SNOC_BIMC_0_SLV
1019
+
};
1020
+
1021
+
static struct qcom_icc_node mas_mdp = {
1022
+
.name = "mas_mdp",
1023
+
.id = MSM8953_MASTER_MDP_PORT0,
1024
+
.buswidth = 16,
1025
+
.qos.ap_owned = true,
1026
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
1027
+
.qos.prio_level = 0,
1028
+
.qos.areq_prio = 0,
1029
+
.qos.qos_port = 7,
1030
+
.num_links = ARRAY_SIZE(mas_mdp_links),
1031
+
.links = mas_mdp_links,
1032
+
};
1033
+
1034
+
static const u16 mas_venus_links[] = {
1035
+
MSM8953_SNOC_BIMC_2_SLV
1036
+
};
1037
+
1038
+
static struct qcom_icc_node mas_venus = {
1039
+
.name = "mas_venus",
1040
+
.id = MSM8953_MASTER_VIDEO_P0,
1041
+
.buswidth = 16,
1042
+
.qos.ap_owned = true,
1043
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
1044
+
.qos.prio_level = 0,
1045
+
.qos.areq_prio = 0,
1046
+
.qos.qos_port = 8,
1047
+
.num_links = ARRAY_SIZE(mas_venus_links),
1048
+
.links = mas_venus_links,
1049
+
};
1050
+
1051
+
static const u16 mas_vfe0_links[] = {
1052
+
MSM8953_SNOC_BIMC_0_SLV
1053
+
};
1054
+
1055
+
static struct qcom_icc_node mas_vfe0 = {
1056
+
.name = "mas_vfe0",
1057
+
.id = MSM8953_MASTER_VFE,
1058
+
.buswidth = 16,
1059
+
.qos.ap_owned = true,
1060
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
1061
+
.qos.prio_level = 0,
1062
+
.qos.areq_prio = 0,
1063
+
.qos.qos_port = 9,
1064
+
.num_links = ARRAY_SIZE(mas_vfe0_links),
1065
+
.links = mas_vfe0_links,
1066
+
};
1067
+
1068
+
static const u16 mas_vfe1_links[] = {
1069
+
MSM8953_SNOC_BIMC_0_SLV
1070
+
};
1071
+
1072
+
static struct qcom_icc_node mas_vfe1 = {
1073
+
.name = "mas_vfe1",
1074
+
.id = MSM8953_MASTER_VFE1,
1075
+
.buswidth = 16,
1076
+
.qos.ap_owned = true,
1077
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
1078
+
.qos.prio_level = 0,
1079
+
.qos.areq_prio = 0,
1080
+
.qos.qos_port = 13,
1081
+
.num_links = ARRAY_SIZE(mas_vfe1_links),
1082
+
.links = mas_vfe1_links,
1083
+
};
1084
+
1085
+
static const u16 mas_cpp_links[] = {
1086
+
MSM8953_SNOC_BIMC_2_SLV
1087
+
};
1088
+
1089
+
static struct qcom_icc_node mas_cpp = {
1090
+
.name = "mas_cpp",
1091
+
.id = MSM8953_MASTER_CPP,
1092
+
.buswidth = 16,
1093
+
.qos.ap_owned = true,
1094
+
.qos.qos_mode = NOC_QOS_MODE_BYPASS,
1095
+
.qos.prio_level = 0,
1096
+
.qos.areq_prio = 0,
1097
+
.qos.qos_port = 12,
1098
+
.num_links = ARRAY_SIZE(mas_cpp_links),
1099
+
.links = mas_cpp_links,
1100
+
};
1101
+
1102
+
static const u16 slv_snoc_bimc_0_links[] = {
1103
+
MSM8953_SNOC_BIMC_0_MAS
1104
+
};
1105
+
1106
+
static struct qcom_icc_node slv_snoc_bimc_0 = {
1107
+
.name = "slv_snoc_bimc_0",
1108
+
.id = MSM8953_SNOC_BIMC_0_SLV,
1109
+
.buswidth = 16,
1110
+
.qos.ap_owned = true,
1111
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1112
+
.qos.prio_level = 0,
1113
+
.qos.areq_prio = 0,
1114
+
.qos.qos_port = -1,
1115
+
.num_links = ARRAY_SIZE(slv_snoc_bimc_0_links),
1116
+
.links = slv_snoc_bimc_0_links,
1117
+
};
1118
+
1119
+
static const u16 slv_snoc_bimc_2_links[] = {
1120
+
MSM8953_SNOC_BIMC_2_MAS
1121
+
};
1122
+
1123
+
static struct qcom_icc_node slv_snoc_bimc_2 = {
1124
+
.name = "slv_snoc_bimc_2",
1125
+
.id = MSM8953_SNOC_BIMC_2_SLV,
1126
+
.buswidth = 16,
1127
+
.qos.ap_owned = true,
1128
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1129
+
.qos.prio_level = 0,
1130
+
.qos.areq_prio = 0,
1131
+
.qos.qos_port = -1,
1132
+
.num_links = ARRAY_SIZE(slv_snoc_bimc_2_links),
1133
+
.links = slv_snoc_bimc_2_links,
1134
+
};
1135
+
1136
+
static struct qcom_icc_node slv_cats_0 = {
1137
+
.name = "slv_cats_0",
1138
+
.id = MSM8953_SLAVE_CATS_128,
1139
+
.buswidth = 16,
1140
+
.qos.ap_owned = true,
1141
+
.qos.qos_mode = NOC_QOS_MODE_INVALID,
1142
+
.qos.prio_level = 0,
1143
+
.qos.areq_prio = 0,
1144
+
.qos.qos_port = -1,
1145
+
};
1146
+
1147
+
static struct qcom_icc_node * const msm8953_bimc_nodes[] = {
1148
+
[MAS_APPS_PROC] = &mas_apps_proc,
1149
+
[MAS_OXILI] = &mas_oxili,
1150
+
[MAS_SNOC_BIMC_0] = &mas_snoc_bimc_0,
1151
+
[MAS_SNOC_BIMC_2] = &mas_snoc_bimc_2,
1152
+
[MAS_SNOC_BIMC_1] = &mas_snoc_bimc_1,
1153
+
[MAS_TCU_0] = &mas_tcu_0,
1154
+
[SLV_EBI] = &slv_ebi,
1155
+
[SLV_BIMC_SNOC] = &slv_bimc_snoc,
1156
+
};
1157
+
1158
+
static const struct regmap_config msm8953_bimc_regmap_config = {
1159
+
.fast_io = true,
1160
+
.max_register = 0x5a000,
1161
+
.reg_bits = 32,
1162
+
.reg_stride = 4,
1163
+
.val_bits = 32,
1164
+
};
1165
+
1166
+
static const struct qcom_icc_desc msm8953_bimc = {
1167
+
.type = QCOM_ICC_BIMC,
1168
+
.bus_clk_desc = &bimc_clk,
1169
+
.nodes = msm8953_bimc_nodes,
1170
+
.num_nodes = ARRAY_SIZE(msm8953_bimc_nodes),
1171
+
.qos_offset = 0x8000,
1172
+
.regmap_cfg = &msm8953_bimc_regmap_config
1173
+
};
1174
+
1175
+
static struct qcom_icc_node * const msm8953_pcnoc_nodes[] = {
1176
+
[MAS_SPDM] = &mas_spdm,
1177
+
[MAS_BLSP_1] = &mas_blsp_1,
1178
+
[MAS_BLSP_2] = &mas_blsp_2,
1179
+
[MAS_USB3] = &mas_usb3,
1180
+
[MAS_CRYPTO] = &mas_crypto,
1181
+
[MAS_SDCC_1] = &mas_sdcc_1,
1182
+
[MAS_SDCC_2] = &mas_sdcc_2,
1183
+
[MAS_SNOC_PCNOC] = &mas_snoc_pcnoc,
1184
+
[PCNOC_M_0] = &pcnoc_m_0,
1185
+
[PCNOC_M_1] = &pcnoc_m_1,
1186
+
[PCNOC_INT_1] = &pcnoc_int_1,
1187
+
[PCNOC_INT_2] = &pcnoc_int_2,
1188
+
[PCNOC_S_0] = &pcnoc_s_0,
1189
+
[PCNOC_S_1] = &pcnoc_s_1,
1190
+
[PCNOC_S_2] = &pcnoc_s_2,
1191
+
[PCNOC_S_3] = &pcnoc_s_3,
1192
+
[PCNOC_S_4] = &pcnoc_s_4,
1193
+
[PCNOC_S_6] = &pcnoc_s_6,
1194
+
[PCNOC_S_7] = &pcnoc_s_7,
1195
+
[PCNOC_S_8] = &pcnoc_s_8,
1196
+
[PCNOC_S_9] = &pcnoc_s_9,
1197
+
[SLV_SPDM] = &slv_spdm,
1198
+
[SLV_PDM] = &slv_pdm,
1199
+
[SLV_TCSR] = &slv_tcsr,
1200
+
[SLV_SNOC_CFG] = &slv_snoc_cfg,
1201
+
[SLV_TLMM] = &slv_tlmm,
1202
+
[SLV_MESSAGE_RAM] = &slv_message_ram,
1203
+
[SLV_BLSP_1] = &slv_blsp_1,
1204
+
[SLV_BLSP_2] = &slv_blsp_2,
1205
+
[SLV_PRNG] = &slv_prng,
1206
+
[SLV_CAMERA_SS_CFG] = &slv_camera_ss_cfg,
1207
+
[SLV_DISP_SS_CFG] = &slv_disp_ss_cfg,
1208
+
[SLV_VENUS_CFG] = &slv_venus_cfg,
1209
+
[SLV_GPU_CFG] = &slv_gpu_cfg,
1210
+
[SLV_SDCC_1] = &slv_sdcc_1,
1211
+
[SLV_SDCC_2] = &slv_sdcc_2,
1212
+
[SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1213
+
[SLV_PMIC_ARB] = &slv_pmic_arb,
1214
+
[SLV_USB3] = &slv_usb3,
1215
+
[SLV_IPA_CFG] = &slv_ipa_cfg,
1216
+
[SLV_TCU] = &slv_tcu,
1217
+
[SLV_PCNOC_SNOC] = &slv_pcnoc_snoc,
1218
+
};
1219
+
1220
+
static const char * const msm8953_pcnoc_intf_clocks[] = {
1221
+
"pcnoc_usb3_axi"
1222
+
};
1223
+
1224
+
static const struct regmap_config msm8953_pcnoc_regmap_config = {
1225
+
.fast_io = true,
1226
+
.max_register = 0x12080,
1227
+
.reg_bits = 32,
1228
+
.reg_stride = 4,
1229
+
.val_bits = 32,
1230
+
};
1231
+
1232
+
static const struct qcom_icc_desc msm8953_pcnoc = {
1233
+
.type = QCOM_ICC_NOC,
1234
+
.bus_clk_desc = &bus_0_clk,
1235
+
.intf_clocks = msm8953_pcnoc_intf_clocks,
1236
+
.num_intf_clocks = ARRAY_SIZE(msm8953_pcnoc_intf_clocks),
1237
+
.nodes = msm8953_pcnoc_nodes,
1238
+
.num_nodes = ARRAY_SIZE(msm8953_pcnoc_nodes),
1239
+
.qos_offset = 0x7000,
1240
+
.regmap_cfg = &msm8953_pcnoc_regmap_config,
1241
+
};
1242
+
1243
+
static struct qcom_icc_node * const msm8953_snoc_nodes[] = {
1244
+
[MAS_QDSS_BAM] = &mas_qdss_bam,
1245
+
[MAS_BIMC_SNOC] = &mas_bimc_snoc,
1246
+
[MAS_PCNOC_SNOC] = &mas_pcnoc_snoc,
1247
+
[MAS_IPA] = &mas_ipa,
1248
+
[MAS_QDSS_ETR] = &mas_qdss_etr,
1249
+
[QDSS_INT] = &qdss_int,
1250
+
[SNOC_INT_0] = &snoc_int_0,
1251
+
[SNOC_INT_1] = &snoc_int_1,
1252
+
[SNOC_INT_2] = &snoc_int_2,
1253
+
[SLV_KPSS_AHB] = &slv_kpss_ahb,
1254
+
[SLV_WCSS] = &slv_wcss,
1255
+
[SLV_SNOC_BIMC_1] = &slv_snoc_bimc_1,
1256
+
[SLV_IMEM] = &slv_imem,
1257
+
[SLV_SNOC_PCNOC] = &slv_snoc_pcnoc,
1258
+
[SLV_QDSS_STM] = &slv_qdss_stm,
1259
+
[SLV_CATS_1] = &slv_cats_1,
1260
+
[SLV_LPASS] = &slv_lpass,
1261
+
};
1262
+
1263
+
static const struct regmap_config msm8953_snoc_regmap_config = {
1264
+
.fast_io = true,
1265
+
.max_register = 0x16080,
1266
+
.reg_bits = 32,
1267
+
.reg_stride = 4,
1268
+
.val_bits = 32,
1269
+
};
1270
+
1271
+
static const struct qcom_icc_desc msm8953_snoc = {
1272
+
.type = QCOM_ICC_NOC,
1273
+
.bus_clk_desc = &bus_1_clk,
1274
+
.nodes = msm8953_snoc_nodes,
1275
+
.num_nodes = ARRAY_SIZE(msm8953_snoc_nodes),
1276
+
.qos_offset = 0x7000,
1277
+
.regmap_cfg = &msm8953_snoc_regmap_config,
1278
+
};
1279
+
1280
+
static struct qcom_icc_node * const msm8953_snoc_mm_nodes[] = {
1281
+
[MAS_JPEG] = &mas_jpeg,
1282
+
[MAS_MDP] = &mas_mdp,
1283
+
[MAS_VENUS] = &mas_venus,
1284
+
[MAS_VFE0] = &mas_vfe0,
1285
+
[MAS_VFE1] = &mas_vfe1,
1286
+
[MAS_CPP] = &mas_cpp,
1287
+
[SLV_SNOC_BIMC_0] = &slv_snoc_bimc_0,
1288
+
[SLV_SNOC_BIMC_2] = &slv_snoc_bimc_2,
1289
+
[SLV_CATS_0] = &slv_cats_0,
1290
+
};
1291
+
1292
+
static const struct qcom_icc_desc msm8953_snoc_mm = {
1293
+
.type = QCOM_ICC_NOC,
1294
+
.bus_clk_desc = &bus_2_clk,
1295
+
.nodes = msm8953_snoc_mm_nodes,
1296
+
.num_nodes = ARRAY_SIZE(msm8953_snoc_mm_nodes),
1297
+
.qos_offset = 0x7000,
1298
+
.regmap_cfg = &msm8953_snoc_regmap_config,
1299
+
};
1300
+
1301
+
static const struct of_device_id msm8953_noc_of_match[] = {
1302
+
{ .compatible = "qcom,msm8953-bimc", .data = &msm8953_bimc },
1303
+
{ .compatible = "qcom,msm8953-pcnoc", .data = &msm8953_pcnoc },
1304
+
{ .compatible = "qcom,msm8953-snoc", .data = &msm8953_snoc },
1305
+
{ .compatible = "qcom,msm8953-snoc-mm", .data = &msm8953_snoc_mm },
1306
+
{ }
1307
+
};
1308
+
1309
+
static struct platform_driver msm8953_noc_driver = {
1310
+
.probe = qnoc_probe,
1311
+
.remove_new = qnoc_remove,
1312
+
.driver = {
1313
+
.name = "qnoc-msm8953",
1314
+
.of_match_table = msm8953_noc_of_match,
1315
+
},
1316
+
};
1317
+
1318
+
module_platform_driver(msm8953_noc_driver);
1319
+
MODULE_DEVICE_TABLE(of, msm8953_noc_of_match);
1320
+
MODULE_DESCRIPTION("Qualcomm MSM8953 NoC driver");
1321
+
MODULE_LICENSE("GPL");
+1
-1
drivers/interconnect/qcom/qcm2290.c
+1
-1
drivers/interconnect/qcom/qcm2290.c
+276
drivers/interconnect/qcom/sc7280.c
+276
drivers/interconnect/qcom/sc7280.c
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
/*
3
3
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
4
5
*
5
6
*/
6
7
···
22
21
.id = SC7280_MASTER_QSPI_0,
23
22
.channels = 1,
24
23
.buswidth = 4,
24
+
.qosbox = &(const struct qcom_icc_qosbox) {
25
+
.num_ports = 1,
26
+
.port_offsets = { 0x7000 },
27
+
.prio = 2,
28
+
.urg_fwd = 0,
29
+
},
25
30
.num_links = 1,
26
31
.links = { SC7280_SLAVE_A1NOC_SNOC },
27
32
};
···
37
30
.id = SC7280_MASTER_QUP_0,
38
31
.channels = 1,
39
32
.buswidth = 4,
33
+
.qosbox = &(const struct qcom_icc_qosbox) {
34
+
.num_ports = 1,
35
+
.port_offsets = { 0x11000 },
36
+
.prio = 2,
37
+
.urg_fwd = 0,
38
+
},
40
39
.num_links = 1,
41
40
.links = { SC7280_SLAVE_A1NOC_SNOC },
42
41
};
···
52
39
.id = SC7280_MASTER_QUP_1,
53
40
.channels = 1,
54
41
.buswidth = 4,
42
+
.qosbox = &(const struct qcom_icc_qosbox) {
43
+
.num_ports = 1,
44
+
.port_offsets = { 0x8000 },
45
+
.prio = 2,
46
+
.urg_fwd = 0,
47
+
},
55
48
.num_links = 1,
56
49
.links = { SC7280_SLAVE_A1NOC_SNOC },
57
50
};
···
76
57
.id = SC7280_MASTER_SDCC_1,
77
58
.channels = 1,
78
59
.buswidth = 8,
60
+
.qosbox = &(const struct qcom_icc_qosbox) {
61
+
.num_ports = 1,
62
+
.port_offsets = { 0xc000 },
63
+
.prio = 2,
64
+
.urg_fwd = 0,
65
+
},
79
66
.num_links = 1,
80
67
.links = { SC7280_SLAVE_A1NOC_SNOC },
81
68
};
···
91
66
.id = SC7280_MASTER_SDCC_2,
92
67
.channels = 1,
93
68
.buswidth = 8,
69
+
.qosbox = &(const struct qcom_icc_qosbox) {
70
+
.num_ports = 1,
71
+
.port_offsets = { 0xe000 },
72
+
.prio = 2,
73
+
.urg_fwd = 0,
74
+
},
94
75
.num_links = 1,
95
76
.links = { SC7280_SLAVE_A1NOC_SNOC },
96
77
};
···
106
75
.id = SC7280_MASTER_SDCC_4,
107
76
.channels = 1,
108
77
.buswidth = 8,
78
+
.qosbox = &(const struct qcom_icc_qosbox) {
79
+
.num_ports = 1,
80
+
.port_offsets = { 0x9000 },
81
+
.prio = 2,
82
+
.urg_fwd = 0,
83
+
},
109
84
.num_links = 1,
110
85
.links = { SC7280_SLAVE_A1NOC_SNOC },
111
86
};
···
121
84
.id = SC7280_MASTER_UFS_MEM,
122
85
.channels = 1,
123
86
.buswidth = 8,
87
+
.qosbox = &(const struct qcom_icc_qosbox) {
88
+
.num_ports = 1,
89
+
.port_offsets = { 0xa000 },
90
+
.prio = 2,
91
+
.urg_fwd = 0,
92
+
},
124
93
.num_links = 1,
125
94
.links = { SC7280_SLAVE_A1NOC_SNOC },
126
95
};
···
145
102
.id = SC7280_MASTER_USB3_0,
146
103
.channels = 1,
147
104
.buswidth = 8,
105
+
.qosbox = &(const struct qcom_icc_qosbox) {
106
+
.num_ports = 1,
107
+
.port_offsets = { 0xb000 },
108
+
.prio = 2,
109
+
.urg_fwd = 0,
110
+
},
148
111
.num_links = 1,
149
112
.links = { SC7280_SLAVE_A1NOC_SNOC },
150
113
};
···
160
111
.id = SC7280_MASTER_QDSS_BAM,
161
112
.channels = 1,
162
113
.buswidth = 4,
114
+
.qosbox = &(const struct qcom_icc_qosbox) {
115
+
.num_ports = 1,
116
+
.port_offsets = { 0x18000 },
117
+
.prio = 2,
118
+
.urg_fwd = 0,
119
+
},
163
120
.num_links = 1,
164
121
.links = { SC7280_SLAVE_A2NOC_SNOC },
165
122
};
···
184
129
.id = SC7280_MASTER_CNOC_A2NOC,
185
130
.channels = 1,
186
131
.buswidth = 8,
132
+
.qosbox = &(const struct qcom_icc_qosbox) {
133
+
.num_ports = 1,
134
+
.port_offsets = { 0x1c000 },
135
+
.prio = 2,
136
+
.urg_fwd = 0,
137
+
},
187
138
.num_links = 1,
188
139
.links = { SC7280_SLAVE_A2NOC_SNOC },
189
140
};
···
199
138
.id = SC7280_MASTER_CRYPTO,
200
139
.channels = 1,
201
140
.buswidth = 8,
141
+
.qosbox = &(const struct qcom_icc_qosbox) {
142
+
.num_ports = 1,
143
+
.port_offsets = { 0x1d000 },
144
+
.prio = 2,
145
+
.urg_fwd = 0,
146
+
},
202
147
.num_links = 1,
203
148
.links = { SC7280_SLAVE_A2NOC_SNOC },
204
149
};
···
214
147
.id = SC7280_MASTER_IPA,
215
148
.channels = 1,
216
149
.buswidth = 8,
150
+
.qosbox = &(const struct qcom_icc_qosbox) {
151
+
.num_ports = 1,
152
+
.port_offsets = { 0x10000 },
153
+
.prio = 2,
154
+
.urg_fwd = 0,
155
+
},
217
156
.num_links = 1,
218
157
.links = { SC7280_SLAVE_A2NOC_SNOC },
219
158
};
···
246
173
.id = SC7280_MASTER_QDSS_ETR,
247
174
.channels = 1,
248
175
.buswidth = 8,
176
+
.qosbox = &(const struct qcom_icc_qosbox) {
177
+
.num_ports = 1,
178
+
.port_offsets = { 0x15000 },
179
+
.prio = 2,
180
+
.urg_fwd = 0,
181
+
},
249
182
.num_links = 1,
250
183
.links = { SC7280_SLAVE_A2NOC_SNOC },
251
184
};
···
384
305
.id = SC7280_MASTER_GPU_TCU,
385
306
.channels = 1,
386
307
.buswidth = 8,
308
+
.qosbox = &(const struct qcom_icc_qosbox) {
309
+
.num_ports = 1,
310
+
.port_offsets = { 0xd7000 },
311
+
.prio = 2,
312
+
.urg_fwd = 0,
313
+
},
387
314
.num_links = 2,
388
315
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
389
316
};
···
399
314
.id = SC7280_MASTER_SYS_TCU,
400
315
.channels = 1,
401
316
.buswidth = 8,
317
+
.qosbox = &(const struct qcom_icc_qosbox) {
318
+
.num_ports = 1,
319
+
.port_offsets = { 0xd6000 },
320
+
.prio = 6,
321
+
.urg_fwd = 0,
322
+
},
402
323
.num_links = 2,
403
324
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
404
325
};
···
424
333
.id = SC7280_MASTER_COMPUTE_NOC,
425
334
.channels = 2,
426
335
.buswidth = 32,
336
+
.qosbox = &(const struct qcom_icc_qosbox) {
337
+
.num_ports = 2,
338
+
.port_offsets = { 0x21000, 0x61000 },
339
+
.prio = 0,
340
+
.urg_fwd = 1,
341
+
},
427
342
.num_links = 2,
428
343
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
429
344
};
···
450
353
.id = SC7280_MASTER_GFX3D,
451
354
.channels = 2,
452
355
.buswidth = 32,
356
+
.qosbox = &(const struct qcom_icc_qosbox) {
357
+
.num_ports = 2,
358
+
.port_offsets = { 0x22000, 0x62000 },
359
+
.prio = 0,
360
+
.urg_fwd = 0,
361
+
},
453
362
.num_links = 2,
454
363
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
455
364
};
···
465
362
.id = SC7280_MASTER_MNOC_HF_MEM_NOC,
466
363
.channels = 2,
467
364
.buswidth = 32,
365
+
.qosbox = &(const struct qcom_icc_qosbox) {
366
+
.num_ports = 2,
367
+
.port_offsets = { 0x23000, 0x63000 },
368
+
.prio = 0,
369
+
.urg_fwd = 1,
370
+
},
468
371
.num_links = 1,
469
372
.links = { SC7280_SLAVE_LLCC },
470
373
};
···
480
371
.id = SC7280_MASTER_MNOC_SF_MEM_NOC,
481
372
.channels = 1,
482
373
.buswidth = 32,
374
+
.qosbox = &(const struct qcom_icc_qosbox) {
375
+
.num_ports = 1,
376
+
.port_offsets = { 0xcf000 },
377
+
.prio = 0,
378
+
.urg_fwd = 1,
379
+
},
483
380
.num_links = 2,
484
381
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
485
382
};
···
504
389
.id = SC7280_MASTER_SNOC_GC_MEM_NOC,
505
390
.channels = 1,
506
391
.buswidth = 8,
392
+
.qosbox = &(const struct qcom_icc_qosbox) {
393
+
.num_ports = 1,
394
+
.port_offsets = { 0xd3000 },
395
+
.prio = 0,
396
+
.urg_fwd = 1,
397
+
},
507
398
.num_links = 1,
508
399
.links = { SC7280_SLAVE_LLCC },
509
400
};
···
519
398
.id = SC7280_MASTER_SNOC_SF_MEM_NOC,
520
399
.channels = 1,
521
400
.buswidth = 16,
401
+
.qosbox = &(const struct qcom_icc_qosbox) {
402
+
.num_ports = 1,
403
+
.port_offsets = { 0xd4000 },
404
+
.prio = 0,
405
+
.urg_fwd = 1,
406
+
},
522
407
.num_links = 3,
523
408
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
524
409
SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
···
564
437
.id = SC7280_MASTER_VIDEO_P0,
565
438
.channels = 1,
566
439
.buswidth = 32,
440
+
.qosbox = &(const struct qcom_icc_qosbox) {
441
+
.num_ports = 1,
442
+
.port_offsets = { 0x14000 },
443
+
.prio = 0,
444
+
.urg_fwd = 1,
445
+
},
567
446
.num_links = 1,
568
447
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
569
448
};
···
579
446
.id = SC7280_MASTER_VIDEO_PROC,
580
447
.channels = 1,
581
448
.buswidth = 8,
449
+
.qosbox = &(const struct qcom_icc_qosbox) {
450
+
.num_ports = 1,
451
+
.port_offsets = { 0x15000 },
452
+
.prio = 0,
453
+
.urg_fwd = 1,
454
+
},
582
455
.num_links = 1,
583
456
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
584
457
};
···
594
455
.id = SC7280_MASTER_CAMNOC_HF,
595
456
.channels = 2,
596
457
.buswidth = 32,
458
+
.qosbox = &(const struct qcom_icc_qosbox) {
459
+
.num_ports = 2,
460
+
.port_offsets = { 0x10000, 0x10180 },
461
+
.prio = 0,
462
+
.urg_fwd = 1,
463
+
},
597
464
.num_links = 1,
598
465
.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
599
466
};
···
609
464
.id = SC7280_MASTER_CAMNOC_ICP,
610
465
.channels = 1,
611
466
.buswidth = 8,
467
+
.qosbox = &(const struct qcom_icc_qosbox) {
468
+
.num_ports = 1,
469
+
.port_offsets = { 0x11000 },
470
+
.prio = 0,
471
+
.urg_fwd = 1,
472
+
},
612
473
.num_links = 1,
613
474
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
614
475
};
···
624
473
.id = SC7280_MASTER_CAMNOC_SF,
625
474
.channels = 1,
626
475
.buswidth = 32,
476
+
.qosbox = &(const struct qcom_icc_qosbox) {
477
+
.num_ports = 1,
478
+
.port_offsets = { 0x12000 },
479
+
.prio = 0,
480
+
.urg_fwd = 1,
481
+
},
627
482
.num_links = 1,
628
483
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
629
484
};
···
639
482
.id = SC7280_MASTER_MDP0,
640
483
.channels = 1,
641
484
.buswidth = 32,
485
+
.qosbox = &(const struct qcom_icc_qosbox) {
486
+
.num_ports = 1,
487
+
.port_offsets = { 0x16000 },
488
+
.prio = 0,
489
+
.urg_fwd = 1,
490
+
},
642
491
.num_links = 1,
643
492
.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
644
493
};
···
699
536
.id = SC7280_MASTER_PIMEM,
700
537
.channels = 1,
701
538
.buswidth = 8,
539
+
.qosbox = &(const struct qcom_icc_qosbox) {
540
+
.num_ports = 1,
541
+
.port_offsets = { 0x8000 },
542
+
.prio = 2,
543
+
.urg_fwd = 0,
544
+
},
702
545
.num_links = 1,
703
546
.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
704
547
};
···
714
545
.id = SC7280_MASTER_GIC,
715
546
.channels = 1,
716
547
.buswidth = 8,
548
+
.qosbox = &(const struct qcom_icc_qosbox) {
549
+
.num_ports = 1,
550
+
.port_offsets = { 0xa000 },
551
+
.prio = 2,
552
+
.urg_fwd = 0,
553
+
},
717
554
.num_links = 1,
718
555
.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
719
556
};
···
1677
1502
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1678
1503
};
1679
1504
1505
+
static const struct regmap_config sc7280_aggre1_noc_regmap_config = {
1506
+
.reg_bits = 32,
1507
+
.reg_stride = 4,
1508
+
.val_bits = 32,
1509
+
.max_register = 0x1c080,
1510
+
.fast_io = true,
1511
+
};
1512
+
1680
1513
static const struct qcom_icc_desc sc7280_aggre1_noc = {
1514
+
.config = &sc7280_aggre1_noc_regmap_config,
1681
1515
.nodes = aggre1_noc_nodes,
1682
1516
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1683
1517
.bcms = aggre1_noc_bcms,
1684
1518
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1519
+
.qos_clks_required = true,
1685
1520
};
1686
1521
1687
1522
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1688
1523
&bcm_ce0,
1524
+
};
1525
+
1526
+
static const struct regmap_config sc7280_aggre2_noc_regmap_config = {
1527
+
.reg_bits = 32,
1528
+
.reg_stride = 4,
1529
+
.val_bits = 32,
1530
+
.max_register = 0x2b080,
1531
+
.fast_io = true,
1689
1532
};
1690
1533
1691
1534
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
···
1718
1525
};
1719
1526
1720
1527
static const struct qcom_icc_desc sc7280_aggre2_noc = {
1528
+
.config = &sc7280_aggre2_noc_regmap_config,
1721
1529
.nodes = aggre2_noc_nodes,
1722
1530
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1723
1531
.bcms = aggre2_noc_bcms,
1724
1532
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1533
+
.qos_clks_required = true,
1725
1534
};
1726
1535
1727
1536
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
···
1800
1605
[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1801
1606
};
1802
1607
1608
+
static const struct regmap_config sc7280_cnoc2_regmap_config = {
1609
+
.reg_bits = 32,
1610
+
.reg_stride = 4,
1611
+
.val_bits = 32,
1612
+
.max_register = 0x1000,
1613
+
.fast_io = true,
1614
+
};
1615
+
1803
1616
static const struct qcom_icc_desc sc7280_cnoc2 = {
1617
+
.config = &sc7280_cnoc2_regmap_config,
1804
1618
.nodes = cnoc2_nodes,
1805
1619
.num_nodes = ARRAY_SIZE(cnoc2_nodes),
1806
1620
.bcms = cnoc2_bcms,
···
1841
1637
[SLAVE_TCU] = &xs_sys_tcu_cfg,
1842
1638
};
1843
1639
1640
+
static const struct regmap_config sc7280_cnoc3_regmap_config = {
1641
+
.reg_bits = 32,
1642
+
.reg_stride = 4,
1643
+
.val_bits = 32,
1644
+
.max_register = 0x1000,
1645
+
.fast_io = true,
1646
+
};
1647
+
1844
1648
static const struct qcom_icc_desc sc7280_cnoc3 = {
1649
+
.config = &sc7280_cnoc3_regmap_config,
1845
1650
.nodes = cnoc3_nodes,
1846
1651
.num_nodes = ARRAY_SIZE(cnoc3_nodes),
1847
1652
.bcms = cnoc3_bcms,
···
1866
1653
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
1867
1654
};
1868
1655
1656
+
static const struct regmap_config sc7280_dc_noc_regmap_config = {
1657
+
.reg_bits = 32,
1658
+
.reg_stride = 4,
1659
+
.val_bits = 32,
1660
+
.max_register = 0x5080,
1661
+
.fast_io = true,
1662
+
};
1663
+
1869
1664
static const struct qcom_icc_desc sc7280_dc_noc = {
1665
+
.config = &sc7280_dc_noc_regmap_config,
1870
1666
.nodes = dc_noc_nodes,
1871
1667
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
1872
1668
.bcms = dc_noc_bcms,
···
1911
1689
[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
1912
1690
};
1913
1691
1692
+
static const struct regmap_config sc7280_gem_noc_regmap_config = {
1693
+
.reg_bits = 32,
1694
+
.reg_stride = 4,
1695
+
.val_bits = 32,
1696
+
.max_register = 0xe2200,
1697
+
.fast_io = true,
1698
+
};
1699
+
1914
1700
static const struct qcom_icc_desc sc7280_gem_noc = {
1701
+
.config = &sc7280_gem_noc_regmap_config,
1915
1702
.nodes = gem_noc_nodes,
1916
1703
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1917
1704
.bcms = gem_noc_bcms,
···
1940
1709
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1941
1710
};
1942
1711
1712
+
static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = {
1713
+
.reg_bits = 32,
1714
+
.reg_stride = 4,
1715
+
.val_bits = 32,
1716
+
.max_register = 0xf080,
1717
+
.fast_io = true,
1718
+
};
1719
+
1943
1720
static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
1721
+
.config = &sc7280_lpass_ag_noc_regmap_config,
1944
1722
.nodes = lpass_ag_noc_nodes,
1945
1723
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1946
1724
.bcms = lpass_ag_noc_bcms,
···
1966
1726
[SLAVE_EBI1] = &ebi,
1967
1727
};
1968
1728
1729
+
static const struct regmap_config sc7280_mc_virt_regmap_config = {
1730
+
.reg_bits = 32,
1731
+
.reg_stride = 4,
1732
+
.val_bits = 32,
1733
+
.max_register = 0x4,
1734
+
.fast_io = true,
1735
+
};
1736
+
1969
1737
static const struct qcom_icc_desc sc7280_mc_virt = {
1738
+
.config = &sc7280_mc_virt_regmap_config,
1970
1739
.nodes = mc_virt_nodes,
1971
1740
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1972
1741
.bcms = mc_virt_bcms,
···
2002
1753
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
2003
1754
};
2004
1755
1756
+
static const struct regmap_config sc7280_mmss_noc_regmap_config = {
1757
+
.reg_bits = 32,
1758
+
.reg_stride = 4,
1759
+
.val_bits = 32,
1760
+
.max_register = 0x1e080,
1761
+
.fast_io = true,
1762
+
};
1763
+
2005
1764
static const struct qcom_icc_desc sc7280_mmss_noc = {
1765
+
.config = &sc7280_mmss_noc_regmap_config,
2006
1766
.nodes = mmss_noc_nodes,
2007
1767
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2008
1768
.bcms = mmss_noc_bcms,
···
2030
1772
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
2031
1773
};
2032
1774
1775
+
static const struct regmap_config sc7280_nsp_noc_regmap_config = {
1776
+
.reg_bits = 32,
1777
+
.reg_stride = 4,
1778
+
.val_bits = 32,
1779
+
.max_register = 0x10000,
1780
+
.fast_io = true,
1781
+
};
1782
+
2033
1783
static const struct qcom_icc_desc sc7280_nsp_noc = {
1784
+
.config = &sc7280_nsp_noc_regmap_config,
2034
1785
.nodes = nsp_noc_nodes,
2035
1786
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
2036
1787
.bcms = nsp_noc_bcms,
···
2064
1797
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
2065
1798
};
2066
1799
1800
+
static const struct regmap_config sc7280_system_noc_regmap_config = {
1801
+
.reg_bits = 32,
1802
+
.reg_stride = 4,
1803
+
.val_bits = 32,
1804
+
.max_register = 0x15480,
1805
+
.fast_io = true,
1806
+
};
1807
+
2067
1808
static const struct qcom_icc_desc sc7280_system_noc = {
1809
+
.config = &sc7280_system_noc_regmap_config,
2068
1810
.nodes = system_noc_nodes,
2069
1811
.num_nodes = ARRAY_SIZE(system_noc_nodes),
2070
1812
.bcms = system_noc_bcms,
+23
include/dt-bindings/interconnect/mediatek,mt8183.h
+23
include/dt-bindings/interconnect/mediatek,mt8183.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Copyright (c) 2024 Collabora Ltd.
5
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6
+
*/
7
+
8
+
#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8183_H
9
+
#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8183_H
10
+
11
+
#define SLAVE_DDR_EMI 0
12
+
#define MASTER_MCUSYS 1
13
+
#define MASTER_MFG 2
14
+
#define MASTER_MMSYS 3
15
+
#define MASTER_MM_VPU 4
16
+
#define MASTER_MM_DISP 5
17
+
#define MASTER_MM_VDEC 6
18
+
#define MASTER_MM_VENC 7
19
+
#define MASTER_MM_CAM 8
20
+
#define MASTER_MM_IMG 9
21
+
#define MASTER_MM_MDP 10
22
+
23
+
#endif
+44
include/dt-bindings/interconnect/mediatek,mt8195.h
+44
include/dt-bindings/interconnect/mediatek,mt8195.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2020 MediaTek Inc.
4
+
* Copyright (c) 2024 Collabora Ltd.
5
+
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6
+
*/
7
+
8
+
#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H
9
+
#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H
10
+
11
+
#define SLAVE_DDR_EMI 0
12
+
#define MASTER_MCUSYS 1
13
+
#define MASTER_GPUSYS 2
14
+
#define MASTER_MMSYS 3
15
+
#define MASTER_MM_VPU 4
16
+
#define MASTER_MM_DISP 5
17
+
#define MASTER_MM_VDEC 6
18
+
#define MASTER_MM_VENC 7
19
+
#define MASTER_MM_CAM 8
20
+
#define MASTER_MM_IMG 9
21
+
#define MASTER_MM_MDP 10
22
+
#define MASTER_VPUSYS 11
23
+
#define MASTER_VPU_0 12
24
+
#define MASTER_VPU_1 13
25
+
#define MASTER_MDLASYS 14
26
+
#define MASTER_MDLA_0 15
27
+
#define MASTER_UFS 16
28
+
#define MASTER_PCIE_0 17
29
+
#define MASTER_PCIE_1 18
30
+
#define MASTER_USB 19
31
+
#define MASTER_DBGIF 20
32
+
#define SLAVE_HRT_DDR_EMI 21
33
+
#define MASTER_HRT_MMSYS 22
34
+
#define MASTER_HRT_MM_DISP 23
35
+
#define MASTER_HRT_MM_VDEC 24
36
+
#define MASTER_HRT_MM_VENC 25
37
+
#define MASTER_HRT_MM_CAM 26
38
+
#define MASTER_HRT_MM_IMG 27
39
+
#define MASTER_HRT_MM_MDP 28
40
+
#define MASTER_HRT_DBGIF 29
41
+
#define MASTER_WIFI 30
42
+
#define MASTER_BT 31
43
+
#define MASTER_NETSYS 32
44
+
#endif
+93
include/dt-bindings/interconnect/qcom,msm8953.h
+93
include/dt-bindings/interconnect/qcom,msm8953.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Qualcomm MSM8953 interconnect IDs
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8953_H
7
+
#define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8953_H
8
+
9
+
/* BIMC fabric */
10
+
#define MAS_APPS_PROC 0
11
+
#define MAS_OXILI 1
12
+
#define MAS_SNOC_BIMC_0 2
13
+
#define MAS_SNOC_BIMC_2 3
14
+
#define MAS_SNOC_BIMC_1 4
15
+
#define MAS_TCU_0 5
16
+
#define SLV_EBI 6
17
+
#define SLV_BIMC_SNOC 7
18
+
19
+
/* PCNOC fabric */
20
+
#define MAS_SPDM 0
21
+
#define MAS_BLSP_1 1
22
+
#define MAS_BLSP_2 2
23
+
#define MAS_USB3 3
24
+
#define MAS_CRYPTO 4
25
+
#define MAS_SDCC_1 5
26
+
#define MAS_SDCC_2 6
27
+
#define MAS_SNOC_PCNOC 7
28
+
#define PCNOC_M_0 8
29
+
#define PCNOC_M_1 9
30
+
#define PCNOC_INT_1 10
31
+
#define PCNOC_INT_2 11
32
+
#define PCNOC_S_0 12
33
+
#define PCNOC_S_1 13
34
+
#define PCNOC_S_2 14
35
+
#define PCNOC_S_3 15
36
+
#define PCNOC_S_4 16
37
+
#define PCNOC_S_6 17
38
+
#define PCNOC_S_7 18
39
+
#define PCNOC_S_8 19
40
+
#define PCNOC_S_9 20
41
+
#define SLV_SPDM 21
42
+
#define SLV_PDM 22
43
+
#define SLV_TCSR 23
44
+
#define SLV_SNOC_CFG 24
45
+
#define SLV_TLMM 25
46
+
#define SLV_MESSAGE_RAM 26
47
+
#define SLV_BLSP_1 27
48
+
#define SLV_BLSP_2 28
49
+
#define SLV_PRNG 29
50
+
#define SLV_CAMERA_SS_CFG 30
51
+
#define SLV_DISP_SS_CFG 31
52
+
#define SLV_VENUS_CFG 32
53
+
#define SLV_GPU_CFG 33
54
+
#define SLV_SDCC_1 34
55
+
#define SLV_SDCC_2 35
56
+
#define SLV_CRYPTO_0_CFG 36
57
+
#define SLV_PMIC_ARB 37
58
+
#define SLV_USB3 38
59
+
#define SLV_IPA_CFG 39
60
+
#define SLV_TCU 40
61
+
#define SLV_PCNOC_SNOC 41
62
+
63
+
/* SNOC fabric */
64
+
#define MAS_QDSS_BAM 0
65
+
#define MAS_BIMC_SNOC 1
66
+
#define MAS_PCNOC_SNOC 2
67
+
#define MAS_IPA 3
68
+
#define MAS_QDSS_ETR 4
69
+
#define QDSS_INT 5
70
+
#define SNOC_INT_0 6
71
+
#define SNOC_INT_1 7
72
+
#define SNOC_INT_2 8
73
+
#define SLV_KPSS_AHB 9
74
+
#define SLV_WCSS 10
75
+
#define SLV_SNOC_BIMC_1 11
76
+
#define SLV_IMEM 12
77
+
#define SLV_SNOC_PCNOC 13
78
+
#define SLV_QDSS_STM 14
79
+
#define SLV_CATS_1 15
80
+
#define SLV_LPASS 16
81
+
82
+
/* SNOC-MM fabric */
83
+
#define MAS_JPEG 0
84
+
#define MAS_MDP 1
85
+
#define MAS_VENUS 2
86
+
#define MAS_VFE0 3
87
+
#define MAS_VFE1 4
88
+
#define MAS_CPP 5
89
+
#define SLV_SNOC_BIMC_0 6
90
+
#define SLV_SNOC_BIMC_2 7
91
+
#define SLV_CATS_0 8
92
+
93
+
#endif /* __DT_BINDINGS_INTERCONNECT_QCOM_MSM8953_H */