Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'x86_urgent_for_v6.8_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Borislav Petkov:
- Make sure 32-bit syscall registers are properly sign-extended
- Add detection for AMD's Zen5 generation CPUs and Intel's Clearwater
Forest CPU model number
- Make a stub function export non-GPL because it is part of the
paravirt alternatives and that can be used by non-GPL code
* tag 'x86_urgent_for_v6.8_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/CPU/AMD: Add more models to X86_FEATURE_ZEN5
x86/entry/ia32: Ensure s32 is sign extended to s64
x86/cpu: Add model number for Intel Clearwater Forest processor
x86/CPU/AMD: Add X86_FEATURE_ZEN5
x86/paravirt: Make BUG_func() usable by non-GPL modules
+50
-12
+1
-3
arch/x86/include/asm/cpufeatures.h
+1
-3
arch/x86/include/asm/cpufeatures.h
···
81
81
#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
82
82
#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
83
83
#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
84
-
85
-
/* CPU types for specific tunings: */
86
84
#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
87
-
/* FREE, was #define X86_FEATURE_K7 ( 3*32+ 5) "" Athlon */
85
+
#define X86_FEATURE_ZEN5 ( 3*32+ 5) /* "" CPU based on Zen5 microarchitecture */
88
86
#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
89
87
#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
90
88
#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
+2
arch/x86/include/asm/intel-family.h
+2
arch/x86/include/asm/intel-family.h
···
162
162
#define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */
163
163
#define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */
164
164
165
+
#define INTEL_FAM6_ATOM_DARKMONT_X 0xDD /* Clearwater Forest */
166
+
165
167
/* Xeon Phi */
166
168
167
169
#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
+21
-4
arch/x86/include/asm/syscall_wrapper.h
+21
-4
arch/x86/include/asm/syscall_wrapper.h
···
58
58
,,regs->di,,regs->si,,regs->dx \
59
59
,,regs->r10,,regs->r8,,regs->r9) \
60
60
61
+
62
+
/* SYSCALL_PT_ARGS is Adapted from s390x */
63
+
#define SYSCALL_PT_ARG6(m, t1, t2, t3, t4, t5, t6) \
64
+
SYSCALL_PT_ARG5(m, t1, t2, t3, t4, t5), m(t6, (regs->bp))
65
+
#define SYSCALL_PT_ARG5(m, t1, t2, t3, t4, t5) \
66
+
SYSCALL_PT_ARG4(m, t1, t2, t3, t4), m(t5, (regs->di))
67
+
#define SYSCALL_PT_ARG4(m, t1, t2, t3, t4) \
68
+
SYSCALL_PT_ARG3(m, t1, t2, t3), m(t4, (regs->si))
69
+
#define SYSCALL_PT_ARG3(m, t1, t2, t3) \
70
+
SYSCALL_PT_ARG2(m, t1, t2), m(t3, (regs->dx))
71
+
#define SYSCALL_PT_ARG2(m, t1, t2) \
72
+
SYSCALL_PT_ARG1(m, t1), m(t2, (regs->cx))
73
+
#define SYSCALL_PT_ARG1(m, t1) m(t1, (regs->bx))
74
+
#define SYSCALL_PT_ARGS(x, ...) SYSCALL_PT_ARG##x(__VA_ARGS__)
75
+
76
+
#define __SC_COMPAT_CAST(t, a) \
77
+
(__typeof(__builtin_choose_expr(__TYPE_IS_L(t), 0, 0U))) \
78
+
(unsigned int)a
79
+
61
80
/* Mapping of registers to parameters for syscalls on i386 */
62
81
#define SC_IA32_REGS_TO_ARGS(x, ...) \
63
-
__MAP(x,__SC_ARGS \
64
-
,,(unsigned int)regs->bx,,(unsigned int)regs->cx \
65
-
,,(unsigned int)regs->dx,,(unsigned int)regs->si \
66
-
,,(unsigned int)regs->di,,(unsigned int)regs->bp)
82
+
SYSCALL_PT_ARGS(x, __SC_COMPAT_CAST, \
83
+
__MAP(x, __SC_TYPE, __VA_ARGS__)) \
67
84
68
85
#define __SYS_STUB0(abi, name) \
69
86
long __##abi##_##name(const struct pt_regs *regs); \
+1
-1
arch/x86/kernel/alternative.c
+1
-1
arch/x86/kernel/alternative.c
+24
-4
arch/x86/kernel/cpu/amd.c
+24
-4
arch/x86/kernel/cpu/amd.c
···
538
538
539
539
/* Figure out Zen generations: */
540
540
switch (c->x86) {
541
-
case 0x17: {
541
+
case 0x17:
542
542
switch (c->x86_model) {
543
543
case 0x00 ... 0x2f:
544
544
case 0x50 ... 0x5f:
···
554
554
goto warn;
555
555
}
556
556
break;
557
-
}
558
-
case 0x19: {
557
+
558
+
case 0x19:
559
559
switch (c->x86_model) {
560
560
case 0x00 ... 0x0f:
561
561
case 0x20 ... 0x5f:
···
569
569
goto warn;
570
570
}
571
571
break;
572
-
}
572
+
573
+
case 0x1a:
574
+
switch (c->x86_model) {
575
+
case 0x00 ... 0x0f:
576
+
case 0x20 ... 0x2f:
577
+
case 0x40 ... 0x4f:
578
+
case 0x70 ... 0x7f:
579
+
setup_force_cpu_cap(X86_FEATURE_ZEN5);
580
+
break;
581
+
default:
582
+
goto warn;
583
+
}
584
+
break;
585
+
573
586
default:
574
587
break;
575
588
}
···
1052
1039
msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
1053
1040
}
1054
1041
1042
+
static void init_amd_zen5(struct cpuinfo_x86 *c)
1043
+
{
1044
+
init_amd_zen_common();
1045
+
}
1046
+
1055
1047
static void init_amd(struct cpuinfo_x86 *c)
1056
1048
{
1057
1049
u64 vm_cr;
···
1102
1084
init_amd_zen3(c);
1103
1085
else if (boot_cpu_has(X86_FEATURE_ZEN4))
1104
1086
init_amd_zen4(c);
1087
+
else if (boot_cpu_has(X86_FEATURE_ZEN5))
1088
+
init_amd_zen5(c);
1105
1089
1106
1090
/*
1107
1091
* Enable workaround for FXSAVE leak on CPUs
+1
include/linux/syscalls.h
+1
include/linux/syscalls.h
···
128
128
#define __TYPE_IS_LL(t) (__TYPE_AS(t, 0LL) || __TYPE_AS(t, 0ULL))
129
129
#define __SC_LONG(t, a) __typeof(__builtin_choose_expr(__TYPE_IS_LL(t), 0LL, 0L)) a
130
130
#define __SC_CAST(t, a) (__force t) a
131
+
#define __SC_TYPE(t, a) t
131
132
#define __SC_ARGS(t, a) a
132
133
#define __SC_TEST(t, a) (void)BUILD_BUG_ON_ZERO(!__TYPE_IS_LL(t) && sizeof(t) > sizeof(long))
133
134