Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
KVM: arm64: gic-v5: Support GICv5 FGTs & FGUs
Extend the existing FGT/FGU infrastructure to include the GICv5 trap
registers (ICH_HFGRTR_EL2, ICH_HFGWTR_EL2, ICH_HFGITR_EL2). This
involves mapping the trap registers and their bits to the
corresponding feature that introduces them (FEAT_GCIE for all, in this
case), and mapping each trap bit to the system register/instruction
controlled by it.
As of this change, none of the GICv5 instructions or register accesses
are being trapped.
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260319154937.3619520-14-sascha.bischoff@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>
authored by
Sascha Bischoff
and committed by
Marc Zyngier
9d6d9514
a258a383
+215
-7
+19
arch/arm64/include/asm/kvm_host.h
+19
arch/arm64/include/asm/kvm_host.h
···
287
287
HDFGRTR2_GROUP,
288
288
HDFGWTR2_GROUP = HDFGRTR2_GROUP,
289
289
HFGITR2_GROUP,
290
+
ICH_HFGRTR_GROUP,
291
+
ICH_HFGWTR_GROUP = ICH_HFGRTR_GROUP,
292
+
ICH_HFGITR_GROUP,
290
293
291
294
/* Must be last */
292
295
__NR_FGT_GROUP_IDS__
···
623
620
VNCR(ICH_HCR_EL2),
624
621
VNCR(ICH_VMCR_EL2),
625
622
623
+
VNCR(ICH_HFGRTR_EL2),
624
+
VNCR(ICH_HFGWTR_EL2),
625
+
VNCR(ICH_HFGITR_EL2),
626
+
626
627
NR_SYS_REGS /* Nothing after this line! */
627
628
};
628
629
···
682
675
extern struct fgt_masks hfgitr2_masks;
683
676
extern struct fgt_masks hdfgrtr2_masks;
684
677
extern struct fgt_masks hdfgwtr2_masks;
678
+
extern struct fgt_masks ich_hfgrtr_masks;
679
+
extern struct fgt_masks ich_hfgwtr_masks;
680
+
extern struct fgt_masks ich_hfgitr_masks;
685
681
686
682
extern struct fgt_masks kvm_nvhe_sym(hfgrtr_masks);
687
683
extern struct fgt_masks kvm_nvhe_sym(hfgwtr_masks);
···
697
687
extern struct fgt_masks kvm_nvhe_sym(hfgitr2_masks);
698
688
extern struct fgt_masks kvm_nvhe_sym(hdfgrtr2_masks);
699
689
extern struct fgt_masks kvm_nvhe_sym(hdfgwtr2_masks);
690
+
extern struct fgt_masks kvm_nvhe_sym(ich_hfgrtr_masks);
691
+
extern struct fgt_masks kvm_nvhe_sym(ich_hfgwtr_masks);
692
+
extern struct fgt_masks kvm_nvhe_sym(ich_hfgitr_masks);
700
693
701
694
struct kvm_cpu_context {
702
695
struct user_pt_regs regs; /* sp = sp_el0 */
···
1672
1659
case HDFGRTR2_EL2:
1673
1660
case HDFGWTR2_EL2:
1674
1661
return HDFGRTR2_GROUP;
1662
+
case ICH_HFGRTR_EL2:
1663
+
case ICH_HFGWTR_EL2:
1664
+
return ICH_HFGRTR_GROUP;
1665
+
case ICH_HFGITR_EL2:
1666
+
return ICH_HFGITR_GROUP;
1675
1667
default:
1676
1668
BUILD_BUG_ON(1);
1677
1669
}
···
1691
1673
case HDFGWTR_EL2: \
1692
1674
case HFGWTR2_EL2: \
1693
1675
case HDFGWTR2_EL2: \
1676
+
case ICH_HFGWTR_EL2: \
1694
1677
p = &(vcpu)->arch.fgt[id].w; \
1695
1678
break; \
1696
1679
default: \
+3
arch/arm64/include/asm/vncr_mapping.h
+3
arch/arm64/include/asm/vncr_mapping.h
+3
arch/arm64/kvm/arm.c
+3
arch/arm64/kvm/arm.c
···
2529
2529
kvm_nvhe_sym(hfgitr2_masks) = hfgitr2_masks;
2530
2530
kvm_nvhe_sym(hdfgrtr2_masks)= hdfgrtr2_masks;
2531
2531
kvm_nvhe_sym(hdfgwtr2_masks)= hdfgwtr2_masks;
2532
+
kvm_nvhe_sym(ich_hfgrtr_masks) = ich_hfgrtr_masks;
2533
+
kvm_nvhe_sym(ich_hfgwtr_masks) = ich_hfgwtr_masks;
2534
+
kvm_nvhe_sym(ich_hfgitr_masks) = ich_hfgitr_masks;
2532
2535
2533
2536
/*
2534
2537
* Flush entire BSS since part of its data containing init symbols is read
+90
-7
arch/arm64/kvm/config.c
+90
-7
arch/arm64/kvm/config.c
···
225
225
#define FEAT_MTPMU ID_AA64DFR0_EL1, MTPMU, IMP
226
226
#define FEAT_HCX ID_AA64MMFR1_EL1, HCX, IMP
227
227
#define FEAT_S2PIE ID_AA64MMFR3_EL1, S2PIE, IMP
228
+
#define FEAT_GCIE ID_AA64PFR2_EL1, GCIE, IMP
228
229
229
230
static bool not_feat_aa64el3(struct kvm *kvm)
230
231
{
···
1278
1277
static const DECLARE_FEAT_MAP(vtcr_el2_desc, VTCR_EL2,
1279
1278
vtcr_el2_feat_map, FEAT_AA64EL2);
1280
1279
1280
+
static const struct reg_bits_to_feat_map ich_hfgrtr_feat_map[] = {
1281
+
NEEDS_FEAT(ICH_HFGRTR_EL2_ICC_APR_EL1 |
1282
+
ICH_HFGRTR_EL2_ICC_IDRn_EL1 |
1283
+
ICH_HFGRTR_EL2_ICC_CR0_EL1 |
1284
+
ICH_HFGRTR_EL2_ICC_HPPIR_EL1 |
1285
+
ICH_HFGRTR_EL2_ICC_PCR_EL1 |
1286
+
ICH_HFGRTR_EL2_ICC_ICSR_EL1 |
1287
+
ICH_HFGRTR_EL2_ICC_IAFFIDR_EL1 |
1288
+
ICH_HFGRTR_EL2_ICC_PPI_HMRn_EL1 |
1289
+
ICH_HFGRTR_EL2_ICC_PPI_ENABLERn_EL1 |
1290
+
ICH_HFGRTR_EL2_ICC_PPI_PENDRn_EL1 |
1291
+
ICH_HFGRTR_EL2_ICC_PPI_PRIORITYRn_EL1 |
1292
+
ICH_HFGRTR_EL2_ICC_PPI_ACTIVERn_EL1,
1293
+
FEAT_GCIE),
1294
+
};
1295
+
1296
+
static const DECLARE_FEAT_MAP_FGT(ich_hfgrtr_desc, ich_hfgrtr_masks,
1297
+
ich_hfgrtr_feat_map, FEAT_GCIE);
1298
+
1299
+
static const struct reg_bits_to_feat_map ich_hfgwtr_feat_map[] = {
1300
+
NEEDS_FEAT(ICH_HFGWTR_EL2_ICC_APR_EL1 |
1301
+
ICH_HFGWTR_EL2_ICC_CR0_EL1 |
1302
+
ICH_HFGWTR_EL2_ICC_PCR_EL1 |
1303
+
ICH_HFGWTR_EL2_ICC_ICSR_EL1 |
1304
+
ICH_HFGWTR_EL2_ICC_PPI_ENABLERn_EL1 |
1305
+
ICH_HFGWTR_EL2_ICC_PPI_PENDRn_EL1 |
1306
+
ICH_HFGWTR_EL2_ICC_PPI_PRIORITYRn_EL1 |
1307
+
ICH_HFGWTR_EL2_ICC_PPI_ACTIVERn_EL1,
1308
+
FEAT_GCIE),
1309
+
};
1310
+
1311
+
static const DECLARE_FEAT_MAP_FGT(ich_hfgwtr_desc, ich_hfgwtr_masks,
1312
+
ich_hfgwtr_feat_map, FEAT_GCIE);
1313
+
1314
+
static const struct reg_bits_to_feat_map ich_hfgitr_feat_map[] = {
1315
+
NEEDS_FEAT(ICH_HFGITR_EL2_GICCDEN |
1316
+
ICH_HFGITR_EL2_GICCDDIS |
1317
+
ICH_HFGITR_EL2_GICCDPRI |
1318
+
ICH_HFGITR_EL2_GICCDAFF |
1319
+
ICH_HFGITR_EL2_GICCDPEND |
1320
+
ICH_HFGITR_EL2_GICCDRCFG |
1321
+
ICH_HFGITR_EL2_GICCDHM |
1322
+
ICH_HFGITR_EL2_GICCDEOI |
1323
+
ICH_HFGITR_EL2_GICCDDI |
1324
+
ICH_HFGITR_EL2_GICRCDIA |
1325
+
ICH_HFGITR_EL2_GICRCDNMIA,
1326
+
FEAT_GCIE),
1327
+
};
1328
+
1329
+
static const DECLARE_FEAT_MAP_FGT(ich_hfgitr_desc, ich_hfgitr_masks,
1330
+
ich_hfgitr_feat_map, FEAT_GCIE);
1331
+
1281
1332
static void __init check_feat_map(const struct reg_bits_to_feat_map *map,
1282
1333
int map_size, u64 resx, const char *str)
1283
1334
{
···
1381
1328
check_reg_desc(&sctlr_el2_desc);
1382
1329
check_reg_desc(&mdcr_el2_desc);
1383
1330
check_reg_desc(&vtcr_el2_desc);
1331
+
check_reg_desc(&ich_hfgrtr_desc);
1332
+
check_reg_desc(&ich_hfgwtr_desc);
1333
+
check_reg_desc(&ich_hfgitr_desc);
1384
1334
}
1385
1335
1386
1336
static bool idreg_feat_match(struct kvm *kvm, const struct reg_bits_to_feat_map *map)
···
1516
1460
val |= compute_fgu_bits(kvm, &hdfgrtr2_desc);
1517
1461
val |= compute_fgu_bits(kvm, &hdfgwtr2_desc);
1518
1462
break;
1463
+
case ICH_HFGRTR_GROUP:
1464
+
val |= compute_fgu_bits(kvm, &ich_hfgrtr_desc);
1465
+
val |= compute_fgu_bits(kvm, &ich_hfgwtr_desc);
1466
+
break;
1467
+
case ICH_HFGITR_GROUP:
1468
+
val |= compute_fgu_bits(kvm, &ich_hfgitr_desc);
1469
+
break;
1519
1470
default:
1520
1471
BUG();
1521
1472
}
···
1594
1531
case VTCR_EL2:
1595
1532
resx = compute_reg_resx_bits(kvm, &vtcr_el2_desc, 0, 0);
1596
1533
break;
1534
+
case ICH_HFGRTR_EL2:
1535
+
resx = compute_reg_resx_bits(kvm, &ich_hfgrtr_desc, 0, 0);
1536
+
break;
1537
+
case ICH_HFGWTR_EL2:
1538
+
resx = compute_reg_resx_bits(kvm, &ich_hfgwtr_desc, 0, 0);
1539
+
break;
1540
+
case ICH_HFGITR_EL2:
1541
+
resx = compute_reg_resx_bits(kvm, &ich_hfgitr_desc, 0, 0);
1542
+
break;
1597
1543
default:
1598
1544
WARN_ON_ONCE(1);
1599
1545
resx = (typeof(resx)){};
···
1637
1565
return &hdfgrtr2_masks;
1638
1566
case HDFGWTR2_EL2:
1639
1567
return &hdfgwtr2_masks;
1568
+
case ICH_HFGRTR_EL2:
1569
+
return &ich_hfgrtr_masks;
1570
+
case ICH_HFGWTR_EL2:
1571
+
return &ich_hfgwtr_masks;
1572
+
case ICH_HFGITR_EL2:
1573
+
return &ich_hfgitr_masks;
1640
1574
default:
1641
1575
BUILD_BUG_ON(1);
1642
1576
}
···
1696
1618
__compute_hdfgwtr(vcpu);
1697
1619
__compute_fgt(vcpu, HAFGRTR_EL2);
1698
1620
1699
-
if (!cpus_have_final_cap(ARM64_HAS_FGT2))
1700
-
return;
1621
+
if (cpus_have_final_cap(ARM64_HAS_FGT2)) {
1622
+
__compute_fgt(vcpu, HFGRTR2_EL2);
1623
+
__compute_fgt(vcpu, HFGWTR2_EL2);
1624
+
__compute_fgt(vcpu, HFGITR2_EL2);
1625
+
__compute_fgt(vcpu, HDFGRTR2_EL2);
1626
+
__compute_fgt(vcpu, HDFGWTR2_EL2);
1627
+
}
1701
1628
1702
-
__compute_fgt(vcpu, HFGRTR2_EL2);
1703
-
__compute_fgt(vcpu, HFGWTR2_EL2);
1704
-
__compute_fgt(vcpu, HFGITR2_EL2);
1705
-
__compute_fgt(vcpu, HDFGRTR2_EL2);
1706
-
__compute_fgt(vcpu, HDFGWTR2_EL2);
1629
+
if (cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF)) {
1630
+
__compute_fgt(vcpu, ICH_HFGRTR_EL2);
1631
+
__compute_fgt(vcpu, ICH_HFGWTR_EL2);
1632
+
__compute_fgt(vcpu, ICH_HFGITR_EL2);
1633
+
}
1707
1634
}
+68
arch/arm64/kvm/emulate-nested.c
+68
arch/arm64/kvm/emulate-nested.c
···
2053
2053
SR_FGT(SYS_AMEVCNTR0_EL0(2), HAFGRTR, AMEVCNTR02_EL0, 1),
2054
2054
SR_FGT(SYS_AMEVCNTR0_EL0(1), HAFGRTR, AMEVCNTR01_EL0, 1),
2055
2055
SR_FGT(SYS_AMEVCNTR0_EL0(0), HAFGRTR, AMEVCNTR00_EL0, 1),
2056
+
2057
+
/*
2058
+
* ICH_HFGRTR_EL2 & ICH_HFGWTR_EL2
2059
+
*/
2060
+
SR_FGT(SYS_ICC_APR_EL1, ICH_HFGRTR, ICC_APR_EL1, 0),
2061
+
SR_FGT(SYS_ICC_IDR0_EL1, ICH_HFGRTR, ICC_IDRn_EL1, 0),
2062
+
SR_FGT(SYS_ICC_CR0_EL1, ICH_HFGRTR, ICC_CR0_EL1, 0),
2063
+
SR_FGT(SYS_ICC_HPPIR_EL1, ICH_HFGRTR, ICC_HPPIR_EL1, 0),
2064
+
SR_FGT(SYS_ICC_PCR_EL1, ICH_HFGRTR, ICC_PCR_EL1, 0),
2065
+
SR_FGT(SYS_ICC_ICSR_EL1, ICH_HFGRTR, ICC_ICSR_EL1, 0),
2066
+
SR_FGT(SYS_ICC_IAFFIDR_EL1, ICH_HFGRTR, ICC_IAFFIDR_EL1, 0),
2067
+
SR_FGT(SYS_ICC_PPI_HMR0_EL1, ICH_HFGRTR, ICC_PPI_HMRn_EL1, 0),
2068
+
SR_FGT(SYS_ICC_PPI_HMR1_EL1, ICH_HFGRTR, ICC_PPI_HMRn_EL1, 0),
2069
+
SR_FGT(SYS_ICC_PPI_ENABLER0_EL1, ICH_HFGRTR, ICC_PPI_ENABLERn_EL1, 0),
2070
+
SR_FGT(SYS_ICC_PPI_ENABLER1_EL1, ICH_HFGRTR, ICC_PPI_ENABLERn_EL1, 0),
2071
+
SR_FGT(SYS_ICC_PPI_CPENDR0_EL1, ICH_HFGRTR, ICC_PPI_PENDRn_EL1, 0),
2072
+
SR_FGT(SYS_ICC_PPI_CPENDR1_EL1, ICH_HFGRTR, ICC_PPI_PENDRn_EL1, 0),
2073
+
SR_FGT(SYS_ICC_PPI_SPENDR0_EL1, ICH_HFGRTR, ICC_PPI_PENDRn_EL1, 0),
2074
+
SR_FGT(SYS_ICC_PPI_SPENDR1_EL1, ICH_HFGRTR, ICC_PPI_PENDRn_EL1, 0),
2075
+
SR_FGT(SYS_ICC_PPI_PRIORITYR0_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2076
+
SR_FGT(SYS_ICC_PPI_PRIORITYR1_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2077
+
SR_FGT(SYS_ICC_PPI_PRIORITYR2_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2078
+
SR_FGT(SYS_ICC_PPI_PRIORITYR3_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2079
+
SR_FGT(SYS_ICC_PPI_PRIORITYR4_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2080
+
SR_FGT(SYS_ICC_PPI_PRIORITYR5_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2081
+
SR_FGT(SYS_ICC_PPI_PRIORITYR6_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2082
+
SR_FGT(SYS_ICC_PPI_PRIORITYR7_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2083
+
SR_FGT(SYS_ICC_PPI_PRIORITYR8_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2084
+
SR_FGT(SYS_ICC_PPI_PRIORITYR9_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2085
+
SR_FGT(SYS_ICC_PPI_PRIORITYR10_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2086
+
SR_FGT(SYS_ICC_PPI_PRIORITYR11_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2087
+
SR_FGT(SYS_ICC_PPI_PRIORITYR12_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2088
+
SR_FGT(SYS_ICC_PPI_PRIORITYR13_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2089
+
SR_FGT(SYS_ICC_PPI_PRIORITYR14_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2090
+
SR_FGT(SYS_ICC_PPI_PRIORITYR15_EL1, ICH_HFGRTR, ICC_PPI_PRIORITYRn_EL1, 0),
2091
+
SR_FGT(SYS_ICC_PPI_CACTIVER0_EL1, ICH_HFGRTR, ICC_PPI_ACTIVERn_EL1, 0),
2092
+
SR_FGT(SYS_ICC_PPI_CACTIVER1_EL1, ICH_HFGRTR, ICC_PPI_ACTIVERn_EL1, 0),
2093
+
SR_FGT(SYS_ICC_PPI_SACTIVER0_EL1, ICH_HFGRTR, ICC_PPI_ACTIVERn_EL1, 0),
2094
+
SR_FGT(SYS_ICC_PPI_SACTIVER1_EL1, ICH_HFGRTR, ICC_PPI_ACTIVERn_EL1, 0),
2095
+
2096
+
/*
2097
+
* ICH_HFGITR_EL2
2098
+
*/
2099
+
SR_FGT(GICV5_OP_GIC_CDEN, ICH_HFGITR, GICCDEN, 0),
2100
+
SR_FGT(GICV5_OP_GIC_CDDIS, ICH_HFGITR, GICCDDIS, 0),
2101
+
SR_FGT(GICV5_OP_GIC_CDPRI, ICH_HFGITR, GICCDPRI, 0),
2102
+
SR_FGT(GICV5_OP_GIC_CDAFF, ICH_HFGITR, GICCDAFF, 0),
2103
+
SR_FGT(GICV5_OP_GIC_CDPEND, ICH_HFGITR, GICCDPEND, 0),
2104
+
SR_FGT(GICV5_OP_GIC_CDRCFG, ICH_HFGITR, GICCDRCFG, 0),
2105
+
SR_FGT(GICV5_OP_GIC_CDHM, ICH_HFGITR, GICCDHM, 0),
2106
+
SR_FGT(GICV5_OP_GIC_CDEOI, ICH_HFGITR, GICCDEOI, 0),
2107
+
SR_FGT(GICV5_OP_GIC_CDDI, ICH_HFGITR, GICCDDI, 0),
2108
+
SR_FGT(GICV5_OP_GICR_CDIA, ICH_HFGITR, GICRCDIA, 0),
2109
+
SR_FGT(GICV5_OP_GICR_CDNMIA, ICH_HFGITR, GICRCDNMIA, 0),
2056
2110
};
2057
2111
2058
2112
/*
···
2181
2127
FGT_MASKS(hfgitr2_masks, HFGITR2_EL2);
2182
2128
FGT_MASKS(hdfgrtr2_masks, HDFGRTR2_EL2);
2183
2129
FGT_MASKS(hdfgwtr2_masks, HDFGWTR2_EL2);
2130
+
FGT_MASKS(ich_hfgrtr_masks, ICH_HFGRTR_EL2);
2131
+
FGT_MASKS(ich_hfgwtr_masks, ICH_HFGWTR_EL2);
2132
+
FGT_MASKS(ich_hfgitr_masks, ICH_HFGITR_EL2);
2184
2133
2185
2134
static __init bool aggregate_fgt(union trap_config tc)
2186
2135
{
···
2217
2160
break;
2218
2161
case HFGITR2_GROUP:
2219
2162
rmasks = &hfgitr2_masks;
2163
+
wmasks = NULL;
2164
+
break;
2165
+
case ICH_HFGRTR_GROUP:
2166
+
rmasks = &ich_hfgrtr_masks;
2167
+
wmasks = &ich_hfgwtr_masks;
2168
+
break;
2169
+
case ICH_HFGITR_GROUP:
2170
+
rmasks = &ich_hfgitr_masks;
2220
2171
wmasks = NULL;
2221
2172
break;
2222
2173
}
···
2297
2232
&hfgitr2_masks,
2298
2233
&hdfgrtr2_masks,
2299
2234
&hdfgwtr2_masks,
2235
+
&ich_hfgrtr_masks,
2236
+
&ich_hfgwtr_masks,
2237
+
&ich_hfgitr_masks,
2300
2238
};
2301
2239
int err = 0;
2302
2240
+27
arch/arm64/kvm/hyp/include/hyp/switch.h
+27
arch/arm64/kvm/hyp/include/hyp/switch.h
···
233
233
__activate_fgt(hctxt, vcpu, HDFGWTR2_EL2);
234
234
}
235
235
236
+
static inline void __activate_traps_ich_hfgxtr(struct kvm_vcpu *vcpu)
237
+
{
238
+
struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
239
+
240
+
if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF))
241
+
return;
242
+
243
+
__activate_fgt(hctxt, vcpu, ICH_HFGRTR_EL2);
244
+
__activate_fgt(hctxt, vcpu, ICH_HFGWTR_EL2);
245
+
__activate_fgt(hctxt, vcpu, ICH_HFGITR_EL2);
246
+
}
247
+
236
248
#define __deactivate_fgt(htcxt, vcpu, reg) \
237
249
do { \
238
250
write_sysreg_s(ctxt_sys_reg(hctxt, reg), \
···
275
263
__deactivate_fgt(hctxt, vcpu, HFGITR2_EL2);
276
264
__deactivate_fgt(hctxt, vcpu, HDFGRTR2_EL2);
277
265
__deactivate_fgt(hctxt, vcpu, HDFGWTR2_EL2);
266
+
}
267
+
268
+
static inline void __deactivate_traps_ich_hfgxtr(struct kvm_vcpu *vcpu)
269
+
{
270
+
struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
271
+
272
+
if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF))
273
+
return;
274
+
275
+
__deactivate_fgt(hctxt, vcpu, ICH_HFGRTR_EL2);
276
+
__deactivate_fgt(hctxt, vcpu, ICH_HFGWTR_EL2);
277
+
__deactivate_fgt(hctxt, vcpu, ICH_HFGITR_EL2);
278
+
278
279
}
279
280
280
281
static inline void __activate_traps_mpam(struct kvm_vcpu *vcpu)
···
353
328
}
354
329
355
330
__activate_traps_hfgxtr(vcpu);
331
+
__activate_traps_ich_hfgxtr(vcpu);
356
332
__activate_traps_mpam(vcpu);
357
333
}
358
334
···
371
345
write_sysreg_s(ctxt_sys_reg(hctxt, HCRX_EL2), SYS_HCRX_EL2);
372
346
373
347
__deactivate_traps_hfgxtr(vcpu);
348
+
__deactivate_traps_ich_hfgxtr(vcpu);
374
349
__deactivate_traps_mpam();
375
350
}
376
351
+3
arch/arm64/kvm/hyp/nvhe/switch.c
+3
arch/arm64/kvm/hyp/nvhe/switch.c
···
44
44
struct fgt_masks hfgitr2_masks;
45
45
struct fgt_masks hdfgrtr2_masks;
46
46
struct fgt_masks hdfgwtr2_masks;
47
+
struct fgt_masks ich_hfgrtr_masks;
48
+
struct fgt_masks ich_hfgwtr_masks;
49
+
struct fgt_masks ich_hfgitr_masks;
47
50
48
51
extern void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc);
49
52
+2
arch/arm64/kvm/sys_regs.c
+2
arch/arm64/kvm/sys_regs.c
···
5661
5661
compute_fgu(kvm, HFGRTR2_GROUP);
5662
5662
compute_fgu(kvm, HFGITR2_GROUP);
5663
5663
compute_fgu(kvm, HDFGRTR2_GROUP);
5664
+
compute_fgu(kvm, ICH_HFGRTR_GROUP);
5665
+
compute_fgu(kvm, ICH_HFGITR_GROUP);
5664
5666
5665
5667
set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags);
5666
5668
out: