Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: net: Correct indentation and style in DTS example
DTS example in the bindings should be indented with 2- or 4-spaces and
aligned with opening '- |', so correct any differences like 3-spaces or
mixtures 2- and 4-spaces in one binding.
No functional changes here, but saves some comments during reviews of
new patches built on existing code.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> # for net/can
Reviewed-by: Roger Quadros <rogerq@kernel.org> # for ti,k3-am654-*
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> # net/brcm,*
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://patch.msgid.link/20250107125613.211478-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
authored by
Krzysztof Kozlowski
and committed by
Paolo Abeni
9d8c354a
33d97a07
+150
-151
+7
-7
Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
+7
-7
Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
···
166
166
examples:
167
167
- |
168
168
ethmac: ethernet@c9410000 {
169
-
compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
170
-
reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
171
-
interrupts = <8>;
172
-
interrupt-names = "macirq";
173
-
clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
174
-
clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
175
-
phy-mode = "rgmii";
169
+
compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
170
+
reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
171
+
interrupts = <8>;
172
+
interrupt-names = "macirq";
173
+
clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
174
+
clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
175
+
phy-mode = "rgmii";
176
176
};
+2
-2
Documentation/devicetree/bindings/net/asix,ax88178.yaml
+2
-2
Documentation/devicetree/bindings/net/asix,ax88178.yaml
+16
-16
Documentation/devicetree/bindings/net/brcm,bcmgenet.yaml
+16
-16
Documentation/devicetree/bindings/net/brcm,bcmgenet.yaml
···
85
85
#size-cells = <1>;
86
86
87
87
mdio0: mdio@e14 {
88
-
compatible = "brcm,genet-mdio-v4";
89
-
#address-cells = <1>;
90
-
#size-cells = <0>;
91
-
reg = <0xe14 0x8>;
88
+
compatible = "brcm,genet-mdio-v4";
89
+
#address-cells = <1>;
90
+
#size-cells = <0>;
91
+
reg = <0xe14 0x8>;
92
92
93
-
phy1: ethernet-phy@1 {
93
+
phy1: ethernet-phy@1 {
94
94
max-speed = <1000>;
95
95
reg = <1>;
96
96
compatible = "ethernet-phy-ieee802.3-c22";
97
-
};
97
+
};
98
98
};
99
99
};
100
100
···
110
110
interrupts = <0x0 0x16 0x0>, <0x0 0x17 0x0>;
111
111
112
112
mdio1: mdio@e14 {
113
-
compatible = "brcm,genet-mdio-v4";
114
-
#address-cells = <1>;
115
-
#size-cells = <0>;
116
-
reg = <0xe14 0x8>;
113
+
compatible = "brcm,genet-mdio-v4";
114
+
#address-cells = <1>;
115
+
#size-cells = <0>;
116
+
reg = <0xe14 0x8>;
117
117
};
118
118
};
119
119
···
129
129
interrupts = <0x0 0x18 0x0>, <0x0 0x19 0x0>;
130
130
131
131
mdio2: mdio@e14 {
132
-
compatible = "brcm,genet-mdio-v4";
133
-
#address-cells = <1>;
134
-
#size-cells = <0>;
135
-
reg = <0xe14 0x8>;
132
+
compatible = "brcm,genet-mdio-v4";
133
+
#address-cells = <1>;
134
+
#size-cells = <0>;
135
+
reg = <0xe14 0x8>;
136
136
137
-
phy0: ethernet-phy@0 {
137
+
phy0: ethernet-phy@0 {
138
138
max-speed = <1000>;
139
139
reg = <0>;
140
140
compatible = "ethernet-phy-ieee802.3-c22";
141
-
};
141
+
};
142
142
};
143
143
};
+23
-23
Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.yaml
+23
-23
Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.yaml
···
38
38
39
39
examples:
40
40
- |
41
-
mdio_mux_iproc: mdio-mux@66020000 {
41
+
mdio-mux@66020000 {
42
42
compatible = "brcm,mdio-mux-iproc";
43
43
reg = <0x66020000 0x250>;
44
44
#address-cells = <1>;
45
45
#size-cells = <0>;
46
46
47
47
mdio@0 {
48
-
reg = <0x0>;
49
-
#address-cells = <1>;
50
-
#size-cells = <0>;
48
+
reg = <0x0>;
49
+
#address-cells = <1>;
50
+
#size-cells = <0>;
51
51
52
-
pci_phy0: pci-phy@0 {
53
-
compatible = "brcm,ns2-pcie-phy";
54
-
reg = <0x0>;
55
-
#phy-cells = <0>;
56
-
};
52
+
pci-phy@0 {
53
+
compatible = "brcm,ns2-pcie-phy";
54
+
reg = <0x0>;
55
+
#phy-cells = <0>;
56
+
};
57
57
};
58
58
59
59
mdio@7 {
60
-
reg = <0x7>;
61
-
#address-cells = <1>;
62
-
#size-cells = <0>;
60
+
reg = <0x7>;
61
+
#address-cells = <1>;
62
+
#size-cells = <0>;
63
63
64
-
pci_phy1: pci-phy@0 {
65
-
compatible = "brcm,ns2-pcie-phy";
66
-
reg = <0x0>;
67
-
#phy-cells = <0>;
68
-
};
64
+
pci-phy@0 {
65
+
compatible = "brcm,ns2-pcie-phy";
66
+
reg = <0x0>;
67
+
#phy-cells = <0>;
68
+
};
69
69
};
70
70
71
71
mdio@10 {
72
-
reg = <0x10>;
73
-
#address-cells = <1>;
74
-
#size-cells = <0>;
72
+
reg = <0x10>;
73
+
#address-cells = <1>;
74
+
#size-cells = <0>;
75
75
76
-
gphy0: eth-phy@10 {
77
-
reg = <0x10>;
78
-
};
76
+
eth-phy@10 {
77
+
reg = <0x10>;
78
+
};
79
79
};
80
80
};
+5
-5
Documentation/devicetree/bindings/net/can/bosch,c_can.yaml
+5
-5
Documentation/devicetree/bindings/net/can/bosch,c_can.yaml
···
99
99
#include <dt-bindings/reset/altr,rst-mgr.h>
100
100
101
101
can@ffc00000 {
102
-
compatible = "bosch,d_can";
103
-
reg = <0xffc00000 0x1000>;
104
-
interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
105
-
clocks = <&can0_clk>;
106
-
resets = <&rst CAN0_RESET>;
102
+
compatible = "bosch,d_can";
103
+
reg = <0xffc00000 0x1000>;
104
+
interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
105
+
clocks = <&can0_clk>;
106
+
resets = <&rst CAN0_RESET>;
107
107
};
108
108
- |
109
109
can@0 {
+9
-9
Documentation/devicetree/bindings/net/can/microchip,mcp2510.yaml
+9
-9
Documentation/devicetree/bindings/net/can/microchip,mcp2510.yaml
···
56
56
#size-cells = <0>;
57
57
58
58
can@1 {
59
-
compatible = "microchip,mcp2515";
60
-
reg = <1>;
61
-
clocks = <&clk24m>;
62
-
interrupt-parent = <&gpio4>;
63
-
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
64
-
vdd-supply = <®5v0>;
65
-
xceiver-supply = <®5v0>;
66
-
gpio-controller;
67
-
#gpio-cells = <2>;
59
+
compatible = "microchip,mcp2515";
60
+
reg = <1>;
61
+
clocks = <&clk24m>;
62
+
interrupt-parent = <&gpio4>;
63
+
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
64
+
vdd-supply = <®5v0>;
65
+
xceiver-supply = <®5v0>;
66
+
gpio-controller;
67
+
#gpio-cells = <2>;
68
68
};
69
69
};
70
70
+47
-47
Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+47
-47
Documentation/devicetree/bindings/net/stm32-dwmac.yaml
···
154
154
#include <dt-bindings/interrupt-controller/arm-gic.h>
155
155
#include <dt-bindings/clock/stm32mp1-clks.h>
156
156
//Example 1
157
-
ethernet0: ethernet@5800a000 {
158
-
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
159
-
reg = <0x5800a000 0x2000>;
160
-
reg-names = "stmmaceth";
161
-
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
162
-
interrupt-names = "macirq";
163
-
clock-names = "stmmaceth",
164
-
"mac-clk-tx",
165
-
"mac-clk-rx",
166
-
"ethstp",
167
-
"eth-ck";
168
-
clocks = <&rcc ETHMAC>,
169
-
<&rcc ETHTX>,
170
-
<&rcc ETHRX>,
171
-
<&rcc ETHSTP>,
172
-
<&rcc ETHCK_K>;
173
-
st,syscon = <&syscfg 0x4>;
174
-
snps,pbl = <2>;
175
-
snps,axi-config = <&stmmac_axi_config_0>;
176
-
snps,tso;
177
-
phy-mode = "rgmii";
178
-
};
157
+
ethernet0: ethernet@5800a000 {
158
+
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
159
+
reg = <0x5800a000 0x2000>;
160
+
reg-names = "stmmaceth";
161
+
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
162
+
interrupt-names = "macirq";
163
+
clock-names = "stmmaceth",
164
+
"mac-clk-tx",
165
+
"mac-clk-rx",
166
+
"ethstp",
167
+
"eth-ck";
168
+
clocks = <&rcc ETHMAC>,
169
+
<&rcc ETHTX>,
170
+
<&rcc ETHRX>,
171
+
<&rcc ETHSTP>,
172
+
<&rcc ETHCK_K>;
173
+
st,syscon = <&syscfg 0x4>;
174
+
snps,pbl = <2>;
175
+
snps,axi-config = <&stmmac_axi_config_0>;
176
+
snps,tso;
177
+
phy-mode = "rgmii";
178
+
};
179
179
180
180
- |
181
181
//Example 2 (MCU example)
182
-
ethernet1: ethernet@40028000 {
183
-
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
184
-
reg = <0x40028000 0x8000>;
185
-
reg-names = "stmmaceth";
186
-
interrupts = <0 61 0>, <0 62 0>;
187
-
interrupt-names = "macirq", "eth_wake_irq";
188
-
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
189
-
clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
190
-
st,syscon = <&syscfg 0x4>;
191
-
snps,pbl = <8>;
192
-
snps,mixed-burst;
193
-
phy-mode = "mii";
194
-
};
182
+
ethernet1: ethernet@40028000 {
183
+
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
184
+
reg = <0x40028000 0x8000>;
185
+
reg-names = "stmmaceth";
186
+
interrupts = <0 61 0>, <0 62 0>;
187
+
interrupt-names = "macirq", "eth_wake_irq";
188
+
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
189
+
clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
190
+
st,syscon = <&syscfg 0x4>;
191
+
snps,pbl = <8>;
192
+
snps,mixed-burst;
193
+
phy-mode = "mii";
194
+
};
195
195
196
196
- |
197
197
//Example 3
198
-
ethernet2: ethernet@40027000 {
199
-
compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
200
-
reg = <0x40028000 0x8000>;
201
-
reg-names = "stmmaceth";
202
-
interrupts = <61>;
203
-
interrupt-names = "macirq";
204
-
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
205
-
clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
206
-
st,syscon = <&syscfg 0x4>;
207
-
snps,pbl = <8>;
208
-
phy-mode = "mii";
209
-
};
198
+
ethernet2: ethernet@40027000 {
199
+
compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
200
+
reg = <0x40028000 0x8000>;
201
+
reg-names = "stmmaceth";
202
+
interrupts = <61>;
203
+
interrupt-names = "macirq";
204
+
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
205
+
clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
206
+
st,syscon = <&syscfg 0x4>;
207
+
snps,pbl = <8>;
208
+
phy-mode = "mii";
209
+
};
+5
-5
Documentation/devicetree/bindings/net/ti,davinci-mdio.yaml
+5
-5
Documentation/devicetree/bindings/net/ti,davinci-mdio.yaml
···
72
72
examples:
73
73
- |
74
74
davinci_mdio: mdio@4a101000 {
75
-
compatible = "ti,davinci_mdio";
76
-
#address-cells = <1>;
77
-
#size-cells = <0>;
78
-
reg = <0x4a101000 0x1000>;
79
-
bus_freq = <1000000>;
75
+
compatible = "ti,davinci_mdio";
76
+
#address-cells = <1>;
77
+
#size-cells = <0>;
78
+
reg = <0x4a101000 0x1000>;
79
+
bus_freq = <1000000>;
80
80
};
+10
-10
Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
+10
-10
Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
···
302
302
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
303
303
};
304
304
};
305
-
};
306
305
307
-
cpts@3d000 {
308
-
compatible = "ti,am65-cpts";
309
-
reg = <0x0 0x3d000 0x0 0x400>;
310
-
clocks = <&k3_clks 18 2>;
311
-
clock-names = "cpts";
312
-
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
313
-
interrupt-names = "cpts";
314
-
ti,cpts-ext-ts-inputs = <4>;
315
-
ti,cpts-periodic-outputs = <2>;
306
+
cpts@3d000 {
307
+
compatible = "ti,am65-cpts";
308
+
reg = <0x0 0x3d000 0x0 0x400>;
309
+
clocks = <&k3_clks 18 2>;
310
+
clock-names = "cpts";
311
+
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
312
+
interrupt-names = "cpts";
313
+
ti,cpts-ext-ts-inputs = <4>;
314
+
ti,cpts-periodic-outputs = <2>;
315
+
};
316
316
};
317
317
};
+18
-18
Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml
+18
-18
Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml
···
131
131
#include <dt-bindings/interrupt-controller/arm-gic.h>
132
132
133
133
cpts@310d0000 {
134
-
compatible = "ti,am65-cpts";
135
-
reg = <0x310d0000 0x400>;
136
-
reg-names = "cpts";
137
-
clocks = <&main_cpts_mux>;
138
-
clock-names = "cpts";
139
-
interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>;
140
-
interrupt-names = "cpts";
141
-
ti,cpts-periodic-outputs = <6>;
142
-
ti,cpts-ext-ts-inputs = <8>;
134
+
compatible = "ti,am65-cpts";
135
+
reg = <0x310d0000 0x400>;
136
+
reg-names = "cpts";
137
+
clocks = <&main_cpts_mux>;
138
+
clock-names = "cpts";
139
+
interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>;
140
+
interrupt-names = "cpts";
141
+
ti,cpts-periodic-outputs = <6>;
142
+
ti,cpts-ext-ts-inputs = <8>;
143
143
144
-
main_cpts_mux: refclk-mux {
145
-
#clock-cells = <0>;
146
-
clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
147
-
<&k3_clks 157 91>, <&k3_clks 157 77>,
148
-
<&k3_clks 157 102>, <&k3_clks 157 80>,
149
-
<&k3_clks 120 3>, <&k3_clks 121 3>;
150
-
assigned-clocks = <&main_cpts_mux>;
151
-
assigned-clock-parents = <&k3_clks 118 11>;
152
-
};
144
+
main_cpts_mux: refclk-mux {
145
+
#clock-cells = <0>;
146
+
clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
147
+
<&k3_clks 157 91>, <&k3_clks 157 77>,
148
+
<&k3_clks 157 102>, <&k3_clks 157 80>,
149
+
<&k3_clks 120 3>, <&k3_clks 121 3>;
150
+
assigned-clocks = <&main_cpts_mux>;
151
+
assigned-clock-parents = <&k3_clks 118 11>;
152
+
};
153
153
};
+8
-9
Documentation/devicetree/bindings/net/wireless/marvell,sd8787.yaml
+8
-9
Documentation/devicetree/bindings/net/wireless/marvell,sd8787.yaml
···
79
79
#include <dt-bindings/interrupt-controller/irq.h>
80
80
81
81
mmc {
82
-
#address-cells = <1>;
83
-
#size-cells = <0>;
82
+
#address-cells = <1>;
83
+
#size-cells = <0>;
84
84
85
-
wifi@1 {
86
-
compatible = "marvell,sd8897";
87
-
reg = <1>;
88
-
interrupt-parent = <&pio>;
89
-
interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
90
-
marvell,wakeup-pin = <3>;
85
+
wifi@1 {
86
+
compatible = "marvell,sd8897";
87
+
reg = <1>;
88
+
interrupt-parent = <&pio>;
89
+
interrupts = <38 IRQ_TYPE_LEVEL_LOW>;
90
+
marvell,wakeup-pin = <3>;
91
91
};
92
92
};
93
-