tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'dmaengine-fix-5.3-rc5' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine fixes from Vinod Koul:
"Fixes in dmaengine drivers for:

- dw-edma: endianess, _iomem type and stack usages

- ste_dma40: unneeded variable and null-pointer dereference

- tegra210-adma: unused function

- omap-dma: off-by-one fix"

* tag 'dmaengine-fix-5.3-rc5' of git://git.infradead.org/users/vkoul/slave-dma:
omap-dma/omap_vout_vrfb: fix off-by-one fi value
dmaengine: stm32-mdma: Fix a possible null-pointer dereference in stm32_mdma_irq_handler()
dmaengine: tegra210-adma: Fix unused function warnings
dmaengine: ste_dma40: fix unneeded variable warning
dmaengine: dw-edma: fix endianess confusion
dmaengine: dw-edma: fix __iomem type confusion
dmaengine: dw-edma: fix unnecessary stack usage

Linus Torvalds 9da5bb24 cfa0bb2a

+48 -52
+1 -1
drivers/dma/dw-edma/dw-edma-core.h
··· 50 50 51 51 struct dw_edma_region { 52 52 phys_addr_t paddr; 53 - dma_addr_t vaddr; 53 + void __iomem *vaddr; 54 54 size_t sz; 55 55 }; 56 56
+9 -9
drivers/dma/dw-edma/dw-edma-pcie.c
··· 130 130 chip->id = pdev->devfn; 131 131 chip->irq = pdev->irq; 132 132 133 - dw->rg_region.vaddr = (dma_addr_t)pcim_iomap_table(pdev)[pdata->rg_bar]; 133 + dw->rg_region.vaddr = pcim_iomap_table(pdev)[pdata->rg_bar]; 134 134 dw->rg_region.vaddr += pdata->rg_off; 135 135 dw->rg_region.paddr = pdev->resource[pdata->rg_bar].start; 136 136 dw->rg_region.paddr += pdata->rg_off; 137 137 dw->rg_region.sz = pdata->rg_sz; 138 138 139 - dw->ll_region.vaddr = (dma_addr_t)pcim_iomap_table(pdev)[pdata->ll_bar]; 139 + dw->ll_region.vaddr = pcim_iomap_table(pdev)[pdata->ll_bar]; 140 140 dw->ll_region.vaddr += pdata->ll_off; 141 141 dw->ll_region.paddr = pdev->resource[pdata->ll_bar].start; 142 142 dw->ll_region.paddr += pdata->ll_off; 143 143 dw->ll_region.sz = pdata->ll_sz; 144 144 145 - dw->dt_region.vaddr = (dma_addr_t)pcim_iomap_table(pdev)[pdata->dt_bar]; 145 + dw->dt_region.vaddr = pcim_iomap_table(pdev)[pdata->dt_bar]; 146 146 dw->dt_region.vaddr += pdata->dt_off; 147 147 dw->dt_region.paddr = pdev->resource[pdata->dt_bar].start; 148 148 dw->dt_region.paddr += pdata->dt_off; ··· 158 158 pci_dbg(pdev, "Mode:\t%s\n", 159 159 dw->mode == EDMA_MODE_LEGACY ? "Legacy" : "Unroll"); 160 160 161 - pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%pa, p=%pa)\n", 161 + pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", 162 162 pdata->rg_bar, pdata->rg_off, pdata->rg_sz, 163 - &dw->rg_region.vaddr, &dw->rg_region.paddr); 163 + dw->rg_region.vaddr, &dw->rg_region.paddr); 164 164 165 - pci_dbg(pdev, "L. List:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%pa, p=%pa)\n", 165 + pci_dbg(pdev, "L. List:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", 166 166 pdata->ll_bar, pdata->ll_off, pdata->ll_sz, 167 - &dw->ll_region.vaddr, &dw->ll_region.paddr); 167 + dw->ll_region.vaddr, &dw->ll_region.paddr); 168 168 169 - pci_dbg(pdev, "Data:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%pa, p=%pa)\n", 169 + pci_dbg(pdev, "Data:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", 170 170 pdata->dt_bar, pdata->dt_off, pdata->dt_sz, 171 - &dw->dt_region.vaddr, &dw->dt_region.paddr); 171 + dw->dt_region.vaddr, &dw->dt_region.paddr); 172 172 173 173 pci_dbg(pdev, "Nr. IRQs:\t%u\n", dw->nr_irqs); 174 174
+15 -19
drivers/dma/dw-edma/dw-edma-v0-core.c
··· 25 25 26 26 static inline struct dw_edma_v0_regs __iomem *__dw_regs(struct dw_edma *dw) 27 27 { 28 - return (struct dw_edma_v0_regs __iomem *)dw->rg_region.vaddr; 28 + return dw->rg_region.vaddr; 29 29 } 30 30 31 31 #define SET(dw, name, value) \ ··· 192 192 static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) 193 193 { 194 194 struct dw_edma_burst *child; 195 - struct dw_edma_v0_lli *lli; 196 - struct dw_edma_v0_llp *llp; 195 + struct dw_edma_v0_lli __iomem *lli; 196 + struct dw_edma_v0_llp __iomem *llp; 197 197 u32 control = 0, i = 0; 198 - u64 sar, dar, addr; 199 198 int j; 200 199 201 - lli = (struct dw_edma_v0_lli *)chunk->ll_region.vaddr; 200 + lli = chunk->ll_region.vaddr; 202 201 203 202 if (chunk->cb) 204 203 control = DW_EDMA_V0_CB; ··· 213 214 /* Transfer size */ 214 215 SET_LL(&lli[i].transfer_size, child->sz); 215 216 /* SAR - low, high */ 216 - sar = cpu_to_le64(child->sar); 217 - SET_LL(&lli[i].sar_low, lower_32_bits(sar)); 218 - SET_LL(&lli[i].sar_high, upper_32_bits(sar)); 217 + SET_LL(&lli[i].sar_low, lower_32_bits(child->sar)); 218 + SET_LL(&lli[i].sar_high, upper_32_bits(child->sar)); 219 219 /* DAR - low, high */ 220 - dar = cpu_to_le64(child->dar); 221 - SET_LL(&lli[i].dar_low, lower_32_bits(dar)); 222 - SET_LL(&lli[i].dar_high, upper_32_bits(dar)); 220 + SET_LL(&lli[i].dar_low, lower_32_bits(child->dar)); 221 + SET_LL(&lli[i].dar_high, upper_32_bits(child->dar)); 223 222 i++; 224 223 } 225 224 226 - llp = (struct dw_edma_v0_llp *)&lli[i]; 225 + llp = (void __iomem *)&lli[i]; 227 226 control = DW_EDMA_V0_LLP | DW_EDMA_V0_TCB; 228 227 if (!chunk->cb) 229 228 control |= DW_EDMA_V0_CB; ··· 229 232 /* Channel control */ 230 233 SET_LL(&llp->control, control); 231 234 /* Linked list - low, high */ 232 - addr = cpu_to_le64(chunk->ll_region.paddr); 233 - SET_LL(&llp->llp_low, lower_32_bits(addr)); 234 - SET_LL(&llp->llp_high, upper_32_bits(addr)); 235 + SET_LL(&llp->llp_low, lower_32_bits(chunk->ll_region.paddr)); 236 + SET_LL(&llp->llp_high, upper_32_bits(chunk->ll_region.paddr)); 235 237 } 236 238 237 239 void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) ··· 238 242 struct dw_edma_chan *chan = chunk->chan; 239 243 struct dw_edma *dw = chan->chip->dw; 240 244 u32 tmp; 241 - u64 llp; 242 245 243 246 dw_edma_v0_core_write_chunk(chunk); 244 247 ··· 257 262 SET_CH(dw, chan->dir, chan->id, ch_control1, 258 263 (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE)); 259 264 /* Linked list - low, high */ 260 - llp = cpu_to_le64(chunk->ll_region.paddr); 261 - SET_CH(dw, chan->dir, chan->id, llp_low, lower_32_bits(llp)); 262 - SET_CH(dw, chan->dir, chan->id, llp_high, upper_32_bits(llp)); 265 + SET_CH(dw, chan->dir, chan->id, llp_low, 266 + lower_32_bits(chunk->ll_region.paddr)); 267 + SET_CH(dw, chan->dir, chan->id, llp_high, 268 + upper_32_bits(chunk->ll_region.paddr)); 263 269 } 264 270 /* Doorbell */ 265 271 SET_RW(dw, chan->dir, doorbell,
+15 -14
drivers/dma/dw-edma/dw-edma-v0-debugfs.c
··· 14 14 #include "dw-edma-core.h" 15 15 16 16 #define REGS_ADDR(name) \ 17 - ((dma_addr_t *)&regs->name) 17 + ((void __force *)&regs->name) 18 18 #define REGISTER(name) \ 19 19 { #name, REGS_ADDR(name) } 20 20 ··· 40 40 41 41 static struct dentry *base_dir; 42 42 static struct dw_edma *dw; 43 - static struct dw_edma_v0_regs *regs; 43 + static struct dw_edma_v0_regs __iomem *regs; 44 44 45 45 static struct { 46 - void *start; 47 - void *end; 46 + void __iomem *start; 47 + void __iomem *end; 48 48 } lim[2][EDMA_V0_MAX_NR_CH]; 49 49 50 50 struct debugfs_entries { 51 - char name[24]; 51 + const char *name; 52 52 dma_addr_t *reg; 53 53 }; 54 54 55 55 static int dw_edma_debugfs_u32_get(void *data, u64 *val) 56 56 { 57 + void __iomem *reg = (void __force __iomem *)data; 57 58 if (dw->mode == EDMA_MODE_LEGACY && 58 - data >= (void *)&regs->type.legacy.ch) { 59 - void *ptr = (void *)&regs->type.legacy.ch; 59 + reg >= (void __iomem *)&regs->type.legacy.ch) { 60 + void __iomem *ptr = &regs->type.legacy.ch; 60 61 u32 viewport_sel = 0; 61 62 unsigned long flags; 62 63 u16 ch; 63 64 64 65 for (ch = 0; ch < dw->wr_ch_cnt; ch++) 65 - if (lim[0][ch].start >= data && data < lim[0][ch].end) { 66 - ptr += (data - lim[0][ch].start); 66 + if (lim[0][ch].start >= reg && reg < lim[0][ch].end) { 67 + ptr += (reg - lim[0][ch].start); 67 68 goto legacy_sel_wr; 68 69 } 69 70 70 71 for (ch = 0; ch < dw->rd_ch_cnt; ch++) 71 - if (lim[1][ch].start >= data && data < lim[1][ch].end) { 72 - ptr += (data - lim[1][ch].start); 72 + if (lim[1][ch].start >= reg && reg < lim[1][ch].end) { 73 + ptr += (reg - lim[1][ch].start); 73 74 goto legacy_sel_rd; 74 75 } 75 76 ··· 87 86 88 87 raw_spin_unlock_irqrestore(&dw->lock, flags); 89 88 } else { 90 - *val = readl(data); 89 + *val = readl(reg); 91 90 } 92 91 93 92 return 0; ··· 106 105 } 107 106 } 108 107 109 - static void dw_edma_debugfs_regs_ch(struct dw_edma_v0_ch_regs *regs, 108 + static void dw_edma_debugfs_regs_ch(struct dw_edma_v0_ch_regs __iomem *regs, 110 109 struct dentry *dir) 111 110 { 112 111 int nr_entries; ··· 289 288 if (!dw) 290 289 return; 291 290 292 - regs = (struct dw_edma_v0_regs *)dw->rg_region.vaddr; 291 + regs = dw->rg_region.vaddr; 293 292 if (!regs) 294 293 return; 295 294
+2 -2
drivers/dma/ste_dma40.c
··· 142 142 * when the DMA hw is powered off. 143 143 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works. 144 144 */ 145 - static u32 d40_backup_regs[] = { 145 + static __maybe_unused u32 d40_backup_regs[] = { 146 146 D40_DREG_LCPA, 147 147 D40_DREG_LCLA, 148 148 D40_DREG_PRMSE, ··· 211 211 212 212 #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b) 213 213 214 - static u32 d40_backup_regs_chan[] = { 214 + static __maybe_unused u32 d40_backup_regs_chan[] = { 215 215 D40_CHAN_REG_SSCFG, 216 216 D40_CHAN_REG_SSELT, 217 217 D40_CHAN_REG_SSPTR,
+1 -1
drivers/dma/stm32-mdma.c
··· 1366 1366 1367 1367 chan = &dmadev->chan[id]; 1368 1368 if (!chan) { 1369 - dev_err(chan2dev(chan), "MDMA channel not initialized\n"); 1369 + dev_dbg(mdma2dev(dmadev), "MDMA channel not initialized\n"); 1370 1370 goto exit; 1371 1371 } 1372 1372
+2 -2
drivers/dma/tegra210-adma.c
··· 712 712 return chan; 713 713 } 714 714 715 - static int tegra_adma_runtime_suspend(struct device *dev) 715 + static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev) 716 716 { 717 717 struct tegra_adma *tdma = dev_get_drvdata(dev); 718 718 struct tegra_adma_chan_regs *ch_reg; ··· 744 744 return 0; 745 745 } 746 746 747 - static int tegra_adma_runtime_resume(struct device *dev) 747 + static int __maybe_unused tegra_adma_runtime_resume(struct device *dev) 748 748 { 749 749 struct tegra_adma *tdma = dev_get_drvdata(dev); 750 750 struct tegra_adma_chan_regs *ch_reg;
+2 -2
drivers/dma/ti/omap-dma.c
··· 1234 1234 if (src_icg) { 1235 1235 d->ccr |= CCR_SRC_AMODE_DBLIDX; 1236 1236 d->ei = 1; 1237 - d->fi = src_icg; 1237 + d->fi = src_icg + 1; 1238 1238 } else if (xt->src_inc) { 1239 1239 d->ccr |= CCR_SRC_AMODE_POSTINC; 1240 1240 d->fi = 0; ··· 1249 1249 if (dst_icg) { 1250 1250 d->ccr |= CCR_DST_AMODE_DBLIDX; 1251 1251 sg->ei = 1; 1252 - sg->fi = dst_icg; 1252 + sg->fi = dst_icg + 1; 1253 1253 } else if (xt->dst_inc) { 1254 1254 d->ccr |= CCR_DST_AMODE_POSTINC; 1255 1255 sg->fi = 0;
+1 -2
drivers/media/platform/omap/omap_vout_vrfb.c
··· 253 253 */ 254 254 255 255 pixsize = vout->bpp * vout->vrfb_bpp; 256 - dst_icg = ((MAX_PIXELS_PER_LINE * pixsize) - 257 - (vout->pix.width * vout->bpp)) + 1; 256 + dst_icg = MAX_PIXELS_PER_LINE * pixsize - vout->pix.width * vout->bpp; 258 257 259 258 xt->src_start = vout->buf_phy_addr[vb->i]; 260 259 xt->dst_start = vout->vrfb_context[vb->i].paddr[0];