Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"A bunch of radeon displayport mode setting fixes, and some misc i915
fixes.
There is one revert, the MST audio code in i915 was causing some
oopses, so we've decided just to drop it until next kernel when we can
fix it properly"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/amdgpu: fix DP mode validation
drm/radeon: fix DP mode validation
drm/i915: Bail out of pipe config compute loop on LPT
drm/radeon: fix PLL sharing on DCE6.1 (v2)
drm/radeon: fix DP link training issue with second 4K monitor
Revert "drm/i915: start adding dp mst audio"
drm/i915/bdw: Add missing delay during L3 SQC credit programming
drm/i915/lvds: separate border enable readout from panel fitter
drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency
+44
-74
+2
-2
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+2
-2
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
···
276
276
}
277
277
}
278
278
} else {
279
-
for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
280
-
for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
279
+
for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
280
+
for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
281
281
max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
282
282
if (max_pix_clock >= pix_clock) {
283
283
*dp_lanes = lane_num;
-16
drivers/gpu/drm/i915/i915_debugfs.c
-16
drivers/gpu/drm/i915/i915_debugfs.c
···
2872
2872
intel_panel_info(m, &intel_connector->panel);
2873
2873
}
2874
2874
2875
-
static void intel_dp_mst_info(struct seq_file *m,
2876
-
struct intel_connector *intel_connector)
2877
-
{
2878
-
struct intel_encoder *intel_encoder = intel_connector->encoder;
2879
-
struct intel_dp_mst_encoder *intel_mst =
2880
-
enc_to_mst(&intel_encoder->base);
2881
-
struct intel_digital_port *intel_dig_port = intel_mst->primary;
2882
-
struct intel_dp *intel_dp = &intel_dig_port->dp;
2883
-
bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2884
-
intel_connector->port);
2885
-
2886
-
seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2887
-
}
2888
-
2889
2875
static void intel_hdmi_info(struct seq_file *m,
2890
2876
struct intel_connector *intel_connector)
2891
2877
{
···
2915
2929
intel_hdmi_info(m, intel_connector);
2916
2930
else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2917
2931
intel_lvds_info(m, intel_connector);
2918
-
else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2919
-
intel_dp_mst_info(m, intel_connector);
2920
2932
}
2921
2933
2922
2934
seq_printf(m, "\tmodes:\n");
+2
drivers/gpu/drm/i915/i915_reg.h
+2
drivers/gpu/drm/i915/i915_reg.h
+3
-6
drivers/gpu/drm/i915/intel_audio.c
+3
-6
drivers/gpu/drm/i915/intel_audio.c
···
262
262
tmp |= AUD_CONFIG_N_PROG_ENABLE;
263
263
tmp &= ~AUD_CONFIG_UPPER_N_MASK;
264
264
tmp &= ~AUD_CONFIG_LOWER_N_MASK;
265
-
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
266
-
intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DP_MST))
265
+
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
267
266
tmp |= AUD_CONFIG_N_VALUE_INDEX;
268
267
I915_WRITE(HSW_AUD_CFG(pipe), tmp);
269
268
···
475
476
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
476
477
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
477
478
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
478
-
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) ||
479
-
intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DP_MST))
479
+
if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
480
480
tmp |= AUD_CONFIG_N_VALUE_INDEX;
481
481
else
482
482
tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
···
513
515
514
516
/* ELD Conn_Type */
515
517
connector->eld[5] &= ~(3 << 2);
516
-
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
517
-
intel_pipe_has_type(crtc, INTEL_OUTPUT_DP_MST))
518
+
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
518
519
connector->eld[5] |= (1 << 2);
519
520
520
521
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
+7
-1
drivers/gpu/drm/i915/intel_crt.c
+7
-1
drivers/gpu/drm/i915/intel_crt.c
···
257
257
pipe_config->has_pch_encoder = true;
258
258
259
259
/* LPT FDI RX only supports 8bpc. */
260
-
if (HAS_PCH_LPT(dev))
260
+
if (HAS_PCH_LPT(dev)) {
261
+
if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
262
+
DRM_DEBUG_KMS("LPT only supports 24bpp\n");
263
+
return false;
264
+
}
265
+
261
266
pipe_config->pipe_bpp = 24;
267
+
}
262
268
263
269
/* FDI must always be 2.7 GHz */
264
270
if (HAS_DDI(dev)) {
+5
-19
drivers/gpu/drm/i915/intel_ddi.c
+5
-19
drivers/gpu/drm/i915/intel_ddi.c
···
3106
3106
I915_WRITE(FDI_RX_CTL(PIPE_A), val);
3107
3107
}
3108
3108
3109
-
bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3110
-
struct intel_crtc *intel_crtc)
3111
-
{
3112
-
u32 temp;
3113
-
3114
-
if (intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3115
-
temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
3116
-
3117
-
intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
3118
-
3119
-
if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3120
-
return true;
3121
-
}
3122
-
3123
-
return false;
3124
-
}
3125
-
3126
3109
void intel_ddi_get_config(struct intel_encoder *encoder,
3127
3110
struct intel_crtc_state *pipe_config)
3128
3111
{
···
3166
3183
break;
3167
3184
}
3168
3185
3169
-
pipe_config->has_audio =
3170
-
intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
3186
+
if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
3187
+
temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
3188
+
if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
3189
+
pipe_config->has_audio = true;
3190
+
}
3171
3191
3172
3192
if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
3173
3193
pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
+2
-3
drivers/gpu/drm/i915/intel_display.c
+2
-3
drivers/gpu/drm/i915/intel_display.c
···
7988
7988
7989
7989
pipe_config->gmch_pfit.control = tmp;
7990
7990
pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7991
-
if (INTEL_INFO(dev)->gen < 5)
7992
-
pipe_config->gmch_pfit.lvds_border_bits =
7993
-
I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7994
7991
}
7995
7992
7996
7993
static void vlv_crtc_clock_get(struct intel_crtc *crtc,
···
9748
9751
mutex_lock(&dev_priv->rps.hw_lock);
9749
9752
sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9750
9753
mutex_unlock(&dev_priv->rps.hw_lock);
9754
+
9755
+
I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
9751
9756
9752
9757
intel_update_cdclk(dev);
9753
9758
-22
drivers/gpu/drm/i915/intel_dp_mst.c
-22
drivers/gpu/drm/i915/intel_dp_mst.c
···
78
78
return false;
79
79
}
80
80
81
-
if (drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, found->port))
82
-
pipe_config->has_audio = true;
83
81
mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp);
84
82
85
83
pipe_config->pbn = mst_pbn;
···
102
104
struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
103
105
struct intel_digital_port *intel_dig_port = intel_mst->primary;
104
106
struct intel_dp *intel_dp = &intel_dig_port->dp;
105
-
struct drm_device *dev = encoder->base.dev;
106
-
struct drm_i915_private *dev_priv = dev->dev_private;
107
-
struct drm_crtc *crtc = encoder->base.crtc;
108
-
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
109
-
110
107
int ret;
111
108
112
109
DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
···
111
118
ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
112
119
if (ret) {
113
120
DRM_ERROR("failed to update payload %d\n", ret);
114
-
}
115
-
if (intel_crtc->config->has_audio) {
116
-
intel_audio_codec_disable(encoder);
117
-
intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
118
121
}
119
122
}
120
123
···
210
221
struct intel_dp *intel_dp = &intel_dig_port->dp;
211
222
struct drm_device *dev = intel_dig_port->base.base.dev;
212
223
struct drm_i915_private *dev_priv = dev->dev_private;
213
-
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
214
224
enum port port = intel_dig_port->port;
215
225
int ret;
216
226
···
222
234
ret = drm_dp_check_act_status(&intel_dp->mst_mgr);
223
235
224
236
ret = drm_dp_update_payload_part2(&intel_dp->mst_mgr);
225
-
226
-
if (crtc->config->has_audio) {
227
-
DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
228
-
pipe_name(crtc->pipe));
229
-
intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
230
-
intel_audio_codec_enable(encoder);
231
-
}
232
237
}
233
238
234
239
static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
···
246
265
u32 temp, flags = 0;
247
266
248
267
pipe_config->has_dp_encoder = true;
249
-
250
-
pipe_config->has_audio =
251
-
intel_ddi_is_audio_enabled(dev_priv, crtc);
252
268
253
269
temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
254
270
if (temp & TRANS_DDI_PHSYNC)
-2
drivers/gpu/drm/i915/intel_drv.h
-2
drivers/gpu/drm/i915/intel_drv.h
···
1019
1019
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1020
1020
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1021
1021
void intel_ddi_fdi_disable(struct drm_crtc *crtc);
1022
-
bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1023
-
struct intel_crtc *intel_crtc);
1024
1022
void intel_ddi_get_config(struct intel_encoder *encoder,
1025
1023
struct intel_crtc_state *pipe_config);
1026
1024
struct intel_encoder *
+4
drivers/gpu/drm/i915/intel_lvds.c
+4
drivers/gpu/drm/i915/intel_lvds.c
···
123
123
124
124
pipe_config->base.adjusted_mode.flags |= flags;
125
125
126
+
if (INTEL_INFO(dev)->gen < 5)
127
+
pipe_config->gmch_pfit.lvds_border_bits =
128
+
tmp & LVDS_BORDER_ENABLE;
129
+
126
130
/* gen2/3 store dither state in pfit control, needs to match */
127
131
if (INTEL_INFO(dev)->gen < 4) {
128
132
tmp = I915_READ(PFIT_CONTROL);
+6
drivers/gpu/drm/i915/intel_pm.c
+6
drivers/gpu/drm/i915/intel_pm.c
···
6646
6646
misccpctl = I915_READ(GEN7_MISCCPCTL);
6647
6647
I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6648
6648
I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6649
+
/*
6650
+
* Wait at least 100 clocks before re-enabling clock gating. See
6651
+
* the definition of L3SQCREG1 in BSpec.
6652
+
*/
6653
+
POSTING_READ(GEN8_L3SQCREG1);
6654
+
udelay(1);
6649
6655
I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6650
6656
6651
6657
/*
+10
drivers/gpu/drm/radeon/atombios_crtc.c
+10
drivers/gpu/drm/radeon/atombios_crtc.c
···
1742
1742
static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1743
1743
{
1744
1744
struct drm_device *dev = crtc->dev;
1745
+
struct radeon_device *rdev = dev->dev_private;
1745
1746
struct drm_crtc *test_crtc;
1746
1747
struct radeon_crtc *test_radeon_crtc;
1747
1748
···
1752
1751
test_radeon_crtc = to_radeon_crtc(test_crtc);
1753
1752
if (test_radeon_crtc->encoder &&
1754
1753
ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1754
+
/* PPLL2 is exclusive to UNIPHYA on DCE61 */
1755
+
if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1756
+
test_radeon_crtc->pll_id == ATOM_PPLL2)
1757
+
continue;
1755
1758
/* for DP use the same PLL for all */
1756
1759
if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1757
1760
return test_radeon_crtc->pll_id;
···
1777
1772
{
1778
1773
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1779
1774
struct drm_device *dev = crtc->dev;
1775
+
struct radeon_device *rdev = dev->dev_private;
1780
1776
struct drm_crtc *test_crtc;
1781
1777
struct radeon_crtc *test_radeon_crtc;
1782
1778
u32 adjusted_clock, test_adjusted_clock;
···
1793
1787
test_radeon_crtc = to_radeon_crtc(test_crtc);
1794
1788
if (test_radeon_crtc->encoder &&
1795
1789
!ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1790
+
/* PPLL2 is exclusive to UNIPHYA on DCE61 */
1791
+
if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1792
+
test_radeon_crtc->pll_id == ATOM_PPLL2)
1793
+
continue;
1796
1794
/* check if we are already driving this connector with another crtc */
1797
1795
if (test_radeon_crtc->connector == radeon_crtc->connector) {
1798
1796
/* if we are, return that pll */
+2
-2
drivers/gpu/drm/radeon/atombios_dp.c
+2
-2
drivers/gpu/drm/radeon/atombios_dp.c
···
326
326
}
327
327
}
328
328
} else {
329
-
for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
330
-
for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
329
+
for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) {
330
+
for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
331
331
max_pix_clock = (lane_num * link_rates[i] * 8) / bpp;
332
332
if (max_pix_clock >= pix_clock) {
333
333
*dp_lanes = lane_num;
+1
-1
drivers/gpu/drm/radeon/radeon_dp_auxch.c
+1
-1
drivers/gpu/drm/radeon/radeon_dp_auxch.c