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phy: qcom-qmp-pcie: Fix high latency with 4x2 PHY when ASPM is enabled

The PCIe QMP 4x2 RC PHY generates high latency when ASPM is enabled. This
seem to be fixed by clearing the QPHY_V5_20_PCS_PCIE_PRESET_P10_POST
register of the pcs_misc register space.

Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20221102081835.41892-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Manivannan Sadhasivam and committed by
Vinod Koul 9ddcd920 2584068a

+2
+1
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
··· 1430 1430 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 1431 1431 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1432 1432 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1433 + QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00), 1433 1434 }; 1434 1435 1435 1436 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = {
+1
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
··· 11 11 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084 12 12 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 13 13 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 14 + #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0 14 15 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 15 16 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 16 17 #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184