tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (38 commits)
MIPS: O32: Fix ppoll
MIPS: Oprofile: Rename cpu_type from godson2 to loongson2
MIPS: Alchemy: Fix hang with high-frequency edge interrupts
MIPS: TXx9: Fix spi-baseclk value
MIPS: bcm63xx: Set the correct BCM3302 CPU name
MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store
MIPS: Avoid potential hazard on Context register
MIPS: Octeon: Use lockless interrupt controller operations when possible.
MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity
MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache
MIPS: SMTC: Avoid queing multiple reschedule IPIs
MIPS: GCMP: Avoid accessing registers when they are not present
MIPS: GIC: Random fixes and enhancements.
MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start
MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands
MIPS: SPRAM: Clean up support code a little
MIPS: 1004K: Enable SPRAM support.
MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4
MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT.
MIPS: MTI: Fix accesses to device registers on MIPS boards
...

Linus Torvalds 9ddfd929 38dc6345

+544 -440
+2 -2
arch/mips/Kconfig
··· 1012 1012 1013 1013 config MIPS_L1_CACHE_SHIFT 1014 1014 int 1015 - default "4" if MACH_DECSTATION || MIKROTIK_RB532 1015 + default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL 1016 + default "6" if MIPS_CPU_SCACHE 1016 1017 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON 1017 - default "4" if PMC_MSP4200_EVAL 1018 1018 default "5" 1019 1019 1020 1020 config HAVE_STD_PC_SERIAL_PORT
+26 -8
arch/mips/alchemy/common/irq.c
··· 354 354 au_sync(); 355 355 } 356 356 357 + static void au1x_ic0_maskack(unsigned int irq_nr) 358 + { 359 + unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 360 + 361 + au_writel(1 << bit, IC0_WAKECLR); 362 + au_writel(1 << bit, IC0_MASKCLR); 363 + au_writel(1 << bit, IC0_RISINGCLR); 364 + au_writel(1 << bit, IC0_FALLINGCLR); 365 + au_sync(); 366 + } 367 + 368 + static void au1x_ic1_maskack(unsigned int irq_nr) 369 + { 370 + unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; 371 + 372 + au_writel(1 << bit, IC1_WAKECLR); 373 + au_writel(1 << bit, IC1_MASKCLR); 374 + au_writel(1 << bit, IC1_RISINGCLR); 375 + au_writel(1 << bit, IC1_FALLINGCLR); 376 + au_sync(); 377 + } 378 + 357 379 static int au1x_ic1_setwake(unsigned int irq, unsigned int on) 358 380 { 359 381 unsigned int bit = irq - AU1000_INTC1_INT_BASE; ··· 401 379 /* 402 380 * irq_chips for both ICs; this way the mask handlers can be 403 381 * as short as possible. 404 - * 405 - * NOTE: the ->ack() callback is used by the handle_edge_irq 406 - * flowhandler only, the ->mask_ack() one by handle_level_irq, 407 - * so no need for an irq_chip for each type of irq (level/edge). 408 382 */ 409 383 static struct irq_chip au1x_ic0_chip = { 410 384 .name = "Alchemy-IC0", 411 - .ack = au1x_ic0_ack, /* edge */ 385 + .ack = au1x_ic0_ack, 412 386 .mask = au1x_ic0_mask, 413 - .mask_ack = au1x_ic0_mask, /* level */ 387 + .mask_ack = au1x_ic0_maskack, 414 388 .unmask = au1x_ic0_unmask, 415 389 .set_type = au1x_ic_settype, 416 390 }; 417 391 418 392 static struct irq_chip au1x_ic1_chip = { 419 393 .name = "Alchemy-IC1", 420 - .ack = au1x_ic1_ack, /* edge */ 394 + .ack = au1x_ic1_ack, 421 395 .mask = au1x_ic1_mask, 422 - .mask_ack = au1x_ic1_mask, /* level */ 396 + .mask_ack = au1x_ic1_maskack, 423 397 .unmask = au1x_ic1_unmask, 424 398 .set_type = au1x_ic_settype, 425 399 .set_wake = au1x_ic1_setwake,
+1 -2
arch/mips/alchemy/mtx-1/board_setup.c
··· 69 69 #else 70 70 au_writel(0xf, Au1500_PCI_CFG); 71 71 #endif 72 + board_pci_idsel = mtx1_pci_idsel; 72 73 #endif 73 74 74 75 /* Initialize sys_pinfunc */ ··· 85 84 /* Enable LED and set it to green */ 86 85 alchemy_gpio_direction_output(211, 1); /* green on */ 87 86 alchemy_gpio_direction_output(212, 0); /* red off */ 88 - 89 - board_pci_idsel = mtx1_pci_idsel; 90 87 91 88 printk(KERN_INFO "4G Systems MTX-1 Board\n"); 92 89 }
+8 -1
arch/mips/ar7/platform.c
··· 503 503 { 504 504 u16 chip_id; 505 505 int res; 506 + u32 *bootcr, val; 506 507 #ifdef CONFIG_SERIAL_8250 507 508 static struct uart_port uart_port[2]; 508 509 ··· 596 595 597 596 ar7_wdt_res.end = ar7_wdt_res.start + 0x20; 598 597 599 - res = platform_device_register(&ar7_wdt); 598 + bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); 599 + val = *bootcr; 600 + iounmap(bootcr); 601 + 602 + /* Register watchdog only if enabled in hardware */ 603 + if (val & AR7_WDT_HW_ENA) 604 + res = platform_device_register(&ar7_wdt); 600 605 601 606 return res; 602 607 }
+1 -1
arch/mips/bcm63xx/Makefile
··· 1 1 obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ 2 - dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o 2 + dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o 3 3 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 4 4 5 5 obj-y += boards/
-3
arch/mips/bcm63xx/boards/board_bcm963xx.c
··· 24 24 #include <bcm63xx_dev_enet.h> 25 25 #include <bcm63xx_dev_dsp.h> 26 26 #include <bcm63xx_dev_pcmcia.h> 27 - #include <bcm63xx_dev_uart.h> 28 27 #include <board_bcm963xx.h> 29 28 30 29 #define PFX "board_bcm963xx: " ··· 792 793 int __init board_register_devices(void) 793 794 { 794 795 u32 val; 795 - 796 - bcm63xx_uart_register(); 797 796 798 797 if (board.has_pccard) 799 798 bcm63xx_pcmcia_register();
+3
arch/mips/bcm63xx/cpu.c
··· 10 10 #include <linux/kernel.h> 11 11 #include <linux/module.h> 12 12 #include <linux/cpu.h> 13 + #include <asm/cpu-info.h> 13 14 #include <bcm63xx_cpu.h> 14 15 #include <bcm63xx_regs.h> 15 16 #include <bcm63xx_io.h> ··· 285 284 { 286 285 unsigned int tmp, expected_cpu_id; 287 286 struct cpuinfo_mips *c = &current_cpu_data; 287 + unsigned int cpu = smp_processor_id(); 288 288 289 289 /* soc registers location depends on cpu type */ 290 290 expected_cpu_id = 0; ··· 295 293 * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c 296 294 */ 297 295 case CPU_BCM3302: 296 + __cpu_name[cpu] = "Broadcom BCM6338"; 298 297 expected_cpu_id = BCM6338_CPU_ID; 299 298 bcm63xx_regs_base = bcm96338_regs_base; 300 299 bcm63xx_irqs = bcm96338_irqs;
+1 -1
arch/mips/bcm63xx/dev-uart.c
··· 10 10 #include <linux/kernel.h> 11 11 #include <linux/platform_device.h> 12 12 #include <bcm63xx_cpu.h> 13 - #include <bcm63xx_dev_uart.h> 14 13 15 14 static struct resource uart_resources[] = { 16 15 { ··· 38 39 uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0); 39 40 return platform_device_register(&bcm63xx_uart_device); 40 41 } 42 + arch_initcall(bcm63xx_uart_register);
+37
arch/mips/bcm63xx/dev-wdt.c
··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org> 7 + */ 8 + 9 + #include <linux/init.h> 10 + #include <linux/kernel.h> 11 + #include <linux/platform_device.h> 12 + #include <bcm63xx_cpu.h> 13 + 14 + static struct resource wdt_resources[] = { 15 + { 16 + .start = -1, /* filled at runtime */ 17 + .end = -1, /* filled at runtime */ 18 + .flags = IORESOURCE_MEM, 19 + }, 20 + }; 21 + 22 + static struct platform_device bcm63xx_wdt_device = { 23 + .name = "bcm63xx-wdt", 24 + .id = 0, 25 + .num_resources = ARRAY_SIZE(wdt_resources), 26 + .resource = wdt_resources, 27 + }; 28 + 29 + int __init bcm63xx_wdt_register(void) 30 + { 31 + wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT); 32 + wdt_resources[0].end = wdt_resources[0].start; 33 + wdt_resources[0].end += RSET_WDT_SIZE - 1; 34 + 35 + return platform_device_register(&bcm63xx_wdt_device); 36 + } 37 + arch_initcall(bcm63xx_wdt_register);
+3 -1
arch/mips/bcm63xx/setup.c
··· 75 75 bcm6348_a1_reboot(); 76 76 77 77 printk(KERN_INFO "triggering watchdog soft-reset...\n"); 78 - bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG); 78 + reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); 79 + reg |= SYS_PLL_SOFT_RESET; 80 + bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG); 79 81 while (1) 80 82 ; 81 83 }
+184 -40
arch/mips/cavium-octeon/octeon-irq.c
··· 17 17 DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); 18 18 DEFINE_SPINLOCK(octeon_irq_msi_lock); 19 19 20 + static int octeon_coreid_for_cpu(int cpu) 21 + { 22 + #ifdef CONFIG_SMP 23 + return cpu_logical_map(cpu); 24 + #else 25 + return cvmx_get_core_num(); 26 + #endif 27 + } 28 + 20 29 static void octeon_irq_core_ack(unsigned int irq) 21 30 { 22 31 unsigned int bit = irq - OCTEON_IRQ_SW0; ··· 161 152 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ 162 153 unsigned long flags; 163 154 uint64_t en0; 164 - #ifdef CONFIG_SMP 165 155 int cpu; 166 156 write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); 167 157 for_each_online_cpu(cpu) { 168 - int coreid = cpu_logical_map(cpu); 158 + int coreid = octeon_coreid_for_cpu(cpu); 169 159 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 170 160 en0 &= ~(1ull << bit); 171 161 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); ··· 175 167 */ 176 168 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); 177 169 write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); 178 - #else 179 - int coreid = cvmx_get_core_num(); 180 - local_irq_save(flags); 181 - en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 182 - en0 &= ~(1ull << bit); 183 - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); 184 - cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 185 - local_irq_restore(flags); 186 - #endif 170 + } 171 + 172 + /* 173 + * Enable the irq on the current core for chips that have the EN*_W1{S,C} 174 + * registers. 175 + */ 176 + static void octeon_irq_ciu0_enable_v2(unsigned int irq) 177 + { 178 + int index = cvmx_get_core_num() * 2; 179 + u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 180 + 181 + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 182 + } 183 + 184 + /* 185 + * Disable the irq on the current core for chips that have the EN*_W1{S,C} 186 + * registers. 187 + */ 188 + static void octeon_irq_ciu0_disable_v2(unsigned int irq) 189 + { 190 + int index = cvmx_get_core_num() * 2; 191 + u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 192 + 193 + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); 194 + } 195 + 196 + /* 197 + * Disable the irq on the all cores for chips that have the EN*_W1{S,C} 198 + * registers. 199 + */ 200 + static void octeon_irq_ciu0_disable_all_v2(unsigned int irq) 201 + { 202 + u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 203 + int index; 204 + int cpu; 205 + for_each_online_cpu(cpu) { 206 + index = octeon_coreid_for_cpu(cpu) * 2; 207 + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); 208 + } 187 209 } 188 210 189 211 #ifdef CONFIG_SMP 190 212 static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) 191 213 { 192 214 int cpu; 215 + unsigned long flags; 193 216 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ 194 217 195 - write_lock(&octeon_irq_ciu0_rwlock); 218 + write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); 196 219 for_each_online_cpu(cpu) { 197 - int coreid = cpu_logical_map(cpu); 220 + int coreid = octeon_coreid_for_cpu(cpu); 198 221 uint64_t en0 = 199 222 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); 200 223 if (cpumask_test_cpu(cpu, dest)) ··· 239 200 * of them are done. 240 201 */ 241 202 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); 242 - write_unlock(&octeon_irq_ciu0_rwlock); 203 + write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); 243 204 244 205 return 0; 245 206 } 207 + 208 + /* 209 + * Set affinity for the irq for chips that have the EN*_W1{S,C} 210 + * registers. 211 + */ 212 + static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq, 213 + const struct cpumask *dest) 214 + { 215 + int cpu; 216 + int index; 217 + u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); 218 + for_each_online_cpu(cpu) { 219 + index = octeon_coreid_for_cpu(cpu) * 2; 220 + if (cpumask_test_cpu(cpu, dest)) 221 + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); 222 + else 223 + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); 224 + } 225 + return 0; 226 + } 246 227 #endif 228 + 229 + /* 230 + * Newer octeon chips have support for lockless CIU operation. 231 + */ 232 + static struct irq_chip octeon_irq_chip_ciu0_v2 = { 233 + .name = "CIU0", 234 + .enable = octeon_irq_ciu0_enable_v2, 235 + .disable = octeon_irq_ciu0_disable_all_v2, 236 + .ack = octeon_irq_ciu0_disable_v2, 237 + .eoi = octeon_irq_ciu0_enable_v2, 238 + #ifdef CONFIG_SMP 239 + .set_affinity = octeon_irq_ciu0_set_affinity_v2, 240 + #endif 241 + }; 247 242 248 243 static struct irq_chip octeon_irq_chip_ciu0 = { 249 244 .name = "CIU0", ··· 342 269 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ 343 270 unsigned long flags; 344 271 uint64_t en1; 345 - #ifdef CONFIG_SMP 346 272 int cpu; 347 273 write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); 348 274 for_each_online_cpu(cpu) { 349 - int coreid = cpu_logical_map(cpu); 275 + int coreid = octeon_coreid_for_cpu(cpu); 350 276 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 351 277 en1 &= ~(1ull << bit); 352 278 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); ··· 356 284 */ 357 285 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); 358 286 write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); 359 - #else 360 - int coreid = cvmx_get_core_num(); 361 - local_irq_save(flags); 362 - en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 363 - en1 &= ~(1ull << bit); 364 - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); 365 - cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); 366 - local_irq_restore(flags); 367 - #endif 287 + } 288 + 289 + /* 290 + * Enable the irq on the current core for chips that have the EN*_W1{S,C} 291 + * registers. 292 + */ 293 + static void octeon_irq_ciu1_enable_v2(unsigned int irq) 294 + { 295 + int index = cvmx_get_core_num() * 2 + 1; 296 + u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); 297 + 298 + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); 299 + } 300 + 301 + /* 302 + * Disable the irq on the current core for chips that have the EN*_W1{S,C} 303 + * registers. 304 + */ 305 + static void octeon_irq_ciu1_disable_v2(unsigned int irq) 306 + { 307 + int index = cvmx_get_core_num() * 2 + 1; 308 + u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); 309 + 310 + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); 311 + } 312 + 313 + /* 314 + * Disable the irq on the all cores for chips that have the EN*_W1{S,C} 315 + * registers. 316 + */ 317 + static void octeon_irq_ciu1_disable_all_v2(unsigned int irq) 318 + { 319 + u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); 320 + int index; 321 + int cpu; 322 + for_each_online_cpu(cpu) { 323 + index = octeon_coreid_for_cpu(cpu) * 2 + 1; 324 + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); 325 + } 368 326 } 369 327 370 328 #ifdef CONFIG_SMP 371 - static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest) 329 + static int octeon_irq_ciu1_set_affinity(unsigned int irq, 330 + const struct cpumask *dest) 372 331 { 373 332 int cpu; 333 + unsigned long flags; 374 334 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ 375 335 376 - write_lock(&octeon_irq_ciu1_rwlock); 336 + write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); 377 337 for_each_online_cpu(cpu) { 378 - int coreid = cpu_logical_map(cpu); 338 + int coreid = octeon_coreid_for_cpu(cpu); 379 339 uint64_t en1 = 380 340 cvmx_read_csr(CVMX_CIU_INTX_EN1 381 341 (coreid * 2 + 1)); ··· 422 318 * of them are done. 423 319 */ 424 320 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); 425 - write_unlock(&octeon_irq_ciu1_rwlock); 321 + write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); 426 322 427 323 return 0; 428 324 } 325 + 326 + /* 327 + * Set affinity for the irq for chips that have the EN*_W1{S,C} 328 + * registers. 329 + */ 330 + static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq, 331 + const struct cpumask *dest) 332 + { 333 + int cpu; 334 + int index; 335 + u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); 336 + for_each_online_cpu(cpu) { 337 + index = octeon_coreid_for_cpu(cpu) * 2 + 1; 338 + if (cpumask_test_cpu(cpu, dest)) 339 + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); 340 + else 341 + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); 342 + } 343 + return 0; 344 + } 429 345 #endif 346 + 347 + /* 348 + * Newer octeon chips have support for lockless CIU operation. 349 + */ 350 + static struct irq_chip octeon_irq_chip_ciu1_v2 = { 351 + .name = "CIU0", 352 + .enable = octeon_irq_ciu1_enable_v2, 353 + .disable = octeon_irq_ciu1_disable_all_v2, 354 + .ack = octeon_irq_ciu1_disable_v2, 355 + .eoi = octeon_irq_ciu1_enable_v2, 356 + #ifdef CONFIG_SMP 357 + .set_affinity = octeon_irq_ciu1_set_affinity_v2, 358 + #endif 359 + }; 430 360 431 361 static struct irq_chip octeon_irq_chip_ciu1 = { 432 362 .name = "CIU1", ··· 558 420 void __init arch_init_irq(void) 559 421 { 560 422 int irq; 423 + struct irq_chip *chip0; 424 + struct irq_chip *chip1; 561 425 562 426 #ifdef CONFIG_SMP 563 427 /* Set the default affinity to the boot cpu. */ ··· 569 429 570 430 if (NR_IRQS < OCTEON_IRQ_LAST) 571 431 pr_err("octeon_irq_init: NR_IRQS is set too low\n"); 432 + 433 + if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || 434 + OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || 435 + OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) { 436 + chip0 = &octeon_irq_chip_ciu0_v2; 437 + chip1 = &octeon_irq_chip_ciu1_v2; 438 + } else { 439 + chip0 = &octeon_irq_chip_ciu0; 440 + chip1 = &octeon_irq_chip_ciu1; 441 + } 572 442 573 443 /* 0 - 15 reserved for i8259 master and slave controller. */ 574 444 ··· 590 440 591 441 /* 24 - 87 CIU_INT_SUM0 */ 592 442 for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { 593 - set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0, 594 - handle_percpu_irq); 443 + set_irq_chip_and_handler(irq, chip0, handle_percpu_irq); 595 444 } 596 445 597 446 /* 88 - 151 CIU_INT_SUM1 */ 598 447 for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) { 599 - set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1, 600 - handle_percpu_irq); 448 + set_irq_chip_and_handler(irq, chip1, handle_percpu_irq); 601 449 } 602 450 603 451 #ifdef CONFIG_PCI_MSI ··· 653 505 #ifdef CONFIG_HOTPLUG_CPU 654 506 static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu) 655 507 { 656 - unsigned int isset; 657 - #ifdef CONFIG_SMP 658 - int coreid = cpu_logical_map(cpu); 659 - #else 660 - int coreid = cvmx_get_core_num(); 661 - #endif 508 + unsigned int isset; 509 + int coreid = octeon_coreid_for_cpu(cpu); 662 510 int bit = (irq < OCTEON_IRQ_WDOG0) ? 663 - irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0; 511 + irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0; 664 512 if (irq < 64) { 665 513 isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) & 666 514 (1ull << bit)) >> bit;
+3 -2
arch/mips/cavium-octeon/smp.c
··· 65 65 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); 66 66 } 67 67 68 - static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action) 68 + static inline void octeon_send_ipi_mask(const struct cpumask *mask, 69 + unsigned int action) 69 70 { 70 71 unsigned int i; 71 72 72 - for_each_cpu_mask(i, mask) 73 + for_each_cpu_mask(i, *mask) 73 74 octeon_send_ipi_single(i, action); 74 75 } 75 76
+2 -2
arch/mips/include/asm/fixmap.h
··· 48 48 #define FIX_N_COLOURS 8 49 49 FIX_CMAP_BEGIN, 50 50 #ifdef CONFIG_MIPS_MT_SMTC 51 - FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS), 51 + FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS * 2), 52 52 #else 53 - FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS, 53 + FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * 2), 54 54 #endif 55 55 #ifdef CONFIG_HIGHMEM 56 56 /* reserved pte's for temporary kernel mappings */
+12 -6
arch/mips/include/asm/gcmpregs.h
··· 19 19 #define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ 20 20 21 21 /* Offsets to individual GCMP registers from GCMP base */ 22 - #define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) 22 + #define GCMPOFS(block, tag, reg) \ 23 + (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) 24 + #define GCMPOFSn(block, tag, reg, n) \ 25 + (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n)) 23 26 24 27 #define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) 28 + #define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n) 25 29 #define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) 26 30 #define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) 27 31 #define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) 28 32 29 33 /* GCMP register access */ 30 34 #define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) 35 + #define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n)) 31 36 #define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) 32 37 #define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) 33 38 #define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) ··· 54 49 #define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) 55 50 #define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 56 51 #define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) 57 - #define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0 58 - #define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1 59 - #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 60 - #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 52 + #define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0 53 + #define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1 54 + #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 55 + #define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 61 56 #define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ 62 57 #define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ 63 58 #define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 ··· 120 115 #define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ 121 116 122 117 extern int __init gcmp_probe(unsigned long, unsigned long); 123 - 118 + extern int __init gcmp_niocu(void); 119 + extern void __init gcmp_setregion(int, unsigned long, unsigned long, int); 124 120 #endif /* _ASM_GCMPREGS_H */
+18 -170
arch/mips/include/asm/gic.h
··· 12 12 #define _ASM_GICREGS_H 13 13 14 14 #undef GICISBYTELITTLEENDIAN 15 - #define GICISWORDLITTLEENDIAN 16 15 17 16 /* Constants */ 18 17 #define GIC_POL_POS 1 ··· 19 20 #define GIC_TRIG_EDGE 1 20 21 #define GIC_TRIG_LEVEL 0 21 22 22 - #ifdef CONFIG_SMP 23 23 #define GIC_NUM_INTRS (24 + NR_CPUS * 2) 24 - #else 25 - #define GIC_NUM_INTRS 32 26 - #endif 27 24 28 25 #define MSK(n) ((1 << (n)) - 1) 29 26 #define REG32(addr) (*(volatile unsigned int *) (addr)) ··· 65 70 #define USM_VISIBLE_SECTION_SIZE 0x10000 66 71 67 72 /* Register Map for Shared Section */ 68 - #if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN) 69 73 70 74 #define GIC_SH_CONFIG_OFS 0x0000 71 75 72 76 /* Shared Global Counter */ 73 77 #define GIC_SH_COUNTER_31_00_OFS 0x0010 74 78 #define GIC_SH_COUNTER_63_32_OFS 0x0014 79 + #define GIC_SH_REVISIONID_OFS 0x0020 75 80 76 81 /* Interrupt Polarity */ 77 82 #define GIC_SH_POL_31_0_OFS 0x0100 ··· 159 164 (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4)) 160 165 #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) 161 166 167 + /* Convert an interrupt number to a byte offset/bit for multi-word registers */ 168 + #define GIC_INTR_OFS(intr) (((intr) / 32)*4) 169 + #define GIC_INTR_BIT(intr) ((intr) % 32) 170 + 162 171 /* Polarity : Reset Value is always 0 */ 163 172 #define GIC_SH_SET_POLARITY_OFS 0x0100 164 173 #define GIC_SET_POLARITY(intr, pol) \ 165 - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32)) 174 + GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \ 175 + GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr)) 166 176 167 177 /* Triggering : Reset Value is always 0 */ 168 178 #define GIC_SH_SET_TRIGGER_OFS 0x0180 169 179 #define GIC_SET_TRIGGER(intr, trig) \ 170 - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32)) 180 + GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \ 181 + GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr)) 171 182 172 183 /* Mask manipulation */ 173 184 #define GIC_SH_SMASK_OFS 0x0380 174 - #define GIC_SET_INTR_MASK(intr, val) \ 175 - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) 176 - 185 + #define GIC_SET_INTR_MASK(intr) \ 186 + GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \ 187 + GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr)) 177 188 #define GIC_SH_RMASK_OFS 0x0300 178 - #define GIC_CLR_INTR_MASK(intr, val) \ 179 - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) 189 + #define GIC_CLR_INTR_MASK(intr) \ 190 + GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \ 191 + GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr)) 180 192 181 193 /* Register Map for Local Section */ 182 194 #define GIC_VPE_CTL_OFS 0x0000 ··· 220 218 /* User Mode Visible Section Register Map */ 221 219 #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 222 220 #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 223 - 224 - #else /* CONFIG_CPU_BIG_ENDIAN */ 225 - 226 - #define GIC_SH_CONFIG_OFS 0x0000 227 - 228 - /* Shared Global Counter */ 229 - #define GIC_SH_COUNTER_31_00_OFS 0x0014 230 - #define GIC_SH_COUNTER_63_32_OFS 0x0010 231 - 232 - /* Interrupt Polarity */ 233 - #define GIC_SH_POL_31_0_OFS 0x0104 234 - #define GIC_SH_POL_63_32_OFS 0x0100 235 - #define GIC_SH_POL_95_64_OFS 0x010c 236 - #define GIC_SH_POL_127_96_OFS 0x0108 237 - #define GIC_SH_POL_159_128_OFS 0x0114 238 - #define GIC_SH_POL_191_160_OFS 0x0110 239 - #define GIC_SH_POL_223_192_OFS 0x011c 240 - #define GIC_SH_POL_255_224_OFS 0x0118 241 - 242 - /* Edge/Level Triggering */ 243 - #define GIC_SH_TRIG_31_0_OFS 0x0184 244 - #define GIC_SH_TRIG_63_32_OFS 0x0180 245 - #define GIC_SH_TRIG_95_64_OFS 0x018c 246 - #define GIC_SH_TRIG_127_96_OFS 0x0188 247 - #define GIC_SH_TRIG_159_128_OFS 0x0194 248 - #define GIC_SH_TRIG_191_160_OFS 0x0190 249 - #define GIC_SH_TRIG_223_192_OFS 0x019c 250 - #define GIC_SH_TRIG_255_224_OFS 0x0198 251 - 252 - /* Dual Edge Triggering */ 253 - #define GIC_SH_DUAL_31_0_OFS 0x0204 254 - #define GIC_SH_DUAL_63_32_OFS 0x0200 255 - #define GIC_SH_DUAL_95_64_OFS 0x020c 256 - #define GIC_SH_DUAL_127_96_OFS 0x0208 257 - #define GIC_SH_DUAL_159_128_OFS 0x0214 258 - #define GIC_SH_DUAL_191_160_OFS 0x0210 259 - #define GIC_SH_DUAL_223_192_OFS 0x021c 260 - #define GIC_SH_DUAL_255_224_OFS 0x0218 261 - 262 - /* Set/Clear corresponding bit in Edge Detect Register */ 263 - #define GIC_SH_WEDGE_OFS 0x0280 264 - 265 - /* Reset Mask - Disables Interrupt */ 266 - #define GIC_SH_RMASK_31_0_OFS 0x0304 267 - #define GIC_SH_RMASK_63_32_OFS 0x0300 268 - #define GIC_SH_RMASK_95_64_OFS 0x030c 269 - #define GIC_SH_RMASK_127_96_OFS 0x0308 270 - #define GIC_SH_RMASK_159_128_OFS 0x0314 271 - #define GIC_SH_RMASK_191_160_OFS 0x0310 272 - #define GIC_SH_RMASK_223_192_OFS 0x031c 273 - #define GIC_SH_RMASK_255_224_OFS 0x0318 274 - 275 - /* Set Mask (WO) - Enables Interrupt */ 276 - #define GIC_SH_SMASK_31_0_OFS 0x0384 277 - #define GIC_SH_SMASK_63_32_OFS 0x0380 278 - #define GIC_SH_SMASK_95_64_OFS 0x038c 279 - #define GIC_SH_SMASK_127_96_OFS 0x0388 280 - #define GIC_SH_SMASK_159_128_OFS 0x0394 281 - #define GIC_SH_SMASK_191_160_OFS 0x0390 282 - #define GIC_SH_SMASK_223_192_OFS 0x039c 283 - #define GIC_SH_SMASK_255_224_OFS 0x0398 284 - 285 - /* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ 286 - #define GIC_SH_MASK_31_0_OFS 0x0404 287 - #define GIC_SH_MASK_63_32_OFS 0x0400 288 - #define GIC_SH_MASK_95_64_OFS 0x040c 289 - #define GIC_SH_MASK_127_96_OFS 0x0408 290 - #define GIC_SH_MASK_159_128_OFS 0x0414 291 - #define GIC_SH_MASK_191_160_OFS 0x0410 292 - #define GIC_SH_MASK_223_192_OFS 0x041c 293 - #define GIC_SH_MASK_255_224_OFS 0x0418 294 - 295 - /* Pending Global Interrupts (RO) */ 296 - #define GIC_SH_PEND_31_0_OFS 0x0484 297 - #define GIC_SH_PEND_63_32_OFS 0x0480 298 - #define GIC_SH_PEND_95_64_OFS 0x048c 299 - #define GIC_SH_PEND_127_96_OFS 0x0488 300 - #define GIC_SH_PEND_159_128_OFS 0x0494 301 - #define GIC_SH_PEND_191_160_OFS 0x0490 302 - #define GIC_SH_PEND_223_192_OFS 0x049c 303 - #define GIC_SH_PEND_255_224_OFS 0x0498 304 - 305 - #define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 306 - 307 - /* Maps Interrupt X to a Pin */ 308 - #define GIC_SH_MAP_TO_PIN(intr) \ 309 - (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr)) 310 - 311 - #define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004 312 - 313 - /* 314 - * Maps Interrupt X to a VPE. This is more complex than the LE case, as 315 - * odd and even registers need to be transposed. It does work - trust me! 316 - */ 317 - #define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ 318 - (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \ 319 - (((((vpe) / 32) ^ 1) - 1) * 4)) 320 - #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) 321 - 322 - /* Polarity */ 323 - #define GIC_SH_SET_POLARITY_OFS 0x0100 324 - #define GIC_SET_POLARITY(intr, pol) \ 325 - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32)) 326 - 327 - /* Triggering */ 328 - #define GIC_SH_SET_TRIGGER_OFS 0x0180 329 - #define GIC_SET_TRIGGER(intr, trig) \ 330 - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32)) 331 - 332 - /* Mask manipulation */ 333 - #define GIC_SH_SMASK_OFS 0x0380 334 - #define GIC_SET_INTR_MASK(intr, val) \ 335 - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))) 336 - 337 - #define GIC_SH_RMASK_OFS 0x0300 338 - #define GIC_CLR_INTR_MASK(intr, val) \ 339 - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))) 340 - 341 - /* Register Map for Local Section */ 342 - #define GIC_VPE_CTL_OFS 0x0000 343 - #define GIC_VPE_PEND_OFS 0x0004 344 - #define GIC_VPE_MASK_OFS 0x0008 345 - #define GIC_VPE_RMASK_OFS 0x000c 346 - #define GIC_VPE_SMASK_OFS 0x0010 347 - #define GIC_VPE_WD_MAP_OFS 0x0040 348 - #define GIC_VPE_COMPARE_MAP_OFS 0x0044 349 - #define GIC_VPE_TIMER_MAP_OFS 0x0048 350 - #define GIC_VPE_PERFCTR_MAP_OFS 0x0050 351 - #define GIC_VPE_SWINT0_MAP_OFS 0x0054 352 - #define GIC_VPE_SWINT1_MAP_OFS 0x0058 353 - #define GIC_VPE_OTHER_ADDR_OFS 0x0080 354 - #define GIC_VPE_WD_CONFIG0_OFS 0x0090 355 - #define GIC_VPE_WD_COUNT0_OFS 0x0094 356 - #define GIC_VPE_WD_INITIAL0_OFS 0x0098 357 - #define GIC_VPE_COMPARE_LO_OFS 0x00a4 358 - #define GIC_VPE_COMPARE_HI_OFS 0x00a0 359 - 360 - #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 361 - #define GIC_VPE_EIC_SS(intr) \ 362 - (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) 363 - 364 - #define GIC_VPE_EIC_VEC_BASE 0x0800 365 - #define GIC_VPE_EIC_VEC(intr) \ 366 - (GIC_VPE_EIC_VEC_BASE + (4 * intr)) 367 - 368 - #define GIC_VPE_TENABLE_NMI_OFS 0x1000 369 - #define GIC_VPE_TENABLE_YQ_OFS 0x1004 370 - #define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080 371 - #define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084 372 - 373 - /* User Mode Visible Section Register Map */ 374 - #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004 375 - #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000 376 - 377 - #endif /* !LE */ 378 221 379 222 /* Masks */ 380 223 #define GIC_SH_CONFIG_COUNTSTOP_SHF 28 ··· 320 473 * in building ipi_map. 321 474 */ 322 475 struct gic_intr_map { 323 - unsigned int intrnum; /* Ext Intr Num */ 324 476 unsigned int cpunum; /* Directed to this CPU */ 325 477 unsigned int pin; /* Directed to this Pin */ 326 478 unsigned int polarity; /* Polarity : +/- */ 327 479 unsigned int trigtype; /* Trigger : Edge/Levl */ 328 - unsigned int ipiflag; /* Is used for IPI ? */ 480 + unsigned int flags; /* Misc flags */ 481 + #define GIC_FLAG_IPI 0x01 482 + #define GIC_FLAG_TRANSPARENT 0x02 329 483 }; 330 484 331 485 extern void gic_init(unsigned long gic_base_addr,
+3
arch/mips/include/asm/mach-ar7/ar7.h
··· 78 78 #define AR7_REF_CLOCK 25000000 79 79 #define AR7_XTAL_CLOCK 24000000 80 80 81 + /* DCL */ 82 + #define AR7_WDT_HW_ENA 0x10 83 + 81 84 struct plat_cpmac_data { 82 85 int reset_bit; 83 86 int power_bit;
+2
arch/mips/include/asm/mach-au1x00/gpio-au1000.h
··· 104 104 105 105 if ((gpio >= 8) && (gpio <= 15)) 106 106 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */ 107 + 108 + return -ENXIO; 107 109 } 108 110 109 111 #ifdef CONFIG_SOC_AU1100
-6
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h
··· 1 - #ifndef BCM63XX_DEV_UART_H_ 2 - #define BCM63XX_DEV_UART_H_ 3 - 4 - int bcm63xx_uart_register(void); 5 - 6 - #endif /* BCM63XX_DEV_UART_H_ */
+2 -2
arch/mips/include/asm/mach-ip27/topology.h
··· 44 44 .busy_factor = 32, \ 45 45 .imbalance_pct = 125, \ 46 46 .cache_nice_tries = 1, \ 47 - .flags = SD_LOAD_BALANCE \ 48 - | SD_BALANCE_EXEC \ 47 + .flags = SD_LOAD_BALANCE | \ 48 + SD_BALANCE_EXEC, \ 49 49 .last_balance = jiffies, \ 50 50 .balance_interval = 1, \ 51 51 .nr_balance_failed = 0, \
+1 -2
arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
··· 29 29 #define cpu_has_cache_cdex_p 0 30 30 #define cpu_has_cache_cdex_s 0 31 31 #define cpu_has_counter 1 32 - #define cpu_has_dc_aliases 1 32 + #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) 33 33 #define cpu_has_divec 0 34 34 #define cpu_has_dsp 0 35 35 #define cpu_has_ejtag 0 ··· 54 54 #define cpu_has_vce 0 55 55 #define cpu_has_vtag_icache 0 56 56 #define cpu_has_watch 1 57 - #define cpu_icache_snoops_remote_store 1 58 57 59 58 #endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */
+8 -5
arch/mips/include/asm/mmu_context.h
··· 16 16 #include <linux/smp.h> 17 17 #include <linux/slab.h> 18 18 #include <asm/cacheflush.h> 19 + #include <asm/hazards.h> 19 20 #include <asm/tlbflush.h> 20 21 #ifdef CONFIG_MIPS_MT_SMTC 21 22 #include <asm/mipsmtregs.h> ··· 37 36 #ifdef CONFIG_32BIT 38 37 #define TLBMISS_HANDLER_SETUP() \ 39 38 write_c0_context((unsigned long) smp_processor_id() << 25); \ 39 + back_to_back_c0_hazard(); \ 40 40 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 41 41 #endif 42 42 #ifdef CONFIG_64BIT 43 43 #define TLBMISS_HANDLER_SETUP() \ 44 44 write_c0_context((unsigned long) smp_processor_id() << 26); \ 45 + back_to_back_c0_hazard(); \ 45 46 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) 46 47 #endif 47 48 ··· 168 165 * having ASID_MASK smaller than the hardware maximum, 169 166 * make sure no "soft" bits become "hard"... 170 167 */ 171 - write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) 172 - | (cpu_context(cpu, next) & ASID_MASK)); 168 + write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 169 + cpu_asid(cpu, next)); 173 170 ehb(); /* Make sure it propagates to TCStatus */ 174 171 evpe(mtflags); 175 172 #else 176 - write_c0_entryhi(cpu_context(cpu, next)); 173 + write_c0_entryhi(cpu_asid(cpu, next)); 177 174 #endif /* CONFIG_MIPS_MT_SMTC */ 178 175 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 179 176 ··· 229 226 } 230 227 /* See comments for similar code above */ 231 228 write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | 232 - (cpu_context(cpu, next) & ASID_MASK)); 229 + cpu_asid(cpu, next)); 233 230 ehb(); /* Make sure it propagates to TCStatus */ 234 231 evpe(mtflags); 235 232 #else 236 - write_c0_entryhi(cpu_context(cpu, next)); 233 + write_c0_entryhi(cpu_asid(cpu, next)); 237 234 #endif /* CONFIG_MIPS_MT_SMTC */ 238 235 TLBMISS_HANDLER_SETUP_PGD(next->pgd); 239 236
+1 -1
arch/mips/include/asm/setup.h
··· 1 1 #ifndef _MIPS_SETUP_H 2 2 #define _MIPS_SETUP_H 3 3 4 - #define COMMAND_LINE_SIZE 256 4 + #define COMMAND_LINE_SIZE 4096 5 5 6 6 #ifdef __KERNEL__ 7 7 extern void setup_early_printk(void);
+1
arch/mips/include/asm/smtc_ipi.h
··· 45 45 spinlock_t lock; 46 46 struct smtc_ipi *tail; 47 47 int depth; 48 + int resched_flag; /* reschedule already queued */ 48 49 }; 49 50 50 51 static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p)
+10
arch/mips/include/asm/spram.h
··· 1 + #ifndef _MIPS_SPRAM_H 2 + #define _MIPS_SPRAM_H 3 + 4 + #ifdef CONFIG_CPU_MIPSR2 5 + extern __init void spram_config(void); 6 + #else 7 + static inline void spram_config(void) { }; 8 + #endif /* CONFIG_CPU_MIPSR2 */ 9 + 10 + #endif /* _MIPS_SPRAM_H */
+1 -8
arch/mips/include/asm/thread_info.h
··· 86 86 #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR 87 87 88 88 #ifdef CONFIG_DEBUG_STACK_USAGE 89 - #define alloc_thread_info(tsk) \ 90 - ({ \ 91 - struct thread_info *ret; \ 92 - \ 93 - ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \ 94 - \ 95 - ret; \ 96 - }) 89 + #define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL) 97 90 #else 98 91 #define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) 99 92 #endif
+1 -1
arch/mips/jazz/irq.c
··· 134 134 135 135 static struct irqaction r4030_timer_irqaction = { 136 136 .handler = r4030_timer_interrupt, 137 - .flags = IRQF_DISABLED, 137 + .flags = IRQF_DISABLED | IRQF_TIMER, 138 138 .name = "R4030 timer", 139 139 }; 140 140
+1 -1
arch/mips/kernel/cevt-bcm1480.c
··· 144 144 bcm1480_unmask_irq(cpu, irq); 145 145 146 146 action->handler = sibyte_counter_handler; 147 - action->flags = IRQF_DISABLED | IRQF_PERCPU; 147 + action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER; 148 148 action->name = name; 149 149 action->dev_id = cd; 150 150
+1 -1
arch/mips/kernel/cevt-ds1287.c
··· 107 107 108 108 static struct irqaction ds1287_irqaction = { 109 109 .handler = ds1287_interrupt, 110 - .flags = IRQF_DISABLED | IRQF_PERCPU, 110 + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 111 111 .name = "ds1287", 112 112 }; 113 113
+1 -1
arch/mips/kernel/cevt-gt641xx.c
··· 113 113 114 114 static struct irqaction gt641xx_timer0_irqaction = { 115 115 .handler = gt641xx_timer0_interrupt, 116 - .flags = IRQF_DISABLED | IRQF_PERCPU, 116 + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 117 117 .name = "gt641xx_timer0", 118 118 }; 119 119
+1 -1
arch/mips/kernel/cevt-r4k.c
··· 83 83 84 84 struct irqaction c0_compare_irqaction = { 85 85 .handler = c0_compare_interrupt, 86 - .flags = IRQF_DISABLED | IRQF_PERCPU, 86 + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 87 87 .name = "timer", 88 88 }; 89 89
+1 -1
arch/mips/kernel/cevt-sb1250.c
··· 143 143 sb1250_unmask_irq(cpu, irq); 144 144 145 145 action->handler = sibyte_counter_handler; 146 - action->flags = IRQF_DISABLED | IRQF_PERCPU; 146 + action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER; 147 147 action->name = name; 148 148 action->dev_id = cd; 149 149
+1 -1
arch/mips/kernel/cevt-txx9.c
··· 146 146 147 147 static struct irqaction txx9tmr_irq = { 148 148 .handler = txx9tmr_interrupt, 149 - .flags = IRQF_DISABLED | IRQF_PERCPU, 149 + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 150 150 .name = "txx9tmr", 151 151 .dev_id = &txx9_clock_event_device, 152 152 };
+1 -7
arch/mips/kernel/cpu-probe.c
··· 23 23 #include <asm/mipsregs.h> 24 24 #include <asm/system.h> 25 25 #include <asm/watch.h> 26 - 26 + #include <asm/spram.h> 27 27 /* 28 28 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, 29 29 * the implementation of the "wait" feature differs between CPU families. This ··· 710 710 711 711 mips_probe_watch_registers(c); 712 712 } 713 - 714 - #ifdef CONFIG_CPU_MIPSR2 715 - extern void spram_config(void); 716 - #else 717 - static inline void spram_config(void) {} 718 - #endif 719 713 720 714 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 721 715 {
+1
arch/mips/kernel/head.S
··· 191 191 /* Set the SP after an empty pt_regs. */ 192 192 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE 193 193 PTR_ADDU sp, $28 194 + back_to_back_c0_hazard 194 195 set_saved_sp sp, t0, t1 195 196 PTR_SUBU sp, 4 * SZREG # init stack pointer 196 197
+1 -1
arch/mips/kernel/i8253.c
··· 98 98 99 99 static struct irqaction irq0 = { 100 100 .handler = timer_interrupt, 101 - .flags = IRQF_DISABLED | IRQF_NOBALANCING, 101 + .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER, 102 102 .name = "timer" 103 103 }; 104 104
+43 -71
arch/mips/kernel/irq-gic.c
··· 14 14 15 15 16 16 static unsigned long _gic_base; 17 - static unsigned int _irqbase, _mapsize, numvpes, numintrs; 18 - static struct gic_intr_map *_intrmap; 17 + static unsigned int _irqbase; 18 + static unsigned int gic_irq_flags[GIC_NUM_INTRS]; 19 + #define GIC_IRQ_FLAG_EDGE 0x0001 19 20 20 - static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; 21 + struct gic_pcpu_mask pcpu_masks[NR_CPUS]; 21 22 static struct gic_pending_regs pending_regs[NR_CPUS]; 22 23 static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; 23 24 24 - #define gic_wedgeb2bok 0 /* 25 - * Can GIC handle b2b writes to wedge register? 26 - */ 27 - #if gic_wedgeb2bok == 0 28 - static DEFINE_SPINLOCK(gic_wedgeb2b_lock); 29 - #endif 30 - 31 25 void gic_send_ipi(unsigned int intr) 32 26 { 33 - #if gic_wedgeb2bok == 0 34 - unsigned long flags; 35 - #endif 36 27 pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__, 37 28 read_c0_status()); 38 - if (!gic_wedgeb2bok) 39 - spin_lock_irqsave(&gic_wedgeb2b_lock, flags); 40 29 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); 41 - if (!gic_wedgeb2bok) { 42 - (void) GIC_REG(SHARED, GIC_SH_CONFIG); 43 - spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags); 44 - } 45 30 } 46 31 47 32 /* This is Malta specific and needs to be exported */ 48 - static void vpe_local_setup(unsigned int numvpes) 33 + static void __init vpe_local_setup(unsigned int numvpes) 49 34 { 50 35 int i; 51 36 unsigned long timer_interrupt = 5, perf_interrupt = 5; ··· 90 105 91 106 static unsigned int gic_irq_startup(unsigned int irq) 92 107 { 93 - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 94 108 irq -= _irqbase; 95 - GIC_SET_INTR_MASK(irq, 1); 109 + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 110 + GIC_SET_INTR_MASK(irq); 96 111 return 0; 97 112 } 98 113 99 114 static void gic_irq_ack(unsigned int irq) 100 115 { 101 - #if gic_wedgeb2bok == 0 102 - unsigned long flags; 103 - #endif 104 - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 105 116 irq -= _irqbase; 106 - GIC_CLR_INTR_MASK(irq, 1); 117 + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 118 + GIC_CLR_INTR_MASK(irq); 107 119 108 - if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) { 109 - if (!gic_wedgeb2bok) 110 - spin_lock_irqsave(&gic_wedgeb2b_lock, flags); 120 + if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE) 111 121 GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); 112 - if (!gic_wedgeb2bok) { 113 - (void) GIC_REG(SHARED, GIC_SH_CONFIG); 114 - spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags); 115 - } 116 - } 117 122 } 118 123 119 124 static void gic_mask_irq(unsigned int irq) 120 125 { 121 - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 122 126 irq -= _irqbase; 123 - GIC_CLR_INTR_MASK(irq, 1); 127 + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 128 + GIC_CLR_INTR_MASK(irq); 124 129 } 125 130 126 131 static void gic_unmask_irq(unsigned int irq) 127 132 { 128 - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 129 133 irq -= _irqbase; 130 - GIC_SET_INTR_MASK(irq, 1); 134 + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); 135 + GIC_SET_INTR_MASK(irq); 131 136 } 132 137 133 138 #ifdef CONFIG_SMP ··· 130 155 unsigned long flags; 131 156 int i; 132 157 133 - pr_debug(KERN_DEBUG "%s called\n", __func__); 134 158 irq -= _irqbase; 135 - 159 + pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq); 136 160 cpumask_and(&tmp, cpumask, cpu_online_mask); 137 161 if (cpus_empty(tmp)) 138 162 return -1; ··· 141 167 for (;;) { 142 168 /* Re-route this IRQ */ 143 169 GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp)); 144 - 145 - /* 146 - * FIXME: assumption that _intrmap is ordered and has no holes 147 - */ 148 - 149 - /* Update the intr_map */ 150 - _intrmap[irq].cpunum = first_cpu(tmp); 151 170 152 171 /* Update the pcpu_masks */ 153 172 for (i = 0; i < NR_CPUS; i++) ··· 168 201 #endif 169 202 }; 170 203 171 - static void __init setup_intr(unsigned int intr, unsigned int cpu, 172 - unsigned int pin, unsigned int polarity, unsigned int trigtype) 204 + static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, 205 + unsigned int pin, unsigned int polarity, unsigned int trigtype, 206 + unsigned int flags) 173 207 { 174 208 /* Setup Intr to Pin mapping */ 175 209 if (pin & GIC_MAP_TO_NMI_MSK) { ··· 195 227 GIC_SET_TRIGGER(intr, trigtype); 196 228 197 229 /* Init Intr Masks */ 198 - GIC_SET_INTR_MASK(intr, 0); 230 + GIC_CLR_INTR_MASK(intr); 231 + /* Initialise per-cpu Interrupt software masks */ 232 + if (flags & GIC_FLAG_IPI) 233 + set_bit(intr, pcpu_masks[cpu].pcpu_mask); 234 + if (flags & GIC_FLAG_TRANSPARENT) 235 + GIC_SET_INTR_MASK(intr); 236 + if (trigtype == GIC_TRIG_EDGE) 237 + gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE; 199 238 } 200 239 201 - static void __init gic_basic_init(void) 240 + static void __init gic_basic_init(int numintrs, int numvpes, 241 + struct gic_intr_map *intrmap, int mapsize) 202 242 { 203 243 unsigned int i, cpu; 204 244 205 245 /* Setup defaults */ 206 - for (i = 0; i < GIC_NUM_INTRS; i++) { 246 + for (i = 0; i < numintrs; i++) { 207 247 GIC_SET_POLARITY(i, GIC_POL_POS); 208 248 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL); 209 - GIC_SET_INTR_MASK(i, 0); 249 + GIC_CLR_INTR_MASK(i); 250 + if (i < GIC_NUM_INTRS) 251 + gic_irq_flags[i] = 0; 210 252 } 211 253 212 254 /* Setup specifics */ 213 - for (i = 0; i < _mapsize; i++) { 214 - cpu = _intrmap[i].cpunum; 255 + for (i = 0; i < mapsize; i++) { 256 + cpu = intrmap[i].cpunum; 215 257 if (cpu == X) 216 258 continue; 217 - 218 - if (cpu == 0 && i != 0 && _intrmap[i].intrnum == 0 && 219 - _intrmap[i].ipiflag == 0) 259 + if (cpu == 0 && i != 0 && intrmap[i].flags == 0) 220 260 continue; 221 - 222 - setup_intr(_intrmap[i].intrnum, 223 - _intrmap[i].cpunum, 224 - _intrmap[i].pin, 225 - _intrmap[i].polarity, 226 - _intrmap[i].trigtype); 227 - /* Initialise per-cpu Interrupt software masks */ 228 - if (_intrmap[i].ipiflag) 229 - set_bit(_intrmap[i].intrnum, pcpu_masks[cpu].pcpu_mask); 261 + gic_setup_intr(i, 262 + intrmap[i].cpunum, 263 + intrmap[i].pin, 264 + intrmap[i].polarity, 265 + intrmap[i].trigtype, 266 + intrmap[i].flags); 230 267 } 231 268 232 269 vpe_local_setup(numvpes); ··· 246 273 unsigned int irqbase) 247 274 { 248 275 unsigned int gicconfig; 276 + int numvpes, numintrs; 249 277 250 278 _gic_base = (unsigned long) ioremap_nocache(gic_base_addr, 251 279 gic_addrspace_size); 252 280 _irqbase = irqbase; 253 - _intrmap = intr_map; 254 - _mapsize = intr_map_size; 255 281 256 282 GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); 257 283 numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> ··· 262 290 263 291 pr_debug("%s called\n", __func__); 264 292 265 - gic_basic_init(); 293 + gic_basic_init(numintrs, numvpes, intr_map, intr_map_size); 266 294 }
+6
arch/mips/kernel/linux32.c
··· 428 428 return do_fork(clone_flags, newsp, &regs, 0, 429 429 parent_tidptr, child_tidptr); 430 430 } 431 + 432 + asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf, 433 + size_t len) 434 + { 435 + return sys_lookup_dcookie(merge_64(a0, a1), buf, len); 436 + }
+2 -2
arch/mips/kernel/scall64-o32.S
··· 450 450 PTR sys_io_submit 451 451 PTR sys_io_cancel /* 4245 */ 452 452 PTR sys_exit_group 453 - PTR sys_lookup_dcookie 453 + PTR sys32_lookup_dcookie 454 454 PTR sys_epoll_create 455 455 PTR sys_epoll_ctl 456 456 PTR sys_epoll_wait /* 4250 */ ··· 505 505 PTR sys_fchmodat 506 506 PTR sys_faccessat /* 4300 */ 507 507 PTR compat_sys_pselect6 508 - PTR sys_ppoll 508 + PTR compat_sys_ppoll 509 509 PTR sys_unshare 510 510 PTR sys_splice 511 511 PTR sys32_sync_file_range /* 4305 */
+30 -4
arch/mips/kernel/smtc.c
··· 75 75 76 76 asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; 77 77 78 - 79 78 /* 80 79 * Number of InterProcessor Interrupt (IPI) message buffers to allocate 81 80 */ ··· 387 388 IPIQ[i].head = IPIQ[i].tail = NULL; 388 389 spin_lock_init(&IPIQ[i].lock); 389 390 IPIQ[i].depth = 0; 391 + IPIQ[i].resched_flag = 0; /* No reschedules queued initially */ 390 392 } 391 393 392 394 /* cpu_data index starts at zero */ ··· 741 741 static void smtc_ipi_qdump(void) 742 742 { 743 743 int i; 744 + struct smtc_ipi *temp; 744 745 745 746 for (i = 0; i < NR_CPUS ;i++) { 746 - printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", 747 + pr_info("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", 747 748 i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail, 748 749 IPIQ[i].depth); 750 + temp = IPIQ[i].head; 751 + 752 + while (temp != IPIQ[i].tail) { 753 + pr_debug("%d %d %d: ", temp->type, temp->dest, 754 + (int)temp->arg); 755 + #ifdef SMTC_IPI_DEBUG 756 + pr_debug("%u %lu\n", temp->sender, temp->stamp); 757 + #else 758 + pr_debug("\n"); 759 + #endif 760 + temp = temp->flink; 761 + } 749 762 } 750 763 } 751 764 ··· 797 784 int mtflags; 798 785 unsigned long tcrestart; 799 786 extern void r4k_wait_irqoff(void), __pastwait(void); 787 + int set_resched_flag = (type == LINUX_SMP_IPI && 788 + action == SMP_RESCHEDULE_YOURSELF); 800 789 801 790 if (cpu == smp_processor_id()) { 802 791 printk("Cannot Send IPI to self!\n"); 803 792 return; 804 793 } 794 + if (set_resched_flag && IPIQ[cpu].resched_flag != 0) 795 + return; /* There is a reschedule queued already */ 796 + 805 797 /* Set up a descriptor, to be delivered either promptly or queued */ 806 798 pipi = smtc_ipi_dq(&freeIPIq); 807 799 if (pipi == NULL) { ··· 819 801 pipi->dest = cpu; 820 802 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { 821 803 /* If not on same VPE, enqueue and send cross-VPE interrupt */ 804 + IPIQ[cpu].resched_flag |= set_resched_flag; 822 805 smtc_ipi_nq(&IPIQ[cpu], pipi); 823 806 LOCK_CORE_PRA(); 824 807 settc(cpu_data[cpu].tc_id); ··· 866 847 */ 867 848 write_tc_c0_tchalt(0); 868 849 UNLOCK_CORE_PRA(); 850 + IPIQ[cpu].resched_flag |= set_resched_flag; 869 851 smtc_ipi_nq(&IPIQ[cpu], pipi); 870 852 } else { 871 853 postdirect: ··· 1016 996 * already enabled. 1017 997 */ 1018 998 local_irq_save(flags); 1019 - 1020 999 spin_lock(&q->lock); 1021 1000 pipi = __smtc_ipi_dq(q); 1022 1001 spin_unlock(&q->lock); 1023 - if (pipi != NULL) 1002 + if (pipi != NULL) { 1003 + if (pipi->type == LINUX_SMP_IPI && 1004 + (int)pipi->arg == SMP_RESCHEDULE_YOURSELF) 1005 + IPIQ[cpu].resched_flag = 0; 1024 1006 ipi_decode(pipi); 1007 + } 1025 1008 /* 1026 1009 * The use of the __raw_local restore isn't 1027 1010 * as obviously necessary here as in smtc_ipi_replay(), ··· 1105 1082 * with interrupts off 1106 1083 */ 1107 1084 local_irq_save(flags); 1085 + if (pipi->type == LINUX_SMP_IPI && 1086 + (int)pipi->arg == SMP_RESCHEDULE_YOURSELF) 1087 + IPIQ[cpu].resched_flag = 0; 1108 1088 ipi_decode(pipi); 1109 1089 local_irq_restore(flags); 1110 1090 }
+2 -3
arch/mips/kernel/spram.c
··· 13 13 #include <linux/ptrace.h> 14 14 #include <linux/stddef.h> 15 15 16 - #include <asm/cpu.h> 17 16 #include <asm/fpu.h> 18 17 #include <asm/mipsregs.h> 19 18 #include <asm/system.h> ··· 197 198 offset += 2 * SPRAM_TAG_STRIDE; 198 199 } 199 200 } 200 - 201 - __cpuinit void spram_config(void) 201 + void __cpuinit spram_config(void) 202 202 { 203 203 struct cpuinfo_mips *c = &current_cpu_data; 204 204 unsigned int config0; ··· 206 208 case CPU_24K: 207 209 case CPU_34K: 208 210 case CPU_74K: 211 + case CPU_1004K: 209 212 config0 = read_c0_config(); 210 213 /* FIXME: addresses are Malta specific */ 211 214 if (config0 & (1<<24)) {
-2
arch/mips/kernel/vpe.c
··· 1116 1116 v->shared_ptr = NULL; 1117 1117 v->__start = 0; 1118 1118 1119 - unlock_kernel(); 1120 - 1121 1119 return 0; 1122 1120 } 1123 1121
-1
arch/mips/loongson/common/irq.c
··· 55 55 * int-handler is not on bootstrap 56 56 */ 57 57 clear_c0_status(ST0_IM | ST0_BEV); 58 - local_irq_disable(); 59 58 60 59 /* setting irq trigger mode */ 61 60 set_irq_trigger_mode();
+4 -9
arch/mips/math-emu/dp_simple.c
··· 62 62 return ieee754dp_nanxcpt(y, "neg"); 63 63 } 64 64 65 - if (ieee754dp_isnan(x)) /* but not infinity */ 66 - return ieee754dp_nanxcpt(x, "neg", x); 67 65 return x; 68 66 } 69 67 ··· 74 76 CLEARCX; 75 77 FLUSHXDP; 76 78 79 + /* Clear sign ALWAYS, irrespective of NaN */ 80 + DPSIGN(x) = 0; 81 + 77 82 if (xc == IEEE754_CLASS_SNAN) { 78 - SETCX(IEEE754_INVALID_OPERATION); 79 - return ieee754dp_nanxcpt(ieee754dp_indef(), "neg"); 83 + return ieee754dp_nanxcpt(ieee754dp_indef(), "abs"); 80 84 } 81 85 82 - if (ieee754dp_isnan(x)) /* but not infinity */ 83 - return ieee754dp_nanxcpt(x, "abs", x); 84 - 85 - /* quick fix up */ 86 - DPSIGN(x) = 0; 87 86 return x; 88 87 }
+3 -8
arch/mips/math-emu/sp_simple.c
··· 62 62 return ieee754sp_nanxcpt(y, "neg"); 63 63 } 64 64 65 - if (ieee754sp_isnan(x)) /* but not infinity */ 66 - return ieee754sp_nanxcpt(x, "neg", x); 67 65 return x; 68 66 } 69 67 ··· 74 76 CLEARCX; 75 77 FLUSHXSP; 76 78 79 + /* Clear sign ALWAYS, irrespective of NaN */ 80 + SPSIGN(x) = 0; 81 + 77 82 if (xc == IEEE754_CLASS_SNAN) { 78 - SETCX(IEEE754_INVALID_OPERATION); 79 83 return ieee754sp_nanxcpt(ieee754sp_indef(), "abs"); 80 84 } 81 85 82 - if (ieee754sp_isnan(x)) /* but not infinity */ 83 - return ieee754sp_nanxcpt(x, "abs", x); 84 - 85 - /* quick fix up */ 86 - SPSIGN(x) = 0; 87 86 return x; 88 87 }
+5 -1
arch/mips/mm/init.c
··· 27 27 #include <linux/swap.h> 28 28 #include <linux/proc_fs.h> 29 29 #include <linux/pfn.h> 30 + #include <linux/hardirq.h> 30 31 31 32 #include <asm/asm-offsets.h> 32 33 #include <asm/bootinfo.h> ··· 133 132 inc_preempt_count(); 134 133 idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); 135 134 #ifdef CONFIG_MIPS_MT_SMTC 136 - idx += FIX_N_COLOURS * smp_processor_id(); 135 + idx += FIX_N_COLOURS * smp_processor_id() + 136 + (in_interrupt() ? (FIX_N_COLOURS * NR_CPUS) : 0); 137 + #else 138 + idx += in_interrupt() ? FIX_N_COLOURS : 0; 137 139 #endif 138 140 vaddr = __fix_to_virt(FIX_CMAP_END - idx); 139 141 pte = mk_pte(page, PAGE_KERNEL);
+4 -3
arch/mips/mti-malta/malta-amon.c
··· 70 70 launch->sp = sp; 71 71 launch->a0 = a0; 72 72 73 - /* Make sure target sees parameters before the go bit */ 74 - smp_mb(); 75 - 73 + smp_wmb(); /* Target must see parameters before go */ 76 74 launch->flags |= LAUNCH_FGO; 75 + smp_wmb(); /* Target must see go before we poll */ 76 + 77 77 while ((launch->flags & LAUNCH_FGONE) == 0) 78 78 ; 79 + smp_rmb(); /* Target will be updating flags soon */ 79 80 pr_debug("launch: cpu%d gone!\n", cpu); 80 81 }
+72 -47
arch/mips/mti-malta/malta-int.c
··· 87 87 dummy = BONITO_PCIMAP_CFG; 88 88 iob(); /* sync */ 89 89 90 - irq = readl((u32 *)_pcictrl_bonito_pcicfg); 90 + irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); 91 91 iob(); /* sync */ 92 92 irq &= 0xff; 93 93 BONITO_PCIMAP_CFG = 0; ··· 379 379 380 380 static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); 381 381 382 - #if defined(CONFIG_MIPS_MT_SMP) 383 382 /* 384 383 * This GIC specific tabular array defines the association between External 385 384 * Interrupts and CPUs/Core Interrupts. The nature of the External 386 385 * Interrupts is also defined here - polarity/trigger. 387 386 */ 387 + 388 + #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK 388 389 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { 389 - { GIC_EXT_INTR(0), X, X, X, X, 0 }, 390 - { GIC_EXT_INTR(1), X, X, X, X, 0 }, 391 - { GIC_EXT_INTR(2), X, X, X, X, 0 }, 392 - { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 393 - { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 394 - { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 395 - { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 396 - { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 397 - { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 398 - { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 399 - { GIC_EXT_INTR(10), X, X, X, X, 0 }, 400 - { GIC_EXT_INTR(11), X, X, X, X, 0 }, 401 - { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 402 - { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 403 - { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, 404 - { GIC_EXT_INTR(15), X, X, X, X, 0 }, 405 - /* This is the end of the general interrupts now we do IPI ones */ 390 + { X, X, X, X, 0 }, 391 + { X, X, X, X, 0 }, 392 + { X, X, X, X, 0 }, 393 + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 394 + { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 395 + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 396 + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 397 + { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 398 + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 399 + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 400 + { X, X, X, X, 0 }, 401 + { X, X, X, X, 0 }, 402 + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 403 + { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 404 + { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, 405 + { X, X, X, X, 0 }, 406 + /* The remainder of this table is initialised by fill_ipi_map */ 406 407 }; 407 - #endif 408 408 409 409 /* 410 410 * GCMP needs to be detected before any SMP initialisation 411 411 */ 412 412 int __init gcmp_probe(unsigned long addr, unsigned long size) 413 413 { 414 + if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) { 415 + gcmp_present = 0; 416 + return gcmp_present; 417 + } 418 + 414 419 if (gcmp_present >= 0) 415 420 return gcmp_present; 416 421 ··· 424 419 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; 425 420 426 421 if (gcmp_present) 427 - printk(KERN_DEBUG "GCMP present\n"); 422 + pr_debug("GCMP present\n"); 428 423 return gcmp_present; 424 + } 425 + 426 + /* Return the number of IOCU's present */ 427 + int __init gcmp_niocu(void) 428 + { 429 + return gcmp_present ? 430 + (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF : 431 + 0; 432 + } 433 + 434 + /* Set GCMP region attributes */ 435 + void __init gcmp_setregion(int region, unsigned long base, 436 + unsigned long mask, int type) 437 + { 438 + GCMPGCBn(CMxBASE, region) = base; 439 + GCMPGCBn(CMxMASK, region) = mask | type; 429 440 } 430 441 431 442 #if defined(CONFIG_MIPS_MT_SMP) 432 443 static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) 433 444 { 434 445 int intr = baseintr + cpu; 435 - gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr); 436 446 gic_intr_map[intr].cpunum = cpu; 437 447 gic_intr_map[intr].pin = cpupin; 438 448 gic_intr_map[intr].polarity = GIC_POL_POS; 439 449 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; 440 - gic_intr_map[intr].ipiflag = 1; 450 + gic_intr_map[intr].flags = GIC_FLAG_IPI; 441 451 ipi_map[cpu] |= (1 << (cpupin + 2)); 442 452 } 443 453 ··· 467 447 } 468 448 #endif 469 449 450 + void __init arch_init_ipiirq(int irq, struct irqaction *action) 451 + { 452 + setup_irq(irq, action); 453 + set_irq_handler(irq, handle_percpu_irq); 454 + } 455 + 470 456 void __init arch_init_irq(void) 471 457 { 472 458 init_i8259_irqs(); ··· 484 458 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; 485 459 gic_present = 1; 486 460 } else { 487 - _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); 488 - gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & 489 - MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; 461 + if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { 462 + _msc01_biu_base = (unsigned long) 463 + ioremap_nocache(MSC01_BIU_REG_BASE, 464 + MSC01_BIU_ADDRSPACE_SZ); 465 + gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & 466 + MSC01_SC_CFG_GICPRES_MSK) >> 467 + MSC01_SC_CFG_GICPRES_SHF; 468 + } 490 469 } 491 470 if (gic_present) 492 - printk(KERN_DEBUG "GIC present\n"); 471 + pr_debug("GIC present\n"); 493 472 494 473 switch (mips_revision_sconid) { 495 474 case MIPS_REVISION_SCON_SOCIT: ··· 557 526 &corehi_irqaction); 558 527 } 559 528 560 - #if defined(CONFIG_MIPS_MT_SMP) 561 529 if (gic_present) { 562 530 /* FIXME */ 563 531 int i; 564 - 532 + #if defined(CONFIG_MIPS_MT_SMP) 565 533 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; 566 534 gic_resched_int_base = gic_call_int_base - NR_CPUS; 567 - 568 535 fill_ipi_map(); 569 - gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); 536 + #endif 537 + gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, 538 + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); 570 539 if (!gcmp_present) { 571 540 /* Enable the GIC */ 572 541 i = REG(_msc01_biu_base, MSC01_SC_CFG); ··· 574 543 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); 575 544 pr_debug("GIC Enabled\n"); 576 545 } 577 - 546 + #if defined(CONFIG_MIPS_MT_SMP) 578 547 /* set up ipi interrupts */ 579 548 if (cpu_has_vint) { 580 549 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); ··· 587 556 write_c0_status(0x1100dc00); 588 557 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); 589 558 for (i = 0; i < NR_CPUS; i++) { 590 - setup_irq(MIPS_GIC_IRQ_BASE + 591 - GIC_RESCHED_INT(i), &irq_resched); 592 - setup_irq(MIPS_GIC_IRQ_BASE + 593 - GIC_CALL_INT(i), &irq_call); 594 - set_irq_handler(MIPS_GIC_IRQ_BASE + 595 - GIC_RESCHED_INT(i), handle_percpu_irq); 596 - set_irq_handler(MIPS_GIC_IRQ_BASE + 597 - GIC_CALL_INT(i), handle_percpu_irq); 559 + arch_init_ipiirq(MIPS_GIC_IRQ_BASE + 560 + GIC_RESCHED_INT(i), &irq_resched); 561 + arch_init_ipiirq(MIPS_GIC_IRQ_BASE + 562 + GIC_CALL_INT(i), &irq_call); 598 563 } 564 + #endif 599 565 } else { 566 + #if defined(CONFIG_MIPS_MT_SMP) 600 567 /* set up ipi interrupts */ 601 568 if (cpu_has_veic) { 602 569 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); ··· 609 580 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 610 581 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; 611 582 } 612 - 613 - setup_irq(cpu_ipi_resched_irq, &irq_resched); 614 - setup_irq(cpu_ipi_call_irq, &irq_call); 615 - 616 - set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); 617 - set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); 618 - } 583 + arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); 584 + arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); 619 585 #endif 586 + } 620 587 } 621 588 622 589 void malta_be_init(void)
+24 -3
arch/mips/mti-malta/malta-pci.c
··· 27 27 #include <linux/init.h> 28 28 29 29 #include <asm/gt64120.h> 30 - 30 + #include <asm/gcmpregs.h> 31 31 #include <asm/mips-boards/generic.h> 32 32 #include <asm/mips-boards/bonito64.h> 33 33 #include <asm/mips-boards/msc01_pci.h> ··· 201 201 msc_mem_resource.start = start & mask; 202 202 msc_mem_resource.end = (start & mask) | ~mask; 203 203 msc_controller.mem_offset = (start & mask) - (map & mask); 204 - 204 + #ifdef CONFIG_MIPS_CMP 205 + if (gcmp_niocu()) 206 + gcmp_setregion(0, start, mask, 207 + GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); 208 + #endif 205 209 MSC_READ(MSC01_PCI_SC2PIOBASL, start); 206 210 MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); 207 211 MSC_READ(MSC01_PCI_SC2PIOMAPL, map); ··· 213 209 msc_io_resource.end = (map & mask) | ~mask; 214 210 msc_controller.io_offset = 0; 215 211 ioport_resource.end = ~mask; 216 - 212 + #ifdef CONFIG_MIPS_CMP 213 + if (gcmp_niocu()) 214 + gcmp_setregion(1, start, mask, 215 + GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); 216 + #endif 217 217 /* If ranges overlap I/O takes precedence. */ 218 218 start = start & mask; 219 219 end = start | ~mask; ··· 249 241 250 242 register_pci_controller(controller); 251 243 } 244 + 245 + /* Enable PCI 2.1 compatibility in PIIX4 */ 246 + static void __init quirk_dlcsetup(struct pci_dev *dev) 247 + { 248 + u8 odlc, ndlc; 249 + (void) pci_read_config_byte(dev, 0x82, &odlc); 250 + /* Enable passive releases and delayed transaction */ 251 + ndlc = odlc | 7; 252 + (void) pci_write_config_byte(dev, 0x82, ndlc); 253 + } 254 + 255 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, 256 + quirk_dlcsetup);
+1 -1
arch/mips/nxp/pnx8550/common/int.c
··· 172 172 173 173 static struct irqaction timer_action = { 174 174 .handler = no_action, 175 - .flags = IRQF_DISABLED, 175 + .flags = IRQF_DISABLED | IRQF_TIMER, 176 176 .name = "Timer", 177 177 }; 178 178
+2 -2
arch/mips/nxp/pnx8550/common/time.c
··· 59 59 60 60 static struct irqaction pnx8xxx_timer_irq = { 61 61 .handler = pnx8xxx_timer_interrupt, 62 - .flags = IRQF_DISABLED | IRQF_PERCPU, 62 + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 63 63 .name = "pnx8xxx_timer", 64 64 }; 65 65 ··· 72 72 73 73 static struct irqaction monotonic_irqaction = { 74 74 .handler = monotonic_interrupt, 75 - .flags = IRQF_DISABLED, 75 + .flags = IRQF_DISABLED | IRQF_TIMER, 76 76 .name = "Monotonic timer", 77 77 }; 78 78
+1 -1
arch/mips/oprofile/op_model_loongson2.c
··· 22 22 * otherwise, the oprofile tool will not recognize this and complain about 23 23 * "cpu_type 'unset' is not valid". 24 24 */ 25 - #define LOONGSON2_CPU_TYPE "mips/godson2" 25 + #define LOONGSON2_CPU_TYPE "mips/loongson2" 26 26 27 27 #define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5) 28 28 #define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9)
+1 -1
arch/mips/sgi-ip27/ip27-timer.c
··· 105 105 106 106 struct irqaction hub_rt_irqaction = { 107 107 .handler = hub_rt_counter_handler, 108 - .flags = IRQF_DISABLED | IRQF_PERCPU, 108 + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 109 109 .name = "hub-rt", 110 110 }; 111 111
+1 -1
arch/mips/sni/time.c
··· 67 67 68 68 static struct irqaction a20r_irqaction = { 69 69 .handler = a20r_interrupt, 70 - .flags = IRQF_DISABLED | IRQF_PERCPU, 70 + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, 71 71 .name = "a20r-timer", 72 72 }; 73 73
+3 -2
arch/mips/txx9/generic/setup.c
··· 85 85 struct clk *clk_get(struct device *dev, const char *id) 86 86 { 87 87 if (!strcmp(id, "spi-baseclk")) 88 - return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4); 88 + return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 2); 89 89 if (!strcmp(id, "imbus_clk")) 90 90 return (struct clk *)((unsigned long)txx9_gbus_clock / 2); 91 91 return ERR_PTR(-ENOENT); ··· 817 817 out_pdev: 818 818 platform_device_put(pdev); 819 819 out_gpio: 820 - gpio_remove(&iocled->chip); 820 + if (gpiochip_remove(&iocled->chip)) 821 + return; 821 822 out_unmap: 822 823 iounmap(iocled->mmioaddr); 823 824 out_free: