amd-xgbe: add support for giant packet size

AMD XGBE hardware supports giant Ethernet frames up to 16K bytes.
Add support for configuring and enabling giant packet handling
in the driver.

- Define new register fields and macros for giant packet support.
- Update the jumbo frame configuration logic to enable giant
packet mode when MTU exceeds the jumbo threshold.

Acked-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20250701121929.319690-1-Raju.Rangoju@amd.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Raju Rangoju and committed by

Jakub Kicinski 11 months ago 9e2a7ad4 7d2dabaa

+24 -4

4 changed files

expand all

drivers

net

ethernet

amd

xgbe

xgbe-common.h

xgbe-dev.c

xgbe-main.c

xgbe.h

drivers/net/ethernet/amd/xgbe/xgbe-common.h

··· 364 364 #define MAC_RCR_CST_WIDTH 1 365 365 #define MAC_RCR_DCRCC_INDEX 3 366 366 #define MAC_RCR_DCRCC_WIDTH 1 367 + #define MAC_RCR_GPSLCE_INDEX 6 368 + #define MAC_RCR_GPSLCE_WIDTH 1 369 + #define MAC_RCR_WD_INDEX 7 370 + #define MAC_RCR_WD_WIDTH 1 367 371 #define MAC_RCR_HDSMS_INDEX 12 368 372 #define MAC_RCR_HDSMS_WIDTH 3 369 373 #define MAC_RCR_IPC_INDEX 9 ··· 378 374 #define MAC_RCR_LM_WIDTH 1 379 375 #define MAC_RCR_RE_INDEX 0 380 376 #define MAC_RCR_RE_WIDTH 1 377 + #define MAC_RCR_GPSL_INDEX 16 378 + #define MAC_RCR_GPSL_WIDTH 14 381 379 #define MAC_RFCR_PFCE_INDEX 8 382 380 #define MAC_RFCR_PFCE_WIDTH 1 383 381 #define MAC_RFCR_RFE_INDEX 0 ··· 418 412 #define MAC_TCR_VNE_WIDTH 1 419 413 #define MAC_TCR_VNM_INDEX 25 420 414 #define MAC_TCR_VNM_WIDTH 1 415 + #define MAC_TCR_JD_INDEX 16 416 + #define MAC_TCR_JD_WIDTH 1 421 417 #define MAC_TIR_TNID_INDEX 0 422 418 #define MAC_TIR_TNID_WIDTH 16 423 419 #define MAC_TSCR_AV8021ASMEN_INDEX 28

+13 -3

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

··· 2850 2850 { 2851 2851 unsigned int val; 2852 2852 2853 - val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; 2854 - 2855 - XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 2853 + if (pdata->netdev->mtu > XGMAC_JUMBO_PACKET_MTU) { 2854 + XGMAC_IOWRITE_BITS(pdata, MAC_RCR, GPSL, 2855 + XGMAC_GIANT_PACKET_MTU); 2856 + XGMAC_IOWRITE_BITS(pdata, MAC_RCR, WD, 1); 2857 + XGMAC_IOWRITE_BITS(pdata, MAC_TCR, JD, 1); 2858 + XGMAC_IOWRITE_BITS(pdata, MAC_RCR, GPSLCE, 1); 2859 + } else { 2860 + val = pdata->netdev->mtu > XGMAC_STD_PACKET_MTU ? 1 : 0; 2861 + XGMAC_IOWRITE_BITS(pdata, MAC_RCR, GPSLCE, 0); 2862 + XGMAC_IOWRITE_BITS(pdata, MAC_RCR, WD, 0); 2863 + XGMAC_IOWRITE_BITS(pdata, MAC_TCR, JD, 0); 2864 + XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 2865 + } 2856 2866 } 2857 2867 2858 2868 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata)

+1 -1

drivers/net/ethernet/amd/xgbe/xgbe-main.c

··· 275 275 276 276 netdev->priv_flags |= IFF_UNICAST_FLT; 277 277 netdev->min_mtu = 0; 278 - netdev->max_mtu = XGMAC_JUMBO_PACKET_MTU; 278 + netdev->max_mtu = XGMAC_GIANT_PACKET_MTU - XGBE_ETH_FRAME_HDR; 279 279 280 280 /* Use default watchdog timeout */ 281 281 netdev->watchdog_timeo = 0;

drivers/net/ethernet/amd/xgbe/xgbe.h

··· 80 80 #define XGBE_IRQ_MODE_EDGE 0 81 81 #define XGBE_IRQ_MODE_LEVEL 1 82 82 83 + #define XGBE_ETH_FRAME_HDR (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN) 83 84 #define XGMAC_MIN_PACKET 60 84 85 #define XGMAC_STD_PACKET_MTU 1500 85 86 #define XGMAC_MAX_STD_PACKET 1518 86 87 #define XGMAC_JUMBO_PACKET_MTU 9000 87 88 #define XGMAC_MAX_JUMBO_PACKET 9018 89 + #define XGMAC_GIANT_PACKET_MTU 16368 88 90 #define XGMAC_ETH_PREAMBLE (12 + 8) /* Inter-frame gap + preamble */ 89 91 90 92 #define XGMAC_PFC_DATA_LEN 46

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