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phy: ti: gmii-sel: Enable USXGMII mode for J7200

TI's J7200 SoC supports USXGMII mode with the CPSW5G instance's MAC Port1.
Add USXGMII mode to the extra_modes member of J7200's SoC data.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20241010144845.2555983-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Siddharth Vadapalli and committed by
Vinod Koul 9e544d46 bbcc9e2b

+2 -1
+2 -1
drivers/phy/ti/phy-gmii-sel.c
··· 230 230 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = { 231 231 .use_of_data = true, 232 232 .regfields = phy_gmii_sel_fields_am654, 233 - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 233 + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 234 + BIT(PHY_INTERFACE_MODE_USXGMII), 234 235 .num_ports = 4, 235 236 .num_qsgmii_main_ports = 1, 236 237 };