clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name()

+9 -4

drivers/clk/ti/apll.c

··· 139 139 struct clk_hw *hw = user; 140 140 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 141 141 struct dpll_data *ad = clk_hw->dpll_data; 142 + const char *name; 142 143 struct clk *clk; 143 144 const struct clk_init_data *init = clk_hw->hw.init; 144 145 ··· 167 166 168 167 ad->clk_bypass = __clk_get_hw(clk); 169 168 170 - clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); 169 + name = ti_dt_clk_name(node); 170 + clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); 171 171 if (!IS_ERR(clk)) { 172 172 of_clk_add_provider(node, of_clk_src_simple_get, clk); 173 173 kfree(init->parent_names); ··· 200 198 clk_hw->dpll_data = ad; 201 199 clk_hw->hw.init = init; 202 200 203 - init->name = node->name; 201 + init->name = ti_dt_clk_name(node); 204 202 init->ops = &apll_ck_ops; 205 203 206 204 init->num_parents = of_clk_get_parent_count(node); ··· 349 347 struct dpll_data *ad = NULL; 350 348 struct clk_hw_omap *clk_hw = NULL; 351 349 struct clk_init_data *init = NULL; 350 + const char *name; 352 351 struct clk *clk; 353 352 const char *parent_name; 354 353 u32 val; ··· 365 362 clk_hw->dpll_data = ad; 366 363 clk_hw->hw.init = init; 367 364 init->ops = &omap2_apll_ops; 368 - init->name = node->name; 365 + name = ti_dt_clk_name(node); 366 + init->name = name; 369 367 clk_hw->ops = &omap2_apll_hwops; 370 368 371 369 init->num_parents = of_clk_get_parent_count(node); ··· 407 403 if (ret) 408 404 goto cleanup; 409 405 410 - clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); 406 + name = ti_dt_clk_name(node); 407 + clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); 411 408 if (!IS_ERR(clk)) { 412 409 of_clk_add_provider(node, of_clk_src_simple_get, clk); 413 410 kfree(init);

+1 -1

drivers/clk/ti/clockdomain.c

··· 131 131 { 132 132 struct clk *clk; 133 133 struct clk_hw *clk_hw; 134 - const char *clkdm_name = node->name; 134 + const char *clkdm_name = ti_dt_clk_name(node); 135 135 int i; 136 136 unsigned int num_clks; 137 137

+5 -3

drivers/clk/ti/dpll.c

··· 164 164 struct clk_hw *hw = user; 165 165 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); 166 166 struct dpll_data *dd = clk_hw->dpll_data; 167 + const char *name; 167 168 struct clk *clk; 168 169 const struct clk_init_data *init = hw->init; 169 170 ··· 194 193 dd->clk_bypass = __clk_get_hw(clk); 195 194 196 195 /* register the clock */ 197 - clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); 196 + name = ti_dt_clk_name(node); 197 + clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); 198 198 199 199 if (!IS_ERR(clk)) { 200 200 of_clk_add_provider(node, of_clk_src_simple_get, clk); ··· 229 227 struct clk *clk; 230 228 struct clk_init_data init = { NULL }; 231 229 struct clk_hw_omap *clk_hw; 232 - const char *name = node->name; 230 + const char *name = ti_dt_clk_name(node); 233 231 const char *parent_name; 234 232 235 233 parent_name = of_clk_get_parent_name(node, 0); ··· 306 304 clk_hw->ops = &clkhwops_omap3_dpll; 307 305 clk_hw->hw.init = init; 308 306 309 - init->name = node->name; 307 + init->name = ti_dt_clk_name(node); 310 308 init->ops = ops; 311 309 312 310 init->num_parents = of_clk_get_parent_count(node);

+7 -4

drivers/clk/ti/fapll.c

··· 19 19 #include <linux/of_address.h> 20 20 #include <linux/clk/ti.h> 21 21 22 + #include "clock.h" 23 + 22 24 /* FAPLL Control Register PLL_CTRL */ 23 25 #define FAPLL_MAIN_MULT_N_SHIFT 16 24 26 #define FAPLL_MAIN_DIV_P_SHIFT 8 ··· 544 542 struct clk_init_data *init = NULL; 545 543 const char *parent_name[2]; 546 544 struct clk *pll_clk; 545 + const char *name; 547 546 int i; 548 547 549 548 fd = kzalloc(sizeof(*fd), GFP_KERNEL); ··· 562 559 goto free; 563 560 564 561 init->ops = &ti_fapll_ops; 565 - init->name = node->name; 562 + name = ti_dt_clk_name(node); 563 + init->name = name; 566 564 567 565 init->num_parents = of_clk_get_parent_count(node); 568 566 if (init->num_parents != 2) { ··· 595 591 if (fapll_is_ddr_pll(fd->base)) 596 592 fd->bypass_bit_inverted = true; 597 593 598 - fd->name = node->name; 594 + fd->name = name; 599 595 fd->hw.init = init; 600 596 601 597 /* Register the parent PLL */ ··· 642 638 freq = NULL; 643 639 } 644 640 synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance, 645 - output_name, node->name, 646 - pll_clk); 641 + output_name, name, pll_clk); 647 642 if (IS_ERR(synth_clk)) 648 643 continue; 649 644

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