Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'dmaengine-6.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul:
"A new driver, couple of device support and binding conversion along
with bunch of driver updates are the main features of this.
New hardware support:
- TI AM62Ax controller support
- Xilinx xdma driver
- Qualcomm SM6125, SM8550, QDU1000/QRU1000 GPI controller
Updates:
- Runtime pm support for at_xdmac driver
- IMX sdma binding conversion to yaml and HDMI audio support
- IMX mxs binding conversion to yaml"
* tag 'dmaengine-6.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (35 commits)
dmaengine: idma64: Update bytes_transferred field
dmaengine: imx-sdma: Set DMA channel to be private
dmaengine: dw: Move check for paused channel to dwc_get_residue()
dmaengine: ptdma: check for null desc before calling pt_cmd_callback
dmaengine: dw-axi-dmac: Do not dereference NULL structure
dmaengine: idxd: Fix default allowed read buffers value in group
dmaengine: sf-pdma: pdma_desc memory leak fix
dmaengine: Simplify dmaenginem_async_device_register() function
dmaengine: use sysfs_emit() to instead of scnprintf()
dmaengine: Make an order in struct dma_device definition
dt-bindings: dma: cleanup examples - indentation, lowercase hex
dt-bindings: dma: drop unneeded quotes
dmaengine: xilinx: xdma: Add user logic interrupt support
dmaengine: xilinx: xdma: Add xilinx xdma driver
dmaengine: drivers: Use devm_platform_ioremap_resource()
dmaengine: at_xdmac: remove empty line
dmaengine: at_xdmac: add runtime pm support
dmaengine: at_xdmac: align properly function members
dmaengine: ppc4xx: Convert to use sysfs_emit()/sysfs_emit_at() APIs
dmaengine: sun6i: Set the maximum segment size
...
+2120
-446
+1
-1
Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/allwinner,sun4i-a10-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/allwinner,sun6i-a31-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/altr,msgdma.yaml
+1
-1
Documentation/devicetree/bindings/dma/altr,msgdma.yaml
+1
-1
Documentation/devicetree/bindings/dma/apple,admac.yaml
+1
-1
Documentation/devicetree/bindings/dma/apple,admac.yaml
+1
-1
Documentation/devicetree/bindings/dma/arm-pl08x.yaml
+1
-1
Documentation/devicetree/bindings/dma/arm-pl08x.yaml
+1
-1
Documentation/devicetree/bindings/dma/dma-controller.yaml
+1
-1
Documentation/devicetree/bindings/dma/dma-controller.yaml
+1
-1
Documentation/devicetree/bindings/dma/dma-router.yaml
+1
-1
Documentation/devicetree/bindings/dma/dma-router.yaml
+1
-1
Documentation/devicetree/bindings/dma/fsl,edma.yaml
+1
-1
Documentation/devicetree/bindings/dma/fsl,edma.yaml
+149
Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml
+149
Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/fsl,imx-sdma.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
8
+
9
+
maintainers:
10
+
- Joy Zou <joy.zou@nxp.com>
11
+
12
+
allOf:
13
+
- $ref: dma-controller.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
oneOf:
18
+
- items:
19
+
- enum:
20
+
- fsl,imx50-sdma
21
+
- fsl,imx51-sdma
22
+
- fsl,imx53-sdma
23
+
- fsl,imx6q-sdma
24
+
- fsl,imx7d-sdma
25
+
- const: fsl,imx35-sdma
26
+
- items:
27
+
- enum:
28
+
- fsl,imx6sx-sdma
29
+
- fsl,imx6sl-sdma
30
+
- const: fsl,imx6q-sdma
31
+
- items:
32
+
- const: fsl,imx6ul-sdma
33
+
- const: fsl,imx6q-sdma
34
+
- const: fsl,imx35-sdma
35
+
- items:
36
+
- const: fsl,imx6sll-sdma
37
+
- const: fsl,imx6ul-sdma
38
+
- items:
39
+
- const: fsl,imx8mq-sdma
40
+
- const: fsl,imx7d-sdma
41
+
- items:
42
+
- enum:
43
+
- fsl,imx8mp-sdma
44
+
- fsl,imx8mn-sdma
45
+
- fsl,imx8mm-sdma
46
+
- const: fsl,imx8mq-sdma
47
+
- items:
48
+
- enum:
49
+
- fsl,imx25-sdma
50
+
- fsl,imx31-sdma
51
+
- fsl,imx35-sdma
52
+
reg:
53
+
maxItems: 1
54
+
55
+
interrupts:
56
+
maxItems: 1
57
+
58
+
fsl,sdma-ram-script-name:
59
+
$ref: /schemas/types.yaml#/definitions/string
60
+
description: Should contain the full path of SDMA RAM scripts firmware.
61
+
62
+
"#dma-cells":
63
+
const: 3
64
+
description: |
65
+
The first cell: request/event ID
66
+
67
+
The second cell: peripheral types ID
68
+
enum:
69
+
- MCU domain SSI: 0
70
+
- Shared SSI: 1
71
+
- MMC: 2
72
+
- SDHC: 3
73
+
- MCU domain UART: 4
74
+
- Shared UART: 5
75
+
- FIRI: 6
76
+
- MCU domain CSPI: 7
77
+
- Shared CSPI: 8
78
+
- SIM: 9
79
+
- ATA: 10
80
+
- CCM: 11
81
+
- External peripheral: 12
82
+
- Memory Stick Host Controller: 13
83
+
- Shared Memory Stick Host Controller: 14
84
+
- DSP: 15
85
+
- Memory: 16
86
+
- FIFO type Memory: 17
87
+
- SPDIF: 18
88
+
- IPU Memory: 19
89
+
- ASRC: 20
90
+
- ESAI: 21
91
+
- SSI Dual FIFO: 22
92
+
description: needs firmware more than ver 2
93
+
- Shared ASRC: 23
94
+
- SAI: 24
95
+
- HDMI Audio: 25
96
+
97
+
The third cell: transfer priority ID
98
+
enum:
99
+
- High: 0
100
+
- Medium: 1
101
+
- Low: 2
102
+
103
+
gpr:
104
+
$ref: /schemas/types.yaml#/definitions/phandle
105
+
description: The phandle to the General Purpose Register (GPR) node
106
+
107
+
fsl,sdma-event-remap:
108
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
109
+
maxItems: 2
110
+
items:
111
+
items:
112
+
- description: GPR register offset
113
+
- description: GPR register shift
114
+
- description: GPR register value
115
+
description: |
116
+
Register bits of sdma event remap, the format is <reg shift val>.
117
+
The order is <RX>, <TX>.
118
+
119
+
clocks:
120
+
maxItems: 2
121
+
122
+
clock-names:
123
+
items:
124
+
- const: ipg
125
+
- const: ahb
126
+
127
+
iram:
128
+
$ref: /schemas/types.yaml#/definitions/phandle
129
+
description: The phandle to the On-chip RAM (OCRAM) node.
130
+
131
+
required:
132
+
- compatible
133
+
- reg
134
+
- interrupts
135
+
- fsl,sdma-ram-script-name
136
+
137
+
additionalProperties: false
138
+
139
+
examples:
140
+
- |
141
+
sdma: dma-controller@83fb0000 {
142
+
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
143
+
reg = <0x83fb0000 0x4000>;
144
+
interrupts = <6>;
145
+
#dma-cells = <3>;
146
+
fsl,sdma-ram-script-name = "sdma-imx51.bin";
147
+
};
148
+
149
+
...
+80
Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml
+80
Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/dma/fsl,mxs-dma.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Freescale Direct Memory Access (DMA) Controller from i.MX23/i.MX28
8
+
9
+
maintainers:
10
+
- Marek Vasut <marex@denx.de>
11
+
12
+
allOf:
13
+
- $ref: dma-controller.yaml#
14
+
15
+
properties:
16
+
compatible:
17
+
oneOf:
18
+
- items:
19
+
- enum:
20
+
- fsl,imx6q-dma-apbh
21
+
- fsl,imx6sx-dma-apbh
22
+
- fsl,imx7d-dma-apbh
23
+
- const: fsl,imx28-dma-apbh
24
+
- enum:
25
+
- fsl,imx23-dma-apbh
26
+
- fsl,imx23-dma-apbx
27
+
- fsl,imx28-dma-apbh
28
+
- fsl,imx28-dma-apbx
29
+
reg:
30
+
maxItems: 1
31
+
32
+
clocks:
33
+
maxItems: 1
34
+
35
+
interrupts:
36
+
minItems: 4
37
+
maxItems: 16
38
+
39
+
"#dma-cells":
40
+
const: 1
41
+
42
+
dma-channels:
43
+
enum: [4, 8, 16]
44
+
45
+
required:
46
+
- compatible
47
+
- reg
48
+
- "#dma-cells"
49
+
- dma-channels
50
+
- interrupts
51
+
52
+
additionalProperties: false
53
+
54
+
examples:
55
+
- |
56
+
interrupt-parent = <&irqc>;
57
+
58
+
dma-controller@80004000 {
59
+
compatible = "fsl,imx28-dma-apbh";
60
+
reg = <0x80004000 0x2000>;
61
+
interrupts = <82 83 84 85
62
+
88 88 88 88
63
+
88 88 88 88
64
+
87 86 0 0>;
65
+
#dma-cells = <1>;
66
+
dma-channels = <16>;
67
+
};
68
+
69
+
dma-controller@80024000 {
70
+
compatible = "fsl,imx28-dma-apbx";
71
+
reg = <0x80024000 0x2000>;
72
+
interrupts = <78 79 66 0
73
+
80 81 68 69
74
+
70 71 72 73
75
+
74 75 76 77>;
76
+
#dma-cells = <1>;
77
+
dma-channels = <16>;
78
+
};
79
+
80
+
...
-118
Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
-118
Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
···
1
-
* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
2
-
3
-
Required properties:
4
-
- compatible : Should be one of
5
-
"fsl,imx25-sdma"
6
-
"fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
7
-
"fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
8
-
"fsl,imx51-sdma"
9
-
"fsl,imx53-sdma"
10
-
"fsl,imx6q-sdma"
11
-
"fsl,imx7d-sdma"
12
-
"fsl,imx6ul-sdma"
13
-
"fsl,imx8mq-sdma"
14
-
"fsl,imx8mm-sdma"
15
-
"fsl,imx8mn-sdma"
16
-
"fsl,imx8mp-sdma"
17
-
The -to variants should be preferred since they allow to determine the
18
-
correct ROM script addresses needed for the driver to work without additional
19
-
firmware.
20
-
- reg : Should contain SDMA registers location and length
21
-
- interrupts : Should contain SDMA interrupt
22
-
- #dma-cells : Must be <3>.
23
-
The first cell specifies the DMA request/event ID. See details below
24
-
about the second and third cell.
25
-
- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
26
-
scripts firmware
27
-
28
-
The second cell of dma phandle specifies the peripheral type of DMA transfer.
29
-
The full ID of peripheral types can be found below.
30
-
31
-
ID transfer type
32
-
---------------------
33
-
0 MCU domain SSI
34
-
1 Shared SSI
35
-
2 MMC
36
-
3 SDHC
37
-
4 MCU domain UART
38
-
5 Shared UART
39
-
6 FIRI
40
-
7 MCU domain CSPI
41
-
8 Shared CSPI
42
-
9 SIM
43
-
10 ATA
44
-
11 CCM
45
-
12 External peripheral
46
-
13 Memory Stick Host Controller
47
-
14 Shared Memory Stick Host Controller
48
-
15 DSP
49
-
16 Memory
50
-
17 FIFO type Memory
51
-
18 SPDIF
52
-
19 IPU Memory
53
-
20 ASRC
54
-
21 ESAI
55
-
22 SSI Dual FIFO (needs firmware ver >= 2)
56
-
23 Shared ASRC
57
-
24 SAI
58
-
59
-
The third cell specifies the transfer priority as below.
60
-
61
-
ID transfer priority
62
-
-------------------------
63
-
0 High
64
-
1 Medium
65
-
2 Low
66
-
67
-
Optional properties:
68
-
69
-
- gpr : The phandle to the General Purpose Register (GPR) node.
70
-
- fsl,sdma-event-remap : Register bits of sdma event remap, the format is
71
-
<reg shift val>.
72
-
reg is the GPR register offset.
73
-
shift is the bit position inside the GPR register.
74
-
val is the value of the bit (0 or 1).
75
-
76
-
Examples:
77
-
78
-
sdma@83fb0000 {
79
-
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
80
-
reg = <0x83fb0000 0x4000>;
81
-
interrupts = <6>;
82
-
#dma-cells = <3>;
83
-
fsl,sdma-ram-script-name = "sdma-imx51.bin";
84
-
};
85
-
86
-
DMA clients connected to the i.MX SDMA controller must use the format
87
-
described in the dma.txt file.
88
-
89
-
Examples:
90
-
91
-
ssi2: ssi@70014000 {
92
-
compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
93
-
reg = <0x70014000 0x4000>;
94
-
interrupts = <30>;
95
-
clocks = <&clks 49>;
96
-
dmas = <&sdma 24 1 0>,
97
-
<&sdma 25 1 0>;
98
-
dma-names = "rx", "tx";
99
-
fsl,fifo-depth = <15>;
100
-
};
101
-
102
-
Using the fsl,sdma-event-remap property:
103
-
104
-
If we want to use SDMA on the SAI1 port on a MX6SX:
105
-
106
-
&sdma {
107
-
gpr = <&gpr>;
108
-
/* SDMA events remap for SAI1_RX and SAI1_TX */
109
-
fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
110
-
};
111
-
112
-
The fsl,sdma-event-remap property in this case has two values:
113
-
- <0 15 1> means that the offset is 0, so GPR0 is the register of the
114
-
SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
115
-
Setting bit 15 to 1 selects SAI1_RX.
116
-
- <0 16 1> means that the offset is 0, so GPR0 is the register of the
117
-
SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
118
-
Setting bit 16 to 1 selects SAI1_TX.
-60
Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
-60
Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
···
1
-
* Freescale MXS DMA
2
-
3
-
Required properties:
4
-
- compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx"
5
-
- reg : Should contain registers location and length
6
-
- interrupts : Should contain the interrupt numbers of DMA channels.
7
-
If a channel is empty/reserved, 0 should be filled in place.
8
-
- #dma-cells : Must be <1>. The number cell specifies the channel ID.
9
-
- dma-channels : Number of channels supported by the DMA controller
10
-
11
-
Optional properties:
12
-
- interrupt-names : Name of DMA channel interrupts
13
-
14
-
Supported chips:
15
-
imx23, imx28.
16
-
17
-
Examples:
18
-
19
-
dma_apbh: dma-apbh@80004000 {
20
-
compatible = "fsl,imx28-dma-apbh";
21
-
reg = <0x80004000 0x2000>;
22
-
interrupts = <82 83 84 85
23
-
88 88 88 88
24
-
88 88 88 88
25
-
87 86 0 0>;
26
-
interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
27
-
"gpmi0", "gmpi1", "gpmi2", "gmpi3",
28
-
"gpmi4", "gmpi5", "gpmi6", "gmpi7",
29
-
"hsadc", "lcdif", "empty", "empty";
30
-
#dma-cells = <1>;
31
-
dma-channels = <16>;
32
-
};
33
-
34
-
dma_apbx: dma-apbx@80024000 {
35
-
compatible = "fsl,imx28-dma-apbx";
36
-
reg = <0x80024000 0x2000>;
37
-
interrupts = <78 79 66 0
38
-
80 81 68 69
39
-
70 71 72 73
40
-
74 75 76 77>;
41
-
interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
42
-
"saif0", "saif1", "i2c0", "i2c1",
43
-
"auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
44
-
"auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
45
-
#dma-cells = <1>;
46
-
dma-channels = <16>;
47
-
};
48
-
49
-
DMA clients connected to the MXS DMA controller must use the format
50
-
described in the dma.txt file.
51
-
52
-
Examples:
53
-
54
-
auart0: serial@8006a000 {
55
-
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
56
-
reg = <0x8006a000 0x2000>;
57
-
interrupts = <112>;
58
-
dmas = <&dma_apbx 8>, <&dma_apbx 9>;
59
-
dma-names = "rx", "tx";
60
-
};
+1
-1
Documentation/devicetree/bindings/dma/ingenic,dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/ingenic,dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/intel,ldma.yaml
+1
-1
Documentation/devicetree/bindings/dma/intel,ldma.yaml
+1
-1
Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml
+1
-1
Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml
+1
-1
Documentation/devicetree/bindings/dma/owl-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/owl-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml
+4
-1
Documentation/devicetree/bindings/dma/qcom,gpi.yaml
+4
-1
Documentation/devicetree/bindings/dma/qcom,gpi.yaml
···
14
14
peripheral buses such as I2C, UART, and SPI.
15
15
16
16
allOf:
17
-
- $ref: "dma-controller.yaml#"
17
+
- $ref: dma-controller.yaml#
18
18
19
19
properties:
20
20
compatible:
···
24
24
- qcom,sm6350-gpi-dma
25
25
- items:
26
26
- enum:
27
+
- qcom,qdu1000-gpi-dma
27
28
- qcom,sc7280-gpi-dma
28
29
- qcom,sm6115-gpi-dma
29
30
- qcom,sm6375-gpi-dma
30
31
- qcom,sm8350-gpi-dma
31
32
- qcom,sm8450-gpi-dma
33
+
- qcom,sm8550-gpi-dma
32
34
- const: qcom,sm6350-gpi-dma
33
35
- items:
34
36
- enum:
35
37
- qcom,sdm670-gpi-dma
38
+
- qcom,sm6125-gpi-dma
36
39
- qcom,sm8150-gpi-dma
37
40
- qcom,sm8250-gpi-dma
38
41
- const: qcom,sdm845-gpi-dma
+1
-1
Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
+1
-1
Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
+1
-1
Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+1
-1
Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+1
-1
Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml
+1
-1
Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml
+1
-1
Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml
+1
-1
Documentation/devicetree/bindings/dma/renesas,usb-dmac.yaml
+1
-1
Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
+1
-1
Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
+1
-1
Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml
+1
-1
Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml
+19
-19
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+19
-19
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
···
13
13
Synopsys DesignWare AXI DMA Controller DT Binding
14
14
15
15
allOf:
16
-
- $ref: "dma-controller.yaml#"
16
+
- $ref: dma-controller.yaml#
17
17
18
18
properties:
19
19
compatible:
···
113
113
114
114
examples:
115
115
- |
116
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
117
-
#include <dt-bindings/interrupt-controller/irq.h>
118
-
/* example with snps,dw-axi-dmac */
119
-
dmac: dma-controller@80000 {
120
-
compatible = "snps,axi-dma-1.01a";
121
-
reg = <0x80000 0x400>;
122
-
clocks = <&core_clk>, <&cfgr_clk>;
123
-
clock-names = "core-clk", "cfgr-clk";
124
-
interrupt-parent = <&intc>;
125
-
interrupts = <27>;
126
-
#dma-cells = <1>;
127
-
dma-channels = <4>;
128
-
snps,dma-masters = <2>;
129
-
snps,data-width = <3>;
130
-
snps,block-size = <4096 4096 4096 4096>;
131
-
snps,priority = <0 1 2 3>;
132
-
snps,axi-max-burst-len = <16>;
133
-
};
116
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
117
+
#include <dt-bindings/interrupt-controller/irq.h>
118
+
/* example with snps,dw-axi-dmac */
119
+
dma-controller@80000 {
120
+
compatible = "snps,axi-dma-1.01a";
121
+
reg = <0x80000 0x400>;
122
+
clocks = <&core_clk>, <&cfgr_clk>;
123
+
clock-names = "core-clk", "cfgr-clk";
124
+
interrupt-parent = <&intc>;
125
+
interrupts = <27>;
126
+
#dma-cells = <1>;
127
+
dma-channels = <4>;
128
+
snps,dma-masters = <2>;
129
+
snps,data-width = <3>;
130
+
snps,block-size = <4096 4096 4096 4096>;
131
+
snps,priority = <0 1 2 3>;
132
+
snps,axi-max-burst-len = <16>;
133
+
};
+1
-1
Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml
+1
-1
Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml
+1
-1
Documentation/devicetree/bindings/dma/socionext,uniphier-xdmac.yaml
+1
-1
Documentation/devicetree/bindings/dma/socionext,uniphier-xdmac.yaml
+1
-1
Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
+1
-1
Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
+1
-1
Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
+1
-1
Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
+1
-1
Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
+9
-9
Documentation/devicetree/bindings/dma/stericsson,dma40.yaml
+9
-9
Documentation/devicetree/bindings/dma/stericsson,dma40.yaml
···
10
10
- Linus Walleij <linus.walleij@linaro.org>
11
11
12
12
allOf:
13
-
- $ref: "dma-controller.yaml#"
13
+
- $ref: dma-controller.yaml#
14
14
15
15
properties:
16
16
"#dma-cells":
···
147
147
#include <dt-bindings/interrupt-controller/irq.h>
148
148
#include <dt-bindings/interrupt-controller/arm-gic.h>
149
149
#include <dt-bindings/mfd/dbx500-prcmu.h>
150
-
dma-controller@801C0000 {
151
-
compatible = "stericsson,db8500-dma40", "stericsson,dma40";
152
-
reg = <0x801C0000 0x1000>, <0x40010000 0x800>;
153
-
reg-names = "base", "lcpa";
154
-
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
155
-
#dma-cells = <3>;
156
-
memcpy-channels = <56 57 58 59 60>;
157
-
clocks = <&prcmu_clk PRCMU_DMACLK>;
150
+
dma-controller@801c0000 {
151
+
compatible = "stericsson,db8500-dma40", "stericsson,dma40";
152
+
reg = <0x801c0000 0x1000>, <0x40010000 0x800>;
153
+
reg-names = "base", "lcpa";
154
+
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
155
+
#dma-cells = <3>;
156
+
memcpy-channels = <56 57 58 59 60>;
157
+
clocks = <&prcmu_clk PRCMU_DMACLK>;
158
158
};
159
159
...
+59
-18
Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml
+59
-18
Documentation/devicetree/bindings/dma/ti/k3-bcdma.yaml
···
28
28
PDMAs can be configured via BCDMA split channel's peer registers to match with
29
29
the configuration of the legacy peripheral.
30
30
31
-
allOf:
32
-
- $ref: /schemas/dma/dma-controller.yaml#
33
-
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
34
-
35
31
properties:
36
32
compatible:
37
-
const: ti,am64-dmss-bcdma
33
+
enum:
34
+
- ti,am62a-dmss-bcdma-csirx
35
+
- ti,am64-dmss-bcdma
36
+
37
+
reg:
38
+
minItems: 3
39
+
maxItems: 5
40
+
41
+
reg-names:
42
+
minItems: 3
43
+
maxItems: 5
38
44
39
45
"#dma-cells":
40
46
const: 3
···
71
65
72
66
cell 3: ASEL value for the channel
73
67
74
-
reg:
75
-
maxItems: 5
76
-
77
-
reg-names:
78
-
items:
79
-
- const: gcfg
80
-
- const: bchanrt
81
-
- const: rchanrt
82
-
- const: tchanrt
83
-
- const: ringrt
84
-
85
68
msi-parent: true
69
+
70
+
power-domains:
71
+
description:
72
+
Power domain if available
73
+
maxItems: 1
86
74
87
75
ti,asel:
88
76
$ref: /schemas/types.yaml#/definitions/uint32
···
123
123
- msi-parent
124
124
- ti,sci
125
125
- ti,sci-dev-id
126
-
- ti,sci-rm-range-bchan
127
-
- ti,sci-rm-range-tchan
128
126
- ti,sci-rm-range-rchan
127
+
128
+
allOf:
129
+
- $ref: /schemas/dma/dma-controller.yaml#
130
+
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
131
+
132
+
- if:
133
+
properties:
134
+
compatible:
135
+
contains:
136
+
const: ti,am62a-dmss-bcdma-csirx
137
+
then:
138
+
properties:
139
+
ti,sci-rm-range-bchan: false
140
+
ti,sci-rm-range-tchan: false
141
+
142
+
reg:
143
+
maxItems: 3
144
+
145
+
reg-names:
146
+
items:
147
+
- const: gcfg
148
+
- const: rchanrt
149
+
- const: ringrt
150
+
151
+
required:
152
+
- power-domains
153
+
154
+
else:
155
+
properties:
156
+
reg:
157
+
minItems: 5
158
+
159
+
reg-names:
160
+
items:
161
+
- const: gcfg
162
+
- const: bchanrt
163
+
- const: rchanrt
164
+
- const: tchanrt
165
+
- const: ringrt
166
+
167
+
required:
168
+
- ti,sci-rm-range-bchan
169
+
- ti,sci-rm-range-tchan
129
170
130
171
unevaluatedProperties: false
131
172
+11
MAINTAINERS
+11
MAINTAINERS
···
22946
22946
F: drivers/media/platform/xilinx/
22947
22947
F: include/uapi/linux/xilinx-v4l2-controls.h
22948
22948
22949
+
XILINX XDMA DRIVER
22950
+
M: Lizhi Hou <lizhi.hou@amd.com>
22951
+
M: Brian Xu <brian.xu@amd.com>
22952
+
M: Raj Kumar Rampelli <raj.kumar.rampelli@amd.com>
22953
+
L: dmaengine@vger.kernel.org
22954
+
S: Supported
22955
+
F: drivers/dma/xilinx/xdma-regs.h
22956
+
F: drivers/dma/xilinx/xdma.c
22957
+
F: include/linux/dma/amd_xdma.h
22958
+
F: include/linux/platform_data/amd_xdma.h
22959
+
22949
22960
XILINX ZYNQMP DPDMA DRIVER
22950
22961
M: Hyun Kwon <hyun.kwon@xilinx.com>
22951
22962
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+15
-1
drivers/dma/Kconfig
+15
-1
drivers/dma/Kconfig
···
245
245
246
246
config HISI_DMA
247
247
tristate "HiSilicon DMA Engine support"
248
-
depends on ARM64 || COMPILE_TEST
248
+
depends on ARCH_HISI || COMPILE_TEST
249
249
depends on PCI_MSI
250
250
select DMA_ENGINE
251
251
select DMA_VIRTUAL_CHANNELS
···
715
715
between memory and AXI4-Stream target peripherals. It provides
716
716
the scatter gather interface with multiple channels independent
717
717
configuration support.
718
+
719
+
config XILINX_XDMA
720
+
tristate "Xilinx DMA/Bridge Subsystem DMA Engine"
721
+
depends on HAS_IOMEM
722
+
select DMA_ENGINE
723
+
select DMA_VIRTUAL_CHANNELS
724
+
select REGMAP_MMIO
725
+
help
726
+
Enable support for Xilinx DMA/Bridge Subsystem DMA engine. The DMA
727
+
provides high performance block data movement between Host memory
728
+
and the DMA subsystem. These direct memory transfers can be both in
729
+
the Host to Card (H2C) and Card to Host (C2H) transfers.
730
+
The core also provides up to 16 user interrupt wires that generate
731
+
interrupts to the host.
718
732
719
733
config XILINX_ZYNQMP_DMA
720
734
tristate "Xilinx ZynqMP DMA Engine"
+204
-18
drivers/dma/at_xdmac.c
+204
-18
drivers/dma/at_xdmac.c
···
21
21
#include <linux/of_platform.h>
22
22
#include <linux/platform_device.h>
23
23
#include <linux/pm.h>
24
+
#include <linux/pm_runtime.h>
24
25
25
26
#include "dmaengine.h"
26
27
···
241
240
struct at_xdmac {
242
241
struct dma_device dma;
243
242
void __iomem *regs;
243
+
struct device *dev;
244
244
int irq;
245
245
struct clk *clk;
246
246
u32 save_gim;
···
363
361
"initial descriptors per channel (default: 64)");
364
362
365
363
364
+
static void at_xdmac_runtime_suspend_descriptors(struct at_xdmac_chan *atchan)
365
+
{
366
+
struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
367
+
struct at_xdmac_desc *desc, *_desc;
368
+
369
+
list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node) {
370
+
if (!desc->active_xfer)
371
+
continue;
372
+
373
+
pm_runtime_mark_last_busy(atxdmac->dev);
374
+
pm_runtime_put_autosuspend(atxdmac->dev);
375
+
}
376
+
}
377
+
378
+
static int at_xdmac_runtime_resume_descriptors(struct at_xdmac_chan *atchan)
379
+
{
380
+
struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
381
+
struct at_xdmac_desc *desc, *_desc;
382
+
int ret;
383
+
384
+
list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node) {
385
+
if (!desc->active_xfer)
386
+
continue;
387
+
388
+
ret = pm_runtime_resume_and_get(atxdmac->dev);
389
+
if (ret < 0)
390
+
return ret;
391
+
}
392
+
393
+
return 0;
394
+
}
395
+
366
396
static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
367
397
{
368
-
return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
398
+
struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
399
+
int ret;
400
+
401
+
ret = pm_runtime_resume_and_get(atxdmac->dev);
402
+
if (ret < 0)
403
+
return false;
404
+
405
+
ret = !!(at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask);
406
+
407
+
pm_runtime_mark_last_busy(atxdmac->dev);
408
+
pm_runtime_put_autosuspend(atxdmac->dev);
409
+
410
+
return ret;
369
411
}
370
412
371
413
static void at_xdmac_off(struct at_xdmac *atxdmac)
372
414
{
415
+
struct dma_chan *chan, *_chan;
416
+
struct at_xdmac_chan *atchan;
417
+
int ret;
418
+
419
+
ret = pm_runtime_resume_and_get(atxdmac->dev);
420
+
if (ret < 0)
421
+
return;
422
+
373
423
at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
374
424
375
425
/* Wait that all chans are disabled. */
···
429
375
cpu_relax();
430
376
431
377
at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
378
+
379
+
/* Decrement runtime PM ref counter for each active descriptor. */
380
+
if (!list_empty(&atxdmac->dma.channels)) {
381
+
list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels,
382
+
device_node) {
383
+
atchan = to_at_xdmac_chan(chan);
384
+
at_xdmac_runtime_suspend_descriptors(atchan);
385
+
}
386
+
}
387
+
388
+
pm_runtime_mark_last_busy(atxdmac->dev);
389
+
pm_runtime_put_autosuspend(atxdmac->dev);
432
390
}
433
391
434
392
/* Call with lock hold. */
···
449
383
{
450
384
struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
451
385
u32 reg;
386
+
int ret;
387
+
388
+
ret = pm_runtime_resume_and_get(atxdmac->dev);
389
+
if (ret < 0)
390
+
return;
452
391
453
392
dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
454
393
···
533
462
at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
534
463
at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
535
464
at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
536
-
537
465
}
538
466
539
467
static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
···
1526
1456
1527
1457
static enum dma_status
1528
1458
at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1529
-
struct dma_tx_state *txstate)
1459
+
struct dma_tx_state *txstate)
1530
1460
{
1531
1461
struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1532
1462
struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1533
1463
struct at_xdmac_desc *desc, *_desc, *iter;
1534
1464
struct list_head *descs_list;
1535
1465
enum dma_status ret;
1536
-
int residue, retry;
1466
+
int residue, retry, pm_status;
1537
1467
u32 cur_nda, check_nda, cur_ubc, mask, value;
1538
1468
u8 dwidth = 0;
1539
1469
unsigned long flags;
···
1542
1472
ret = dma_cookie_status(chan, cookie, txstate);
1543
1473
if (ret == DMA_COMPLETE || !txstate)
1544
1474
return ret;
1475
+
1476
+
pm_status = pm_runtime_resume_and_get(atxdmac->dev);
1477
+
if (pm_status < 0)
1478
+
return DMA_ERROR;
1545
1479
1546
1480
spin_lock_irqsave(&atchan->lock, flags);
1547
1481
···
1664
1590
1665
1591
spin_unlock:
1666
1592
spin_unlock_irqrestore(&atchan->lock, flags);
1593
+
pm_runtime_mark_last_busy(atxdmac->dev);
1594
+
pm_runtime_put_autosuspend(atxdmac->dev);
1667
1595
return ret;
1668
1596
}
1669
1597
···
1712
1636
{
1713
1637
struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1714
1638
struct at_xdmac_desc *bad_desc;
1639
+
int ret;
1640
+
1641
+
ret = pm_runtime_resume_and_get(atxdmac->dev);
1642
+
if (ret < 0)
1643
+
return;
1715
1644
1716
1645
/*
1717
1646
* The descriptor currently at the head of the active list is
···
1746
1665
__func__, &bad_desc->lld.mbr_sa, &bad_desc->lld.mbr_da,
1747
1666
bad_desc->lld.mbr_ubc);
1748
1667
1668
+
pm_runtime_mark_last_busy(atxdmac->dev);
1669
+
pm_runtime_put_autosuspend(atxdmac->dev);
1670
+
1749
1671
/* Then continue with usual descriptor management */
1750
1672
}
1751
1673
1752
1674
static void at_xdmac_tasklet(struct tasklet_struct *t)
1753
1675
{
1754
1676
struct at_xdmac_chan *atchan = from_tasklet(atchan, t, tasklet);
1677
+
struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1755
1678
struct at_xdmac_desc *desc;
1756
1679
struct dma_async_tx_descriptor *txd;
1757
1680
u32 error_mask;
···
1805
1720
list_splice_tail_init(&desc->descs_list, &atchan->free_descs_list);
1806
1721
at_xdmac_advance_work(atchan);
1807
1722
spin_unlock_irq(&atchan->lock);
1723
+
1724
+
/*
1725
+
* Decrement runtime PM ref counter incremented in
1726
+
* at_xdmac_start_xfer().
1727
+
*/
1728
+
pm_runtime_mark_last_busy(atxdmac->dev);
1729
+
pm_runtime_put_autosuspend(atxdmac->dev);
1808
1730
}
1809
1731
1810
1732
static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
···
1903
1811
struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1904
1812
struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1905
1813
unsigned long flags;
1814
+
int ret;
1906
1815
1907
1816
dev_dbg(chan2dev(chan), "%s\n", __func__);
1908
1817
1909
1818
if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1910
1819
return 0;
1911
1820
1821
+
ret = pm_runtime_resume_and_get(atxdmac->dev);
1822
+
if (ret < 0)
1823
+
return ret;
1824
+
1912
1825
spin_lock_irqsave(&atchan->lock, flags);
1913
1826
at_xdmac_write(atxdmac, atxdmac->layout->grws, atchan->mask);
1914
1827
while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1915
1828
& (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1916
1829
cpu_relax();
1830
+
1831
+
/* Decrement runtime PM ref counter for each active descriptor. */
1832
+
at_xdmac_runtime_suspend_descriptors(atchan);
1833
+
1917
1834
spin_unlock_irqrestore(&atchan->lock, flags);
1835
+
1836
+
pm_runtime_mark_last_busy(atxdmac->dev);
1837
+
pm_runtime_put_autosuspend(atxdmac->dev);
1918
1838
1919
1839
return 0;
1920
1840
}
···
1936
1832
struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1937
1833
struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1938
1834
unsigned long flags;
1835
+
int ret;
1939
1836
1940
1837
dev_dbg(chan2dev(chan), "%s\n", __func__);
1941
1838
1839
+
ret = pm_runtime_resume_and_get(atxdmac->dev);
1840
+
if (ret < 0)
1841
+
return ret;
1842
+
1942
1843
spin_lock_irqsave(&atchan->lock, flags);
1943
-
if (!at_xdmac_chan_is_paused(atchan)) {
1944
-
spin_unlock_irqrestore(&atchan->lock, flags);
1945
-
return 0;
1946
-
}
1844
+
if (!at_xdmac_chan_is_paused(atchan))
1845
+
goto unlock;
1846
+
1847
+
/* Increment runtime PM ref counter for each active descriptor. */
1848
+
ret = at_xdmac_runtime_resume_descriptors(atchan);
1849
+
if (ret < 0)
1850
+
goto unlock;
1947
1851
1948
1852
at_xdmac_write(atxdmac, atxdmac->layout->grwr, atchan->mask);
1949
1853
clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1950
-
spin_unlock_irqrestore(&atchan->lock, flags);
1951
1854
1952
-
return 0;
1855
+
unlock:
1856
+
spin_unlock_irqrestore(&atchan->lock, flags);
1857
+
pm_runtime_mark_last_busy(atxdmac->dev);
1858
+
pm_runtime_put_autosuspend(atxdmac->dev);
1859
+
1860
+
return ret;
1953
1861
}
1954
1862
1955
1863
static int at_xdmac_device_terminate_all(struct dma_chan *chan)
···
1970
1854
struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1971
1855
struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1972
1856
unsigned long flags;
1857
+
int ret;
1973
1858
1974
1859
dev_dbg(chan2dev(chan), "%s\n", __func__);
1860
+
1861
+
ret = pm_runtime_resume_and_get(atxdmac->dev);
1862
+
if (ret < 0)
1863
+
return ret;
1975
1864
1976
1865
spin_lock_irqsave(&atchan->lock, flags);
1977
1866
at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
···
1988
1867
list_del(&desc->xfer_node);
1989
1868
list_splice_tail_init(&desc->descs_list,
1990
1869
&atchan->free_descs_list);
1870
+
/*
1871
+
* We incremented the runtime PM reference count on
1872
+
* at_xdmac_start_xfer() for this descriptor. Now it's time
1873
+
* to release it.
1874
+
*/
1875
+
if (desc->active_xfer) {
1876
+
pm_runtime_put_autosuspend(atxdmac->dev);
1877
+
pm_runtime_mark_last_busy(atxdmac->dev);
1878
+
}
1991
1879
}
1992
1880
1993
1881
clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1994
1882
clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
1995
1883
spin_unlock_irqrestore(&atchan->lock, flags);
1884
+
1885
+
pm_runtime_mark_last_busy(atxdmac->dev);
1886
+
pm_runtime_put_autosuspend(atxdmac->dev);
1996
1887
1997
1888
return 0;
1998
1889
}
···
2107
1974
{
2108
1975
struct at_xdmac *atxdmac = dev_get_drvdata(dev);
2109
1976
struct dma_chan *chan, *_chan;
1977
+
int ret;
1978
+
1979
+
ret = pm_runtime_resume_and_get(atxdmac->dev);
1980
+
if (ret < 0)
1981
+
return ret;
2110
1982
2111
1983
list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
2112
1984
struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
···
2124
1986
atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
2125
1987
atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
2126
1988
}
1989
+
1990
+
at_xdmac_runtime_suspend_descriptors(atchan);
2127
1991
}
2128
1992
atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
2129
1993
2130
1994
at_xdmac_off(atxdmac);
2131
-
clk_disable_unprepare(atxdmac->clk);
2132
-
return 0;
1995
+
return pm_runtime_force_suspend(atxdmac->dev);
2133
1996
}
2134
1997
2135
1998
static int __maybe_unused atmel_xdmac_resume(struct device *dev)
···
2142
2003
int i;
2143
2004
int ret;
2144
2005
2145
-
ret = clk_prepare_enable(atxdmac->clk);
2146
-
if (ret)
2006
+
ret = pm_runtime_force_resume(atxdmac->dev);
2007
+
if (ret < 0)
2147
2008
return ret;
2148
2009
2149
2010
at_xdmac_axi_config(pdev);
···
2158
2019
at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
2159
2020
list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
2160
2021
atchan = to_at_xdmac_chan(chan);
2022
+
2023
+
ret = at_xdmac_runtime_resume_descriptors(atchan);
2024
+
if (ret < 0)
2025
+
return ret;
2026
+
2161
2027
at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
2162
2028
if (at_xdmac_chan_is_cyclic(atchan)) {
2163
2029
if (at_xdmac_chan_is_paused(atchan))
···
2174
2030
at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
2175
2031
}
2176
2032
}
2033
+
2034
+
pm_runtime_mark_last_busy(atxdmac->dev);
2035
+
pm_runtime_put_autosuspend(atxdmac->dev);
2036
+
2177
2037
return 0;
2038
+
}
2039
+
2040
+
static int __maybe_unused atmel_xdmac_runtime_suspend(struct device *dev)
2041
+
{
2042
+
struct at_xdmac *atxdmac = dev_get_drvdata(dev);
2043
+
2044
+
clk_disable(atxdmac->clk);
2045
+
2046
+
return 0;
2047
+
}
2048
+
2049
+
static int __maybe_unused atmel_xdmac_runtime_resume(struct device *dev)
2050
+
{
2051
+
struct at_xdmac *atxdmac = dev_get_drvdata(dev);
2052
+
2053
+
return clk_enable(atxdmac->clk);
2178
2054
}
2179
2055
2180
2056
static int at_xdmac_probe(struct platform_device *pdev)
···
2235
2071
2236
2072
atxdmac->regs = base;
2237
2073
atxdmac->irq = irq;
2074
+
atxdmac->dev = &pdev->dev;
2238
2075
2239
2076
atxdmac->layout = of_device_get_match_data(&pdev->dev);
2240
2077
if (!atxdmac->layout)
···
2300
2135
atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2301
2136
atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
2302
2137
2303
-
/* Disable all chans and interrupts. */
2304
-
at_xdmac_off(atxdmac);
2138
+
platform_set_drvdata(pdev, atxdmac);
2139
+
2140
+
pm_runtime_set_autosuspend_delay(&pdev->dev, 500);
2141
+
pm_runtime_use_autosuspend(&pdev->dev);
2142
+
pm_runtime_set_active(&pdev->dev);
2143
+
pm_runtime_enable(&pdev->dev);
2144
+
pm_runtime_get_noresume(&pdev->dev);
2305
2145
2306
2146
/* Init channels. */
2307
2147
INIT_LIST_HEAD(&atxdmac->dma.channels);
2148
+
2149
+
/* Disable all chans and interrupts. */
2150
+
at_xdmac_off(atxdmac);
2151
+
2308
2152
for (i = 0; i < nr_channels; i++) {
2309
2153
struct at_xdmac_chan *atchan = &atxdmac->chan[i];
2310
2154
···
2333
2159
while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
2334
2160
cpu_relax();
2335
2161
}
2336
-
platform_set_drvdata(pdev, atxdmac);
2337
2162
2338
2163
ret = dma_async_device_register(&atxdmac->dma);
2339
2164
if (ret) {
2340
2165
dev_err(&pdev->dev, "fail to register DMA engine device\n");
2341
-
goto err_clk_disable;
2166
+
goto err_pm_disable;
2342
2167
}
2343
2168
2344
2169
ret = of_dma_controller_register(pdev->dev.of_node,
···
2352
2179
2353
2180
at_xdmac_axi_config(pdev);
2354
2181
2182
+
pm_runtime_mark_last_busy(&pdev->dev);
2183
+
pm_runtime_put_autosuspend(&pdev->dev);
2184
+
2355
2185
return 0;
2356
2186
2357
2187
err_dma_unregister:
2358
2188
dma_async_device_unregister(&atxdmac->dma);
2189
+
err_pm_disable:
2190
+
pm_runtime_put_noidle(&pdev->dev);
2191
+
pm_runtime_disable(&pdev->dev);
2192
+
pm_runtime_set_suspended(&pdev->dev);
2193
+
pm_runtime_dont_use_autosuspend(&pdev->dev);
2359
2194
err_clk_disable:
2360
2195
clk_disable_unprepare(atxdmac->clk);
2361
2196
err_free_irq:
···
2379
2198
at_xdmac_off(atxdmac);
2380
2199
of_dma_controller_free(pdev->dev.of_node);
2381
2200
dma_async_device_unregister(&atxdmac->dma);
2201
+
pm_runtime_disable(atxdmac->dev);
2202
+
pm_runtime_set_suspended(&pdev->dev);
2203
+
pm_runtime_dont_use_autosuspend(&pdev->dev);
2382
2204
clk_disable_unprepare(atxdmac->clk);
2383
2205
2384
2206
free_irq(atxdmac->irq, atxdmac);
···
2399
2215
static const struct dev_pm_ops __maybe_unused atmel_xdmac_dev_pm_ops = {
2400
2216
.prepare = atmel_xdmac_prepare,
2401
2217
SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
2218
+
SET_RUNTIME_PM_OPS(atmel_xdmac_runtime_suspend,
2219
+
atmel_xdmac_runtime_resume, NULL)
2402
2220
};
2403
2221
2404
2222
static const struct of_device_id atmel_xdmac_dt_ids[] = {
+1
-3
drivers/dma/bcm2835-dma.c
+1
-3
drivers/dma/bcm2835-dma.c
···
878
878
static int bcm2835_dma_probe(struct platform_device *pdev)
879
879
{
880
880
struct bcm2835_dmadev *od;
881
-
struct resource *res;
882
881
void __iomem *base;
883
882
int rc;
884
883
int i, j;
···
901
902
902
903
dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
903
904
904
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
905
-
base = devm_ioremap_resource(&pdev->dev, res);
905
+
base = devm_platform_ioremap_resource(pdev, 0);
906
906
if (IS_ERR(base))
907
907
return PTR_ERR(base);
908
908
+1
-3
drivers/dma/dma-axi-dmac.c
+1
-3
drivers/dma/dma-axi-dmac.c
···
910
910
{
911
911
struct dma_device *dma_dev;
912
912
struct axi_dmac *dmac;
913
-
struct resource *res;
914
913
struct regmap *regmap;
915
914
unsigned int version;
916
915
int ret;
···
924
925
if (dmac->irq == 0)
925
926
return -EINVAL;
926
927
927
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
928
-
dmac->base = devm_ioremap_resource(&pdev->dev, res);
928
+
dmac->base = devm_platform_ioremap_resource(pdev, 0);
929
929
if (IS_ERR(dmac->base))
930
930
return PTR_ERR(dmac->base);
931
931
+7
-19
drivers/dma/dmaengine.c
+7
-19
drivers/dma/dmaengine.c
···
172
172
if (chan) {
173
173
for_each_possible_cpu(i)
174
174
count += per_cpu_ptr(chan->local, i)->memcpy_count;
175
-
err = sprintf(buf, "%lu\n", count);
175
+
err = sysfs_emit(buf, "%lu\n", count);
176
176
} else
177
177
err = -ENODEV;
178
178
mutex_unlock(&dma_list_mutex);
···
194
194
if (chan) {
195
195
for_each_possible_cpu(i)
196
196
count += per_cpu_ptr(chan->local, i)->bytes_transferred;
197
-
err = sprintf(buf, "%lu\n", count);
197
+
err = sysfs_emit(buf, "%lu\n", count);
198
198
} else
199
199
err = -ENODEV;
200
200
mutex_unlock(&dma_list_mutex);
···
212
212
mutex_lock(&dma_list_mutex);
213
213
chan = dev_to_dma_chan(dev);
214
214
if (chan)
215
-
err = sprintf(buf, "%d\n", chan->client_count);
215
+
err = sysfs_emit(buf, "%d\n", chan->client_count);
216
216
else
217
217
err = -ENODEV;
218
218
mutex_unlock(&dma_list_mutex);
···
1323
1323
}
1324
1324
EXPORT_SYMBOL(dma_async_device_unregister);
1325
1325
1326
-
static void dmam_device_release(struct device *dev, void *res)
1326
+
static void dmaenginem_async_device_unregister(void *device)
1327
1327
{
1328
-
struct dma_device *device;
1329
-
1330
-
device = *(struct dma_device **)res;
1331
1328
dma_async_device_unregister(device);
1332
1329
}
1333
1330
···
1336
1339
*/
1337
1340
int dmaenginem_async_device_register(struct dma_device *device)
1338
1341
{
1339
-
void *p;
1340
1342
int ret;
1341
1343
1342
-
p = devres_alloc(dmam_device_release, sizeof(void *), GFP_KERNEL);
1343
-
if (!p)
1344
-
return -ENOMEM;
1345
-
1346
1344
ret = dma_async_device_register(device);
1347
-
if (!ret) {
1348
-
*(struct dma_device **)p = device;
1349
-
devres_add(device->dev, p);
1350
-
} else {
1351
-
devres_free(p);
1352
-
}
1345
+
if (ret)
1346
+
return ret;
1353
1347
1354
-
return ret;
1348
+
return devm_add_action(device->dev, dmaenginem_async_device_unregister, device);
1355
1349
}
1356
1350
EXPORT_SYMBOL(dmaenginem_async_device_register);
1357
1351
+1
-5
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+1
-5
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
···
325
325
len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
326
326
completed_length = completed_blocks * len;
327
327
bytes = length - completed_length;
328
-
} else {
329
-
bytes = vd_to_axi_desc(vdesc)->length;
330
328
}
331
329
332
330
spin_unlock_irqrestore(&chan->vc.lock, flags);
···
1369
1371
{
1370
1372
struct device_node *node = pdev->dev.of_node;
1371
1373
struct axi_dma_chip *chip;
1372
-
struct resource *mem;
1373
1374
struct dw_axi_dma *dw;
1374
1375
struct dw_axi_dma_hcfg *hdata;
1375
1376
u32 i;
···
1394
1397
if (chip->irq < 0)
1395
1398
return chip->irq;
1396
1399
1397
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1398
-
chip->regs = devm_ioremap_resource(chip->dev, mem);
1400
+
chip->regs = devm_platform_ioremap_resource(pdev, 0);
1399
1401
if (IS_ERR(chip->regs))
1400
1402
return PTR_ERR(chip->regs);
1401
1403
+5
-6
drivers/dma/dw/core.c
+5
-6
drivers/dma/dw/core.c
···
889
889
return NULL;
890
890
}
891
891
892
-
static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie)
892
+
static u32 dwc_get_residue_and_status(struct dw_dma_chan *dwc, dma_cookie_t cookie,
893
+
enum dma_status *status)
893
894
{
894
895
struct dw_desc *desc;
895
896
unsigned long flags;
···
904
903
residue = desc->residue;
905
904
if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
906
905
residue -= dwc_get_sent(dwc);
906
+
if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags))
907
+
*status = DMA_PAUSED;
907
908
} else {
908
909
residue = desc->total_len;
909
910
}
···
935
932
if (ret == DMA_COMPLETE)
936
933
return ret;
937
934
938
-
dma_set_residue(txstate, dwc_get_residue(dwc, cookie));
939
-
940
-
if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS)
941
-
return DMA_PAUSED;
942
-
935
+
dma_set_residue(txstate, dwc_get_residue_and_status(dwc, cookie, &ret));
943
936
return ret;
944
937
}
945
938
+3
-5
drivers/dma/fsl-edma.c
+3
-5
drivers/dma/fsl-edma.c
···
272
272
const struct fsl_edma_drvdata *drvdata = NULL;
273
273
struct fsl_edma_chan *fsl_chan;
274
274
struct edma_regs *regs;
275
-
struct resource *res;
276
275
int len, chans;
277
276
int ret, i;
278
277
···
297
298
fsl_edma->n_chans = chans;
298
299
mutex_init(&fsl_edma->fsl_edma_mutex);
299
300
300
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
301
-
fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res);
301
+
fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0);
302
302
if (IS_ERR(fsl_edma->membase))
303
303
return PTR_ERR(fsl_edma->membase);
304
304
···
321
323
for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
322
324
char clkname[32];
323
325
324
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i);
325
-
fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res);
326
+
fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev,
327
+
1 + i);
326
328
if (IS_ERR(fsl_edma->muxbase[i])) {
327
329
/* on error: disable all previously enabled clks */
328
330
fsl_disable_clocks(fsl_edma, i);
+3
-7
drivers/dma/fsl-qdma.c
+3
-7
drivers/dma/fsl-qdma.c
···
1119
1119
int ret, i;
1120
1120
int blk_num, blk_off;
1121
1121
u32 len, chans, queues;
1122
-
struct resource *res;
1123
1122
struct fsl_qdma_chan *fsl_chan;
1124
1123
struct fsl_qdma_engine *fsl_qdma;
1125
1124
struct device_node *np = pdev->dev.of_node;
···
1182
1183
if (!fsl_qdma->status[i])
1183
1184
return -ENOMEM;
1184
1185
}
1185
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1186
-
fsl_qdma->ctrl_base = devm_ioremap_resource(&pdev->dev, res);
1186
+
fsl_qdma->ctrl_base = devm_platform_ioremap_resource(pdev, 0);
1187
1187
if (IS_ERR(fsl_qdma->ctrl_base))
1188
1188
return PTR_ERR(fsl_qdma->ctrl_base);
1189
1189
1190
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1191
-
fsl_qdma->status_base = devm_ioremap_resource(&pdev->dev, res);
1190
+
fsl_qdma->status_base = devm_platform_ioremap_resource(pdev, 1);
1192
1191
if (IS_ERR(fsl_qdma->status_base))
1193
1192
return PTR_ERR(fsl_qdma->status_base);
1194
1193
1195
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1196
-
fsl_qdma->block_base = devm_ioremap_resource(&pdev->dev, res);
1194
+
fsl_qdma->block_base = devm_platform_ioremap_resource(pdev, 2);
1197
1195
if (IS_ERR(fsl_qdma->block_base))
1198
1196
return PTR_ERR(fsl_qdma->block_base);
1199
1197
fsl_qdma->queue = fsl_qdma_alloc_queue_resources(pdev, fsl_qdma);
+5
-3
drivers/dma/idma64.c
+5
-3
drivers/dma/idma64.c
···
137
137
u32 status_err, u32 status_xfer)
138
138
{
139
139
struct idma64_chan *idma64c = &idma64->chan[c];
140
+
struct dma_chan_percpu *stat;
140
141
struct idma64_desc *desc;
142
+
143
+
stat = this_cpu_ptr(idma64c->vchan.chan.local);
141
144
142
145
spin_lock(&idma64c->vchan.lock);
143
146
desc = idma64c->desc;
···
152
149
dma_writel(idma64, CLEAR(XFER), idma64c->mask);
153
150
desc->status = DMA_COMPLETE;
154
151
vchan_cookie_complete(&desc->vdesc);
152
+
stat->bytes_transferred += desc->length;
155
153
idma64_start_transfer(idma64c);
156
154
}
157
155
···
631
627
struct idma64_chip *chip;
632
628
struct device *dev = &pdev->dev;
633
629
struct device *sysdev = dev->parent;
634
-
struct resource *mem;
635
630
int ret;
636
631
637
632
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
···
641
638
if (chip->irq < 0)
642
639
return chip->irq;
643
640
644
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
645
-
chip->regs = devm_ioremap_resource(dev, mem);
641
+
chip->regs = devm_platform_ioremap_resource(pdev, 0);
646
642
if (IS_ERR(chip->regs))
647
643
return PTR_ERR(chip->regs);
648
644
+7
-7
drivers/dma/idxd/device.c
+7
-7
drivers/dma/idxd/device.c
···
699
699
group->num_engines = 0;
700
700
group->num_wqs = 0;
701
701
group->use_rdbuf_limit = false;
702
-
group->rdbufs_allowed = 0;
702
+
/*
703
+
* The default value is the same as the value of
704
+
* total read buffers in GRPCAP.
705
+
*/
706
+
group->rdbufs_allowed = idxd->max_rdbufs;
703
707
group->rdbufs_reserved = 0;
704
-
if (idxd->hw.version < DEVICE_VERSION_2 && !tc_override) {
708
+
if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) {
705
709
group->tc_a = 1;
706
710
group->tc_b = 1;
707
711
} else {
···
938
934
group->grpcfg.flags.tc_b = group->tc_b;
939
935
group->grpcfg.flags.use_rdbuf_limit = group->use_rdbuf_limit;
940
936
group->grpcfg.flags.rdbufs_reserved = group->rdbufs_reserved;
941
-
if (group->rdbufs_allowed)
942
-
group->grpcfg.flags.rdbufs_allowed = group->rdbufs_allowed;
943
-
else
944
-
group->grpcfg.flags.rdbufs_allowed = idxd->max_rdbufs;
945
-
937
+
group->grpcfg.flags.rdbufs_allowed = group->rdbufs_allowed;
946
938
group->grpcfg.flags.desc_progress_limit = group->desc_progress_limit;
947
939
group->grpcfg.flags.batch_progress_limit = group->batch_progress_limit;
948
940
}
-6
drivers/dma/idxd/dma.c
-6
drivers/dma/idxd/dma.c
···
63
63
*desc_flags |= IDXD_OP_FLAG_RCI;
64
64
}
65
65
66
-
static inline void set_completion_address(struct idxd_desc *desc,
67
-
u64 *compl_addr)
68
-
{
69
-
*compl_addr = desc->compl_dma;
70
-
}
71
-
72
66
static inline void idxd_prep_desc_common(struct idxd_wq *wq,
73
67
struct dsa_hw_desc *hw, char opcode,
74
68
u64 addr_f1, u64 addr_f2, u64 len,
+6
-1
drivers/dma/idxd/init.c
+6
-1
drivers/dma/idxd/init.c
···
295
295
}
296
296
297
297
idxd->groups[i] = group;
298
-
if (idxd->hw.version < DEVICE_VERSION_2 && !tc_override) {
298
+
if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) {
299
299
group->tc_a = 1;
300
300
group->tc_b = 1;
301
301
} else {
302
302
group->tc_a = -1;
303
303
group->tc_b = -1;
304
304
}
305
+
/*
306
+
* The default value is the same as the value of
307
+
* total read buffers in GRPCAP.
308
+
*/
309
+
group->rdbufs_allowed = idxd->max_rdbufs;
305
310
}
306
311
307
312
return 0;
+2
-2
drivers/dma/idxd/sysfs.c
+2
-2
drivers/dma/idxd/sysfs.c
···
387
387
if (idxd->state == IDXD_DEV_ENABLED)
388
388
return -EPERM;
389
389
390
-
if (idxd->hw.version < DEVICE_VERSION_2 && !tc_override)
390
+
if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override)
391
391
return -EPERM;
392
392
393
393
if (val < 0 || val > 7)
···
429
429
if (idxd->state == IDXD_DEV_ENABLED)
430
430
return -EPERM;
431
431
432
-
if (idxd->hw.version < DEVICE_VERSION_2 && !tc_override)
432
+
if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override)
433
433
return -EPERM;
434
434
435
435
if (val < 0 || val > 7)
+1
-3
drivers/dma/img-mdc-dma.c
+1
-3
drivers/dma/img-mdc-dma.c
···
886
886
static int mdc_dma_probe(struct platform_device *pdev)
887
887
{
888
888
struct mdc_dma *mdma;
889
-
struct resource *res;
890
889
unsigned int i;
891
890
u32 val;
892
891
int ret;
···
897
898
898
899
mdma->soc = of_device_get_match_data(&pdev->dev);
899
900
900
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
901
-
mdma->regs = devm_ioremap_resource(&pdev->dev, res);
901
+
mdma->regs = devm_platform_ioremap_resource(pdev, 0);
902
902
if (IS_ERR(mdma->regs))
903
903
return PTR_ERR(mdma->regs);
904
904
+1
-3
drivers/dma/imx-dma.c
+1
-3
drivers/dma/imx-dma.c
···
1038
1038
static int __init imxdma_probe(struct platform_device *pdev)
1039
1039
{
1040
1040
struct imxdma_engine *imxdma;
1041
-
struct resource *res;
1042
1041
int ret, i;
1043
1042
int irq, irq_err;
1044
1043
···
1048
1049
imxdma->dev = &pdev->dev;
1049
1050
imxdma->devtype = (uintptr_t)of_device_get_match_data(&pdev->dev);
1050
1051
1051
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1052
-
imxdma->base = devm_ioremap_resource(&pdev->dev, res);
1052
+
imxdma->base = devm_platform_ioremap_resource(pdev, 0);
1053
1053
if (IS_ERR(imxdma->base))
1054
1054
return PTR_ERR(imxdma->base);
1055
1055
+32
-11
drivers/dma/imx-sdma.c
+32
-11
drivers/dma/imx-sdma.c
···
954
954
desc = sdmac->desc;
955
955
if (desc) {
956
956
if (sdmac->flags & IMX_DMA_SG_LOOP) {
957
-
sdma_update_channel_loop(sdmac);
957
+
if (sdmac->peripheral_type != IMX_DMATYPE_HDMI)
958
+
sdma_update_channel_loop(sdmac);
959
+
else
960
+
vchan_cyclic_callback(&desc->vd);
958
961
} else {
959
962
mxc_sdma_handle_channel_normal(sdmac);
960
963
vchan_cookie_complete(&desc->vd);
···
1077
1074
per_2_emi = sdma->script_addrs->sai_2_mcu_addr;
1078
1075
emi_2_per = sdma->script_addrs->mcu_2_sai_addr;
1079
1076
break;
1077
+
case IMX_DMATYPE_HDMI:
1078
+
emi_2_per = sdma->script_addrs->hdmi_dma_addr;
1079
+
sdmac->is_ram_script = true;
1080
+
break;
1080
1081
default:
1081
1082
dev_err(sdma->dev, "Unsupported transfer type %d\n",
1082
1083
peripheral_type);
···
1132
1125
/* Send by context the event mask,base address for peripheral
1133
1126
* and watermark level
1134
1127
*/
1135
-
context->gReg[0] = sdmac->event_mask[1];
1136
-
context->gReg[1] = sdmac->event_mask[0];
1137
-
context->gReg[2] = sdmac->per_addr;
1138
-
context->gReg[6] = sdmac->shp_addr;
1139
-
context->gReg[7] = sdmac->watermark_level;
1128
+
if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) {
1129
+
context->gReg[4] = sdmac->per_addr;
1130
+
context->gReg[6] = sdmac->shp_addr;
1131
+
} else {
1132
+
context->gReg[0] = sdmac->event_mask[1];
1133
+
context->gReg[1] = sdmac->event_mask[0];
1134
+
context->gReg[2] = sdmac->per_addr;
1135
+
context->gReg[6] = sdmac->shp_addr;
1136
+
context->gReg[7] = sdmac->watermark_level;
1137
+
}
1140
1138
1141
1139
bd0->mode.command = C0_SETDM;
1142
1140
bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
···
1525
1513
desc->sdmac = sdmac;
1526
1514
desc->num_bd = bds;
1527
1515
1528
-
if (sdma_alloc_bd(desc))
1516
+
if (bds && sdma_alloc_bd(desc))
1529
1517
goto err_desc_out;
1530
1518
1531
1519
/* No slave_config called in MEMCPY case, so do here */
···
1692
1680
{
1693
1681
struct sdma_channel *sdmac = to_sdma_chan(chan);
1694
1682
struct sdma_engine *sdma = sdmac->sdma;
1695
-
int num_periods = buf_len / period_len;
1683
+
int num_periods = 0;
1696
1684
int channel = sdmac->channel;
1697
1685
int i = 0, buf = 0;
1698
1686
struct sdma_desc *desc;
1699
1687
1700
1688
dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1689
+
1690
+
if (sdmac->peripheral_type != IMX_DMATYPE_HDMI)
1691
+
num_periods = buf_len / period_len;
1701
1692
1702
1693
sdma_config_write(chan, &sdmac->slave_config, direction);
1703
1694
···
1717
1702
channel, period_len, SDMA_BD_MAX_CNT);
1718
1703
goto err_bd_out;
1719
1704
}
1705
+
1706
+
if (sdmac->peripheral_type == IMX_DMATYPE_HDMI)
1707
+
return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1720
1708
1721
1709
while (buf < buf_len) {
1722
1710
struct sdma_buffer_descriptor *bd = &desc->bd[i];
···
1781
1763
sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1782
1764
SDMA_WATERMARK_LEVEL_HWML;
1783
1765
sdmac->word_size = dmaengine_cfg->dst_addr_width;
1766
+
} else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) {
1767
+
sdmac->per_address = dmaengine_cfg->dst_addr;
1768
+
sdmac->per_address2 = dmaengine_cfg->src_addr;
1769
+
sdmac->watermark_level = 0;
1784
1770
} else {
1785
1771
sdmac->per_address = dmaengine_cfg->dst_addr;
1786
1772
sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
···
2191
2169
const char *fw_name;
2192
2170
int ret;
2193
2171
int irq;
2194
-
struct resource *iores;
2195
2172
struct resource spba_res;
2196
2173
int i;
2197
2174
struct sdma_engine *sdma;
···
2213
2192
if (irq < 0)
2214
2193
return irq;
2215
2194
2216
-
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2217
-
sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
2195
+
sdma->regs = devm_platform_ioremap_resource(pdev, 0);
2218
2196
if (IS_ERR(sdma->regs))
2219
2197
return PTR_ERR(sdma->regs);
2220
2198
···
2254
2234
dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2255
2235
dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2256
2236
dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2237
+
dma_cap_set(DMA_PRIVATE, sdma->dma_device.cap_mask);
2257
2238
2258
2239
INIT_LIST_HEAD(&sdma->dma_device.channels);
2259
2240
/* Initialize channel parameters */
+1
-4
drivers/dma/mcf-edma.c
+1
-4
drivers/dma/mcf-edma.c
···
182
182
struct fsl_edma_engine *mcf_edma;
183
183
struct fsl_edma_chan *mcf_chan;
184
184
struct edma_regs *regs;
185
-
struct resource *res;
186
185
int ret, i, len, chans;
187
186
188
187
pdata = dev_get_platdata(&pdev->dev);
···
209
210
210
211
mutex_init(&mcf_edma->fsl_edma_mutex);
211
212
212
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
213
-
214
-
mcf_edma->membase = devm_ioremap_resource(&pdev->dev, res);
213
+
mcf_edma->membase = devm_platform_ioremap_resource(pdev, 0);
215
214
if (IS_ERR(mcf_edma->membase))
216
215
return PTR_ERR(mcf_edma->membase);
217
216
+1
-3
drivers/dma/mediatek/mtk-hsdma.c
+1
-3
drivers/dma/mediatek/mtk-hsdma.c
···
896
896
struct mtk_hsdma_device *hsdma;
897
897
struct mtk_hsdma_vchan *vc;
898
898
struct dma_device *dd;
899
-
struct resource *res;
900
899
int i, err;
901
900
902
901
hsdma = devm_kzalloc(&pdev->dev, sizeof(*hsdma), GFP_KERNEL);
···
904
905
905
906
dd = &hsdma->ddev;
906
907
907
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
908
-
hsdma->base = devm_ioremap_resource(&pdev->dev, res);
908
+
hsdma->base = devm_platform_ioremap_resource(pdev, 0);
909
909
if (IS_ERR(hsdma->base))
910
910
return PTR_ERR(hsdma->base);
911
911
+1
-3
drivers/dma/mmp_pdma.c
+1
-3
drivers/dma/mmp_pdma.c
···
1022
1022
struct mmp_pdma_device *pdev;
1023
1023
const struct of_device_id *of_id;
1024
1024
struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
1025
-
struct resource *iores;
1026
1025
int i, ret, irq = 0;
1027
1026
int dma_channels = 0, irq_num = 0;
1028
1027
const enum dma_slave_buswidth widths =
···
1036
1037
1037
1038
spin_lock_init(&pdev->phy_lock);
1038
1039
1039
-
iores = platform_get_resource(op, IORESOURCE_MEM, 0);
1040
-
pdev->base = devm_ioremap_resource(pdev->dev, iores);
1040
+
pdev->base = devm_platform_ioremap_resource(op, 0);
1041
1041
if (IS_ERR(pdev->base))
1042
1042
return PTR_ERR(pdev->base);
1043
1043
+1
-3
drivers/dma/mmp_tdma.c
+1
-3
drivers/dma/mmp_tdma.c
···
639
639
enum mmp_tdma_type type;
640
640
const struct of_device_id *of_id;
641
641
struct mmp_tdma_device *tdev;
642
-
struct resource *iores;
643
642
int i, ret;
644
643
int irq = 0, irq_num = 0;
645
644
int chan_num = TDMA_CHANNEL_NUM;
···
662
663
irq_num++;
663
664
}
664
665
665
-
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
666
-
tdev->base = devm_ioremap_resource(&pdev->dev, iores);
666
+
tdev->base = devm_platform_ioremap_resource(pdev, 0);
667
667
if (IS_ERR(tdev->base))
668
668
return PTR_ERR(tdev->base);
669
669
+1
-3
drivers/dma/moxart-dma.c
+1
-3
drivers/dma/moxart-dma.c
···
563
563
{
564
564
struct device *dev = &pdev->dev;
565
565
struct device_node *node = dev->of_node;
566
-
struct resource *res;
567
566
void __iomem *dma_base_addr;
568
567
int ret, i;
569
568
unsigned int irq;
···
579
580
return -EINVAL;
580
581
}
581
582
582
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
583
-
dma_base_addr = devm_ioremap_resource(dev, res);
583
+
dma_base_addr = devm_platform_ioremap_resource(pdev, 0);
584
584
if (IS_ERR(dma_base_addr))
585
585
return PTR_ERR(dma_base_addr);
586
586
+2
-5
drivers/dma/mv_xor_v2.c
+2
-5
drivers/dma/mv_xor_v2.c
···
714
714
static int mv_xor_v2_probe(struct platform_device *pdev)
715
715
{
716
716
struct mv_xor_v2_device *xor_dev;
717
-
struct resource *res;
718
717
int i, ret = 0;
719
718
struct dma_device *dma_dev;
720
719
struct mv_xor_v2_sw_desc *sw_desc;
···
725
726
if (!xor_dev)
726
727
return -ENOMEM;
727
728
728
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
729
-
xor_dev->dma_base = devm_ioremap_resource(&pdev->dev, res);
729
+
xor_dev->dma_base = devm_platform_ioremap_resource(pdev, 0);
730
730
if (IS_ERR(xor_dev->dma_base))
731
731
return PTR_ERR(xor_dev->dma_base);
732
732
733
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
734
-
xor_dev->glob_base = devm_ioremap_resource(&pdev->dev, res);
733
+
xor_dev->glob_base = devm_platform_ioremap_resource(pdev, 1);
735
734
if (IS_ERR(xor_dev->glob_base))
736
735
return PTR_ERR(xor_dev->glob_base);
737
736
+1
-3
drivers/dma/mxs-dma.c
+1
-3
drivers/dma/mxs-dma.c
···
746
746
struct device_node *np = pdev->dev.of_node;
747
747
const struct mxs_dma_type *dma_type;
748
748
struct mxs_dma_engine *mxs_dma;
749
-
struct resource *iores;
750
749
int ret, i;
751
750
752
751
mxs_dma = devm_kzalloc(&pdev->dev, sizeof(*mxs_dma), GFP_KERNEL);
···
762
763
mxs_dma->type = dma_type->type;
763
764
mxs_dma->dev_id = dma_type->id;
764
765
765
-
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
766
-
mxs_dma->base = devm_ioremap_resource(&pdev->dev, iores);
766
+
mxs_dma->base = devm_platform_ioremap_resource(pdev, 0);
767
767
if (IS_ERR(mxs_dma->base))
768
768
return PTR_ERR(mxs_dma->base);
769
769
+1
-3
drivers/dma/nbpfaxi.c
+1
-3
drivers/dma/nbpfaxi.c
···
1294
1294
struct device_node *np = dev->of_node;
1295
1295
struct nbpf_device *nbpf;
1296
1296
struct dma_device *dma_dev;
1297
-
struct resource *iomem;
1298
1297
const struct nbpf_config *cfg;
1299
1298
int num_channels;
1300
1299
int ret, irq, eirq, i;
···
1317
1318
dma_dev = &nbpf->dma_dev;
1318
1319
dma_dev->dev = dev;
1319
1320
1320
-
iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1321
-
nbpf->base = devm_ioremap_resource(dev, iomem);
1321
+
nbpf->base = devm_platform_ioremap_resource(pdev, 0);
1322
1322
if (IS_ERR(nbpf->base))
1323
1323
return PTR_ERR(nbpf->base);
1324
1324
+5
-7
drivers/dma/ppc4xx/adma.c
+5
-7
drivers/dma/ppc4xx/adma.c
···
4299
4299
for (i = 0; i < PPC440SPE_ADMA_ENGINES_NUM; i++) {
4300
4300
if (ppc440spe_adma_devices[i] == -1)
4301
4301
continue;
4302
-
size += scnprintf(buf + size, PAGE_SIZE - size,
4303
-
"PPC440SP(E)-ADMA.%d: %s\n", i,
4304
-
ppc_adma_errors[ppc440spe_adma_devices[i]]);
4302
+
size += sysfs_emit_at(buf, size, "PPC440SP(E)-ADMA.%d: %s\n",
4303
+
i, ppc_adma_errors[ppc440spe_adma_devices[i]]);
4305
4304
}
4306
4305
return size;
4307
4306
}
···
4308
4309
4309
4310
static ssize_t enable_show(struct device_driver *dev, char *buf)
4310
4311
{
4311
-
return snprintf(buf, PAGE_SIZE,
4312
-
"PPC440SP(e) RAID-6 capabilities are %sABLED.\n",
4313
-
ppc440spe_r6_enabled ? "EN" : "DIS");
4312
+
return sysfs_emit(buf, "PPC440SP(e) RAID-6 capabilities are %sABLED.\n",
4313
+
ppc440spe_r6_enabled ? "EN" : "DIS");
4314
4314
}
4315
4315
4316
4316
static ssize_t enable_store(struct device_driver *dev, const char *buf,
···
4360
4362
reg &= 0xFF;
4361
4363
#endif
4362
4364
4363
-
size = snprintf(buf, PAGE_SIZE, "PPC440SP(e) RAID-6 driver "
4365
+
size = sysfs_emit(buf, "PPC440SP(e) RAID-6 driver "
4364
4366
"uses 0x1%02x polynomial.\n", reg);
4365
4367
return size;
4366
4368
}
+1
-1
drivers/dma/ptdma/ptdma-dmaengine.c
+1
-1
drivers/dma/ptdma/ptdma-dmaengine.c
+1
-3
drivers/dma/pxa_dma.c
+1
-3
drivers/dma/pxa_dma.c
···
1346
1346
const struct of_device_id *of_id;
1347
1347
const struct dma_slave_map *slave_map = NULL;
1348
1348
struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
1349
-
struct resource *iores;
1350
1349
int ret, dma_channels = 0, nb_requestors = 0, slave_map_cnt = 0;
1351
1350
const enum dma_slave_buswidth widths =
1352
1351
DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES |
···
1357
1358
1358
1359
spin_lock_init(&pdev->phy_lock);
1359
1360
1360
-
iores = platform_get_resource(op, IORESOURCE_MEM, 0);
1361
-
pdev->base = devm_ioremap_resource(&op->dev, iores);
1361
+
pdev->base = devm_platform_ioremap_resource(op, 0);
1362
1362
if (IS_ERR(pdev->base))
1363
1363
return PTR_ERR(pdev->base);
1364
1364
+1
-3
drivers/dma/qcom/bam_dma.c
+1
-3
drivers/dma/qcom/bam_dma.c
···
1237
1237
{
1238
1238
struct bam_device *bdev;
1239
1239
const struct of_device_id *match;
1240
-
struct resource *iores;
1241
1240
int ret, i;
1242
1241
1243
1242
bdev = devm_kzalloc(&pdev->dev, sizeof(*bdev), GFP_KERNEL);
···
1253
1254
1254
1255
bdev->layout = match->data;
1255
1256
1256
-
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1257
-
bdev->regs = devm_ioremap_resource(&pdev->dev, iores);
1257
+
bdev->regs = devm_platform_ioremap_resource(pdev, 0);
1258
1258
if (IS_ERR(bdev->regs))
1259
1259
return PTR_ERR(bdev->regs);
1260
1260
+2
-5
drivers/dma/sf-pdma/sf-pdma.c
+2
-5
drivers/dma/sf-pdma/sf-pdma.c
···
96
96
if (!desc)
97
97
return NULL;
98
98
99
-
desc->in_use = true;
100
99
desc->dirn = DMA_MEM_TO_MEM;
101
100
desc->async_tx = vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
102
101
···
289
290
struct sf_pdma_desc *desc;
290
291
291
292
desc = to_sf_pdma_desc(vdesc);
292
-
desc->in_use = false;
293
+
kfree(desc);
293
294
}
294
295
295
296
static void sf_pdma_donebh_tasklet(struct tasklet_struct *t)
···
493
494
static int sf_pdma_probe(struct platform_device *pdev)
494
495
{
495
496
struct sf_pdma *pdma;
496
-
struct resource *res;
497
497
int ret, n_chans;
498
498
const enum dma_slave_buswidth widths =
499
499
DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES |
···
517
519
518
520
pdma->n_chans = n_chans;
519
521
520
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
521
-
pdma->membase = devm_ioremap_resource(&pdev->dev, res);
522
+
pdma->membase = devm_platform_ioremap_resource(pdev, 0);
522
523
if (IS_ERR(pdma->membase))
523
524
return PTR_ERR(pdma->membase);
524
525
-1
drivers/dma/sf-pdma/sf-pdma.h
-1
drivers/dma/sf-pdma/sf-pdma.h
+1
-3
drivers/dma/sh/usb-dmac.c
+1
-3
drivers/dma/sh/usb-dmac.c
···
768
768
const enum dma_slave_buswidth widths = USB_DMAC_SLAVE_BUSWIDTH;
769
769
struct dma_device *engine;
770
770
struct usb_dmac *dmac;
771
-
struct resource *mem;
772
771
unsigned int i;
773
772
int ret;
774
773
···
788
789
return -ENOMEM;
789
790
790
791
/* Request resources. */
791
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
792
-
dmac->iomem = devm_ioremap_resource(&pdev->dev, mem);
792
+
dmac->iomem = devm_platform_ioremap_resource(pdev, 0);
793
793
if (IS_ERR(dmac->iomem))
794
794
return PTR_ERR(dmac->iomem);
795
795
+1
-3
drivers/dma/stm32-dmamux.c
+1
-3
drivers/dma/stm32-dmamux.c
···
179
179
const struct of_device_id *match;
180
180
struct device_node *dma_node;
181
181
struct stm32_dmamux_data *stm32_dmamux;
182
-
struct resource *res;
183
182
void __iomem *iomem;
184
183
struct reset_control *rst;
185
184
int i, count, ret;
···
237
238
}
238
239
pm_runtime_get_noresume(&pdev->dev);
239
240
240
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
241
-
iomem = devm_ioremap_resource(&pdev->dev, res);
241
+
iomem = devm_platform_ioremap_resource(pdev, 0);
242
242
if (IS_ERR(iomem))
243
243
return PTR_ERR(iomem);
244
244
+1
-3
drivers/dma/stm32-mdma.c
+1
-3
drivers/dma/stm32-mdma.c
···
1580
1580
struct stm32_mdma_device *dmadev;
1581
1581
struct dma_device *dd;
1582
1582
struct device_node *of_node;
1583
-
struct resource *res;
1584
1583
struct reset_control *rst;
1585
1584
u32 nr_channels, nr_requests;
1586
1585
int i, count, ret;
···
1621
1622
count);
1622
1623
dmadev->nr_ahb_addr_masks = count;
1623
1624
1624
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1625
-
dmadev->base = devm_ioremap_resource(&pdev->dev, res);
1625
+
dmadev->base = devm_platform_ioremap_resource(pdev, 0);
1626
1626
if (IS_ERR(dmadev->base))
1627
1627
return PTR_ERR(dmadev->base);
1628
1628
+1
-3
drivers/dma/sun4i-dma.c
+1
-3
drivers/dma/sun4i-dma.c
···
1144
1144
static int sun4i_dma_probe(struct platform_device *pdev)
1145
1145
{
1146
1146
struct sun4i_dma_dev *priv;
1147
-
struct resource *res;
1148
1147
int i, j, ret;
1149
1148
1150
1149
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1151
1150
if (!priv)
1152
1151
return -ENOMEM;
1153
1152
1154
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1155
-
priv->base = devm_ioremap_resource(&pdev->dev, res);
1153
+
priv->base = devm_platform_ioremap_resource(pdev, 0);
1156
1154
if (IS_ERR(priv->base))
1157
1155
return PTR_ERR(priv->base);
1158
1156
+4
-3
drivers/dma/sun6i-dma.c
+4
-3
drivers/dma/sun6i-dma.c
···
9
9
10
10
#include <linux/clk.h>
11
11
#include <linux/delay.h>
12
+
#include <linux/dma-mapping.h>
12
13
#include <linux/dmaengine.h>
13
14
#include <linux/dmapool.h>
14
15
#include <linux/interrupt.h>
···
1284
1283
{
1285
1284
struct device_node *np = pdev->dev.of_node;
1286
1285
struct sun6i_dma_dev *sdc;
1287
-
struct resource *res;
1288
1286
int ret, i;
1289
1287
1290
1288
sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL);
···
1294
1294
if (!sdc->cfg)
1295
1295
return -ENODEV;
1296
1296
1297
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1298
-
sdc->base = devm_ioremap_resource(&pdev->dev, res);
1297
+
sdc->base = devm_platform_ioremap_resource(pdev, 0);
1299
1298
if (IS_ERR(sdc->base))
1300
1299
return PTR_ERR(sdc->base);
1301
1300
···
1332
1333
platform_set_drvdata(pdev, sdc);
1333
1334
INIT_LIST_HEAD(&sdc->pending);
1334
1335
spin_lock_init(&sdc->lock);
1336
+
1337
+
dma_set_max_seg_size(&pdev->dev, SZ_32M - 1);
1335
1338
1336
1339
dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask);
1337
1340
dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask);
+1
-3
drivers/dma/tegra210-adma.c
+1
-3
drivers/dma/tegra210-adma.c
···
837
837
{
838
838
const struct tegra_adma_chip_data *cdata;
839
839
struct tegra_adma *tdma;
840
-
struct resource *res;
841
840
int ret, i;
842
841
843
842
cdata = of_device_get_match_data(&pdev->dev);
···
856
857
tdma->nr_channels = cdata->nr_channels;
857
858
platform_set_drvdata(pdev, tdma);
858
859
859
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
860
-
tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);
860
+
tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
861
861
if (IS_ERR(tdma->base_addr))
862
862
return PTR_ERR(tdma->base_addr);
863
863
+2
-1
drivers/dma/ti/Makefile
+2
-1
drivers/dma/ti/Makefile
+3
-7
drivers/dma/ti/cppi41.c
+3
-7
drivers/dma/ti/cppi41.c
···
1039
1039
struct cppi41_dd *cdd;
1040
1040
struct device *dev = &pdev->dev;
1041
1041
const struct cppi_glue_infos *glue_info;
1042
-
struct resource *mem;
1043
1042
int index;
1044
1043
int irq;
1045
1044
int ret;
···
1071
1072
if (index < 0)
1072
1073
return index;
1073
1074
1074
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, index);
1075
-
cdd->ctrl_mem = devm_ioremap_resource(dev, mem);
1075
+
cdd->ctrl_mem = devm_platform_ioremap_resource(pdev, index);
1076
1076
if (IS_ERR(cdd->ctrl_mem))
1077
1077
return PTR_ERR(cdd->ctrl_mem);
1078
1078
1079
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, index + 1);
1080
-
cdd->sched_mem = devm_ioremap_resource(dev, mem);
1079
+
cdd->sched_mem = devm_platform_ioremap_resource(pdev, index + 1);
1081
1080
if (IS_ERR(cdd->sched_mem))
1082
1081
return PTR_ERR(cdd->sched_mem);
1083
1082
1084
-
mem = platform_get_resource(pdev, IORESOURCE_MEM, index + 2);
1085
-
cdd->qmgr_mem = devm_ioremap_resource(dev, mem);
1083
+
cdd->qmgr_mem = devm_platform_ioremap_resource(pdev, index + 2);
1086
1084
if (IS_ERR(cdd->qmgr_mem))
1087
1085
return PTR_ERR(cdd->qmgr_mem);
1088
1086
+196
drivers/dma/ti/k3-psil-am62a.c
+196
drivers/dma/ti/k3-psil-am62a.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
4
+
*/
5
+
6
+
#include <linux/kernel.h>
7
+
8
+
#include "k3-psil-priv.h"
9
+
10
+
#define PSIL_PDMA_XY_TR(x) \
11
+
{ \
12
+
.thread_id = x, \
13
+
.ep_config = { \
14
+
.ep_type = PSIL_EP_PDMA_XY, \
15
+
.mapped_channel_id = -1, \
16
+
.default_flow_id = -1, \
17
+
}, \
18
+
}
19
+
20
+
#define PSIL_PDMA_XY_PKT(x) \
21
+
{ \
22
+
.thread_id = x, \
23
+
.ep_config = { \
24
+
.ep_type = PSIL_EP_PDMA_XY, \
25
+
.mapped_channel_id = -1, \
26
+
.default_flow_id = -1, \
27
+
.pkt_mode = 1, \
28
+
}, \
29
+
}
30
+
31
+
#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
32
+
{ \
33
+
.thread_id = x, \
34
+
.ep_config = { \
35
+
.ep_type = PSIL_EP_NATIVE, \
36
+
.pkt_mode = 1, \
37
+
.needs_epib = 1, \
38
+
.psd_size = 16, \
39
+
.mapped_channel_id = ch, \
40
+
.flow_start = flow_base, \
41
+
.flow_num = flow_cnt, \
42
+
.default_flow_id = flow_base, \
43
+
}, \
44
+
}
45
+
46
+
#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
47
+
{ \
48
+
.thread_id = x, \
49
+
.ep_config = { \
50
+
.ep_type = PSIL_EP_NATIVE, \
51
+
.pkt_mode = 1, \
52
+
.needs_epib = 1, \
53
+
.psd_size = 64, \
54
+
.mapped_channel_id = ch, \
55
+
.flow_start = flow_base, \
56
+
.flow_num = flow_cnt, \
57
+
.default_flow_id = default_flow, \
58
+
.notdpkt = tx, \
59
+
}, \
60
+
}
61
+
62
+
#define PSIL_PDMA_MCASP(x) \
63
+
{ \
64
+
.thread_id = x, \
65
+
.ep_config = { \
66
+
.ep_type = PSIL_EP_PDMA_XY, \
67
+
.pdma_acc32 = 1, \
68
+
.pdma_burst = 1, \
69
+
}, \
70
+
}
71
+
72
+
#define PSIL_CSI2RX(x) \
73
+
{ \
74
+
.thread_id = x, \
75
+
.ep_config = { \
76
+
.ep_type = PSIL_EP_NATIVE, \
77
+
}, \
78
+
}
79
+
80
+
/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
81
+
static struct psil_ep am62a_src_ep_map[] = {
82
+
/* SAUL */
83
+
PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
84
+
PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
85
+
PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
86
+
PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
87
+
/* PDMA_MAIN0 - SPI0-3 */
88
+
PSIL_PDMA_XY_PKT(0x4302),
89
+
PSIL_PDMA_XY_PKT(0x4303),
90
+
PSIL_PDMA_XY_PKT(0x4304),
91
+
PSIL_PDMA_XY_PKT(0x4305),
92
+
PSIL_PDMA_XY_PKT(0x4306),
93
+
PSIL_PDMA_XY_PKT(0x4307),
94
+
PSIL_PDMA_XY_PKT(0x4308),
95
+
PSIL_PDMA_XY_PKT(0x4309),
96
+
PSIL_PDMA_XY_PKT(0x430a),
97
+
PSIL_PDMA_XY_PKT(0x430b),
98
+
PSIL_PDMA_XY_PKT(0x430c),
99
+
PSIL_PDMA_XY_PKT(0x430d),
100
+
/* PDMA_MAIN1 - UART0-6 */
101
+
PSIL_PDMA_XY_PKT(0x4400),
102
+
PSIL_PDMA_XY_PKT(0x4401),
103
+
PSIL_PDMA_XY_PKT(0x4402),
104
+
PSIL_PDMA_XY_PKT(0x4403),
105
+
PSIL_PDMA_XY_PKT(0x4404),
106
+
PSIL_PDMA_XY_PKT(0x4405),
107
+
PSIL_PDMA_XY_PKT(0x4406),
108
+
/* PDMA_MAIN2 - MCASP0-2 */
109
+
PSIL_PDMA_MCASP(0x4500),
110
+
PSIL_PDMA_MCASP(0x4501),
111
+
PSIL_PDMA_MCASP(0x4502),
112
+
/* CPSW3G */
113
+
PSIL_ETHERNET(0x4600, 19, 19, 16),
114
+
/* CSI2RX */
115
+
PSIL_CSI2RX(0x5000),
116
+
PSIL_CSI2RX(0x5001),
117
+
PSIL_CSI2RX(0x5002),
118
+
PSIL_CSI2RX(0x5003),
119
+
PSIL_CSI2RX(0x5004),
120
+
PSIL_CSI2RX(0x5005),
121
+
PSIL_CSI2RX(0x5006),
122
+
PSIL_CSI2RX(0x5007),
123
+
PSIL_CSI2RX(0x5008),
124
+
PSIL_CSI2RX(0x5009),
125
+
PSIL_CSI2RX(0x500a),
126
+
PSIL_CSI2RX(0x500b),
127
+
PSIL_CSI2RX(0x500c),
128
+
PSIL_CSI2RX(0x500d),
129
+
PSIL_CSI2RX(0x500e),
130
+
PSIL_CSI2RX(0x500f),
131
+
PSIL_CSI2RX(0x5010),
132
+
PSIL_CSI2RX(0x5011),
133
+
PSIL_CSI2RX(0x5012),
134
+
PSIL_CSI2RX(0x5013),
135
+
PSIL_CSI2RX(0x5014),
136
+
PSIL_CSI2RX(0x5015),
137
+
PSIL_CSI2RX(0x5016),
138
+
PSIL_CSI2RX(0x5017),
139
+
PSIL_CSI2RX(0x5018),
140
+
PSIL_CSI2RX(0x5019),
141
+
PSIL_CSI2RX(0x501a),
142
+
PSIL_CSI2RX(0x501b),
143
+
PSIL_CSI2RX(0x501c),
144
+
PSIL_CSI2RX(0x501d),
145
+
PSIL_CSI2RX(0x501e),
146
+
PSIL_CSI2RX(0x501f),
147
+
};
148
+
149
+
/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
150
+
static struct psil_ep am62a_dst_ep_map[] = {
151
+
/* SAUL */
152
+
PSIL_SAUL(0xf500, 27, 83, 8, 83, 1),
153
+
PSIL_SAUL(0xf501, 28, 91, 8, 91, 1),
154
+
/* PDMA_MAIN0 - SPI0-3 */
155
+
PSIL_PDMA_XY_PKT(0xc302),
156
+
PSIL_PDMA_XY_PKT(0xc303),
157
+
PSIL_PDMA_XY_PKT(0xc304),
158
+
PSIL_PDMA_XY_PKT(0xc305),
159
+
PSIL_PDMA_XY_PKT(0xc306),
160
+
PSIL_PDMA_XY_PKT(0xc307),
161
+
PSIL_PDMA_XY_PKT(0xc308),
162
+
PSIL_PDMA_XY_PKT(0xc309),
163
+
PSIL_PDMA_XY_PKT(0xc30a),
164
+
PSIL_PDMA_XY_PKT(0xc30b),
165
+
PSIL_PDMA_XY_PKT(0xc30c),
166
+
PSIL_PDMA_XY_PKT(0xc30d),
167
+
/* PDMA_MAIN1 - UART0-6 */
168
+
PSIL_PDMA_XY_PKT(0xc400),
169
+
PSIL_PDMA_XY_PKT(0xc401),
170
+
PSIL_PDMA_XY_PKT(0xc402),
171
+
PSIL_PDMA_XY_PKT(0xc403),
172
+
PSIL_PDMA_XY_PKT(0xc404),
173
+
PSIL_PDMA_XY_PKT(0xc405),
174
+
PSIL_PDMA_XY_PKT(0xc406),
175
+
/* PDMA_MAIN2 - MCASP0-2 */
176
+
PSIL_PDMA_MCASP(0xc500),
177
+
PSIL_PDMA_MCASP(0xc501),
178
+
PSIL_PDMA_MCASP(0xc502),
179
+
/* CPSW3G */
180
+
PSIL_ETHERNET(0xc600, 19, 19, 8),
181
+
PSIL_ETHERNET(0xc601, 20, 27, 8),
182
+
PSIL_ETHERNET(0xc602, 21, 35, 8),
183
+
PSIL_ETHERNET(0xc603, 22, 43, 8),
184
+
PSIL_ETHERNET(0xc604, 23, 51, 8),
185
+
PSIL_ETHERNET(0xc605, 24, 59, 8),
186
+
PSIL_ETHERNET(0xc606, 25, 67, 8),
187
+
PSIL_ETHERNET(0xc607, 26, 75, 8),
188
+
};
189
+
190
+
struct psil_ep_map am62a_ep_map = {
191
+
.name = "am62a",
192
+
.src = am62a_src_ep_map,
193
+
.src_count = ARRAY_SIZE(am62a_src_ep_map),
194
+
.dst = am62a_dst_ep_map,
195
+
.dst_count = ARRAY_SIZE(am62a_dst_ep_map),
196
+
};
+1
drivers/dma/ti/k3-psil-priv.h
+1
drivers/dma/ti/k3-psil-priv.h
+1
drivers/dma/ti/k3-psil.c
+1
drivers/dma/ti/k3-psil.c
+36
-6
drivers/dma/ti/k3-udma.c
+36
-6
drivers/dma/ti/k3-udma.c
···
135
135
u32 flags;
136
136
u32 statictr_z_mask;
137
137
u8 burst_size[3];
138
+
struct udma_soc_data *soc_data;
138
139
};
139
140
140
141
struct udma_soc_data {
···
4297
4296
},
4298
4297
};
4299
4298
4299
+
static struct udma_soc_data am62a_dmss_csi_soc_data = {
4300
+
.oes = {
4301
+
.bcdma_rchan_data = 0xe00,
4302
+
.bcdma_rchan_ring = 0x1000,
4303
+
},
4304
+
};
4305
+
4306
+
static struct udma_match_data am62a_bcdma_csirx_data = {
4307
+
.type = DMA_TYPE_BCDMA,
4308
+
.psil_base = 0x3100,
4309
+
.enable_memcpy_support = false,
4310
+
.burst_size = {
4311
+
TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES, /* Normal Channels */
4312
+
0, /* No H Channels */
4313
+
0, /* No UH Channels */
4314
+
},
4315
+
.soc_data = &am62a_dmss_csi_soc_data,
4316
+
};
4317
+
4300
4318
static struct udma_match_data am64_bcdma_data = {
4301
4319
.type = DMA_TYPE_BCDMA,
4302
4320
.psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */
···
4365
4345
.compatible = "ti,am64-dmss-pktdma",
4366
4346
.data = &am64_pktdma_data,
4367
4347
},
4348
+
{
4349
+
.compatible = "ti,am62a-dmss-bcdma-csirx",
4350
+
.data = &am62a_bcdma_csirx_data,
4351
+
},
4368
4352
{ /* Sentinel */ },
4369
4353
};
4370
4354
···
4411
4387
{ .family = "AM64X", .data = &am64_soc_data },
4412
4388
{ .family = "J721S2", .data = &j721e_soc_data},
4413
4389
{ .family = "AM62X", .data = &am64_soc_data },
4390
+
{ .family = "AM62AX", .data = &am64_soc_data },
4414
4391
{ /* sentinel */ }
4415
4392
};
4416
4393
···
4800
4775
irq_res.desc[i].num = rm_res->desc[i].num;
4801
4776
}
4802
4777
}
4778
+
} else {
4779
+
i = 0;
4803
4780
}
4781
+
4804
4782
if (ud->tchan_cnt) {
4805
4783
rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
4806
4784
if (IS_ERR(rm_res)) {
···
5299
5271
}
5300
5272
ud->match_data = match->data;
5301
5273
5302
-
soc = soc_device_match(k3_soc_devices);
5303
-
if (!soc) {
5304
-
dev_err(dev, "No compatible SoC found\n");
5305
-
return -ENODEV;
5274
+
ud->soc_data = ud->match_data->soc_data;
5275
+
if (!ud->soc_data) {
5276
+
soc = soc_device_match(k3_soc_devices);
5277
+
if (!soc) {
5278
+
dev_err(dev, "No compatible SoC found\n");
5279
+
return -ENODEV;
5280
+
}
5281
+
ud->soc_data = soc->data;
5306
5282
}
5307
-
ud->soc_data = soc->data;
5308
5283
5309
5284
ret = udma_get_mmrs(pdev, ud);
5310
5285
if (ret)
···
5376
5345
dev->msi.domain = of_msi_get_domain(dev, dev->of_node,
5377
5346
DOMAIN_BUS_TI_SCI_INTA_MSI);
5378
5347
if (!dev->msi.domain) {
5379
-
dev_err(dev, "Failed to get MSI domain\n");
5380
5348
return -EPROBE_DEFER;
5381
5349
}
5382
5350
+1
-3
drivers/dma/ti/omap-dma.c
+1
-3
drivers/dma/ti/omap-dma.c
···
1658
1658
{
1659
1659
const struct omap_dma_config *conf;
1660
1660
struct omap_dmadev *od;
1661
-
struct resource *res;
1662
1661
int rc, i, irq;
1663
1662
u32 val;
1664
1663
···
1665
1666
if (!od)
1666
1667
return -ENOMEM;
1667
1668
1668
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1669
-
od->base = devm_ioremap_resource(&pdev->dev, res);
1669
+
od->base = devm_platform_ioremap_resource(pdev, 0);
1670
1670
if (IS_ERR(od->base))
1671
1671
return PTR_ERR(od->base);
1672
1672
+1
drivers/dma/xilinx/Makefile
+1
drivers/dma/xilinx/Makefile
+166
drivers/dma/xilinx/xdma-regs.h
+166
drivers/dma/xilinx/xdma-regs.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
+
/*
3
+
* Copyright (C) 2017-2020 Xilinx, Inc. All rights reserved.
4
+
* Copyright (C) 2022, Advanced Micro Devices, Inc.
5
+
*/
6
+
7
+
#ifndef __DMA_XDMA_REGS_H
8
+
#define __DMA_XDMA_REGS_H
9
+
10
+
/* The length of register space exposed to host */
11
+
#define XDMA_REG_SPACE_LEN 65536
12
+
13
+
/*
14
+
* maximum number of DMA channels for each direction:
15
+
* Host to Card (H2C) or Card to Host (C2H)
16
+
*/
17
+
#define XDMA_MAX_CHANNELS 4
18
+
19
+
/*
20
+
* macros to define the number of descriptor blocks can be used in one
21
+
* DMA transfer request.
22
+
* the DMA engine uses a linked list of descriptor blocks that specify the
23
+
* source, destination, and length of the DMA transfers.
24
+
*/
25
+
#define XDMA_DESC_BLOCK_NUM BIT(7)
26
+
#define XDMA_DESC_BLOCK_MASK (XDMA_DESC_BLOCK_NUM - 1)
27
+
28
+
/* descriptor definitions */
29
+
#define XDMA_DESC_ADJACENT 32
30
+
#define XDMA_DESC_ADJACENT_MASK (XDMA_DESC_ADJACENT - 1)
31
+
#define XDMA_DESC_ADJACENT_BITS GENMASK(13, 8)
32
+
#define XDMA_DESC_MAGIC 0xad4bUL
33
+
#define XDMA_DESC_MAGIC_BITS GENMASK(31, 16)
34
+
#define XDMA_DESC_FLAGS_BITS GENMASK(7, 0)
35
+
#define XDMA_DESC_STOPPED BIT(0)
36
+
#define XDMA_DESC_COMPLETED BIT(1)
37
+
#define XDMA_DESC_BLEN_BITS 28
38
+
#define XDMA_DESC_BLEN_MAX (BIT(XDMA_DESC_BLEN_BITS) - PAGE_SIZE)
39
+
40
+
/* macros to construct the descriptor control word */
41
+
#define XDMA_DESC_CONTROL(adjacent, flag) \
42
+
(FIELD_PREP(XDMA_DESC_MAGIC_BITS, XDMA_DESC_MAGIC) | \
43
+
FIELD_PREP(XDMA_DESC_ADJACENT_BITS, (adjacent) - 1) | \
44
+
FIELD_PREP(XDMA_DESC_FLAGS_BITS, (flag)))
45
+
#define XDMA_DESC_CONTROL_LAST \
46
+
XDMA_DESC_CONTROL(1, XDMA_DESC_STOPPED | XDMA_DESC_COMPLETED)
47
+
48
+
/*
49
+
* Descriptor for a single contiguous memory block transfer.
50
+
*
51
+
* Multiple descriptors are linked by means of the next pointer. An additional
52
+
* extra adjacent number gives the amount of extra contiguous descriptors.
53
+
*
54
+
* The descriptors are in root complex memory, and the bytes in the 32-bit
55
+
* words must be in little-endian byte ordering.
56
+
*/
57
+
struct xdma_hw_desc {
58
+
__le32 control;
59
+
__le32 bytes;
60
+
__le64 src_addr;
61
+
__le64 dst_addr;
62
+
__le64 next_desc;
63
+
};
64
+
65
+
#define XDMA_DESC_SIZE sizeof(struct xdma_hw_desc)
66
+
#define XDMA_DESC_BLOCK_SIZE (XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)
67
+
#define XDMA_DESC_BLOCK_ALIGN 4096
68
+
69
+
/*
70
+
* Channel registers
71
+
*/
72
+
#define XDMA_CHAN_IDENTIFIER 0x0
73
+
#define XDMA_CHAN_CONTROL 0x4
74
+
#define XDMA_CHAN_CONTROL_W1S 0x8
75
+
#define XDMA_CHAN_CONTROL_W1C 0xc
76
+
#define XDMA_CHAN_STATUS 0x40
77
+
#define XDMA_CHAN_COMPLETED_DESC 0x48
78
+
#define XDMA_CHAN_ALIGNMENTS 0x4c
79
+
#define XDMA_CHAN_INTR_ENABLE 0x90
80
+
#define XDMA_CHAN_INTR_ENABLE_W1S 0x94
81
+
#define XDMA_CHAN_INTR_ENABLE_W1C 0x9c
82
+
83
+
#define XDMA_CHAN_STRIDE 0x100
84
+
#define XDMA_CHAN_H2C_OFFSET 0x0
85
+
#define XDMA_CHAN_C2H_OFFSET 0x1000
86
+
#define XDMA_CHAN_H2C_TARGET 0x0
87
+
#define XDMA_CHAN_C2H_TARGET 0x1
88
+
89
+
/* macro to check if channel is available */
90
+
#define XDMA_CHAN_MAGIC 0x1fc0
91
+
#define XDMA_CHAN_CHECK_TARGET(id, target) \
92
+
(((u32)(id) >> 16) == XDMA_CHAN_MAGIC + (target))
93
+
94
+
/* bits of the channel control register */
95
+
#define CHAN_CTRL_RUN_STOP BIT(0)
96
+
#define CHAN_CTRL_IE_DESC_STOPPED BIT(1)
97
+
#define CHAN_CTRL_IE_DESC_COMPLETED BIT(2)
98
+
#define CHAN_CTRL_IE_DESC_ALIGN_MISMATCH BIT(3)
99
+
#define CHAN_CTRL_IE_MAGIC_STOPPED BIT(4)
100
+
#define CHAN_CTRL_IE_IDLE_STOPPED BIT(6)
101
+
#define CHAN_CTRL_IE_READ_ERROR GENMASK(13, 9)
102
+
#define CHAN_CTRL_IE_DESC_ERROR GENMASK(23, 19)
103
+
#define CHAN_CTRL_NON_INCR_ADDR BIT(25)
104
+
#define CHAN_CTRL_POLL_MODE_WB BIT(26)
105
+
106
+
#define CHAN_CTRL_START (CHAN_CTRL_RUN_STOP | \
107
+
CHAN_CTRL_IE_DESC_STOPPED | \
108
+
CHAN_CTRL_IE_DESC_COMPLETED | \
109
+
CHAN_CTRL_IE_DESC_ALIGN_MISMATCH | \
110
+
CHAN_CTRL_IE_MAGIC_STOPPED | \
111
+
CHAN_CTRL_IE_READ_ERROR | \
112
+
CHAN_CTRL_IE_DESC_ERROR)
113
+
114
+
/* bits of the channel interrupt enable mask */
115
+
#define CHAN_IM_DESC_ERROR BIT(19)
116
+
#define CHAN_IM_READ_ERROR BIT(9)
117
+
#define CHAN_IM_IDLE_STOPPED BIT(6)
118
+
#define CHAN_IM_MAGIC_STOPPED BIT(4)
119
+
#define CHAN_IM_DESC_COMPLETED BIT(2)
120
+
#define CHAN_IM_DESC_STOPPED BIT(1)
121
+
122
+
#define CHAN_IM_ALL (CHAN_IM_DESC_ERROR | CHAN_IM_READ_ERROR | \
123
+
CHAN_IM_IDLE_STOPPED | CHAN_IM_MAGIC_STOPPED | \
124
+
CHAN_IM_DESC_COMPLETED | CHAN_IM_DESC_STOPPED)
125
+
126
+
/*
127
+
* Channel SGDMA registers
128
+
*/
129
+
#define XDMA_SGDMA_IDENTIFIER 0x4000
130
+
#define XDMA_SGDMA_DESC_LO 0x4080
131
+
#define XDMA_SGDMA_DESC_HI 0x4084
132
+
#define XDMA_SGDMA_DESC_ADJ 0x4088
133
+
#define XDMA_SGDMA_DESC_CREDIT 0x408c
134
+
135
+
/* bits of the SG DMA control register */
136
+
#define XDMA_CTRL_RUN_STOP BIT(0)
137
+
#define XDMA_CTRL_IE_DESC_STOPPED BIT(1)
138
+
#define XDMA_CTRL_IE_DESC_COMPLETED BIT(2)
139
+
#define XDMA_CTRL_IE_DESC_ALIGN_MISMATCH BIT(3)
140
+
#define XDMA_CTRL_IE_MAGIC_STOPPED BIT(4)
141
+
#define XDMA_CTRL_IE_IDLE_STOPPED BIT(6)
142
+
#define XDMA_CTRL_IE_READ_ERROR GENMASK(13, 9)
143
+
#define XDMA_CTRL_IE_DESC_ERROR GENMASK(23, 19)
144
+
#define XDMA_CTRL_NON_INCR_ADDR BIT(25)
145
+
#define XDMA_CTRL_POLL_MODE_WB BIT(26)
146
+
147
+
/*
148
+
* interrupt registers
149
+
*/
150
+
#define XDMA_IRQ_IDENTIFIER 0x2000
151
+
#define XDMA_IRQ_USER_INT_EN 0x2004
152
+
#define XDMA_IRQ_USER_INT_EN_W1S 0x2008
153
+
#define XDMA_IRQ_USER_INT_EN_W1C 0x200c
154
+
#define XDMA_IRQ_CHAN_INT_EN 0x2010
155
+
#define XDMA_IRQ_CHAN_INT_EN_W1S 0x2014
156
+
#define XDMA_IRQ_CHAN_INT_EN_W1C 0x2018
157
+
#define XDMA_IRQ_USER_INT_REQ 0x2040
158
+
#define XDMA_IRQ_CHAN_INT_REQ 0x2044
159
+
#define XDMA_IRQ_USER_INT_PEND 0x2048
160
+
#define XDMA_IRQ_CHAN_INT_PEND 0x204c
161
+
#define XDMA_IRQ_USER_VEC_NUM 0x2080
162
+
#define XDMA_IRQ_CHAN_VEC_NUM 0x20a0
163
+
164
+
#define XDMA_IRQ_VEC_SHIFT 8
165
+
166
+
#endif /* __DMA_XDMA_REGS_H */
+974
drivers/dma/xilinx/xdma.c
+974
drivers/dma/xilinx/xdma.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* DMA driver for Xilinx DMA/Bridge Subsystem
4
+
*
5
+
* Copyright (C) 2017-2020 Xilinx, Inc. All rights reserved.
6
+
* Copyright (C) 2022, Advanced Micro Devices, Inc.
7
+
*/
8
+
9
+
/*
10
+
* The DMA/Bridge Subsystem for PCI Express allows for the movement of data
11
+
* between Host memory and the DMA subsystem. It does this by operating on
12
+
* 'descriptors' that contain information about the source, destination and
13
+
* amount of data to transfer. These direct memory transfers can be both in
14
+
* the Host to Card (H2C) and Card to Host (C2H) transfers. The DMA can be
15
+
* configured to have a single AXI4 Master interface shared by all channels
16
+
* or one AXI4-Stream interface for each channel enabled. Memory transfers are
17
+
* specified on a per-channel basis in descriptor linked lists, which the DMA
18
+
* fetches from host memory and processes. Events such as descriptor completion
19
+
* and errors are signaled using interrupts. The core also provides up to 16
20
+
* user interrupt wires that generate interrupts to the host.
21
+
*/
22
+
23
+
#include <linux/mod_devicetable.h>
24
+
#include <linux/bitfield.h>
25
+
#include <linux/dmapool.h>
26
+
#include <linux/regmap.h>
27
+
#include <linux/dmaengine.h>
28
+
#include <linux/dma/amd_xdma.h>
29
+
#include <linux/platform_device.h>
30
+
#include <linux/platform_data/amd_xdma.h>
31
+
#include <linux/dma-mapping.h>
32
+
#include <linux/pci.h>
33
+
#include "../virt-dma.h"
34
+
#include "xdma-regs.h"
35
+
36
+
/* mmio regmap config for all XDMA registers */
37
+
static const struct regmap_config xdma_regmap_config = {
38
+
.reg_bits = 32,
39
+
.val_bits = 32,
40
+
.reg_stride = 4,
41
+
.max_register = XDMA_REG_SPACE_LEN,
42
+
};
43
+
44
+
/**
45
+
* struct xdma_desc_block - Descriptor block
46
+
* @virt_addr: Virtual address of block start
47
+
* @dma_addr: DMA address of block start
48
+
*/
49
+
struct xdma_desc_block {
50
+
void *virt_addr;
51
+
dma_addr_t dma_addr;
52
+
};
53
+
54
+
/**
55
+
* struct xdma_chan - Driver specific DMA channel structure
56
+
* @vchan: Virtual channel
57
+
* @xdev_hdl: Pointer to DMA device structure
58
+
* @base: Offset of channel registers
59
+
* @desc_pool: Descriptor pool
60
+
* @busy: Busy flag of the channel
61
+
* @dir: Transferring direction of the channel
62
+
* @cfg: Transferring config of the channel
63
+
* @irq: IRQ assigned to the channel
64
+
*/
65
+
struct xdma_chan {
66
+
struct virt_dma_chan vchan;
67
+
void *xdev_hdl;
68
+
u32 base;
69
+
struct dma_pool *desc_pool;
70
+
bool busy;
71
+
enum dma_transfer_direction dir;
72
+
struct dma_slave_config cfg;
73
+
u32 irq;
74
+
};
75
+
76
+
/**
77
+
* struct xdma_desc - DMA desc structure
78
+
* @vdesc: Virtual DMA descriptor
79
+
* @chan: DMA channel pointer
80
+
* @dir: Transferring direction of the request
81
+
* @dev_addr: Physical address on DMA device side
82
+
* @desc_blocks: Hardware descriptor blocks
83
+
* @dblk_num: Number of hardware descriptor blocks
84
+
* @desc_num: Number of hardware descriptors
85
+
* @completed_desc_num: Completed hardware descriptors
86
+
*/
87
+
struct xdma_desc {
88
+
struct virt_dma_desc vdesc;
89
+
struct xdma_chan *chan;
90
+
enum dma_transfer_direction dir;
91
+
u64 dev_addr;
92
+
struct xdma_desc_block *desc_blocks;
93
+
u32 dblk_num;
94
+
u32 desc_num;
95
+
u32 completed_desc_num;
96
+
};
97
+
98
+
#define XDMA_DEV_STATUS_REG_DMA BIT(0)
99
+
#define XDMA_DEV_STATUS_INIT_MSIX BIT(1)
100
+
101
+
/**
102
+
* struct xdma_device - DMA device structure
103
+
* @pdev: Platform device pointer
104
+
* @dma_dev: DMA device structure
105
+
* @rmap: MMIO regmap for DMA registers
106
+
* @h2c_chans: Host to Card channels
107
+
* @c2h_chans: Card to Host channels
108
+
* @h2c_chan_num: Number of H2C channels
109
+
* @c2h_chan_num: Number of C2H channels
110
+
* @irq_start: Start IRQ assigned to device
111
+
* @irq_num: Number of IRQ assigned to device
112
+
* @status: Initialization status
113
+
*/
114
+
struct xdma_device {
115
+
struct platform_device *pdev;
116
+
struct dma_device dma_dev;
117
+
struct regmap *rmap;
118
+
struct xdma_chan *h2c_chans;
119
+
struct xdma_chan *c2h_chans;
120
+
u32 h2c_chan_num;
121
+
u32 c2h_chan_num;
122
+
u32 irq_start;
123
+
u32 irq_num;
124
+
u32 status;
125
+
};
126
+
127
+
#define xdma_err(xdev, fmt, args...) \
128
+
dev_err(&(xdev)->pdev->dev, fmt, ##args)
129
+
#define XDMA_CHAN_NUM(_xd) ({ \
130
+
typeof(_xd) (xd) = (_xd); \
131
+
((xd)->h2c_chan_num + (xd)->c2h_chan_num); })
132
+
133
+
/* Get the last desc in a desc block */
134
+
static inline void *xdma_blk_last_desc(struct xdma_desc_block *block)
135
+
{
136
+
return block->virt_addr + (XDMA_DESC_ADJACENT - 1) * XDMA_DESC_SIZE;
137
+
}
138
+
139
+
/**
140
+
* xdma_link_desc_blocks - Link descriptor blocks for DMA transfer
141
+
* @sw_desc: Tx descriptor pointer
142
+
*/
143
+
static void xdma_link_desc_blocks(struct xdma_desc *sw_desc)
144
+
{
145
+
struct xdma_desc_block *block;
146
+
u32 last_blk_desc, desc_control;
147
+
struct xdma_hw_desc *desc;
148
+
int i;
149
+
150
+
desc_control = XDMA_DESC_CONTROL(XDMA_DESC_ADJACENT, 0);
151
+
for (i = 1; i < sw_desc->dblk_num; i++) {
152
+
block = &sw_desc->desc_blocks[i - 1];
153
+
desc = xdma_blk_last_desc(block);
154
+
155
+
if (!(i & XDMA_DESC_BLOCK_MASK)) {
156
+
desc->control = cpu_to_le32(XDMA_DESC_CONTROL_LAST);
157
+
continue;
158
+
}
159
+
desc->control = cpu_to_le32(desc_control);
160
+
desc->next_desc = cpu_to_le64(block[1].dma_addr);
161
+
}
162
+
163
+
/* update the last block */
164
+
last_blk_desc = (sw_desc->desc_num - 1) & XDMA_DESC_ADJACENT_MASK;
165
+
if (((sw_desc->dblk_num - 1) & XDMA_DESC_BLOCK_MASK) > 0) {
166
+
block = &sw_desc->desc_blocks[sw_desc->dblk_num - 2];
167
+
desc = xdma_blk_last_desc(block);
168
+
desc_control = XDMA_DESC_CONTROL(last_blk_desc + 1, 0);
169
+
desc->control = cpu_to_le32(desc_control);
170
+
}
171
+
172
+
block = &sw_desc->desc_blocks[sw_desc->dblk_num - 1];
173
+
desc = block->virt_addr + last_blk_desc * XDMA_DESC_SIZE;
174
+
desc->control = cpu_to_le32(XDMA_DESC_CONTROL_LAST);
175
+
}
176
+
177
+
static inline struct xdma_chan *to_xdma_chan(struct dma_chan *chan)
178
+
{
179
+
return container_of(chan, struct xdma_chan, vchan.chan);
180
+
}
181
+
182
+
static inline struct xdma_desc *to_xdma_desc(struct virt_dma_desc *vdesc)
183
+
{
184
+
return container_of(vdesc, struct xdma_desc, vdesc);
185
+
}
186
+
187
+
/**
188
+
* xdma_channel_init - Initialize DMA channel registers
189
+
* @chan: DMA channel pointer
190
+
*/
191
+
static int xdma_channel_init(struct xdma_chan *chan)
192
+
{
193
+
struct xdma_device *xdev = chan->xdev_hdl;
194
+
int ret;
195
+
196
+
ret = regmap_write(xdev->rmap, chan->base + XDMA_CHAN_CONTROL_W1C,
197
+
CHAN_CTRL_NON_INCR_ADDR);
198
+
if (ret)
199
+
return ret;
200
+
201
+
ret = regmap_write(xdev->rmap, chan->base + XDMA_CHAN_INTR_ENABLE,
202
+
CHAN_IM_ALL);
203
+
if (ret)
204
+
return ret;
205
+
206
+
return 0;
207
+
}
208
+
209
+
/**
210
+
* xdma_free_desc - Free descriptor
211
+
* @vdesc: Virtual DMA descriptor
212
+
*/
213
+
static void xdma_free_desc(struct virt_dma_desc *vdesc)
214
+
{
215
+
struct xdma_desc *sw_desc;
216
+
int i;
217
+
218
+
sw_desc = to_xdma_desc(vdesc);
219
+
for (i = 0; i < sw_desc->dblk_num; i++) {
220
+
if (!sw_desc->desc_blocks[i].virt_addr)
221
+
break;
222
+
dma_pool_free(sw_desc->chan->desc_pool,
223
+
sw_desc->desc_blocks[i].virt_addr,
224
+
sw_desc->desc_blocks[i].dma_addr);
225
+
}
226
+
kfree(sw_desc->desc_blocks);
227
+
kfree(sw_desc);
228
+
}
229
+
230
+
/**
231
+
* xdma_alloc_desc - Allocate descriptor
232
+
* @chan: DMA channel pointer
233
+
* @desc_num: Number of hardware descriptors
234
+
*/
235
+
static struct xdma_desc *
236
+
xdma_alloc_desc(struct xdma_chan *chan, u32 desc_num)
237
+
{
238
+
struct xdma_desc *sw_desc;
239
+
struct xdma_hw_desc *desc;
240
+
dma_addr_t dma_addr;
241
+
u32 dblk_num;
242
+
void *addr;
243
+
int i, j;
244
+
245
+
sw_desc = kzalloc(sizeof(*sw_desc), GFP_NOWAIT);
246
+
if (!sw_desc)
247
+
return NULL;
248
+
249
+
sw_desc->chan = chan;
250
+
sw_desc->desc_num = desc_num;
251
+
dblk_num = DIV_ROUND_UP(desc_num, XDMA_DESC_ADJACENT);
252
+
sw_desc->desc_blocks = kcalloc(dblk_num, sizeof(*sw_desc->desc_blocks),
253
+
GFP_NOWAIT);
254
+
if (!sw_desc->desc_blocks)
255
+
goto failed;
256
+
257
+
sw_desc->dblk_num = dblk_num;
258
+
for (i = 0; i < sw_desc->dblk_num; i++) {
259
+
addr = dma_pool_alloc(chan->desc_pool, GFP_NOWAIT, &dma_addr);
260
+
if (!addr)
261
+
goto failed;
262
+
263
+
sw_desc->desc_blocks[i].virt_addr = addr;
264
+
sw_desc->desc_blocks[i].dma_addr = dma_addr;
265
+
for (j = 0, desc = addr; j < XDMA_DESC_ADJACENT; j++)
266
+
desc[j].control = cpu_to_le32(XDMA_DESC_CONTROL(1, 0));
267
+
}
268
+
269
+
xdma_link_desc_blocks(sw_desc);
270
+
271
+
return sw_desc;
272
+
273
+
failed:
274
+
xdma_free_desc(&sw_desc->vdesc);
275
+
return NULL;
276
+
}
277
+
278
+
/**
279
+
* xdma_xfer_start - Start DMA transfer
280
+
* @xdma_chan: DMA channel pointer
281
+
*/
282
+
static int xdma_xfer_start(struct xdma_chan *xchan)
283
+
{
284
+
struct virt_dma_desc *vd = vchan_next_desc(&xchan->vchan);
285
+
struct xdma_device *xdev = xchan->xdev_hdl;
286
+
struct xdma_desc_block *block;
287
+
u32 val, completed_blocks;
288
+
struct xdma_desc *desc;
289
+
int ret;
290
+
291
+
/*
292
+
* check if there is not any submitted descriptor or channel is busy.
293
+
* vchan lock should be held where this function is called.
294
+
*/
295
+
if (!vd || xchan->busy)
296
+
return -EINVAL;
297
+
298
+
/* clear run stop bit to get ready for transfer */
299
+
ret = regmap_write(xdev->rmap, xchan->base + XDMA_CHAN_CONTROL_W1C,
300
+
CHAN_CTRL_RUN_STOP);
301
+
if (ret)
302
+
return ret;
303
+
304
+
desc = to_xdma_desc(vd);
305
+
if (desc->dir != xchan->dir) {
306
+
xdma_err(xdev, "incorrect request direction");
307
+
return -EINVAL;
308
+
}
309
+
310
+
/* set DMA engine to the first descriptor block */
311
+
completed_blocks = desc->completed_desc_num / XDMA_DESC_ADJACENT;
312
+
block = &desc->desc_blocks[completed_blocks];
313
+
val = lower_32_bits(block->dma_addr);
314
+
ret = regmap_write(xdev->rmap, xchan->base + XDMA_SGDMA_DESC_LO, val);
315
+
if (ret)
316
+
return ret;
317
+
318
+
val = upper_32_bits(block->dma_addr);
319
+
ret = regmap_write(xdev->rmap, xchan->base + XDMA_SGDMA_DESC_HI, val);
320
+
if (ret)
321
+
return ret;
322
+
323
+
if (completed_blocks + 1 == desc->dblk_num)
324
+
val = (desc->desc_num - 1) & XDMA_DESC_ADJACENT_MASK;
325
+
else
326
+
val = XDMA_DESC_ADJACENT - 1;
327
+
ret = regmap_write(xdev->rmap, xchan->base + XDMA_SGDMA_DESC_ADJ, val);
328
+
if (ret)
329
+
return ret;
330
+
331
+
/* kick off DMA transfer */
332
+
ret = regmap_write(xdev->rmap, xchan->base + XDMA_CHAN_CONTROL,
333
+
CHAN_CTRL_START);
334
+
if (ret)
335
+
return ret;
336
+
337
+
xchan->busy = true;
338
+
return 0;
339
+
}
340
+
341
+
/**
342
+
* xdma_alloc_channels - Detect and allocate DMA channels
343
+
* @xdev: DMA device pointer
344
+
* @dir: Channel direction
345
+
*/
346
+
static int xdma_alloc_channels(struct xdma_device *xdev,
347
+
enum dma_transfer_direction dir)
348
+
{
349
+
struct xdma_platdata *pdata = dev_get_platdata(&xdev->pdev->dev);
350
+
struct xdma_chan **chans, *xchan;
351
+
u32 base, identifier, target;
352
+
u32 *chan_num;
353
+
int i, j, ret;
354
+
355
+
if (dir == DMA_MEM_TO_DEV) {
356
+
base = XDMA_CHAN_H2C_OFFSET;
357
+
target = XDMA_CHAN_H2C_TARGET;
358
+
chans = &xdev->h2c_chans;
359
+
chan_num = &xdev->h2c_chan_num;
360
+
} else if (dir == DMA_DEV_TO_MEM) {
361
+
base = XDMA_CHAN_C2H_OFFSET;
362
+
target = XDMA_CHAN_C2H_TARGET;
363
+
chans = &xdev->c2h_chans;
364
+
chan_num = &xdev->c2h_chan_num;
365
+
} else {
366
+
xdma_err(xdev, "invalid direction specified");
367
+
return -EINVAL;
368
+
}
369
+
370
+
/* detect number of available DMA channels */
371
+
for (i = 0, *chan_num = 0; i < pdata->max_dma_channels; i++) {
372
+
ret = regmap_read(xdev->rmap, base + i * XDMA_CHAN_STRIDE,
373
+
&identifier);
374
+
if (ret)
375
+
return ret;
376
+
377
+
/* check if it is available DMA channel */
378
+
if (XDMA_CHAN_CHECK_TARGET(identifier, target))
379
+
(*chan_num)++;
380
+
}
381
+
382
+
if (!*chan_num) {
383
+
xdma_err(xdev, "does not probe any channel");
384
+
return -EINVAL;
385
+
}
386
+
387
+
*chans = devm_kcalloc(&xdev->pdev->dev, *chan_num, sizeof(**chans),
388
+
GFP_KERNEL);
389
+
if (!*chans)
390
+
return -ENOMEM;
391
+
392
+
for (i = 0, j = 0; i < pdata->max_dma_channels; i++) {
393
+
ret = regmap_read(xdev->rmap, base + i * XDMA_CHAN_STRIDE,
394
+
&identifier);
395
+
if (ret)
396
+
return ret;
397
+
398
+
if (!XDMA_CHAN_CHECK_TARGET(identifier, target))
399
+
continue;
400
+
401
+
if (j == *chan_num) {
402
+
xdma_err(xdev, "invalid channel number");
403
+
return -EIO;
404
+
}
405
+
406
+
/* init channel structure and hardware */
407
+
xchan = &(*chans)[j];
408
+
xchan->xdev_hdl = xdev;
409
+
xchan->base = base + i * XDMA_CHAN_STRIDE;
410
+
xchan->dir = dir;
411
+
412
+
ret = xdma_channel_init(xchan);
413
+
if (ret)
414
+
return ret;
415
+
xchan->vchan.desc_free = xdma_free_desc;
416
+
vchan_init(&xchan->vchan, &xdev->dma_dev);
417
+
418
+
j++;
419
+
}
420
+
421
+
dev_info(&xdev->pdev->dev, "configured %d %s channels", j,
422
+
(dir == DMA_MEM_TO_DEV) ? "H2C" : "C2H");
423
+
424
+
return 0;
425
+
}
426
+
427
+
/**
428
+
* xdma_issue_pending - Issue pending transactions
429
+
* @chan: DMA channel pointer
430
+
*/
431
+
static void xdma_issue_pending(struct dma_chan *chan)
432
+
{
433
+
struct xdma_chan *xdma_chan = to_xdma_chan(chan);
434
+
unsigned long flags;
435
+
436
+
spin_lock_irqsave(&xdma_chan->vchan.lock, flags);
437
+
if (vchan_issue_pending(&xdma_chan->vchan))
438
+
xdma_xfer_start(xdma_chan);
439
+
spin_unlock_irqrestore(&xdma_chan->vchan.lock, flags);
440
+
}
441
+
442
+
/**
443
+
* xdma_prep_device_sg - prepare a descriptor for a DMA transaction
444
+
* @chan: DMA channel pointer
445
+
* @sgl: Transfer scatter gather list
446
+
* @sg_len: Length of scatter gather list
447
+
* @dir: Transfer direction
448
+
* @flags: transfer ack flags
449
+
* @context: APP words of the descriptor
450
+
*/
451
+
static struct dma_async_tx_descriptor *
452
+
xdma_prep_device_sg(struct dma_chan *chan, struct scatterlist *sgl,
453
+
unsigned int sg_len, enum dma_transfer_direction dir,
454
+
unsigned long flags, void *context)
455
+
{
456
+
struct xdma_chan *xdma_chan = to_xdma_chan(chan);
457
+
struct dma_async_tx_descriptor *tx_desc;
458
+
u32 desc_num = 0, i, len, rest;
459
+
struct xdma_desc_block *dblk;
460
+
struct xdma_hw_desc *desc;
461
+
struct xdma_desc *sw_desc;
462
+
u64 dev_addr, *src, *dst;
463
+
struct scatterlist *sg;
464
+
u64 addr;
465
+
466
+
for_each_sg(sgl, sg, sg_len, i)
467
+
desc_num += DIV_ROUND_UP(sg_dma_len(sg), XDMA_DESC_BLEN_MAX);
468
+
469
+
sw_desc = xdma_alloc_desc(xdma_chan, desc_num);
470
+
if (!sw_desc)
471
+
return NULL;
472
+
sw_desc->dir = dir;
473
+
474
+
if (dir == DMA_MEM_TO_DEV) {
475
+
dev_addr = xdma_chan->cfg.dst_addr;
476
+
src = &addr;
477
+
dst = &dev_addr;
478
+
} else {
479
+
dev_addr = xdma_chan->cfg.src_addr;
480
+
src = &dev_addr;
481
+
dst = &addr;
482
+
}
483
+
484
+
dblk = sw_desc->desc_blocks;
485
+
desc = dblk->virt_addr;
486
+
desc_num = 1;
487
+
for_each_sg(sgl, sg, sg_len, i) {
488
+
addr = sg_dma_address(sg);
489
+
rest = sg_dma_len(sg);
490
+
491
+
do {
492
+
len = min_t(u32, rest, XDMA_DESC_BLEN_MAX);
493
+
/* set hardware descriptor */
494
+
desc->bytes = cpu_to_le32(len);
495
+
desc->src_addr = cpu_to_le64(*src);
496
+
desc->dst_addr = cpu_to_le64(*dst);
497
+
498
+
if (!(desc_num & XDMA_DESC_ADJACENT_MASK)) {
499
+
dblk++;
500
+
desc = dblk->virt_addr;
501
+
} else {
502
+
desc++;
503
+
}
504
+
505
+
desc_num++;
506
+
dev_addr += len;
507
+
addr += len;
508
+
rest -= len;
509
+
} while (rest);
510
+
}
511
+
512
+
tx_desc = vchan_tx_prep(&xdma_chan->vchan, &sw_desc->vdesc, flags);
513
+
if (!tx_desc)
514
+
goto failed;
515
+
516
+
return tx_desc;
517
+
518
+
failed:
519
+
xdma_free_desc(&sw_desc->vdesc);
520
+
521
+
return NULL;
522
+
}
523
+
524
+
/**
525
+
* xdma_device_config - Configure the DMA channel
526
+
* @chan: DMA channel
527
+
* @cfg: channel configuration
528
+
*/
529
+
static int xdma_device_config(struct dma_chan *chan,
530
+
struct dma_slave_config *cfg)
531
+
{
532
+
struct xdma_chan *xdma_chan = to_xdma_chan(chan);
533
+
534
+
memcpy(&xdma_chan->cfg, cfg, sizeof(*cfg));
535
+
536
+
return 0;
537
+
}
538
+
539
+
/**
540
+
* xdma_free_chan_resources - Free channel resources
541
+
* @chan: DMA channel
542
+
*/
543
+
static void xdma_free_chan_resources(struct dma_chan *chan)
544
+
{
545
+
struct xdma_chan *xdma_chan = to_xdma_chan(chan);
546
+
547
+
vchan_free_chan_resources(&xdma_chan->vchan);
548
+
dma_pool_destroy(xdma_chan->desc_pool);
549
+
xdma_chan->desc_pool = NULL;
550
+
}
551
+
552
+
/**
553
+
* xdma_alloc_chan_resources - Allocate channel resources
554
+
* @chan: DMA channel
555
+
*/
556
+
static int xdma_alloc_chan_resources(struct dma_chan *chan)
557
+
{
558
+
struct xdma_chan *xdma_chan = to_xdma_chan(chan);
559
+
struct xdma_device *xdev = xdma_chan->xdev_hdl;
560
+
struct device *dev = xdev->dma_dev.dev;
561
+
562
+
while (dev && !dev_is_pci(dev))
563
+
dev = dev->parent;
564
+
if (!dev) {
565
+
xdma_err(xdev, "unable to find pci device");
566
+
return -EINVAL;
567
+
}
568
+
569
+
xdma_chan->desc_pool = dma_pool_create(dma_chan_name(chan),
570
+
dev, XDMA_DESC_BLOCK_SIZE,
571
+
XDMA_DESC_BLOCK_ALIGN, 0);
572
+
if (!xdma_chan->desc_pool) {
573
+
xdma_err(xdev, "unable to allocate descriptor pool");
574
+
return -ENOMEM;
575
+
}
576
+
577
+
return 0;
578
+
}
579
+
580
+
/**
581
+
* xdma_channel_isr - XDMA channel interrupt handler
582
+
* @irq: IRQ number
583
+
* @dev_id: Pointer to the DMA channel structure
584
+
*/
585
+
static irqreturn_t xdma_channel_isr(int irq, void *dev_id)
586
+
{
587
+
struct xdma_chan *xchan = dev_id;
588
+
u32 complete_desc_num = 0;
589
+
struct xdma_device *xdev;
590
+
struct virt_dma_desc *vd;
591
+
struct xdma_desc *desc;
592
+
int ret;
593
+
594
+
spin_lock(&xchan->vchan.lock);
595
+
596
+
/* get submitted request */
597
+
vd = vchan_next_desc(&xchan->vchan);
598
+
if (!vd)
599
+
goto out;
600
+
601
+
xchan->busy = false;
602
+
desc = to_xdma_desc(vd);
603
+
xdev = xchan->xdev_hdl;
604
+
605
+
ret = regmap_read(xdev->rmap, xchan->base + XDMA_CHAN_COMPLETED_DESC,
606
+
&complete_desc_num);
607
+
if (ret)
608
+
goto out;
609
+
610
+
desc->completed_desc_num += complete_desc_num;
611
+
/*
612
+
* if all data blocks are transferred, remove and complete the request
613
+
*/
614
+
if (desc->completed_desc_num == desc->desc_num) {
615
+
list_del(&vd->node);
616
+
vchan_cookie_complete(vd);
617
+
goto out;
618
+
}
619
+
620
+
if (desc->completed_desc_num > desc->desc_num ||
621
+
complete_desc_num != XDMA_DESC_BLOCK_NUM * XDMA_DESC_ADJACENT)
622
+
goto out;
623
+
624
+
/* transfer the rest of data */
625
+
xdma_xfer_start(xchan);
626
+
627
+
out:
628
+
spin_unlock(&xchan->vchan.lock);
629
+
return IRQ_HANDLED;
630
+
}
631
+
632
+
/**
633
+
* xdma_irq_fini - Uninitialize IRQ
634
+
* @xdev: DMA device pointer
635
+
*/
636
+
static void xdma_irq_fini(struct xdma_device *xdev)
637
+
{
638
+
int i;
639
+
640
+
/* disable interrupt */
641
+
regmap_write(xdev->rmap, XDMA_IRQ_CHAN_INT_EN_W1C, ~0);
642
+
643
+
/* free irq handler */
644
+
for (i = 0; i < xdev->h2c_chan_num; i++)
645
+
free_irq(xdev->h2c_chans[i].irq, &xdev->h2c_chans[i]);
646
+
647
+
for (i = 0; i < xdev->c2h_chan_num; i++)
648
+
free_irq(xdev->c2h_chans[i].irq, &xdev->c2h_chans[i]);
649
+
}
650
+
651
+
/**
652
+
* xdma_set_vector_reg - configure hardware IRQ registers
653
+
* @xdev: DMA device pointer
654
+
* @vec_tbl_start: Start of IRQ registers
655
+
* @irq_start: Start of IRQ
656
+
* @irq_num: Number of IRQ
657
+
*/
658
+
static int xdma_set_vector_reg(struct xdma_device *xdev, u32 vec_tbl_start,
659
+
u32 irq_start, u32 irq_num)
660
+
{
661
+
u32 shift, i, val = 0;
662
+
int ret;
663
+
664
+
/* Each IRQ register is 32 bit and contains 4 IRQs */
665
+
while (irq_num > 0) {
666
+
for (i = 0; i < 4; i++) {
667
+
shift = XDMA_IRQ_VEC_SHIFT * i;
668
+
val |= irq_start << shift;
669
+
irq_start++;
670
+
irq_num--;
671
+
}
672
+
673
+
/* write IRQ register */
674
+
ret = regmap_write(xdev->rmap, vec_tbl_start, val);
675
+
if (ret)
676
+
return ret;
677
+
vec_tbl_start += sizeof(u32);
678
+
val = 0;
679
+
}
680
+
681
+
return 0;
682
+
}
683
+
684
+
/**
685
+
* xdma_irq_init - initialize IRQs
686
+
* @xdev: DMA device pointer
687
+
*/
688
+
static int xdma_irq_init(struct xdma_device *xdev)
689
+
{
690
+
u32 irq = xdev->irq_start;
691
+
u32 user_irq_start;
692
+
int i, j, ret;
693
+
694
+
/* return failure if there are not enough IRQs */
695
+
if (xdev->irq_num < XDMA_CHAN_NUM(xdev)) {
696
+
xdma_err(xdev, "not enough irq");
697
+
return -EINVAL;
698
+
}
699
+
700
+
/* setup H2C interrupt handler */
701
+
for (i = 0; i < xdev->h2c_chan_num; i++) {
702
+
ret = request_irq(irq, xdma_channel_isr, 0,
703
+
"xdma-h2c-channel", &xdev->h2c_chans[i]);
704
+
if (ret) {
705
+
xdma_err(xdev, "H2C channel%d request irq%d failed: %d",
706
+
i, irq, ret);
707
+
goto failed_init_h2c;
708
+
}
709
+
xdev->h2c_chans[i].irq = irq;
710
+
irq++;
711
+
}
712
+
713
+
/* setup C2H interrupt handler */
714
+
for (j = 0; j < xdev->c2h_chan_num; j++) {
715
+
ret = request_irq(irq, xdma_channel_isr, 0,
716
+
"xdma-c2h-channel", &xdev->c2h_chans[j]);
717
+
if (ret) {
718
+
xdma_err(xdev, "H2C channel%d request irq%d failed: %d",
719
+
j, irq, ret);
720
+
goto failed_init_c2h;
721
+
}
722
+
xdev->c2h_chans[j].irq = irq;
723
+
irq++;
724
+
}
725
+
726
+
/* config hardware IRQ registers */
727
+
ret = xdma_set_vector_reg(xdev, XDMA_IRQ_CHAN_VEC_NUM, 0,
728
+
XDMA_CHAN_NUM(xdev));
729
+
if (ret) {
730
+
xdma_err(xdev, "failed to set channel vectors: %d", ret);
731
+
goto failed_init_c2h;
732
+
}
733
+
734
+
/* config user IRQ registers if needed */
735
+
user_irq_start = XDMA_CHAN_NUM(xdev);
736
+
if (xdev->irq_num > user_irq_start) {
737
+
ret = xdma_set_vector_reg(xdev, XDMA_IRQ_USER_VEC_NUM,
738
+
user_irq_start,
739
+
xdev->irq_num - user_irq_start);
740
+
if (ret) {
741
+
xdma_err(xdev, "failed to set user vectors: %d", ret);
742
+
goto failed_init_c2h;
743
+
}
744
+
}
745
+
746
+
/* enable interrupt */
747
+
ret = regmap_write(xdev->rmap, XDMA_IRQ_CHAN_INT_EN_W1S, ~0);
748
+
if (ret)
749
+
goto failed_init_c2h;
750
+
751
+
return 0;
752
+
753
+
failed_init_c2h:
754
+
while (j--)
755
+
free_irq(xdev->c2h_chans[j].irq, &xdev->c2h_chans[j]);
756
+
failed_init_h2c:
757
+
while (i--)
758
+
free_irq(xdev->h2c_chans[i].irq, &xdev->h2c_chans[i]);
759
+
760
+
return ret;
761
+
}
762
+
763
+
static bool xdma_filter_fn(struct dma_chan *chan, void *param)
764
+
{
765
+
struct xdma_chan *xdma_chan = to_xdma_chan(chan);
766
+
struct xdma_chan_info *chan_info = param;
767
+
768
+
return chan_info->dir == xdma_chan->dir;
769
+
}
770
+
771
+
/**
772
+
* xdma_disable_user_irq - Disable user interrupt
773
+
* @pdev: Pointer to the platform_device structure
774
+
* @irq_num: System IRQ number
775
+
*/
776
+
void xdma_disable_user_irq(struct platform_device *pdev, u32 irq_num)
777
+
{
778
+
struct xdma_device *xdev = platform_get_drvdata(pdev);
779
+
u32 index;
780
+
781
+
index = irq_num - xdev->irq_start;
782
+
if (index < XDMA_CHAN_NUM(xdev) || index >= xdev->irq_num) {
783
+
xdma_err(xdev, "invalid user irq number");
784
+
return;
785
+
}
786
+
index -= XDMA_CHAN_NUM(xdev);
787
+
788
+
regmap_write(xdev->rmap, XDMA_IRQ_USER_INT_EN_W1C, 1 << index);
789
+
}
790
+
EXPORT_SYMBOL(xdma_disable_user_irq);
791
+
792
+
/**
793
+
* xdma_enable_user_irq - Enable user logic interrupt
794
+
* @pdev: Pointer to the platform_device structure
795
+
* @irq_num: System IRQ number
796
+
*/
797
+
int xdma_enable_user_irq(struct platform_device *pdev, u32 irq_num)
798
+
{
799
+
struct xdma_device *xdev = platform_get_drvdata(pdev);
800
+
u32 index;
801
+
int ret;
802
+
803
+
index = irq_num - xdev->irq_start;
804
+
if (index < XDMA_CHAN_NUM(xdev) || index >= xdev->irq_num) {
805
+
xdma_err(xdev, "invalid user irq number");
806
+
return -EINVAL;
807
+
}
808
+
index -= XDMA_CHAN_NUM(xdev);
809
+
810
+
ret = regmap_write(xdev->rmap, XDMA_IRQ_USER_INT_EN_W1S, 1 << index);
811
+
if (ret)
812
+
return ret;
813
+
814
+
return 0;
815
+
}
816
+
EXPORT_SYMBOL(xdma_enable_user_irq);
817
+
818
+
/**
819
+
* xdma_get_user_irq - Get system IRQ number
820
+
* @pdev: Pointer to the platform_device structure
821
+
* @user_irq_index: User logic IRQ wire index
822
+
*
823
+
* Return: The system IRQ number allocated for the given wire index.
824
+
*/
825
+
int xdma_get_user_irq(struct platform_device *pdev, u32 user_irq_index)
826
+
{
827
+
struct xdma_device *xdev = platform_get_drvdata(pdev);
828
+
829
+
if (XDMA_CHAN_NUM(xdev) + user_irq_index >= xdev->irq_num) {
830
+
xdma_err(xdev, "invalid user irq index");
831
+
return -EINVAL;
832
+
}
833
+
834
+
return xdev->irq_start + XDMA_CHAN_NUM(xdev) + user_irq_index;
835
+
}
836
+
EXPORT_SYMBOL(xdma_get_user_irq);
837
+
838
+
/**
839
+
* xdma_remove - Driver remove function
840
+
* @pdev: Pointer to the platform_device structure
841
+
*/
842
+
static int xdma_remove(struct platform_device *pdev)
843
+
{
844
+
struct xdma_device *xdev = platform_get_drvdata(pdev);
845
+
846
+
if (xdev->status & XDMA_DEV_STATUS_INIT_MSIX)
847
+
xdma_irq_fini(xdev);
848
+
849
+
if (xdev->status & XDMA_DEV_STATUS_REG_DMA)
850
+
dma_async_device_unregister(&xdev->dma_dev);
851
+
852
+
return 0;
853
+
}
854
+
855
+
/**
856
+
* xdma_probe - Driver probe function
857
+
* @pdev: Pointer to the platform_device structure
858
+
*/
859
+
static int xdma_probe(struct platform_device *pdev)
860
+
{
861
+
struct xdma_platdata *pdata = dev_get_platdata(&pdev->dev);
862
+
struct xdma_device *xdev;
863
+
void __iomem *reg_base;
864
+
struct resource *res;
865
+
int ret = -ENODEV;
866
+
867
+
if (pdata->max_dma_channels > XDMA_MAX_CHANNELS) {
868
+
dev_err(&pdev->dev, "invalid max dma channels %d",
869
+
pdata->max_dma_channels);
870
+
return -EINVAL;
871
+
}
872
+
873
+
xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
874
+
if (!xdev)
875
+
return -ENOMEM;
876
+
877
+
platform_set_drvdata(pdev, xdev);
878
+
xdev->pdev = pdev;
879
+
880
+
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
881
+
if (!res) {
882
+
xdma_err(xdev, "failed to get irq resource");
883
+
goto failed;
884
+
}
885
+
xdev->irq_start = res->start;
886
+
xdev->irq_num = res->end - res->start + 1;
887
+
888
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
889
+
if (!res) {
890
+
xdma_err(xdev, "failed to get io resource");
891
+
goto failed;
892
+
}
893
+
894
+
reg_base = devm_ioremap_resource(&pdev->dev, res);
895
+
if (!reg_base) {
896
+
xdma_err(xdev, "ioremap failed");
897
+
goto failed;
898
+
}
899
+
900
+
xdev->rmap = devm_regmap_init_mmio(&pdev->dev, reg_base,
901
+
&xdma_regmap_config);
902
+
if (!xdev->rmap) {
903
+
xdma_err(xdev, "config regmap failed: %d", ret);
904
+
goto failed;
905
+
}
906
+
INIT_LIST_HEAD(&xdev->dma_dev.channels);
907
+
908
+
ret = xdma_alloc_channels(xdev, DMA_MEM_TO_DEV);
909
+
if (ret) {
910
+
xdma_err(xdev, "config H2C channels failed: %d", ret);
911
+
goto failed;
912
+
}
913
+
914
+
ret = xdma_alloc_channels(xdev, DMA_DEV_TO_MEM);
915
+
if (ret) {
916
+
xdma_err(xdev, "config C2H channels failed: %d", ret);
917
+
goto failed;
918
+
}
919
+
920
+
dma_cap_set(DMA_SLAVE, xdev->dma_dev.cap_mask);
921
+
dma_cap_set(DMA_PRIVATE, xdev->dma_dev.cap_mask);
922
+
923
+
xdev->dma_dev.dev = &pdev->dev;
924
+
xdev->dma_dev.device_free_chan_resources = xdma_free_chan_resources;
925
+
xdev->dma_dev.device_alloc_chan_resources = xdma_alloc_chan_resources;
926
+
xdev->dma_dev.device_tx_status = dma_cookie_status;
927
+
xdev->dma_dev.device_prep_slave_sg = xdma_prep_device_sg;
928
+
xdev->dma_dev.device_config = xdma_device_config;
929
+
xdev->dma_dev.device_issue_pending = xdma_issue_pending;
930
+
xdev->dma_dev.filter.map = pdata->device_map;
931
+
xdev->dma_dev.filter.mapcnt = pdata->device_map_cnt;
932
+
xdev->dma_dev.filter.fn = xdma_filter_fn;
933
+
934
+
ret = dma_async_device_register(&xdev->dma_dev);
935
+
if (ret) {
936
+
xdma_err(xdev, "failed to register Xilinx XDMA: %d", ret);
937
+
goto failed;
938
+
}
939
+
xdev->status |= XDMA_DEV_STATUS_REG_DMA;
940
+
941
+
ret = xdma_irq_init(xdev);
942
+
if (ret) {
943
+
xdma_err(xdev, "failed to init msix: %d", ret);
944
+
goto failed;
945
+
}
946
+
xdev->status |= XDMA_DEV_STATUS_INIT_MSIX;
947
+
948
+
return 0;
949
+
950
+
failed:
951
+
xdma_remove(pdev);
952
+
953
+
return ret;
954
+
}
955
+
956
+
static const struct platform_device_id xdma_id_table[] = {
957
+
{ "xdma", 0},
958
+
{ },
959
+
};
960
+
961
+
static struct platform_driver xdma_driver = {
962
+
.driver = {
963
+
.name = "xdma",
964
+
},
965
+
.id_table = xdma_id_table,
966
+
.probe = xdma_probe,
967
+
.remove = xdma_remove,
968
+
};
969
+
970
+
module_platform_driver(xdma_driver);
971
+
972
+
MODULE_DESCRIPTION("AMD XDMA driver");
973
+
MODULE_AUTHOR("XRT Team <runtimeca39d@amd.com>");
974
+
MODULE_LICENSE("GPL");
+1
-3
drivers/dma/xilinx/zynqmp_dma.c
+1
-3
drivers/dma/xilinx/zynqmp_dma.c
···
890
890
struct platform_device *pdev)
891
891
{
892
892
struct zynqmp_dma_chan *chan;
893
-
struct resource *res;
894
893
struct device_node *node = pdev->dev.of_node;
895
894
int err;
896
895
···
899
900
chan->dev = zdev->dev;
900
901
chan->zdev = zdev;
901
902
902
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
903
-
chan->regs = devm_ioremap_resource(&pdev->dev, res);
903
+
chan->regs = devm_platform_ioremap_resource(pdev, 0);
904
904
if (IS_ERR(chan->regs))
905
905
return PTR_ERR(chan->regs);
906
906
+16
include/linux/dma/amd_xdma.h
+16
include/linux/dma/amd_xdma.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
+
/*
3
+
* Copyright (C) 2022, Advanced Micro Devices, Inc.
4
+
*/
5
+
6
+
#ifndef _DMAENGINE_AMD_XDMA_H
7
+
#define _DMAENGINE_AMD_XDMA_H
8
+
9
+
#include <linux/interrupt.h>
10
+
#include <linux/platform_device.h>
11
+
12
+
int xdma_enable_user_irq(struct platform_device *pdev, u32 irq_num);
13
+
void xdma_disable_user_irq(struct platform_device *pdev, u32 irq_num);
14
+
int xdma_get_user_irq(struct platform_device *pdev, u32 user_irq_index);
15
+
16
+
#endif /* _DMAENGINE_AMD_XDMA_H */
+1
include/linux/dma/imx-dma.h
+1
include/linux/dma/imx-dma.h
+7
-6
include/linux/dmaengine.h
+7
-6
include/linux/dmaengine.h
···
773
773
774
774
/**
775
775
* struct dma_device - info on the entity supplying DMA services
776
+
* @ref: reference is taken and put every time a channel is allocated or freed
776
777
* @chancnt: how many DMA channels are supported
777
778
* @privatecnt: how many DMA channels are requested by dma_request_channel
778
779
* @channels: the list of struct dma_chan
···
790
789
* @dev_id: unique device ID
791
790
* @dev: struct device reference for dma mapping api
792
791
* @owner: owner module (automatically set based on the provided dev)
792
+
* @chan_ida: unique channel ID
793
793
* @src_addr_widths: bit mask of src addr widths the device supports
794
794
* Width is specified in bytes, e.g. for a device supporting
795
795
* a width of 4 the mask should have BIT(4) set.
···
804
802
* @max_sg_burst: max number of SG list entries executed in a single burst
805
803
* DMA tansaction with no software intervention for reinitialization.
806
804
* Zero value means unlimited number of entries.
805
+
* @descriptor_reuse: a submitted transfer can be resubmitted after completion
807
806
* @residue_granularity: granularity of the transfer residue reported
808
807
* by tx_status
809
808
* @device_alloc_chan_resources: allocate resources and return the
···
842
839
* struct with auxiliary transfer status information, otherwise the call
843
840
* will just return a simple status code
844
841
* @device_issue_pending: push pending transactions to hardware
845
-
* @descriptor_reuse: a submitted transfer can be resubmitted after completion
846
842
* @device_release: called sometime atfer dma_async_device_unregister() is
847
843
* called and there are no further references to this structure. This
848
844
* must be implemented to free resources however many existing drivers
···
849
847
* @dbg_summary_show: optional routine to show contents in debugfs; default code
850
848
* will be used when this is omitted, but custom code can show extra,
851
849
* controller specific information.
850
+
* @dbg_dev_root: the root folder in debugfs for this device
852
851
*/
853
852
struct dma_device {
854
853
struct kref ref;
···
858
855
struct list_head channels;
859
856
struct list_head global_node;
860
857
struct dma_filter filter;
861
-
dma_cap_mask_t cap_mask;
858
+
dma_cap_mask_t cap_mask;
862
859
enum dma_desc_metadata_mode desc_metadata_modes;
863
860
unsigned short max_xor;
864
861
unsigned short max_pq;
···
927
924
struct dma_chan *chan, dma_addr_t dst, u64 data,
928
925
unsigned long flags);
929
926
930
-
void (*device_caps)(struct dma_chan *chan,
931
-
struct dma_slave_caps *caps);
932
-
int (*device_config)(struct dma_chan *chan,
933
-
struct dma_slave_config *config);
927
+
void (*device_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
928
+
int (*device_config)(struct dma_chan *chan, struct dma_slave_config *config);
934
929
int (*device_pause)(struct dma_chan *chan);
935
930
int (*device_resume)(struct dma_chan *chan);
936
931
int (*device_terminate_all)(struct dma_chan *chan);
+34
include/linux/platform_data/amd_xdma.h
+34
include/linux/platform_data/amd_xdma.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
+
/*
3
+
* Copyright (C) 2022, Advanced Micro Devices, Inc.
4
+
*/
5
+
6
+
#ifndef _PLATDATA_AMD_XDMA_H
7
+
#define _PLATDATA_AMD_XDMA_H
8
+
9
+
#include <linux/dmaengine.h>
10
+
11
+
/**
12
+
* struct xdma_chan_info - DMA channel information
13
+
* This information is used to match channel when request dma channel
14
+
* @dir: Channel transfer direction
15
+
*/
16
+
struct xdma_chan_info {
17
+
enum dma_transfer_direction dir;
18
+
};
19
+
20
+
#define XDMA_FILTER_PARAM(chan_info) ((void *)(chan_info))
21
+
22
+
struct dma_slave_map;
23
+
24
+
/**
25
+
* struct xdma_platdata - platform specific data for XDMA engine
26
+
* @max_dma_channels: Maximum dma channels in each direction
27
+
*/
28
+
struct xdma_platdata {
29
+
u32 max_dma_channels;
30
+
u32 device_map_cnt;
31
+
struct dma_slave_map *device_map;
32
+
};
33
+
34
+
#endif /* _PLATDATA_AMD_XDMA_H */