Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: meson: axg-fifo: use FIELD helpers
Use FIELD_GET() and FIELD_PREP() helpers instead of doing it manually.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://msgid.link/r/20240227150826.573581-1-jbrunet@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Jerome Brunet
and committed by
Mark Brown
9e6f3953
cb9d8a2c
+31
-33
+13
-12
sound/soc/meson/axg-fifo.c
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-12
sound/soc/meson/axg-fifo.c
···
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// Copyright (c) 2018 BayLibre, SAS.
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// Author: Jerome Brunet <jbrunet@baylibre.com>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
···
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/* Enable irq if necessary */
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irq_en = runtime->no_period_wakeup ? 0 : FIFO_INT_COUNT_REPEAT;
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regmap_update_bits(fifo->map, FIFO_CTRL0,
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CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT),
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CTRL0_INT_EN(irq_en));
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CTRL0_INT_EN,
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FIELD_PREP(CTRL0_INT_EN, irq_en));
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return 0;
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}
···
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{
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struct axg_fifo *fifo = axg_fifo_data(ss);
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/* Disable the block count irq */
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/* Disable irqs */
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regmap_update_bits(fifo->map, FIFO_CTRL0,
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CTRL0_INT_EN(FIFO_INT_COUNT_REPEAT), 0);
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CTRL0_INT_EN, 0);
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return 0;
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}
···
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static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
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{
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regmap_update_bits(fifo->map, FIFO_CTRL1,
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CTRL1_INT_CLR(FIFO_INT_MASK),
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CTRL1_INT_CLR(mask));
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CTRL1_INT_CLR,
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FIELD_PREP(CTRL1_INT_CLR, mask));
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/* Clear must also be cleared */
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regmap_update_bits(fifo->map, FIFO_CTRL1,
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CTRL1_INT_CLR(FIFO_INT_MASK),
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0);
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CTRL1_INT_CLR,
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FIELD_PREP(CTRL1_INT_CLR, 0));
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}
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static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id)
···
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regmap_read(fifo->map, FIFO_STATUS1, &status);
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status = STATUS1_INT_STS(status) & FIFO_INT_MASK;
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status = FIELD_GET(STATUS1_INT_STS, status);
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if (status & FIFO_INT_COUNT_REPEAT)
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snd_pcm_period_elapsed(ss);
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else
···
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/* Setup status2 so it reports the memory pointer */
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regmap_update_bits(fifo->map, FIFO_CTRL1,
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CTRL1_STATUS2_SEL_MASK,
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CTRL1_STATUS2_SEL(STATUS2_SEL_DDR_READ));
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CTRL1_STATUS2_SEL,
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FIELD_PREP(CTRL1_STATUS2_SEL, STATUS2_SEL_DDR_READ));
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/* Make sure the dma is initially disabled */
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__dma_enable(fifo, false);
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/* Disable irqs until params are ready */
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regmap_update_bits(fifo->map, FIFO_CTRL0,
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CTRL0_INT_EN(FIFO_INT_MASK), 0);
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CTRL0_INT_EN, 0);
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/* Clear any pending interrupt */
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axg_fifo_ack_irq(fifo, FIFO_INT_MASK);
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-7
sound/soc/meson/axg-fifo.h
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sound/soc/meson/axg-fifo.h
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#define FIFO_CTRL0 0x00
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#define CTRL0_DMA_EN BIT(31)
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#define CTRL0_INT_EN(x) ((x) << 16)
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#define CTRL0_INT_EN GENMASK(23, 16)
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#define CTRL0_SEL_MASK GENMASK(2, 0)
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#define CTRL0_SEL_SHIFT 0
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#define FIFO_CTRL1 0x04
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#define CTRL1_INT_CLR(x) ((x) << 0)
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#define CTRL1_STATUS2_SEL_MASK GENMASK(11, 8)
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#define CTRL1_STATUS2_SEL(x) ((x) << 8)
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#define CTRL1_INT_CLR GENMASK(7, 0)
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#define CTRL1_STATUS2_SEL GENMASK(11, 8)
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#define STATUS2_SEL_DDR_READ 0
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#define CTRL1_FRDDR_DEPTH_MASK GENMASK(31, 24)
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#define CTRL1_FRDDR_DEPTH(x) ((x) << 24)
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#define CTRL1_FRDDR_DEPTH GENMASK(31, 24)
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#define FIFO_START_ADDR 0x08
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#define FIFO_FINISH_ADDR 0x0c
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#define FIFO_INT_ADDR 0x10
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#define FIFO_STATUS1 0x14
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#define STATUS1_INT_STS(x) ((x) << 0)
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#define STATUS1_INT_STS GENMASK(7, 0)
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#define FIFO_STATUS2 0x18
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#define FIFO_INIT_ADDR 0x24
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#define FIFO_CTRL2 0x28
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sound/soc/meson/axg-frddr.c
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sound/soc/meson/axg-frddr.c
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* This driver implements the frontend playback DAI of AXG and G12A based SoCs
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/module.h>
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/* Trim the FIFO depth if the period is small to improve latency */
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depth = min(period, fifo->depth);
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val = (depth / AXG_FIFO_BURST) - 1;
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regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH_MASK,
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CTRL1_FRDDR_DEPTH(val));
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regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH,
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FIELD_PREP(CTRL1_FRDDR_DEPTH, val));
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return 0;
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}
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sound/soc/meson/axg-toddr.c
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sound/soc/meson/axg-toddr.c
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/* This driver implements the frontend capture DAI of AXG based SoCs */
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/module.h>
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#define CTRL0_TODDR_EXT_SIGNED BIT(29)
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#define CTRL0_TODDR_PP_MODE BIT(28)
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#define CTRL0_TODDR_SYNC_CH BIT(27)
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#define CTRL0_TODDR_TYPE_MASK GENMASK(15, 13)
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#define CTRL0_TODDR_TYPE(x) ((x) << 13)
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#define CTRL0_TODDR_MSB_POS_MASK GENMASK(12, 8)
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#define CTRL0_TODDR_MSB_POS(x) ((x) << 8)
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#define CTRL0_TODDR_LSB_POS_MASK GENMASK(7, 3)
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#define CTRL0_TODDR_LSB_POS(x) ((x) << 3)
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#define CTRL0_TODDR_TYPE GENMASK(15, 13)
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#define CTRL0_TODDR_MSB_POS GENMASK(12, 8)
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#define CTRL0_TODDR_LSB_POS GENMASK(7, 3)
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#define CTRL1_TODDR_FORCE_FINISH BIT(25)
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#define CTRL1_SEL_SHIFT 28
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···
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width = params_width(params);
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regmap_update_bits(fifo->map, FIFO_CTRL0,
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CTRL0_TODDR_TYPE_MASK |
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CTRL0_TODDR_MSB_POS_MASK |
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CTRL0_TODDR_LSB_POS_MASK,
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CTRL0_TODDR_TYPE(type) |
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CTRL0_TODDR_MSB_POS(TODDR_MSB_POS) |
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CTRL0_TODDR_LSB_POS(TODDR_MSB_POS - (width - 1)));
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CTRL0_TODDR_TYPE |
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CTRL0_TODDR_MSB_POS |
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CTRL0_TODDR_LSB_POS,
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FIELD_PREP(CTRL0_TODDR_TYPE, type) |
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FIELD_PREP(CTRL0_TODDR_MSB_POS, TODDR_MSB_POS) |
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FIELD_PREP(CTRL0_TODDR_LSB_POS, TODDR_MSB_POS - (width - 1)));
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return 0;
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}