tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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clk: qcom: add the SM8650 Display Clock Controller driver

Add Display Clock Controller (DISPCC) support for SM8650 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-clocks-v3-9-761a6fadb4c0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Neil Armstrong and committed by
Bjorn Andersson 9e939f00 e3388328

+1821
+10
drivers/clk/qcom/Kconfig
··· 851 851 Say Y if you want to support display devices and functionality such as 852 852 splash screen. 853 853 854 + config SM_DISPCC_8650 855 + tristate "SM8650 Display Clock Controller" 856 + depends on ARM64 || COMPILE_TEST 857 + select SM_GCC_8650 858 + help 859 + Support for the display clock controller on Qualcomm Technologies, Inc 860 + SM8650 devices. 861 + Say Y if you want to support display devices and functionality such as 862 + splash screen. 863 + 854 864 config SM_GCC_4450 855 865 tristate "SM4450 Global Clock Controller" 856 866 depends on ARM64 || COMPILE_TEST
+1
drivers/clk/qcom/Makefile
··· 111 111 obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o 112 112 obj-$(CONFIG_SM_DISPCC_8450) += dispcc-sm8450.o 113 113 obj-$(CONFIG_SM_DISPCC_8550) += dispcc-sm8550.o 114 + obj-$(CONFIG_SM_DISPCC_8650) += dispcc-sm8650.o 114 115 obj-$(CONFIG_SM_GCC_4450) += gcc-sm4450.o 115 116 obj-$(CONFIG_SM_GCC_6115) += gcc-sm6115.o 116 117 obj-$(CONFIG_SM_GCC_6125) += gcc-sm6125.o
+1810
drivers/clk/qcom/dispcc-sm8650.c
··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved 4 + * Copyright (c) 2023, Linaro Ltd. 5 + */ 6 + 7 + #include <linux/clk-provider.h> 8 + #include <linux/err.h> 9 + #include <linux/kernel.h> 10 + #include <linux/mod_devicetable.h> 11 + #include <linux/module.h> 12 + #include <linux/platform_device.h> 13 + #include <linux/pm_runtime.h> 14 + #include <linux/regmap.h> 15 + 16 + #include <dt-bindings/clock/qcom,sm8650-dispcc.h> 17 + 18 + #include "common.h" 19 + #include "clk-alpha-pll.h" 20 + #include "clk-branch.h" 21 + #include "clk-pll.h" 22 + #include "clk-rcg.h" 23 + #include "clk-regmap.h" 24 + #include "clk-regmap-divider.h" 25 + #include "reset.h" 26 + #include "gdsc.h" 27 + 28 + /* Need to match the order of clocks in DT binding */ 29 + enum { 30 + DT_BI_TCXO, 31 + DT_BI_TCXO_AO, 32 + DT_AHB_CLK, 33 + DT_SLEEP_CLK, 34 + 35 + DT_DSI0_PHY_PLL_OUT_BYTECLK, 36 + DT_DSI0_PHY_PLL_OUT_DSICLK, 37 + DT_DSI1_PHY_PLL_OUT_BYTECLK, 38 + DT_DSI1_PHY_PLL_OUT_DSICLK, 39 + 40 + DT_DP0_PHY_PLL_LINK_CLK, 41 + DT_DP0_PHY_PLL_VCO_DIV_CLK, 42 + DT_DP1_PHY_PLL_LINK_CLK, 43 + DT_DP1_PHY_PLL_VCO_DIV_CLK, 44 + DT_DP2_PHY_PLL_LINK_CLK, 45 + DT_DP2_PHY_PLL_VCO_DIV_CLK, 46 + DT_DP3_PHY_PLL_LINK_CLK, 47 + DT_DP3_PHY_PLL_VCO_DIV_CLK, 48 + }; 49 + 50 + #define DISP_CC_MISC_CMD 0xF000 51 + 52 + enum { 53 + P_BI_TCXO, 54 + P_DISP_CC_PLL0_OUT_MAIN, 55 + P_DISP_CC_PLL1_OUT_EVEN, 56 + P_DISP_CC_PLL1_OUT_MAIN, 57 + P_DP0_PHY_PLL_LINK_CLK, 58 + P_DP0_PHY_PLL_VCO_DIV_CLK, 59 + P_DP1_PHY_PLL_LINK_CLK, 60 + P_DP1_PHY_PLL_VCO_DIV_CLK, 61 + P_DP2_PHY_PLL_LINK_CLK, 62 + P_DP2_PHY_PLL_VCO_DIV_CLK, 63 + P_DP3_PHY_PLL_LINK_CLK, 64 + P_DP3_PHY_PLL_VCO_DIV_CLK, 65 + P_DSI0_PHY_PLL_OUT_BYTECLK, 66 + P_DSI0_PHY_PLL_OUT_DSICLK, 67 + P_DSI1_PHY_PLL_OUT_BYTECLK, 68 + P_DSI1_PHY_PLL_OUT_DSICLK, 69 + P_SLEEP_CLK, 70 + }; 71 + 72 + static struct pll_vco lucid_ole_vco[] = { 73 + { 249600000, 2100000000, 0 }, 74 + }; 75 + 76 + static const struct alpha_pll_config disp_cc_pll0_config = { 77 + .l = 0xd, 78 + .alpha = 0x6492, 79 + .config_ctl_val = 0x20485699, 80 + .config_ctl_hi_val = 0x00182261, 81 + .config_ctl_hi1_val = 0x82aa299c, 82 + .user_ctl_val = 0x00000000, 83 + .user_ctl_hi_val = 0x00000005, 84 + }; 85 + 86 + static struct clk_alpha_pll disp_cc_pll0 = { 87 + .offset = 0x0, 88 + .vco_table = lucid_ole_vco, 89 + .num_vco = ARRAY_SIZE(lucid_ole_vco), 90 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 91 + .clkr = { 92 + .hw.init = &(const struct clk_init_data) { 93 + .name = "disp_cc_pll0", 94 + .parent_data = &(const struct clk_parent_data) { 95 + .index = DT_BI_TCXO, 96 + }, 97 + .num_parents = 1, 98 + .ops = &clk_alpha_pll_reset_lucid_ole_ops, 99 + }, 100 + }, 101 + }; 102 + 103 + static const struct alpha_pll_config disp_cc_pll1_config = { 104 + .l = 0x1f, 105 + .alpha = 0x4000, 106 + .config_ctl_val = 0x20485699, 107 + .config_ctl_hi_val = 0x00182261, 108 + .config_ctl_hi1_val = 0x82aa299c, 109 + .user_ctl_val = 0x00000000, 110 + .user_ctl_hi_val = 0x00000005, 111 + }; 112 + 113 + static struct clk_alpha_pll disp_cc_pll1 = { 114 + .offset = 0x1000, 115 + .vco_table = lucid_ole_vco, 116 + .num_vco = ARRAY_SIZE(lucid_ole_vco), 117 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 118 + .clkr = { 119 + .hw.init = &(const struct clk_init_data) { 120 + .name = "disp_cc_pll1", 121 + .parent_data = &(const struct clk_parent_data) { 122 + .index = DT_BI_TCXO, 123 + }, 124 + .num_parents = 1, 125 + .ops = &clk_alpha_pll_reset_lucid_ole_ops, 126 + }, 127 + }, 128 + }; 129 + 130 + static const struct parent_map disp_cc_parent_map_0[] = { 131 + { P_BI_TCXO, 0 }, 132 + }; 133 + 134 + static const struct clk_parent_data disp_cc_parent_data_0[] = { 135 + { .index = DT_BI_TCXO }, 136 + }; 137 + 138 + static const struct clk_parent_data disp_cc_parent_data_0_ao[] = { 139 + { .index = DT_BI_TCXO_AO }, 140 + }; 141 + 142 + static const struct parent_map disp_cc_parent_map_1[] = { 143 + { P_BI_TCXO, 0 }, 144 + { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 145 + { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 146 + { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 147 + }; 148 + 149 + static const struct clk_parent_data disp_cc_parent_data_1[] = { 150 + { .index = DT_BI_TCXO }, 151 + { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 152 + { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 153 + { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 154 + }; 155 + 156 + static const struct parent_map disp_cc_parent_map_2[] = { 157 + { P_BI_TCXO, 0 }, 158 + { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, 159 + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 160 + { P_DSI1_PHY_PLL_OUT_DSICLK, 3 }, 161 + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 162 + }; 163 + 164 + static const struct clk_parent_data disp_cc_parent_data_2[] = { 165 + { .index = DT_BI_TCXO }, 166 + { .index = DT_DSI0_PHY_PLL_OUT_DSICLK }, 167 + { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 168 + { .index = DT_DSI1_PHY_PLL_OUT_DSICLK }, 169 + { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 170 + }; 171 + 172 + static const struct parent_map disp_cc_parent_map_3[] = { 173 + { P_BI_TCXO, 0 }, 174 + { P_DP1_PHY_PLL_LINK_CLK, 2 }, 175 + { P_DP2_PHY_PLL_LINK_CLK, 3 }, 176 + { P_DP3_PHY_PLL_LINK_CLK, 4 }, 177 + }; 178 + 179 + static const struct clk_parent_data disp_cc_parent_data_3[] = { 180 + { .index = DT_BI_TCXO }, 181 + { .index = DT_DP1_PHY_PLL_LINK_CLK }, 182 + { .index = DT_DP2_PHY_PLL_LINK_CLK }, 183 + { .index = DT_DP3_PHY_PLL_LINK_CLK }, 184 + }; 185 + 186 + static const struct parent_map disp_cc_parent_map_4[] = { 187 + { P_BI_TCXO, 0 }, 188 + { P_DP0_PHY_PLL_LINK_CLK, 1 }, 189 + { P_DP0_PHY_PLL_VCO_DIV_CLK, 2 }, 190 + { P_DP3_PHY_PLL_VCO_DIV_CLK, 3 }, 191 + { P_DP1_PHY_PLL_VCO_DIV_CLK, 4 }, 192 + { P_DP2_PHY_PLL_VCO_DIV_CLK, 6 }, 193 + }; 194 + 195 + static const struct clk_parent_data disp_cc_parent_data_4[] = { 196 + { .index = DT_BI_TCXO }, 197 + { .index = DT_DP0_PHY_PLL_LINK_CLK }, 198 + { .index = DT_DP0_PHY_PLL_VCO_DIV_CLK }, 199 + { .index = DT_DP3_PHY_PLL_VCO_DIV_CLK }, 200 + { .index = DT_DP1_PHY_PLL_VCO_DIV_CLK }, 201 + { .index = DT_DP2_PHY_PLL_VCO_DIV_CLK }, 202 + }; 203 + 204 + static const struct parent_map disp_cc_parent_map_5[] = { 205 + { P_BI_TCXO, 0 }, 206 + { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, 207 + { P_DSI1_PHY_PLL_OUT_BYTECLK, 4 }, 208 + }; 209 + 210 + static const struct clk_parent_data disp_cc_parent_data_5[] = { 211 + { .index = DT_BI_TCXO }, 212 + { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK }, 213 + { .index = DT_DSI1_PHY_PLL_OUT_BYTECLK }, 214 + }; 215 + 216 + static const struct parent_map disp_cc_parent_map_6[] = { 217 + { P_BI_TCXO, 0 }, 218 + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 219 + { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 220 + }; 221 + 222 + static const struct clk_parent_data disp_cc_parent_data_6[] = { 223 + { .index = DT_BI_TCXO }, 224 + { .hw = &disp_cc_pll1.clkr.hw }, 225 + { .hw = &disp_cc_pll1.clkr.hw }, 226 + }; 227 + 228 + static const struct parent_map disp_cc_parent_map_7[] = { 229 + { P_BI_TCXO, 0 }, 230 + { P_DP0_PHY_PLL_LINK_CLK, 1 }, 231 + { P_DP1_PHY_PLL_LINK_CLK, 2 }, 232 + { P_DP2_PHY_PLL_LINK_CLK, 3 }, 233 + { P_DP3_PHY_PLL_LINK_CLK, 4 }, 234 + }; 235 + 236 + static const struct clk_parent_data disp_cc_parent_data_7[] = { 237 + { .index = DT_BI_TCXO }, 238 + { .index = DT_DP0_PHY_PLL_LINK_CLK }, 239 + { .index = DT_DP1_PHY_PLL_LINK_CLK }, 240 + { .index = DT_DP2_PHY_PLL_LINK_CLK }, 241 + { .index = DT_DP3_PHY_PLL_LINK_CLK }, 242 + }; 243 + 244 + static const struct parent_map disp_cc_parent_map_8[] = { 245 + { P_BI_TCXO, 0 }, 246 + { P_DISP_CC_PLL0_OUT_MAIN, 1 }, 247 + { P_DISP_CC_PLL1_OUT_MAIN, 4 }, 248 + { P_DISP_CC_PLL1_OUT_EVEN, 6 }, 249 + }; 250 + 251 + static const struct clk_parent_data disp_cc_parent_data_8[] = { 252 + { .index = DT_BI_TCXO }, 253 + { .hw = &disp_cc_pll0.clkr.hw }, 254 + { .hw = &disp_cc_pll1.clkr.hw }, 255 + { .hw = &disp_cc_pll1.clkr.hw }, 256 + }; 257 + 258 + static const struct parent_map disp_cc_parent_map_9[] = { 259 + { P_SLEEP_CLK, 0 }, 260 + }; 261 + 262 + static const struct clk_parent_data disp_cc_parent_data_9[] = { 263 + { .index = DT_SLEEP_CLK }, 264 + }; 265 + 266 + static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { 267 + F(19200000, P_BI_TCXO, 1, 0, 0), 268 + F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0), 269 + F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0), 270 + { } 271 + }; 272 + 273 + static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { 274 + .cmd_rcgr = 0x82e8, 275 + .mnd_width = 0, 276 + .hid_width = 5, 277 + .parent_map = disp_cc_parent_map_6, 278 + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, 279 + .clkr.hw.init = &(const struct clk_init_data) { 280 + .name = "disp_cc_mdss_ahb_clk_src", 281 + .parent_data = disp_cc_parent_data_6, 282 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), 283 + .flags = CLK_SET_RATE_PARENT, 284 + .ops = &clk_rcg2_shared_ops, 285 + }, 286 + }; 287 + 288 + static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = { 289 + F(19200000, P_BI_TCXO, 1, 0, 0), 290 + { } 291 + }; 292 + 293 + static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { 294 + .cmd_rcgr = 0x8108, 295 + .mnd_width = 0, 296 + .hid_width = 5, 297 + .parent_map = disp_cc_parent_map_2, 298 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 299 + .clkr.hw.init = &(const struct clk_init_data) { 300 + .name = "disp_cc_mdss_byte0_clk_src", 301 + .parent_data = disp_cc_parent_data_2, 302 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 303 + .flags = CLK_SET_RATE_PARENT, 304 + .ops = &clk_byte2_ops, 305 + }, 306 + }; 307 + 308 + static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { 309 + .cmd_rcgr = 0x8124, 310 + .mnd_width = 0, 311 + .hid_width = 5, 312 + .parent_map = disp_cc_parent_map_2, 313 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 314 + .clkr.hw.init = &(const struct clk_init_data) { 315 + .name = "disp_cc_mdss_byte1_clk_src", 316 + .parent_data = disp_cc_parent_data_2, 317 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 318 + .flags = CLK_SET_RATE_PARENT, 319 + .ops = &clk_byte2_ops, 320 + }, 321 + }; 322 + 323 + static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { 324 + .cmd_rcgr = 0x81bc, 325 + .mnd_width = 0, 326 + .hid_width = 5, 327 + .parent_map = disp_cc_parent_map_0, 328 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 329 + .clkr.hw.init = &(const struct clk_init_data) { 330 + .name = "disp_cc_mdss_dptx0_aux_clk_src", 331 + .parent_data = disp_cc_parent_data_0, 332 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 333 + .flags = CLK_SET_RATE_PARENT, 334 + .ops = &clk_rcg2_ops, 335 + }, 336 + }; 337 + 338 + static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = { 339 + F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), 340 + F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), 341 + F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), 342 + F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), 343 + { } 344 + }; 345 + 346 + static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { 347 + .cmd_rcgr = 0x8170, 348 + .mnd_width = 0, 349 + .hid_width = 5, 350 + .parent_map = disp_cc_parent_map_7, 351 + .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, 352 + .clkr.hw.init = &(const struct clk_init_data) { 353 + .name = "disp_cc_mdss_dptx0_link_clk_src", 354 + .parent_data = disp_cc_parent_data_7, 355 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), 356 + .flags = CLK_SET_RATE_PARENT, 357 + .ops = &clk_rcg2_ops, 358 + }, 359 + }; 360 + 361 + static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { 362 + .cmd_rcgr = 0x818c, 363 + .mnd_width = 16, 364 + .hid_width = 5, 365 + .parent_map = disp_cc_parent_map_4, 366 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 367 + .clkr.hw.init = &(const struct clk_init_data) { 368 + .name = "disp_cc_mdss_dptx0_pixel0_clk_src", 369 + .parent_data = disp_cc_parent_data_4, 370 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 371 + .flags = CLK_SET_RATE_PARENT, 372 + .ops = &clk_dp_ops, 373 + }, 374 + }; 375 + 376 + static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { 377 + .cmd_rcgr = 0x81a4, 378 + .mnd_width = 16, 379 + .hid_width = 5, 380 + .parent_map = disp_cc_parent_map_4, 381 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 382 + .clkr.hw.init = &(const struct clk_init_data) { 383 + .name = "disp_cc_mdss_dptx0_pixel1_clk_src", 384 + .parent_data = disp_cc_parent_data_4, 385 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), 386 + .flags = CLK_SET_RATE_PARENT, 387 + .ops = &clk_dp_ops, 388 + }, 389 + }; 390 + 391 + static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { 392 + .cmd_rcgr = 0x8220, 393 + .mnd_width = 0, 394 + .hid_width = 5, 395 + .parent_map = disp_cc_parent_map_0, 396 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 397 + .clkr.hw.init = &(const struct clk_init_data) { 398 + .name = "disp_cc_mdss_dptx1_aux_clk_src", 399 + .parent_data = disp_cc_parent_data_0, 400 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 401 + .flags = CLK_SET_RATE_PARENT, 402 + .ops = &clk_dp_ops, 403 + }, 404 + }; 405 + 406 + static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { 407 + .cmd_rcgr = 0x8204, 408 + .mnd_width = 0, 409 + .hid_width = 5, 410 + .parent_map = disp_cc_parent_map_3, 411 + .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, 412 + .clkr.hw.init = &(const struct clk_init_data) { 413 + .name = "disp_cc_mdss_dptx1_link_clk_src", 414 + .parent_data = disp_cc_parent_data_3, 415 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 416 + .flags = CLK_SET_RATE_PARENT, 417 + .ops = &clk_rcg2_ops, 418 + }, 419 + }; 420 + 421 + static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { 422 + .cmd_rcgr = 0x81d4, 423 + .mnd_width = 16, 424 + .hid_width = 5, 425 + .parent_map = disp_cc_parent_map_1, 426 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 427 + .clkr.hw.init = &(const struct clk_init_data) { 428 + .name = "disp_cc_mdss_dptx1_pixel0_clk_src", 429 + .parent_data = disp_cc_parent_data_1, 430 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 431 + .flags = CLK_SET_RATE_PARENT, 432 + .ops = &clk_dp_ops, 433 + }, 434 + }; 435 + 436 + static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { 437 + .cmd_rcgr = 0x81ec, 438 + .mnd_width = 16, 439 + .hid_width = 5, 440 + .parent_map = disp_cc_parent_map_1, 441 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 442 + .clkr.hw.init = &(const struct clk_init_data) { 443 + .name = "disp_cc_mdss_dptx1_pixel1_clk_src", 444 + .parent_data = disp_cc_parent_data_1, 445 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 446 + .flags = CLK_SET_RATE_PARENT, 447 + .ops = &clk_dp_ops, 448 + }, 449 + }; 450 + 451 + static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { 452 + .cmd_rcgr = 0x8284, 453 + .mnd_width = 0, 454 + .hid_width = 5, 455 + .parent_map = disp_cc_parent_map_0, 456 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 457 + .clkr.hw.init = &(const struct clk_init_data) { 458 + .name = "disp_cc_mdss_dptx2_aux_clk_src", 459 + .parent_data = disp_cc_parent_data_0, 460 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 461 + .flags = CLK_SET_RATE_PARENT, 462 + .ops = &clk_rcg2_ops, 463 + }, 464 + }; 465 + 466 + static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { 467 + .cmd_rcgr = 0x8238, 468 + .mnd_width = 0, 469 + .hid_width = 5, 470 + .parent_map = disp_cc_parent_map_3, 471 + .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, 472 + .clkr.hw.init = &(const struct clk_init_data) { 473 + .name = "disp_cc_mdss_dptx2_link_clk_src", 474 + .parent_data = disp_cc_parent_data_3, 475 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 476 + .flags = CLK_SET_RATE_PARENT, 477 + .ops = &clk_rcg2_ops, 478 + }, 479 + }; 480 + 481 + static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { 482 + .cmd_rcgr = 0x8254, 483 + .mnd_width = 16, 484 + .hid_width = 5, 485 + .parent_map = disp_cc_parent_map_1, 486 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 487 + .clkr.hw.init = &(const struct clk_init_data) { 488 + .name = "disp_cc_mdss_dptx2_pixel0_clk_src", 489 + .parent_data = disp_cc_parent_data_1, 490 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 491 + .flags = CLK_SET_RATE_PARENT, 492 + .ops = &clk_dp_ops, 493 + }, 494 + }; 495 + 496 + static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { 497 + .cmd_rcgr = 0x826c, 498 + .mnd_width = 16, 499 + .hid_width = 5, 500 + .parent_map = disp_cc_parent_map_1, 501 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 502 + .clkr.hw.init = &(const struct clk_init_data) { 503 + .name = "disp_cc_mdss_dptx2_pixel1_clk_src", 504 + .parent_data = disp_cc_parent_data_1, 505 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 506 + .flags = CLK_SET_RATE_PARENT, 507 + .ops = &clk_dp_ops, 508 + }, 509 + }; 510 + 511 + static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { 512 + .cmd_rcgr = 0x82d0, 513 + .mnd_width = 0, 514 + .hid_width = 5, 515 + .parent_map = disp_cc_parent_map_0, 516 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 517 + .clkr.hw.init = &(const struct clk_init_data) { 518 + .name = "disp_cc_mdss_dptx3_aux_clk_src", 519 + .parent_data = disp_cc_parent_data_0, 520 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 521 + .flags = CLK_SET_RATE_PARENT, 522 + .ops = &clk_rcg2_ops, 523 + }, 524 + }; 525 + 526 + static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { 527 + .cmd_rcgr = 0x82b4, 528 + .mnd_width = 0, 529 + .hid_width = 5, 530 + .parent_map = disp_cc_parent_map_3, 531 + .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, 532 + .clkr.hw.init = &(const struct clk_init_data) { 533 + .name = "disp_cc_mdss_dptx3_link_clk_src", 534 + .parent_data = disp_cc_parent_data_3, 535 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), 536 + .flags = CLK_SET_RATE_PARENT, 537 + .ops = &clk_rcg2_ops, 538 + }, 539 + }; 540 + 541 + static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { 542 + .cmd_rcgr = 0x829c, 543 + .mnd_width = 16, 544 + .hid_width = 5, 545 + .parent_map = disp_cc_parent_map_1, 546 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 547 + .clkr.hw.init = &(const struct clk_init_data) { 548 + .name = "disp_cc_mdss_dptx3_pixel0_clk_src", 549 + .parent_data = disp_cc_parent_data_1, 550 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), 551 + .flags = CLK_SET_RATE_PARENT, 552 + .ops = &clk_dp_ops, 553 + }, 554 + }; 555 + 556 + static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { 557 + .cmd_rcgr = 0x8140, 558 + .mnd_width = 0, 559 + .hid_width = 5, 560 + .parent_map = disp_cc_parent_map_5, 561 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 562 + .clkr.hw.init = &(const struct clk_init_data) { 563 + .name = "disp_cc_mdss_esc0_clk_src", 564 + .parent_data = disp_cc_parent_data_5, 565 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 566 + .flags = CLK_SET_RATE_PARENT, 567 + .ops = &clk_rcg2_ops, 568 + }, 569 + }; 570 + 571 + static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { 572 + .cmd_rcgr = 0x8158, 573 + .mnd_width = 0, 574 + .hid_width = 5, 575 + .parent_map = disp_cc_parent_map_5, 576 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 577 + .clkr.hw.init = &(const struct clk_init_data) { 578 + .name = "disp_cc_mdss_esc1_clk_src", 579 + .parent_data = disp_cc_parent_data_5, 580 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), 581 + .flags = CLK_SET_RATE_PARENT, 582 + .ops = &clk_rcg2_ops, 583 + }, 584 + }; 585 + 586 + static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { 587 + F(19200000, P_BI_TCXO, 1, 0, 0), 588 + F(85714286, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 589 + F(100000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 590 + F(150000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 591 + F(200000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 592 + F(325000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 593 + F(402000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 594 + F(514000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0), 595 + { } 596 + }; 597 + 598 + static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { 599 + .cmd_rcgr = 0x80d8, 600 + .mnd_width = 0, 601 + .hid_width = 5, 602 + .parent_map = disp_cc_parent_map_8, 603 + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, 604 + .clkr.hw.init = &(const struct clk_init_data) { 605 + .name = "disp_cc_mdss_mdp_clk_src", 606 + .parent_data = disp_cc_parent_data_8, 607 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), 608 + .flags = CLK_SET_RATE_PARENT, 609 + .ops = &clk_rcg2_shared_ops, 610 + }, 611 + }; 612 + 613 + static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { 614 + .cmd_rcgr = 0x80a8, 615 + .mnd_width = 8, 616 + .hid_width = 5, 617 + .parent_map = disp_cc_parent_map_2, 618 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 619 + .clkr.hw.init = &(const struct clk_init_data) { 620 + .name = "disp_cc_mdss_pclk0_clk_src", 621 + .parent_data = disp_cc_parent_data_2, 622 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 623 + .flags = CLK_SET_RATE_PARENT, 624 + .ops = &clk_pixel_ops, 625 + }, 626 + }; 627 + 628 + static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { 629 + .cmd_rcgr = 0x80c0, 630 + .mnd_width = 8, 631 + .hid_width = 5, 632 + .parent_map = disp_cc_parent_map_2, 633 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 634 + .clkr.hw.init = &(const struct clk_init_data) { 635 + .name = "disp_cc_mdss_pclk1_clk_src", 636 + .parent_data = disp_cc_parent_data_2, 637 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), 638 + .flags = CLK_SET_RATE_PARENT, 639 + .ops = &clk_pixel_ops, 640 + }, 641 + }; 642 + 643 + static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { 644 + .cmd_rcgr = 0x80f0, 645 + .mnd_width = 0, 646 + .hid_width = 5, 647 + .parent_map = disp_cc_parent_map_0, 648 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 649 + .clkr.hw.init = &(const struct clk_init_data) { 650 + .name = "disp_cc_mdss_vsync_clk_src", 651 + .parent_data = disp_cc_parent_data_0, 652 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), 653 + .flags = CLK_SET_RATE_PARENT, 654 + .ops = &clk_rcg2_ops, 655 + }, 656 + }; 657 + 658 + static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = { 659 + F(32000, P_SLEEP_CLK, 1, 0, 0), 660 + { } 661 + }; 662 + 663 + static struct clk_rcg2 disp_cc_sleep_clk_src = { 664 + .cmd_rcgr = 0xe05c, 665 + .mnd_width = 0, 666 + .hid_width = 5, 667 + .parent_map = disp_cc_parent_map_9, 668 + .freq_tbl = ftbl_disp_cc_sleep_clk_src, 669 + .clkr.hw.init = &(const struct clk_init_data) { 670 + .name = "disp_cc_sleep_clk_src", 671 + .parent_data = disp_cc_parent_data_9, 672 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_9), 673 + .flags = CLK_SET_RATE_PARENT, 674 + .ops = &clk_rcg2_ops, 675 + }, 676 + }; 677 + 678 + static struct clk_rcg2 disp_cc_xo_clk_src = { 679 + .cmd_rcgr = 0xe03c, 680 + .mnd_width = 0, 681 + .hid_width = 5, 682 + .parent_map = disp_cc_parent_map_0, 683 + .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, 684 + .clkr.hw.init = &(const struct clk_init_data) { 685 + .name = "disp_cc_xo_clk_src", 686 + .parent_data = disp_cc_parent_data_0_ao, 687 + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao), 688 + .flags = CLK_SET_RATE_PARENT, 689 + .ops = &clk_rcg2_ops, 690 + }, 691 + }; 692 + 693 + static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { 694 + .reg = 0x8120, 695 + .shift = 0, 696 + .width = 4, 697 + .clkr.hw.init = &(const struct clk_init_data) { 698 + .name = "disp_cc_mdss_byte0_div_clk_src", 699 + .parent_hws = (const struct clk_hw*[]) { 700 + &disp_cc_mdss_byte0_clk_src.clkr.hw, 701 + }, 702 + .num_parents = 1, 703 + .ops = &clk_regmap_div_ops, 704 + }, 705 + }; 706 + 707 + static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { 708 + .reg = 0x813c, 709 + .shift = 0, 710 + .width = 4, 711 + .clkr.hw.init = &(const struct clk_init_data) { 712 + .name = "disp_cc_mdss_byte1_div_clk_src", 713 + .parent_hws = (const struct clk_hw*[]) { 714 + &disp_cc_mdss_byte1_clk_src.clkr.hw, 715 + }, 716 + .num_parents = 1, 717 + .ops = &clk_regmap_div_ops, 718 + }, 719 + }; 720 + 721 + static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { 722 + .reg = 0x8188, 723 + .shift = 0, 724 + .width = 4, 725 + .clkr.hw.init = &(const struct clk_init_data) { 726 + .name = "disp_cc_mdss_dptx0_link_div_clk_src", 727 + .parent_hws = (const struct clk_hw*[]) { 728 + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 729 + }, 730 + .num_parents = 1, 731 + .flags = CLK_SET_RATE_PARENT, 732 + .ops = &clk_regmap_div_ro_ops, 733 + }, 734 + }; 735 + 736 + static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { 737 + .reg = 0x821c, 738 + .shift = 0, 739 + .width = 4, 740 + .clkr.hw.init = &(const struct clk_init_data) { 741 + .name = "disp_cc_mdss_dptx1_link_div_clk_src", 742 + .parent_hws = (const struct clk_hw*[]) { 743 + &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 744 + }, 745 + .num_parents = 1, 746 + .flags = CLK_SET_RATE_PARENT, 747 + .ops = &clk_regmap_div_ro_ops, 748 + }, 749 + }; 750 + 751 + static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { 752 + .reg = 0x8250, 753 + .shift = 0, 754 + .width = 4, 755 + .clkr.hw.init = &(const struct clk_init_data) { 756 + .name = "disp_cc_mdss_dptx2_link_div_clk_src", 757 + .parent_hws = (const struct clk_hw*[]) { 758 + &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 759 + }, 760 + .num_parents = 1, 761 + .flags = CLK_SET_RATE_PARENT, 762 + .ops = &clk_regmap_div_ro_ops, 763 + }, 764 + }; 765 + 766 + static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { 767 + .reg = 0x82cc, 768 + .shift = 0, 769 + .width = 4, 770 + .clkr.hw.init = &(const struct clk_init_data) { 771 + .name = "disp_cc_mdss_dptx3_link_div_clk_src", 772 + .parent_hws = (const struct clk_hw*[]) { 773 + &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 774 + }, 775 + .num_parents = 1, 776 + .flags = CLK_SET_RATE_PARENT, 777 + .ops = &clk_regmap_div_ro_ops, 778 + }, 779 + }; 780 + 781 + static struct clk_branch disp_cc_mdss_accu_clk = { 782 + .halt_reg = 0xe058, 783 + .halt_check = BRANCH_HALT_VOTED, 784 + .clkr = { 785 + .enable_reg = 0xe058, 786 + .enable_mask = BIT(0), 787 + .hw.init = &(const struct clk_init_data) { 788 + .name = "disp_cc_mdss_accu_clk", 789 + .parent_hws = (const struct clk_hw*[]) { 790 + &disp_cc_xo_clk_src.clkr.hw, 791 + }, 792 + .num_parents = 1, 793 + .flags = CLK_SET_RATE_PARENT, 794 + .ops = &clk_branch2_ops, 795 + }, 796 + }, 797 + }; 798 + 799 + static struct clk_branch disp_cc_mdss_ahb1_clk = { 800 + .halt_reg = 0xa020, 801 + .halt_check = BRANCH_HALT, 802 + .clkr = { 803 + .enable_reg = 0xa020, 804 + .enable_mask = BIT(0), 805 + .hw.init = &(const struct clk_init_data) { 806 + .name = "disp_cc_mdss_ahb1_clk", 807 + .parent_hws = (const struct clk_hw*[]) { 808 + &disp_cc_mdss_ahb_clk_src.clkr.hw, 809 + }, 810 + .num_parents = 1, 811 + .flags = CLK_SET_RATE_PARENT, 812 + .ops = &clk_branch2_ops, 813 + }, 814 + }, 815 + }; 816 + 817 + static struct clk_branch disp_cc_mdss_ahb_clk = { 818 + .halt_reg = 0x80a4, 819 + .halt_check = BRANCH_HALT, 820 + .clkr = { 821 + .enable_reg = 0x80a4, 822 + .enable_mask = BIT(0), 823 + .hw.init = &(const struct clk_init_data) { 824 + .name = "disp_cc_mdss_ahb_clk", 825 + .parent_hws = (const struct clk_hw*[]) { 826 + &disp_cc_mdss_ahb_clk_src.clkr.hw, 827 + }, 828 + .num_parents = 1, 829 + .flags = CLK_SET_RATE_PARENT, 830 + .ops = &clk_branch2_ops, 831 + }, 832 + }, 833 + }; 834 + 835 + static struct clk_branch disp_cc_mdss_byte0_clk = { 836 + .halt_reg = 0x8028, 837 + .halt_check = BRANCH_HALT, 838 + .clkr = { 839 + .enable_reg = 0x8028, 840 + .enable_mask = BIT(0), 841 + .hw.init = &(const struct clk_init_data) { 842 + .name = "disp_cc_mdss_byte0_clk", 843 + .parent_hws = (const struct clk_hw*[]) { 844 + &disp_cc_mdss_byte0_clk_src.clkr.hw, 845 + }, 846 + .num_parents = 1, 847 + .flags = CLK_SET_RATE_PARENT, 848 + .ops = &clk_branch2_ops, 849 + }, 850 + }, 851 + }; 852 + 853 + static struct clk_branch disp_cc_mdss_byte0_intf_clk = { 854 + .halt_reg = 0x802c, 855 + .halt_check = BRANCH_HALT, 856 + .clkr = { 857 + .enable_reg = 0x802c, 858 + .enable_mask = BIT(0), 859 + .hw.init = &(const struct clk_init_data) { 860 + .name = "disp_cc_mdss_byte0_intf_clk", 861 + .parent_hws = (const struct clk_hw*[]) { 862 + &disp_cc_mdss_byte0_div_clk_src.clkr.hw, 863 + }, 864 + .num_parents = 1, 865 + .flags = CLK_SET_RATE_PARENT, 866 + .ops = &clk_branch2_ops, 867 + }, 868 + }, 869 + }; 870 + 871 + static struct clk_branch disp_cc_mdss_byte1_clk = { 872 + .halt_reg = 0x8030, 873 + .halt_check = BRANCH_HALT, 874 + .clkr = { 875 + .enable_reg = 0x8030, 876 + .enable_mask = BIT(0), 877 + .hw.init = &(const struct clk_init_data) { 878 + .name = "disp_cc_mdss_byte1_clk", 879 + .parent_hws = (const struct clk_hw*[]) { 880 + &disp_cc_mdss_byte1_clk_src.clkr.hw, 881 + }, 882 + .num_parents = 1, 883 + .flags = CLK_SET_RATE_PARENT, 884 + .ops = &clk_branch2_ops, 885 + }, 886 + }, 887 + }; 888 + 889 + static struct clk_branch disp_cc_mdss_byte1_intf_clk = { 890 + .halt_reg = 0x8034, 891 + .halt_check = BRANCH_HALT, 892 + .clkr = { 893 + .enable_reg = 0x8034, 894 + .enable_mask = BIT(0), 895 + .hw.init = &(const struct clk_init_data) { 896 + .name = "disp_cc_mdss_byte1_intf_clk", 897 + .parent_hws = (const struct clk_hw*[]) { 898 + &disp_cc_mdss_byte1_div_clk_src.clkr.hw, 899 + }, 900 + .num_parents = 1, 901 + .flags = CLK_SET_RATE_PARENT, 902 + .ops = &clk_branch2_ops, 903 + }, 904 + }, 905 + }; 906 + 907 + static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { 908 + .halt_reg = 0x8058, 909 + .halt_check = BRANCH_HALT, 910 + .clkr = { 911 + .enable_reg = 0x8058, 912 + .enable_mask = BIT(0), 913 + .hw.init = &(const struct clk_init_data) { 914 + .name = "disp_cc_mdss_dptx0_aux_clk", 915 + .parent_hws = (const struct clk_hw*[]) { 916 + &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, 917 + }, 918 + .num_parents = 1, 919 + .flags = CLK_SET_RATE_PARENT, 920 + .ops = &clk_branch2_ops, 921 + }, 922 + }, 923 + }; 924 + 925 + static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { 926 + .halt_reg = 0x804c, 927 + .halt_check = BRANCH_HALT, 928 + .clkr = { 929 + .enable_reg = 0x804c, 930 + .enable_mask = BIT(0), 931 + .hw.init = &(const struct clk_init_data) { 932 + .name = "disp_cc_mdss_dptx0_crypto_clk", 933 + .parent_hws = (const struct clk_hw*[]) { 934 + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 935 + }, 936 + .num_parents = 1, 937 + .flags = CLK_SET_RATE_PARENT, 938 + .ops = &clk_branch2_ops, 939 + }, 940 + }, 941 + }; 942 + 943 + static struct clk_branch disp_cc_mdss_dptx0_link_clk = { 944 + .halt_reg = 0x8040, 945 + .halt_check = BRANCH_HALT, 946 + .clkr = { 947 + .enable_reg = 0x8040, 948 + .enable_mask = BIT(0), 949 + .hw.init = &(const struct clk_init_data) { 950 + .name = "disp_cc_mdss_dptx0_link_clk", 951 + .parent_hws = (const struct clk_hw*[]) { 952 + &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, 953 + }, 954 + .num_parents = 1, 955 + .flags = CLK_SET_RATE_PARENT, 956 + .ops = &clk_branch2_ops, 957 + }, 958 + }, 959 + }; 960 + 961 + static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { 962 + .halt_reg = 0x8048, 963 + .halt_check = BRANCH_HALT, 964 + .clkr = { 965 + .enable_reg = 0x8048, 966 + .enable_mask = BIT(0), 967 + .hw.init = &(const struct clk_init_data) { 968 + .name = "disp_cc_mdss_dptx0_link_intf_clk", 969 + .parent_hws = (const struct clk_hw*[]) { 970 + &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 971 + }, 972 + .num_parents = 1, 973 + .flags = CLK_SET_RATE_PARENT, 974 + .ops = &clk_branch2_ops, 975 + }, 976 + }, 977 + }; 978 + 979 + static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { 980 + .halt_reg = 0x8050, 981 + .halt_check = BRANCH_HALT, 982 + .clkr = { 983 + .enable_reg = 0x8050, 984 + .enable_mask = BIT(0), 985 + .hw.init = &(const struct clk_init_data) { 986 + .name = "disp_cc_mdss_dptx0_pixel0_clk", 987 + .parent_hws = (const struct clk_hw*[]) { 988 + &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, 989 + }, 990 + .num_parents = 1, 991 + .flags = CLK_SET_RATE_PARENT, 992 + .ops = &clk_branch2_ops, 993 + }, 994 + }, 995 + }; 996 + 997 + static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { 998 + .halt_reg = 0x8054, 999 + .halt_check = BRANCH_HALT, 1000 + .clkr = { 1001 + .enable_reg = 0x8054, 1002 + .enable_mask = BIT(0), 1003 + .hw.init = &(const struct clk_init_data) { 1004 + .name = "disp_cc_mdss_dptx0_pixel1_clk", 1005 + .parent_hws = (const struct clk_hw*[]) { 1006 + &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, 1007 + }, 1008 + .num_parents = 1, 1009 + .flags = CLK_SET_RATE_PARENT, 1010 + .ops = &clk_branch2_ops, 1011 + }, 1012 + }, 1013 + }; 1014 + 1015 + static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { 1016 + .halt_reg = 0x8044, 1017 + .halt_check = BRANCH_HALT, 1018 + .clkr = { 1019 + .enable_reg = 0x8044, 1020 + .enable_mask = BIT(0), 1021 + .hw.init = &(const struct clk_init_data) { 1022 + .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", 1023 + .parent_hws = (const struct clk_hw*[]) { 1024 + &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, 1025 + }, 1026 + .num_parents = 1, 1027 + .flags = CLK_SET_RATE_PARENT, 1028 + .ops = &clk_branch2_ops, 1029 + }, 1030 + }, 1031 + }; 1032 + 1033 + static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { 1034 + .halt_reg = 0x8074, 1035 + .halt_check = BRANCH_HALT, 1036 + .clkr = { 1037 + .enable_reg = 0x8074, 1038 + .enable_mask = BIT(0), 1039 + .hw.init = &(const struct clk_init_data) { 1040 + .name = "disp_cc_mdss_dptx1_aux_clk", 1041 + .parent_hws = (const struct clk_hw*[]) { 1042 + &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, 1043 + }, 1044 + .num_parents = 1, 1045 + .flags = CLK_SET_RATE_PARENT, 1046 + .ops = &clk_branch2_ops, 1047 + }, 1048 + }, 1049 + }; 1050 + 1051 + static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { 1052 + .halt_reg = 0x8070, 1053 + .halt_check = BRANCH_HALT, 1054 + .clkr = { 1055 + .enable_reg = 0x8070, 1056 + .enable_mask = BIT(0), 1057 + .hw.init = &(const struct clk_init_data) { 1058 + .name = "disp_cc_mdss_dptx1_crypto_clk", 1059 + .parent_hws = (const struct clk_hw*[]) { 1060 + &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1061 + }, 1062 + .num_parents = 1, 1063 + .flags = CLK_SET_RATE_PARENT, 1064 + .ops = &clk_branch2_ops, 1065 + }, 1066 + }, 1067 + }; 1068 + 1069 + static struct clk_branch disp_cc_mdss_dptx1_link_clk = { 1070 + .halt_reg = 0x8064, 1071 + .halt_check = BRANCH_HALT, 1072 + .clkr = { 1073 + .enable_reg = 0x8064, 1074 + .enable_mask = BIT(0), 1075 + .hw.init = &(const struct clk_init_data) { 1076 + .name = "disp_cc_mdss_dptx1_link_clk", 1077 + .parent_hws = (const struct clk_hw*[]) { 1078 + &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, 1079 + }, 1080 + .num_parents = 1, 1081 + .flags = CLK_SET_RATE_PARENT, 1082 + .ops = &clk_branch2_ops, 1083 + }, 1084 + }, 1085 + }; 1086 + 1087 + static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { 1088 + .halt_reg = 0x806c, 1089 + .halt_check = BRANCH_HALT, 1090 + .clkr = { 1091 + .enable_reg = 0x806c, 1092 + .enable_mask = BIT(0), 1093 + .hw.init = &(const struct clk_init_data) { 1094 + .name = "disp_cc_mdss_dptx1_link_intf_clk", 1095 + .parent_hws = (const struct clk_hw*[]) { 1096 + &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1097 + }, 1098 + .num_parents = 1, 1099 + .flags = CLK_SET_RATE_PARENT, 1100 + .ops = &clk_branch2_ops, 1101 + }, 1102 + }, 1103 + }; 1104 + 1105 + static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { 1106 + .halt_reg = 0x805c, 1107 + .halt_check = BRANCH_HALT, 1108 + .clkr = { 1109 + .enable_reg = 0x805c, 1110 + .enable_mask = BIT(0), 1111 + .hw.init = &(const struct clk_init_data) { 1112 + .name = "disp_cc_mdss_dptx1_pixel0_clk", 1113 + .parent_hws = (const struct clk_hw*[]) { 1114 + &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, 1115 + }, 1116 + .num_parents = 1, 1117 + .flags = CLK_SET_RATE_PARENT, 1118 + .ops = &clk_branch2_ops, 1119 + }, 1120 + }, 1121 + }; 1122 + 1123 + static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { 1124 + .halt_reg = 0x8060, 1125 + .halt_check = BRANCH_HALT, 1126 + .clkr = { 1127 + .enable_reg = 0x8060, 1128 + .enable_mask = BIT(0), 1129 + .hw.init = &(const struct clk_init_data) { 1130 + .name = "disp_cc_mdss_dptx1_pixel1_clk", 1131 + .parent_hws = (const struct clk_hw*[]) { 1132 + &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, 1133 + }, 1134 + .num_parents = 1, 1135 + .flags = CLK_SET_RATE_PARENT, 1136 + .ops = &clk_branch2_ops, 1137 + }, 1138 + }, 1139 + }; 1140 + 1141 + static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { 1142 + .halt_reg = 0x8068, 1143 + .halt_check = BRANCH_HALT, 1144 + .clkr = { 1145 + .enable_reg = 0x8068, 1146 + .enable_mask = BIT(0), 1147 + .hw.init = &(const struct clk_init_data) { 1148 + .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", 1149 + .parent_hws = (const struct clk_hw*[]) { 1150 + &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, 1151 + }, 1152 + .num_parents = 1, 1153 + .flags = CLK_SET_RATE_PARENT, 1154 + .ops = &clk_branch2_ops, 1155 + }, 1156 + }, 1157 + }; 1158 + 1159 + static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { 1160 + .halt_reg = 0x808c, 1161 + .halt_check = BRANCH_HALT, 1162 + .clkr = { 1163 + .enable_reg = 0x808c, 1164 + .enable_mask = BIT(0), 1165 + .hw.init = &(const struct clk_init_data) { 1166 + .name = "disp_cc_mdss_dptx2_aux_clk", 1167 + .parent_hws = (const struct clk_hw*[]) { 1168 + &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, 1169 + }, 1170 + .num_parents = 1, 1171 + .flags = CLK_SET_RATE_PARENT, 1172 + .ops = &clk_branch2_ops, 1173 + }, 1174 + }, 1175 + }; 1176 + 1177 + static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { 1178 + .halt_reg = 0x8088, 1179 + .halt_check = BRANCH_HALT, 1180 + .clkr = { 1181 + .enable_reg = 0x8088, 1182 + .enable_mask = BIT(0), 1183 + .hw.init = &(const struct clk_init_data) { 1184 + .name = "disp_cc_mdss_dptx2_crypto_clk", 1185 + .parent_hws = (const struct clk_hw*[]) { 1186 + &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1187 + }, 1188 + .num_parents = 1, 1189 + .flags = CLK_SET_RATE_PARENT, 1190 + .ops = &clk_branch2_ops, 1191 + }, 1192 + }, 1193 + }; 1194 + 1195 + static struct clk_branch disp_cc_mdss_dptx2_link_clk = { 1196 + .halt_reg = 0x8080, 1197 + .halt_check = BRANCH_HALT, 1198 + .clkr = { 1199 + .enable_reg = 0x8080, 1200 + .enable_mask = BIT(0), 1201 + .hw.init = &(const struct clk_init_data) { 1202 + .name = "disp_cc_mdss_dptx2_link_clk", 1203 + .parent_hws = (const struct clk_hw*[]) { 1204 + &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, 1205 + }, 1206 + .num_parents = 1, 1207 + .flags = CLK_SET_RATE_PARENT, 1208 + .ops = &clk_branch2_ops, 1209 + }, 1210 + }, 1211 + }; 1212 + 1213 + static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { 1214 + .halt_reg = 0x8084, 1215 + .halt_check = BRANCH_HALT, 1216 + .clkr = { 1217 + .enable_reg = 0x8084, 1218 + .enable_mask = BIT(0), 1219 + .hw.init = &(const struct clk_init_data) { 1220 + .name = "disp_cc_mdss_dptx2_link_intf_clk", 1221 + .parent_hws = (const struct clk_hw*[]) { 1222 + &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, 1223 + }, 1224 + .num_parents = 1, 1225 + .flags = CLK_SET_RATE_PARENT, 1226 + .ops = &clk_branch2_ops, 1227 + }, 1228 + }, 1229 + }; 1230 + 1231 + static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { 1232 + .halt_reg = 0x8078, 1233 + .halt_check = BRANCH_HALT, 1234 + .clkr = { 1235 + .enable_reg = 0x8078, 1236 + .enable_mask = BIT(0), 1237 + .hw.init = &(const struct clk_init_data) { 1238 + .name = "disp_cc_mdss_dptx2_pixel0_clk", 1239 + .parent_hws = (const struct clk_hw*[]) { 1240 + &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, 1241 + }, 1242 + .num_parents = 1, 1243 + .flags = CLK_SET_RATE_PARENT, 1244 + .ops = &clk_branch2_ops, 1245 + }, 1246 + }, 1247 + }; 1248 + 1249 + static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { 1250 + .halt_reg = 0x807c, 1251 + .halt_check = BRANCH_HALT, 1252 + .clkr = { 1253 + .enable_reg = 0x807c, 1254 + .enable_mask = BIT(0), 1255 + .hw.init = &(const struct clk_init_data) { 1256 + .name = "disp_cc_mdss_dptx2_pixel1_clk", 1257 + .parent_hws = (const struct clk_hw*[]) { 1258 + &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, 1259 + }, 1260 + .num_parents = 1, 1261 + .flags = CLK_SET_RATE_PARENT, 1262 + .ops = &clk_branch2_ops, 1263 + }, 1264 + }, 1265 + }; 1266 + 1267 + static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { 1268 + .halt_reg = 0x809c, 1269 + .halt_check = BRANCH_HALT, 1270 + .clkr = { 1271 + .enable_reg = 0x809c, 1272 + .enable_mask = BIT(0), 1273 + .hw.init = &(const struct clk_init_data) { 1274 + .name = "disp_cc_mdss_dptx3_aux_clk", 1275 + .parent_hws = (const struct clk_hw*[]) { 1276 + &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, 1277 + }, 1278 + .num_parents = 1, 1279 + .flags = CLK_SET_RATE_PARENT, 1280 + .ops = &clk_branch2_ops, 1281 + }, 1282 + }, 1283 + }; 1284 + 1285 + static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { 1286 + .halt_reg = 0x80a0, 1287 + .halt_check = BRANCH_HALT, 1288 + .clkr = { 1289 + .enable_reg = 0x80a0, 1290 + .enable_mask = BIT(0), 1291 + .hw.init = &(const struct clk_init_data) { 1292 + .name = "disp_cc_mdss_dptx3_crypto_clk", 1293 + .parent_hws = (const struct clk_hw*[]) { 1294 + &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1295 + }, 1296 + .num_parents = 1, 1297 + .flags = CLK_SET_RATE_PARENT, 1298 + .ops = &clk_branch2_ops, 1299 + }, 1300 + }, 1301 + }; 1302 + 1303 + static struct clk_branch disp_cc_mdss_dptx3_link_clk = { 1304 + .halt_reg = 0x8094, 1305 + .halt_check = BRANCH_HALT, 1306 + .clkr = { 1307 + .enable_reg = 0x8094, 1308 + .enable_mask = BIT(0), 1309 + .hw.init = &(const struct clk_init_data) { 1310 + .name = "disp_cc_mdss_dptx3_link_clk", 1311 + .parent_hws = (const struct clk_hw*[]) { 1312 + &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, 1313 + }, 1314 + .num_parents = 1, 1315 + .flags = CLK_SET_RATE_PARENT, 1316 + .ops = &clk_branch2_ops, 1317 + }, 1318 + }, 1319 + }; 1320 + 1321 + static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { 1322 + .halt_reg = 0x8098, 1323 + .halt_check = BRANCH_HALT, 1324 + .clkr = { 1325 + .enable_reg = 0x8098, 1326 + .enable_mask = BIT(0), 1327 + .hw.init = &(const struct clk_init_data) { 1328 + .name = "disp_cc_mdss_dptx3_link_intf_clk", 1329 + .parent_hws = (const struct clk_hw*[]) { 1330 + &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, 1331 + }, 1332 + .num_parents = 1, 1333 + .flags = CLK_SET_RATE_PARENT, 1334 + .ops = &clk_branch2_ops, 1335 + }, 1336 + }, 1337 + }; 1338 + 1339 + static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { 1340 + .halt_reg = 0x8090, 1341 + .halt_check = BRANCH_HALT, 1342 + .clkr = { 1343 + .enable_reg = 0x8090, 1344 + .enable_mask = BIT(0), 1345 + .hw.init = &(const struct clk_init_data) { 1346 + .name = "disp_cc_mdss_dptx3_pixel0_clk", 1347 + .parent_hws = (const struct clk_hw*[]) { 1348 + &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, 1349 + }, 1350 + .num_parents = 1, 1351 + .flags = CLK_SET_RATE_PARENT, 1352 + .ops = &clk_branch2_ops, 1353 + }, 1354 + }, 1355 + }; 1356 + 1357 + static struct clk_branch disp_cc_mdss_esc0_clk = { 1358 + .halt_reg = 0x8038, 1359 + .halt_check = BRANCH_HALT, 1360 + .clkr = { 1361 + .enable_reg = 0x8038, 1362 + .enable_mask = BIT(0), 1363 + .hw.init = &(const struct clk_init_data) { 1364 + .name = "disp_cc_mdss_esc0_clk", 1365 + .parent_hws = (const struct clk_hw*[]) { 1366 + &disp_cc_mdss_esc0_clk_src.clkr.hw, 1367 + }, 1368 + .num_parents = 1, 1369 + .flags = CLK_SET_RATE_PARENT, 1370 + .ops = &clk_branch2_ops, 1371 + }, 1372 + }, 1373 + }; 1374 + 1375 + static struct clk_branch disp_cc_mdss_esc1_clk = { 1376 + .halt_reg = 0x803c, 1377 + .halt_check = BRANCH_HALT, 1378 + .clkr = { 1379 + .enable_reg = 0x803c, 1380 + .enable_mask = BIT(0), 1381 + .hw.init = &(const struct clk_init_data) { 1382 + .name = "disp_cc_mdss_esc1_clk", 1383 + .parent_hws = (const struct clk_hw*[]) { 1384 + &disp_cc_mdss_esc1_clk_src.clkr.hw, 1385 + }, 1386 + .num_parents = 1, 1387 + .flags = CLK_SET_RATE_PARENT, 1388 + .ops = &clk_branch2_ops, 1389 + }, 1390 + }, 1391 + }; 1392 + 1393 + static struct clk_branch disp_cc_mdss_mdp1_clk = { 1394 + .halt_reg = 0xa004, 1395 + .halt_check = BRANCH_HALT, 1396 + .clkr = { 1397 + .enable_reg = 0xa004, 1398 + .enable_mask = BIT(0), 1399 + .hw.init = &(const struct clk_init_data) { 1400 + .name = "disp_cc_mdss_mdp1_clk", 1401 + .parent_hws = (const struct clk_hw*[]) { 1402 + &disp_cc_mdss_mdp_clk_src.clkr.hw, 1403 + }, 1404 + .num_parents = 1, 1405 + .flags = CLK_SET_RATE_PARENT, 1406 + .ops = &clk_branch2_ops, 1407 + }, 1408 + }, 1409 + }; 1410 + 1411 + static struct clk_branch disp_cc_mdss_mdp_clk = { 1412 + .halt_reg = 0x800c, 1413 + .halt_check = BRANCH_HALT, 1414 + .clkr = { 1415 + .enable_reg = 0x800c, 1416 + .enable_mask = BIT(0), 1417 + .hw.init = &(const struct clk_init_data) { 1418 + .name = "disp_cc_mdss_mdp_clk", 1419 + .parent_hws = (const struct clk_hw*[]) { 1420 + &disp_cc_mdss_mdp_clk_src.clkr.hw, 1421 + }, 1422 + .num_parents = 1, 1423 + .flags = CLK_SET_RATE_PARENT, 1424 + .ops = &clk_branch2_ops, 1425 + }, 1426 + }, 1427 + }; 1428 + 1429 + static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { 1430 + .halt_reg = 0xa010, 1431 + .halt_check = BRANCH_HALT, 1432 + .clkr = { 1433 + .enable_reg = 0xa010, 1434 + .enable_mask = BIT(0), 1435 + .hw.init = &(const struct clk_init_data) { 1436 + .name = "disp_cc_mdss_mdp_lut1_clk", 1437 + .parent_hws = (const struct clk_hw*[]) { 1438 + &disp_cc_mdss_mdp_clk_src.clkr.hw, 1439 + }, 1440 + .num_parents = 1, 1441 + .flags = CLK_SET_RATE_PARENT, 1442 + .ops = &clk_branch2_ops, 1443 + }, 1444 + }, 1445 + }; 1446 + 1447 + static struct clk_branch disp_cc_mdss_mdp_lut_clk = { 1448 + .halt_reg = 0x8018, 1449 + .halt_check = BRANCH_HALT_VOTED, 1450 + .clkr = { 1451 + .enable_reg = 0x8018, 1452 + .enable_mask = BIT(0), 1453 + .hw.init = &(const struct clk_init_data) { 1454 + .name = "disp_cc_mdss_mdp_lut_clk", 1455 + .parent_hws = (const struct clk_hw*[]) { 1456 + &disp_cc_mdss_mdp_clk_src.clkr.hw, 1457 + }, 1458 + .num_parents = 1, 1459 + .flags = CLK_SET_RATE_PARENT, 1460 + .ops = &clk_branch2_ops, 1461 + }, 1462 + }, 1463 + }; 1464 + 1465 + static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { 1466 + .halt_reg = 0xc004, 1467 + .halt_check = BRANCH_HALT_VOTED, 1468 + .clkr = { 1469 + .enable_reg = 0xc004, 1470 + .enable_mask = BIT(0), 1471 + .hw.init = &(const struct clk_init_data) { 1472 + .name = "disp_cc_mdss_non_gdsc_ahb_clk", 1473 + .parent_hws = (const struct clk_hw*[]) { 1474 + &disp_cc_mdss_ahb_clk_src.clkr.hw, 1475 + }, 1476 + .num_parents = 1, 1477 + .flags = CLK_SET_RATE_PARENT, 1478 + .ops = &clk_branch2_ops, 1479 + }, 1480 + }, 1481 + }; 1482 + 1483 + static struct clk_branch disp_cc_mdss_pclk0_clk = { 1484 + .halt_reg = 0x8004, 1485 + .halt_check = BRANCH_HALT, 1486 + .clkr = { 1487 + .enable_reg = 0x8004, 1488 + .enable_mask = BIT(0), 1489 + .hw.init = &(const struct clk_init_data) { 1490 + .name = "disp_cc_mdss_pclk0_clk", 1491 + .parent_hws = (const struct clk_hw*[]) { 1492 + &disp_cc_mdss_pclk0_clk_src.clkr.hw, 1493 + }, 1494 + .num_parents = 1, 1495 + .flags = CLK_SET_RATE_PARENT, 1496 + .ops = &clk_branch2_ops, 1497 + }, 1498 + }, 1499 + }; 1500 + 1501 + static struct clk_branch disp_cc_mdss_pclk1_clk = { 1502 + .halt_reg = 0x8008, 1503 + .halt_check = BRANCH_HALT, 1504 + .clkr = { 1505 + .enable_reg = 0x8008, 1506 + .enable_mask = BIT(0), 1507 + .hw.init = &(const struct clk_init_data) { 1508 + .name = "disp_cc_mdss_pclk1_clk", 1509 + .parent_hws = (const struct clk_hw*[]) { 1510 + &disp_cc_mdss_pclk1_clk_src.clkr.hw, 1511 + }, 1512 + .num_parents = 1, 1513 + .flags = CLK_SET_RATE_PARENT, 1514 + .ops = &clk_branch2_ops, 1515 + }, 1516 + }, 1517 + }; 1518 + 1519 + static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { 1520 + .halt_reg = 0xc00c, 1521 + .halt_check = BRANCH_HALT, 1522 + .clkr = { 1523 + .enable_reg = 0xc00c, 1524 + .enable_mask = BIT(0), 1525 + .hw.init = &(const struct clk_init_data) { 1526 + .name = "disp_cc_mdss_rscc_ahb_clk", 1527 + .parent_hws = (const struct clk_hw*[]) { 1528 + &disp_cc_mdss_ahb_clk_src.clkr.hw, 1529 + }, 1530 + .num_parents = 1, 1531 + .flags = CLK_SET_RATE_PARENT, 1532 + .ops = &clk_branch2_ops, 1533 + }, 1534 + }, 1535 + }; 1536 + 1537 + static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { 1538 + .halt_reg = 0xc008, 1539 + .halt_check = BRANCH_HALT, 1540 + .clkr = { 1541 + .enable_reg = 0xc008, 1542 + .enable_mask = BIT(0), 1543 + .hw.init = &(const struct clk_init_data) { 1544 + .name = "disp_cc_mdss_rscc_vsync_clk", 1545 + .parent_hws = (const struct clk_hw*[]) { 1546 + &disp_cc_mdss_vsync_clk_src.clkr.hw, 1547 + }, 1548 + .num_parents = 1, 1549 + .flags = CLK_SET_RATE_PARENT, 1550 + .ops = &clk_branch2_ops, 1551 + }, 1552 + }, 1553 + }; 1554 + 1555 + static struct clk_branch disp_cc_mdss_vsync1_clk = { 1556 + .halt_reg = 0xa01c, 1557 + .halt_check = BRANCH_HALT, 1558 + .clkr = { 1559 + .enable_reg = 0xa01c, 1560 + .enable_mask = BIT(0), 1561 + .hw.init = &(const struct clk_init_data) { 1562 + .name = "disp_cc_mdss_vsync1_clk", 1563 + .parent_hws = (const struct clk_hw*[]) { 1564 + &disp_cc_mdss_vsync_clk_src.clkr.hw, 1565 + }, 1566 + .num_parents = 1, 1567 + .flags = CLK_SET_RATE_PARENT, 1568 + .ops = &clk_branch2_ops, 1569 + }, 1570 + }, 1571 + }; 1572 + 1573 + static struct clk_branch disp_cc_mdss_vsync_clk = { 1574 + .halt_reg = 0x8024, 1575 + .halt_check = BRANCH_HALT, 1576 + .clkr = { 1577 + .enable_reg = 0x8024, 1578 + .enable_mask = BIT(0), 1579 + .hw.init = &(const struct clk_init_data) { 1580 + .name = "disp_cc_mdss_vsync_clk", 1581 + .parent_hws = (const struct clk_hw*[]) { 1582 + &disp_cc_mdss_vsync_clk_src.clkr.hw, 1583 + }, 1584 + .num_parents = 1, 1585 + .flags = CLK_SET_RATE_PARENT, 1586 + .ops = &clk_branch2_ops, 1587 + }, 1588 + }, 1589 + }; 1590 + 1591 + static struct clk_branch disp_cc_sleep_clk = { 1592 + .halt_reg = 0xe074, 1593 + .halt_check = BRANCH_HALT, 1594 + .clkr = { 1595 + .enable_reg = 0xe074, 1596 + .enable_mask = BIT(0), 1597 + .hw.init = &(const struct clk_init_data) { 1598 + .name = "disp_cc_sleep_clk", 1599 + .parent_hws = (const struct clk_hw*[]) { 1600 + &disp_cc_sleep_clk_src.clkr.hw, 1601 + }, 1602 + .num_parents = 1, 1603 + .flags = CLK_SET_RATE_PARENT, 1604 + .ops = &clk_branch2_ops, 1605 + }, 1606 + }, 1607 + }; 1608 + 1609 + static struct gdsc mdss_gdsc = { 1610 + .gdscr = 0x9000, 1611 + .pd = { 1612 + .name = "mdss_gdsc", 1613 + }, 1614 + .pwrsts = PWRSTS_OFF_ON, 1615 + .flags = HW_CTRL | RETAIN_FF_ENABLE, 1616 + }; 1617 + 1618 + static struct gdsc mdss_int2_gdsc = { 1619 + .gdscr = 0xb000, 1620 + .pd = { 1621 + .name = "mdss_int2_gdsc", 1622 + }, 1623 + .pwrsts = PWRSTS_OFF_ON, 1624 + .flags = HW_CTRL | RETAIN_FF_ENABLE, 1625 + }; 1626 + 1627 + static struct clk_regmap *disp_cc_sm8650_clocks[] = { 1628 + [DISP_CC_MDSS_ACCU_CLK] = &disp_cc_mdss_accu_clk.clkr, 1629 + [DISP_CC_MDSS_AHB1_CLK] = &disp_cc_mdss_ahb1_clk.clkr, 1630 + [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr, 1631 + [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr, 1632 + [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr, 1633 + [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr, 1634 + [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr, 1635 + [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr, 1636 + [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr, 1637 + [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr, 1638 + [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, 1639 + [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, 1640 + [DISP_CC_MDSS_DPTX0_AUX_CLK] = &disp_cc_mdss_dptx0_aux_clk.clkr, 1641 + [DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &disp_cc_mdss_dptx0_aux_clk_src.clkr, 1642 + [DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &disp_cc_mdss_dptx0_crypto_clk.clkr, 1643 + [DISP_CC_MDSS_DPTX0_LINK_CLK] = &disp_cc_mdss_dptx0_link_clk.clkr, 1644 + [DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &disp_cc_mdss_dptx0_link_clk_src.clkr, 1645 + [DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx0_link_div_clk_src.clkr, 1646 + [DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &disp_cc_mdss_dptx0_link_intf_clk.clkr, 1647 + [DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &disp_cc_mdss_dptx0_pixel0_clk.clkr, 1648 + [DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx0_pixel0_clk_src.clkr, 1649 + [DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &disp_cc_mdss_dptx0_pixel1_clk.clkr, 1650 + [DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx0_pixel1_clk_src.clkr, 1651 + [DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] = 1652 + &disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr, 1653 + [DISP_CC_MDSS_DPTX1_AUX_CLK] = &disp_cc_mdss_dptx1_aux_clk.clkr, 1654 + [DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &disp_cc_mdss_dptx1_aux_clk_src.clkr, 1655 + [DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &disp_cc_mdss_dptx1_crypto_clk.clkr, 1656 + [DISP_CC_MDSS_DPTX1_LINK_CLK] = &disp_cc_mdss_dptx1_link_clk.clkr, 1657 + [DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &disp_cc_mdss_dptx1_link_clk_src.clkr, 1658 + [DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx1_link_div_clk_src.clkr, 1659 + [DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &disp_cc_mdss_dptx1_link_intf_clk.clkr, 1660 + [DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &disp_cc_mdss_dptx1_pixel0_clk.clkr, 1661 + [DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx1_pixel0_clk_src.clkr, 1662 + [DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &disp_cc_mdss_dptx1_pixel1_clk.clkr, 1663 + [DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx1_pixel1_clk_src.clkr, 1664 + [DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] = 1665 + &disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr, 1666 + [DISP_CC_MDSS_DPTX2_AUX_CLK] = &disp_cc_mdss_dptx2_aux_clk.clkr, 1667 + [DISP_CC_MDSS_DPTX2_AUX_CLK_SRC] = &disp_cc_mdss_dptx2_aux_clk_src.clkr, 1668 + [DISP_CC_MDSS_DPTX2_CRYPTO_CLK] = &disp_cc_mdss_dptx2_crypto_clk.clkr, 1669 + [DISP_CC_MDSS_DPTX2_LINK_CLK] = &disp_cc_mdss_dptx2_link_clk.clkr, 1670 + [DISP_CC_MDSS_DPTX2_LINK_CLK_SRC] = &disp_cc_mdss_dptx2_link_clk_src.clkr, 1671 + [DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx2_link_div_clk_src.clkr, 1672 + [DISP_CC_MDSS_DPTX2_LINK_INTF_CLK] = &disp_cc_mdss_dptx2_link_intf_clk.clkr, 1673 + [DISP_CC_MDSS_DPTX2_PIXEL0_CLK] = &disp_cc_mdss_dptx2_pixel0_clk.clkr, 1674 + [DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx2_pixel0_clk_src.clkr, 1675 + [DISP_CC_MDSS_DPTX2_PIXEL1_CLK] = &disp_cc_mdss_dptx2_pixel1_clk.clkr, 1676 + [DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC] = &disp_cc_mdss_dptx2_pixel1_clk_src.clkr, 1677 + [DISP_CC_MDSS_DPTX3_AUX_CLK] = &disp_cc_mdss_dptx3_aux_clk.clkr, 1678 + [DISP_CC_MDSS_DPTX3_AUX_CLK_SRC] = &disp_cc_mdss_dptx3_aux_clk_src.clkr, 1679 + [DISP_CC_MDSS_DPTX3_CRYPTO_CLK] = &disp_cc_mdss_dptx3_crypto_clk.clkr, 1680 + [DISP_CC_MDSS_DPTX3_LINK_CLK] = &disp_cc_mdss_dptx3_link_clk.clkr, 1681 + [DISP_CC_MDSS_DPTX3_LINK_CLK_SRC] = &disp_cc_mdss_dptx3_link_clk_src.clkr, 1682 + [DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dptx3_link_div_clk_src.clkr, 1683 + [DISP_CC_MDSS_DPTX3_LINK_INTF_CLK] = &disp_cc_mdss_dptx3_link_intf_clk.clkr, 1684 + [DISP_CC_MDSS_DPTX3_PIXEL0_CLK] = &disp_cc_mdss_dptx3_pixel0_clk.clkr, 1685 + [DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC] = &disp_cc_mdss_dptx3_pixel0_clk_src.clkr, 1686 + [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, 1687 + [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, 1688 + [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, 1689 + [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr, 1690 + [DISP_CC_MDSS_MDP1_CLK] = &disp_cc_mdss_mdp1_clk.clkr, 1691 + [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr, 1692 + [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr, 1693 + [DISP_CC_MDSS_MDP_LUT1_CLK] = &disp_cc_mdss_mdp_lut1_clk.clkr, 1694 + [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr, 1695 + [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, 1696 + [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr, 1697 + [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr, 1698 + [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr, 1699 + [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr, 1700 + [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr, 1701 + [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr, 1702 + [DISP_CC_MDSS_VSYNC1_CLK] = &disp_cc_mdss_vsync1_clk.clkr, 1703 + [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr, 1704 + [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr, 1705 + [DISP_CC_PLL0] = &disp_cc_pll0.clkr, 1706 + [DISP_CC_PLL1] = &disp_cc_pll1.clkr, 1707 + [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr, 1708 + [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr, 1709 + [DISP_CC_XO_CLK_SRC] = &disp_cc_xo_clk_src.clkr, 1710 + }; 1711 + 1712 + static const struct qcom_reset_map disp_cc_sm8650_resets[] = { 1713 + [DISP_CC_MDSS_CORE_BCR] = { 0x8000 }, 1714 + [DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 }, 1715 + [DISP_CC_MDSS_RSCC_BCR] = { 0xc000 }, 1716 + }; 1717 + 1718 + static struct gdsc *disp_cc_sm8650_gdscs[] = { 1719 + [MDSS_GDSC] = &mdss_gdsc, 1720 + [MDSS_INT2_GDSC] = &mdss_int2_gdsc, 1721 + }; 1722 + 1723 + static const struct regmap_config disp_cc_sm8650_regmap_config = { 1724 + .reg_bits = 32, 1725 + .reg_stride = 4, 1726 + .val_bits = 32, 1727 + .max_register = 0x11008, 1728 + .fast_io = true, 1729 + }; 1730 + 1731 + static struct qcom_cc_desc disp_cc_sm8650_desc = { 1732 + .config = &disp_cc_sm8650_regmap_config, 1733 + .clks = disp_cc_sm8650_clocks, 1734 + .num_clks = ARRAY_SIZE(disp_cc_sm8650_clocks), 1735 + .resets = disp_cc_sm8650_resets, 1736 + .num_resets = ARRAY_SIZE(disp_cc_sm8650_resets), 1737 + .gdscs = disp_cc_sm8650_gdscs, 1738 + .num_gdscs = ARRAY_SIZE(disp_cc_sm8650_gdscs), 1739 + }; 1740 + 1741 + static const struct of_device_id disp_cc_sm8650_match_table[] = { 1742 + { .compatible = "qcom,sm8650-dispcc" }, 1743 + { } 1744 + }; 1745 + MODULE_DEVICE_TABLE(of, disp_cc_sm8650_match_table); 1746 + 1747 + static int disp_cc_sm8650_probe(struct platform_device *pdev) 1748 + { 1749 + struct regmap *regmap; 1750 + int ret; 1751 + 1752 + ret = devm_pm_runtime_enable(&pdev->dev); 1753 + if (ret) 1754 + return ret; 1755 + 1756 + ret = pm_runtime_resume_and_get(&pdev->dev); 1757 + if (ret) 1758 + return ret; 1759 + 1760 + regmap = qcom_cc_map(pdev, &disp_cc_sm8650_desc); 1761 + if (IS_ERR(regmap)) { 1762 + ret = PTR_ERR(regmap); 1763 + goto err_put_rpm; 1764 + } 1765 + 1766 + clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 1767 + clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); 1768 + 1769 + /* Enable clock gating for MDP clocks */ 1770 + regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1771 + 1772 + /* Keep clocks always enabled */ 1773 + regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); /* disp_cc_xo_clk */ 1774 + 1775 + ret = qcom_cc_really_probe(pdev, &disp_cc_sm8650_desc, regmap); 1776 + if (ret) 1777 + goto err_put_rpm; 1778 + 1779 + pm_runtime_put(&pdev->dev); 1780 + 1781 + return 0; 1782 + 1783 + err_put_rpm: 1784 + pm_runtime_put_sync(&pdev->dev); 1785 + 1786 + return ret; 1787 + } 1788 + 1789 + static struct platform_driver disp_cc_sm8650_driver = { 1790 + .probe = disp_cc_sm8650_probe, 1791 + .driver = { 1792 + .name = "disp_cc-sm8650", 1793 + .of_match_table = disp_cc_sm8650_match_table, 1794 + }, 1795 + }; 1796 + 1797 + static int __init disp_cc_sm8650_init(void) 1798 + { 1799 + return platform_driver_register(&disp_cc_sm8650_driver); 1800 + } 1801 + subsys_initcall(disp_cc_sm8650_init); 1802 + 1803 + static void __exit disp_cc_sm8650_exit(void) 1804 + { 1805 + platform_driver_unregister(&disp_cc_sm8650_driver); 1806 + } 1807 + module_exit(disp_cc_sm8650_exit); 1808 + 1809 + MODULE_DESCRIPTION("QTI DISPCC SM8650 Driver"); 1810 + MODULE_LICENSE("GPL");