+3 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

reviewed

··· 100 100 /** 101 101 * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter 102 102 * 103 103 + * @adev: amdgpu device pointer 103 104 * @mask: array in which the per-shader array disable masks will be stored 104 105 * @max_se: number of SEs 105 106 * @max_sh: number of SHs ··· 108 107 * The bitmask of CUs to be disabled in the shader array determined by se and 109 108 * sh is stored in mask[se * max_sh + sh]. 110 109 */ 111 111 - void amdgpu_gfx_parse_disable_cu(unsigned int *mask, unsigned int max_se, unsigned int max_sh) 110 110 + void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask, 111 111 + unsigned int max_se, unsigned int max_sh) 112 112 { 113 113 unsigned int se, sh, cu; 114 114 const char *p;

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

reviewed

··· 569 569 return (u32)((1ULL << bit_width) - 1); 570 570 } 571 571 572 572 - void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, 573 573 - unsigned max_sh); 572 572 + void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask, 573 573 + unsigned int max_se, unsigned int max_sh); 574 574 575 575 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id); 576 576

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

reviewed

··· 10114 10114 if (!adev || !cu_info) 10115 10115 return -EINVAL; 10116 10116 10117 10117 - amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 10117 10117 + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); 10118 10118 10119 10119 mutex_lock(&adev->grbm_idx_mutex); 10120 10120 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

reviewed

··· 7482 7482 if (!adev || !cu_info) 7483 7483 return -EINVAL; 7484 7484 7485 7485 - amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 7485 7485 + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2); 7486 7486 7487 7487 mutex_lock(&adev->grbm_idx_mutex); 7488 7488 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

reviewed

··· 5728 5728 if (!adev || !cu_info) 5729 5729 return -EINVAL; 5730 5730 5731 5731 - amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); 5731 5731 + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2); 5732 5732 5733 5733 mutex_lock(&adev->grbm_idx_mutex); 5734 5734 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

reviewed

··· 3933 3933 return -EINVAL; 3934 3934 } 3935 3935 3936 3936 - amdgpu_gfx_parse_disable_cu(disable_masks, 3936 3936 + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 3937 3937 adev->gfx.config.max_shader_engines, 3938 3938 adev->gfx.config.max_sh_per_se); 3939 3939

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

reviewed

··· 3555 3555 3556 3556 memset(cu_info, 0, sizeof(*cu_info)); 3557 3557 3558 3558 - amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 3558 3558 + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); 3559 3559 3560 3560 mutex_lock(&adev->grbm_idx_mutex); 3561 3561 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

reviewed

··· 5063 5063 5064 5064 memset(cu_info, 0, sizeof(*cu_info)); 5065 5065 5066 5066 - amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5066 5066 + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); 5067 5067 5068 5068 mutex_lock(&adev->grbm_idx_mutex); 5069 5069 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

reviewed

··· 7084 7084 else 7085 7085 ao_cu_num = adev->gfx.config.max_cu_per_sh; 7086 7086 7087 7087 - amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 7087 7087 + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); 7088 7088 7089 7089 mutex_lock(&adev->grbm_idx_mutex); 7090 7090 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

reviewed

··· 7762 7762 adev->gfx.config.max_sh_per_se > 16) 7763 7763 return -EINVAL; 7764 7764 7765 7765 - amdgpu_gfx_parse_disable_cu(disable_masks, 7765 7765 + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 7766 7766 adev->gfx.config.max_shader_engines, 7767 7767 adev->gfx.config.max_sh_per_se); 7768 7768

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

reviewed

··· 4903 4903 adev->gfx.config.max_sh_per_se > 16) 4904 4904 return -EINVAL; 4905 4905 4906 4906 - amdgpu_gfx_parse_disable_cu(disable_masks, 4906 4906 + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4907 4907 adev->gfx.config.max_shader_engines, 4908 4908 adev->gfx.config.max_sh_per_se); 4909 4909