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crypto: octeontx2 - disable DMA black hole on an DMA fault

When CPT_AF_DIAG[FLT_DIS] = 0 and a CPT engine access to
LLC/DRAM encounters a fault/poison, a rare case may result
in unpredictable data being delivered to a CPT engine.
So, this patch adds code to set FLT_DIS as a workaround.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Srujana Challa and committed by
Herbert Xu
9eef6e97 bd9305b0

+14
+13
drivers/crypto/marvell/octeontx2/otx2_cptpf_ucode.c
··· 1144 1144 struct otx2_cpt_engines engs[OTX2_CPT_MAX_ETYPES_PER_GRP] = { {0} }; 1145 1145 struct pci_dev *pdev = cptpf->pdev; 1146 1146 struct fw_info_t fw_info; 1147 + u64 reg_val; 1147 1148 int ret = 0; 1148 1149 1149 1150 mutex_lock(&eng_grps->lock); ··· 1245 1244 */ 1246 1245 otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTX_FLUSH_TIMER, 1247 1246 CTX_FLUSH_TIMER_CNT, BLKADDR_CPT0); 1247 + 1248 + /* 1249 + * Set CPT_AF_DIAG[FLT_DIS], as a workaround for HW errata, when 1250 + * CPT_AF_DIAG[FLT_DIS] = 0 and a CPT engine access to LLC/DRAM 1251 + * encounters a fault/poison, a rare case may result in 1252 + * unpredictable data being delivered to a CPT engine. 1253 + */ 1254 + otx2_cpt_read_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_DIAG, &reg_val, 1255 + BLKADDR_CPT0); 1256 + otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_DIAG, 1257 + reg_val | BIT_ULL(24), BLKADDR_CPT0); 1258 + 1248 1259 mutex_unlock(&eng_grps->lock); 1249 1260 return 0; 1250 1261
+1
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
··· 605 605 } else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) { 606 606 /* Registers that can be accessed from PF */ 607 607 switch (offset) { 608 + case CPT_AF_DIAG: 608 609 case CPT_AF_CTL: 609 610 case CPT_AF_PF_FUNC: 610 611 case CPT_AF_BLK_RST: