tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'char-misc-6.1-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc fixes from Greg KH:
"Some small driver fixes for 6.1-rc3. They include:

- iio driver bugfixes

- counter driver bugfixes

- coresight bugfixes, including a revert and then a second fix to get
it right.

All of these have been in linux-next with no reported problems"

* tag 'char-misc-6.1-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (21 commits)
misc: sgi-gru: use explicitly signed char
coresight: cti: Fix hang in cti_disable_hw()
Revert "coresight: cti: Fix hang in cti_disable_hw()"
counter: 104-quad-8: Fix race getting function mode and direction
counter: microchip-tcb-capture: Handle Signal1 read and Synapse
coresight: cti: Fix hang in cti_disable_hw()
coresight: Fix possible deadlock with lock dependency
counter: ti-ecap-capture: fix IS_ERR() vs NULL check
counter: Reduce DEFINE_COUNTER_ARRAY_POLARITY() to defining counter_array
iio: bmc150-accel-core: Fix unsafe buffer attributes
iio: adxl367: Fix unsafe buffer attributes
iio: adxl372: Fix unsafe buffer attributes
iio: at91-sama5d2_adc: Fix unsafe buffer attributes
iio: temperature: ltc2983: allocate iio channels once
tools: iio: iio_utils: fix digit calculation
iio: adc: stm32-adc: fix channel sampling time init
iio: adc: mcp3911: mask out device ID in debug prints
iio: adc: mcp3911: use correct id bits
iio: adc: mcp3911: return proper error code on failure to allocate trigger
iio: adc: mcp3911: fix sizeof() vs ARRAY_SIZE() bug
...

Linus Torvalds 9f127546 c4d25ce6

+175 -91
+42 -22
drivers/counter/104-quad-8.c
··· 232 232 COUNTER_FUNCTION_QUADRATURE_X4, 233 233 }; 234 234 235 + static int quad8_function_get(const struct quad8 *const priv, const size_t id, 236 + enum counter_function *const function) 237 + { 238 + if (!priv->quadrature_mode[id]) { 239 + *function = COUNTER_FUNCTION_PULSE_DIRECTION; 240 + return 0; 241 + } 242 + 243 + switch (priv->quadrature_scale[id]) { 244 + case 0: 245 + *function = COUNTER_FUNCTION_QUADRATURE_X1_A; 246 + return 0; 247 + case 1: 248 + *function = COUNTER_FUNCTION_QUADRATURE_X2_A; 249 + return 0; 250 + case 2: 251 + *function = COUNTER_FUNCTION_QUADRATURE_X4; 252 + return 0; 253 + default: 254 + /* should never reach this path */ 255 + return -EINVAL; 256 + } 257 + } 258 + 235 259 static int quad8_function_read(struct counter_device *counter, 236 260 struct counter_count *count, 237 261 enum counter_function *function) 238 262 { 239 263 struct quad8 *const priv = counter_priv(counter); 240 - const int id = count->id; 241 264 unsigned long irqflags; 265 + int retval; 242 266 243 267 spin_lock_irqsave(&priv->lock, irqflags); 244 268 245 - if (priv->quadrature_mode[id]) 246 - switch (priv->quadrature_scale[id]) { 247 - case 0: 248 - *function = COUNTER_FUNCTION_QUADRATURE_X1_A; 249 - break; 250 - case 1: 251 - *function = COUNTER_FUNCTION_QUADRATURE_X2_A; 252 - break; 253 - case 2: 254 - *function = COUNTER_FUNCTION_QUADRATURE_X4; 255 - break; 256 - } 257 - else 258 - *function = COUNTER_FUNCTION_PULSE_DIRECTION; 269 + retval = quad8_function_get(priv, count->id, function); 259 270 260 271 spin_unlock_irqrestore(&priv->lock, irqflags); 261 272 262 - return 0; 273 + return retval; 263 274 } 264 275 265 276 static int quad8_function_write(struct counter_device *counter, ··· 370 359 enum counter_synapse_action *action) 371 360 { 372 361 struct quad8 *const priv = counter_priv(counter); 362 + unsigned long irqflags; 373 363 int err; 374 364 enum counter_function function; 375 365 const size_t signal_a_id = count->synapses[0].signal->id; ··· 386 374 return 0; 387 375 } 388 376 389 - err = quad8_function_read(counter, count, &function); 390 - if (err) 377 + spin_lock_irqsave(&priv->lock, irqflags); 378 + 379 + /* Get Count function and direction atomically */ 380 + err = quad8_function_get(priv, count->id, &function); 381 + if (err) { 382 + spin_unlock_irqrestore(&priv->lock, irqflags); 391 383 return err; 384 + } 385 + err = quad8_direction_read(counter, count, &direction); 386 + if (err) { 387 + spin_unlock_irqrestore(&priv->lock, irqflags); 388 + return err; 389 + } 390 + 391 + spin_unlock_irqrestore(&priv->lock, irqflags); 392 392 393 393 /* Default action mode */ 394 394 *action = COUNTER_SYNAPSE_ACTION_NONE; ··· 413 389 return 0; 414 390 case COUNTER_FUNCTION_QUADRATURE_X1_A: 415 391 if (synapse->signal->id == signal_a_id) { 416 - err = quad8_direction_read(counter, count, &direction); 417 - if (err) 418 - return err; 419 - 420 392 if (direction == COUNTER_COUNT_DIRECTION_FORWARD) 421 393 *action = COUNTER_SYNAPSE_ACTION_RISING_EDGE; 422 394 else
+14 -4
drivers/counter/microchip-tcb-capture.c
··· 28 28 int qdec_mode; 29 29 int num_channels; 30 30 int channel[2]; 31 - bool trig_inverted; 32 31 }; 33 32 34 33 static const enum counter_function mchp_tc_count_functions[] = { ··· 152 153 153 154 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr); 154 155 155 - if (priv->trig_inverted) 156 + if (signal->id == 1) 156 157 sigstatus = (sr & ATMEL_TC_MTIOB); 157 158 else 158 159 sigstatus = (sr & ATMEL_TC_MTIOA); ··· 169 170 { 170 171 struct mchp_tc_data *const priv = counter_priv(counter); 171 172 u32 cmr; 173 + 174 + if (priv->qdec_mode) { 175 + *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES; 176 + return 0; 177 + } 178 + 179 + /* Only TIOA signal is evaluated in non-QDEC mode */ 180 + if (synapse->signal->id != 0) { 181 + *action = COUNTER_SYNAPSE_ACTION_NONE; 182 + return 0; 183 + } 172 184 173 185 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr); 174 186 ··· 209 199 struct mchp_tc_data *const priv = counter_priv(counter); 210 200 u32 edge = ATMEL_TC_ETRGEDG_NONE; 211 201 212 - /* QDEC mode is rising edge only */ 213 - if (priv->qdec_mode) 202 + /* QDEC mode is rising edge only; only TIOA handled in non-QDEC mode */ 203 + if (priv->qdec_mode || synapse->signal->id != 0) 214 204 return -EINVAL; 215 205 216 206 switch (action) {
+4 -3
drivers/counter/ti-ecap-capture.c
··· 377 377 COUNTER_SIGNAL_POLARITY_NEGATIVE, 378 378 }; 379 379 380 - static DEFINE_COUNTER_ARRAY_POLARITY(ecap_cnt_pol_array, ecap_cnt_pol_avail, ECAP_NB_CEVT); 380 + static DEFINE_COUNTER_AVAILABLE(ecap_cnt_pol_available, ecap_cnt_pol_avail); 381 + static DEFINE_COUNTER_ARRAY_POLARITY(ecap_cnt_pol_array, ecap_cnt_pol_available, ECAP_NB_CEVT); 381 382 382 383 static struct counter_comp ecap_cnt_signal_ext[] = { 383 384 COUNTER_COMP_ARRAY_POLARITY(ecap_cnt_pol_read, ecap_cnt_pol_write, ecap_cnt_pol_array), ··· 480 479 int ret; 481 480 482 481 counter_dev = devm_counter_alloc(dev, sizeof(*ecap_dev)); 483 - if (IS_ERR(counter_dev)) 484 - return PTR_ERR(counter_dev); 482 + if (!counter_dev) 483 + return -ENOMEM; 485 484 486 485 counter_dev->name = ECAP_DRV_NAME; 487 486 counter_dev->parent = dev;
+4 -3
drivers/hwtracing/coresight/coresight-core.c
··· 1687 1687 ret = coresight_fixup_device_conns(csdev); 1688 1688 if (!ret) 1689 1689 ret = coresight_fixup_orphan_conns(csdev); 1690 - if (!ret && cti_assoc_ops && cti_assoc_ops->add) 1691 - cti_assoc_ops->add(csdev); 1692 1690 1693 1691 out_unlock: 1694 1692 mutex_unlock(&coresight_mutex); 1695 1693 /* Success */ 1696 - if (!ret) 1694 + if (!ret) { 1695 + if (cti_assoc_ops && cti_assoc_ops->add) 1696 + cti_assoc_ops->add(csdev); 1697 1697 return csdev; 1698 + } 1698 1699 1699 1700 /* Unregister the device if needed */ 1700 1701 if (registered) {
+3 -7
drivers/hwtracing/coresight/coresight-cti-core.c
··· 90 90 static int cti_enable_hw(struct cti_drvdata *drvdata) 91 91 { 92 92 struct cti_config *config = &drvdata->config; 93 - struct device *dev = &drvdata->csdev->dev; 94 93 unsigned long flags; 95 94 int rc = 0; 96 95 97 - pm_runtime_get_sync(dev->parent); 98 96 spin_lock_irqsave(&drvdata->spinlock, flags); 99 97 100 98 /* no need to do anything if enabled or unpowered*/ ··· 117 119 /* cannot enable due to error */ 118 120 cti_err_not_enabled: 119 121 spin_unlock_irqrestore(&drvdata->spinlock, flags); 120 - pm_runtime_put(dev->parent); 121 122 return rc; 122 123 } 123 124 ··· 150 153 static int cti_disable_hw(struct cti_drvdata *drvdata) 151 154 { 152 155 struct cti_config *config = &drvdata->config; 153 - struct device *dev = &drvdata->csdev->dev; 154 156 struct coresight_device *csdev = drvdata->csdev; 155 157 156 158 spin_lock(&drvdata->spinlock); ··· 171 175 coresight_disclaim_device_unlocked(csdev); 172 176 CS_LOCK(drvdata->base); 173 177 spin_unlock(&drvdata->spinlock); 174 - pm_runtime_put(dev->parent); 175 178 return 0; 176 179 177 180 /* not disabled this call */ ··· 536 541 /* 537 542 * Search the cti list to add an associated CTI into the supplied CS device 538 543 * This will set the association if CTI declared before the CS device. 539 - * (called from coresight_register() with coresight_mutex locked). 544 + * (called from coresight_register() without coresight_mutex locked). 540 545 */ 541 546 static void cti_add_assoc_to_csdev(struct coresight_device *csdev) 542 547 { ··· 564 569 * if we found a matching csdev then update the ECT 565 570 * association pointer for the device with this CTI. 566 571 */ 567 - csdev->ect_dev = ect_item->csdev; 572 + coresight_set_assoc_ectdev_mutex(csdev->ect_dev, 573 + ect_item->csdev); 568 574 break; 569 575 } 570 576 }
+18 -5
drivers/iio/accel/adxl367.c
··· 1185 1185 return sysfs_emit(buf, "%d\n", fifo_watermark); 1186 1186 } 1187 1187 1188 - static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); 1189 - static IIO_CONST_ATTR(hwfifo_watermark_max, 1190 - __stringify(ADXL367_FIFO_MAX_WATERMARK)); 1188 + static ssize_t hwfifo_watermark_min_show(struct device *dev, 1189 + struct device_attribute *attr, 1190 + char *buf) 1191 + { 1192 + return sysfs_emit(buf, "%s\n", "1"); 1193 + } 1194 + 1195 + static ssize_t hwfifo_watermark_max_show(struct device *dev, 1196 + struct device_attribute *attr, 1197 + char *buf) 1198 + { 1199 + return sysfs_emit(buf, "%s\n", __stringify(ADXL367_FIFO_MAX_WATERMARK)); 1200 + } 1201 + 1202 + static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0); 1203 + static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0); 1191 1204 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 1192 1205 adxl367_get_fifo_watermark, NULL, 0); 1193 1206 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 1194 1207 adxl367_get_fifo_enabled, NULL, 0); 1195 1208 1196 1209 static const struct attribute *adxl367_fifo_attributes[] = { 1197 - &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 1198 - &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 1210 + &iio_dev_attr_hwfifo_watermark_min.dev_attr.attr, 1211 + &iio_dev_attr_hwfifo_watermark_max.dev_attr.attr, 1199 1212 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 1200 1213 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 1201 1214 NULL,
+18 -5
drivers/iio/accel/adxl372.c
··· 998 998 return sprintf(buf, "%d\n", st->watermark); 999 999 } 1000 1000 1001 - static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); 1002 - static IIO_CONST_ATTR(hwfifo_watermark_max, 1003 - __stringify(ADXL372_FIFO_SIZE)); 1001 + static ssize_t hwfifo_watermark_min_show(struct device *dev, 1002 + struct device_attribute *attr, 1003 + char *buf) 1004 + { 1005 + return sysfs_emit(buf, "%s\n", "1"); 1006 + } 1007 + 1008 + static ssize_t hwfifo_watermark_max_show(struct device *dev, 1009 + struct device_attribute *attr, 1010 + char *buf) 1011 + { 1012 + return sysfs_emit(buf, "%s\n", __stringify(ADXL372_FIFO_SIZE)); 1013 + } 1014 + 1015 + static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0); 1016 + static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0); 1004 1017 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 1005 1018 adxl372_get_fifo_watermark, NULL, 0); 1006 1019 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 1007 1020 adxl372_get_fifo_enabled, NULL, 0); 1008 1021 1009 1022 static const struct attribute *adxl372_fifo_attributes[] = { 1010 - &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 1011 - &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 1023 + &iio_dev_attr_hwfifo_watermark_min.dev_attr.attr, 1024 + &iio_dev_attr_hwfifo_watermark_max.dev_attr.attr, 1012 1025 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 1013 1026 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 1014 1027 NULL,
+18 -5
drivers/iio/accel/bmc150-accel-core.c
··· 925 925 { } 926 926 }; 927 927 928 - static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); 929 - static IIO_CONST_ATTR(hwfifo_watermark_max, 930 - __stringify(BMC150_ACCEL_FIFO_LENGTH)); 928 + static ssize_t hwfifo_watermark_min_show(struct device *dev, 929 + struct device_attribute *attr, 930 + char *buf) 931 + { 932 + return sysfs_emit(buf, "%s\n", "1"); 933 + } 934 + 935 + static ssize_t hwfifo_watermark_max_show(struct device *dev, 936 + struct device_attribute *attr, 937 + char *buf) 938 + { 939 + return sysfs_emit(buf, "%s\n", __stringify(BMC150_ACCEL_FIFO_LENGTH)); 940 + } 941 + 942 + static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0); 943 + static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0); 931 944 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO, 932 945 bmc150_accel_get_fifo_state, NULL, 0); 933 946 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO, 934 947 bmc150_accel_get_fifo_watermark, NULL, 0); 935 948 936 949 static const struct attribute *bmc150_accel_fifo_attributes[] = { 937 - &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 938 - &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 950 + &iio_dev_attr_hwfifo_watermark_min.dev_attr.attr, 951 + &iio_dev_attr_hwfifo_watermark_max.dev_attr.attr, 939 952 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 940 953 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 941 954 NULL,
+18 -5
drivers/iio/adc/at91-sama5d2_adc.c
··· 2193 2193 return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark); 2194 2194 } 2195 2195 2196 + static ssize_t hwfifo_watermark_min_show(struct device *dev, 2197 + struct device_attribute *attr, 2198 + char *buf) 2199 + { 2200 + return sysfs_emit(buf, "%s\n", "2"); 2201 + } 2202 + 2203 + static ssize_t hwfifo_watermark_max_show(struct device *dev, 2204 + struct device_attribute *attr, 2205 + char *buf) 2206 + { 2207 + return sysfs_emit(buf, "%s\n", AT91_HWFIFO_MAX_SIZE_STR); 2208 + } 2209 + 2196 2210 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 2197 2211 at91_adc_get_fifo_state, NULL, 0); 2198 2212 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 2199 2213 at91_adc_get_watermark, NULL, 0); 2200 - 2201 - static IIO_CONST_ATTR(hwfifo_watermark_min, "2"); 2202 - static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR); 2214 + static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0); 2215 + static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0); 2203 2216 2204 2217 static const struct attribute *at91_adc_fifo_attributes[] = { 2205 - &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 2206 - &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 2218 + &iio_dev_attr_hwfifo_watermark_min.dev_attr.attr, 2219 + &iio_dev_attr_hwfifo_watermark_max.dev_attr.attr, 2207 2220 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 2208 2221 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 2209 2222 NULL,
+7 -6
drivers/iio/adc/mcp3911.c
··· 55 55 /* Internal voltage reference in mV */ 56 56 #define MCP3911_INT_VREF_MV 1200 57 57 58 - #define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 5) | (1 << 0)) & 0xff) 59 - #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 5) | (0 << 0)) & 0xff) 58 + #define MCP3911_REG_READ(reg, id) ((((reg) << 1) | ((id) << 6) | (1 << 0)) & 0xff) 59 + #define MCP3911_REG_WRITE(reg, id) ((((reg) << 1) | ((id) << 6) | (0 << 0)) & 0xff) 60 + #define MCP3911_REG_MASK GENMASK(4, 1) 60 61 61 62 #define MCP3911_NUM_CHANNELS 2 62 63 ··· 90 89 91 90 be32_to_cpus(val); 92 91 *val >>= ((4 - len) * 8); 93 - dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%x\n", *val, 94 - reg >> 1); 92 + dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val, 93 + FIELD_GET(MCP3911_REG_MASK, reg)); 95 94 return ret; 96 95 } 97 96 ··· 249 248 break; 250 249 251 250 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 252 - for (int i = 0; i < sizeof(mcp3911_osr_table); i++) { 251 + for (int i = 0; i < ARRAY_SIZE(mcp3911_osr_table); i++) { 253 252 if (val == mcp3911_osr_table[i]) { 254 253 val = FIELD_PREP(MCP3911_CONFIG_OSR, i); 255 254 ret = mcp3911_update(adc, MCP3911_REG_CONFIG, MCP3911_CONFIG_OSR, ··· 497 496 indio_dev->name, 498 497 iio_device_id(indio_dev)); 499 498 if (!adc->trig) 500 - return PTR_ERR(adc->trig); 499 + return -ENOMEM; 501 500 502 501 adc->trig->ops = &mcp3911_trigger_ops; 503 502 iio_trigger_set_drvdata(adc->trig, adc);
+6 -5
drivers/iio/adc/stm32-adc.c
··· 2086 2086 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val, 2087 2087 vin[1], scan_index, differential); 2088 2088 2089 + val = 0; 2089 2090 ret = fwnode_property_read_u32(child, "st,min-sample-time-ns", &val); 2090 2091 /* st,min-sample-time-ns is optional */ 2091 - if (!ret) { 2092 - stm32_adc_smpr_init(adc, channels[scan_index].channel, val); 2093 - if (differential) 2094 - stm32_adc_smpr_init(adc, vin[1], val); 2095 - } else if (ret != -EINVAL) { 2092 + if (ret && ret != -EINVAL) { 2096 2093 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-ns property %d\n", 2097 2094 ret); 2098 2095 goto err; 2099 2096 } 2097 + 2098 + stm32_adc_smpr_init(adc, channels[scan_index].channel, val); 2099 + if (differential) 2100 + stm32_adc_smpr_init(adc, vin[1], val); 2100 2101 2101 2102 scan_index++; 2102 2103 }
+1 -1
drivers/iio/light/tsl2583.c
··· 858 858 TSL2583_POWER_OFF_DELAY_MS); 859 859 pm_runtime_use_autosuspend(&clientp->dev); 860 860 861 - ret = devm_iio_device_register(indio_dev->dev.parent, indio_dev); 861 + ret = iio_device_register(indio_dev); 862 862 if (ret) { 863 863 dev_err(&clientp->dev, "%s: iio registration failed\n", 864 864 __func__);
+6 -7
drivers/iio/temperature/ltc2983.c
··· 1385 1385 return ret; 1386 1386 } 1387 1387 1388 - st->iio_chan = devm_kzalloc(&st->spi->dev, 1389 - st->iio_channels * sizeof(*st->iio_chan), 1390 - GFP_KERNEL); 1391 - 1392 - if (!st->iio_chan) 1393 - return -ENOMEM; 1394 - 1395 1388 ret = regmap_update_bits(st->regmap, LTC2983_GLOBAL_CONFIG_REG, 1396 1389 LTC2983_NOTCH_FREQ_MASK, 1397 1390 LTC2983_NOTCH_FREQ(st->filter_notch_freq)); ··· 1506 1513 usleep_range(1000, 1200); 1507 1514 gpiod_set_value_cansleep(gpio, 0); 1508 1515 } 1516 + 1517 + st->iio_chan = devm_kzalloc(&spi->dev, 1518 + st->iio_channels * sizeof(*st->iio_chan), 1519 + GFP_KERNEL); 1520 + if (!st->iio_chan) 1521 + return -ENOMEM; 1509 1522 1510 1523 ret = ltc2983_setup(st, true); 1511 1524 if (ret)
+3 -3
drivers/misc/sgi-gru/grumain.c
··· 152 152 * Optionally, build an array of chars that contain the bit numbers allocated. 153 153 */ 154 154 static unsigned long reserve_resources(unsigned long *p, int n, int mmax, 155 - char *idx) 155 + signed char *idx) 156 156 { 157 157 unsigned long bits = 0; 158 158 int i; ··· 170 170 } 171 171 172 172 unsigned long gru_reserve_cb_resources(struct gru_state *gru, int cbr_au_count, 173 - char *cbmap) 173 + signed char *cbmap) 174 174 { 175 175 return reserve_resources(&gru->gs_cbr_map, cbr_au_count, GRU_CBR_AU, 176 176 cbmap); 177 177 } 178 178 179 179 unsigned long gru_reserve_ds_resources(struct gru_state *gru, int dsr_au_count, 180 - char *dsmap) 180 + signed char *dsmap) 181 181 { 182 182 return reserve_resources(&gru->gs_dsr_map, dsr_au_count, GRU_DSR_AU, 183 183 dsmap);
+7 -7
drivers/misc/sgi-gru/grutables.h
··· 351 351 pid_t ts_tgid_owner; /* task that is using the 352 352 context - for migration */ 353 353 short ts_user_blade_id;/* user selected blade */ 354 - char ts_user_chiplet_id;/* user selected chiplet */ 354 + signed char ts_user_chiplet_id;/* user selected chiplet */ 355 355 unsigned short ts_sizeavail; /* Pagesizes in use */ 356 356 int ts_tsid; /* thread that owns the 357 357 structure */ ··· 364 364 required for contest */ 365 365 unsigned char ts_cbr_au_count;/* Number of CBR resources 366 366 required for contest */ 367 - char ts_cch_req_slice;/* CCH packet slice */ 368 - char ts_blade; /* If >= 0, migrate context if 367 + signed char ts_cch_req_slice;/* CCH packet slice */ 368 + signed char ts_blade; /* If >= 0, migrate context if 369 369 ref from different blade */ 370 - char ts_force_cch_reload; 371 - char ts_cbr_idx[GRU_CBR_AU];/* CBR numbers of each 370 + signed char ts_force_cch_reload; 371 + signed char ts_cbr_idx[GRU_CBR_AU];/* CBR numbers of each 372 372 allocated CB */ 373 373 int ts_data_valid; /* Indicates if ts_gdata has 374 374 valid data */ ··· 643 643 int cbr_au_count, int dsr_au_count, 644 644 unsigned char tlb_preload_count, int options, int tsid); 645 645 extern unsigned long gru_reserve_cb_resources(struct gru_state *gru, 646 - int cbr_au_count, char *cbmap); 646 + int cbr_au_count, signed char *cbmap); 647 647 extern unsigned long gru_reserve_ds_resources(struct gru_state *gru, 648 - int dsr_au_count, char *dsmap); 648 + int dsr_au_count, signed char *dsmap); 649 649 extern vm_fault_t gru_fault(struct vm_fault *vmf); 650 650 extern struct gru_mm_struct *gru_register_mmu_notifier(void); 651 651 extern void gru_drop_mmu_notifier(struct gru_mm_struct *gms);
+2 -3
include/linux/counter.h
··· 542 542 #define DEFINE_COUNTER_ARRAY_CAPTURE(_name, _length) \ 543 543 DEFINE_COUNTER_ARRAY_U64(_name, _length) 544 544 545 - #define DEFINE_COUNTER_ARRAY_POLARITY(_name, _enums, _length) \ 546 - DEFINE_COUNTER_AVAILABLE(_name##_available, _enums); \ 545 + #define DEFINE_COUNTER_ARRAY_POLARITY(_name, _available, _length) \ 547 546 struct counter_array _name = { \ 548 547 .type = COUNTER_COMP_SIGNAL_POLARITY, \ 549 - .avail = &(_name##_available), \ 548 + .avail = &(_available), \ 550 549 .length = (_length), \ 551 550 } 552 551
+4
tools/iio/iio_utils.c
··· 547 547 { 548 548 int count = 0; 549 549 550 + /* It takes a digit to represent zero */ 551 + if (!num) 552 + return 1; 553 + 550 554 while (num != 0) { 551 555 num /= 10; 552 556 count++;