Merge tag 'x86_cpu_for_7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

+3 -1

Documentation/admin-guide/kernel-parameters.txt

··· 8398 8398 8399 8399 emulate Vsyscalls turn into traps and are emulated 8400 8400 reasonably safely. The vsyscall page is 8401 - readable. 8401 + readable. This disables the Linear 8402 + Address Space Separation (LASS) security 8403 + feature and makes the system less secure. 8402 8404 8403 8405 xonly [default] Vsyscalls turn into traps and are 8404 8406 emulated reasonably safely. The vsyscall

+56 -35

arch/x86/entry/vsyscall/vsyscall_64.c

··· 23 23 * soon be no new userspace code that will ever use a vsyscall. 24 24 * 25 25 * The code in this file emulates vsyscalls when notified of a page 26 - * fault to a vsyscall address. 26 + * fault or a general protection fault to a vsyscall address. 27 27 */ 28 28 29 29 #include <linux/kernel.h> ··· 61 61 vsyscall_mode = NONE; 62 62 else 63 63 return -EINVAL; 64 + 65 + if (cpu_feature_enabled(X86_FEATURE_LASS) && vsyscall_mode == EMULATE) { 66 + setup_clear_cpu_cap(X86_FEATURE_LASS); 67 + pr_warn_once("x86/cpu: Disabling LASS due to vsyscall=emulate\n"); 68 + } 64 69 65 70 return 0; 66 71 } ··· 116 111 } 117 112 } 118 113 119 - bool emulate_vsyscall(unsigned long error_code, 120 - struct pt_regs *regs, unsigned long address) 114 + static bool __emulate_vsyscall(struct pt_regs *regs, unsigned long address) 121 115 { 122 116 unsigned long caller; 123 117 int vsyscall_nr, syscall_nr, tmp; 124 118 long ret; 125 119 unsigned long orig_dx; 126 120 127 - /* Write faults or kernel-privilege faults never get fixed up. */ 128 - if ((error_code & (X86_PF_WRITE | X86_PF_USER)) != X86_PF_USER) 121 + /* Confirm that the fault happened in 64-bit user mode */ 122 + if (!user_64bit_mode(regs)) 129 123 return false; 130 - 131 - /* 132 - * Assume that faults at regs->ip are because of an 133 - * instruction fetch. Return early and avoid 134 - * emulation for faults during data accesses: 135 - */ 136 - if (address != regs->ip) { 137 - /* Failed vsyscall read */ 138 - if (vsyscall_mode == EMULATE) 139 - return false; 140 - 141 - /* 142 - * User code tried and failed to read the vsyscall page. 143 - */ 144 - warn_bad_vsyscall(KERN_INFO, regs, "vsyscall read attempt denied -- look up the vsyscall kernel parameter if you need a workaround"); 145 - return false; 146 - } 147 - 148 - /* 149 - * X86_PF_INSTR is only set when NX is supported. When 150 - * available, use it to double-check that the emulation code 151 - * is only being used for instruction fetches: 152 - */ 153 - if (cpu_feature_enabled(X86_FEATURE_NX)) 154 - WARN_ON_ONCE(!(error_code & X86_PF_INSTR)); 155 - 156 - /* 157 - * No point in checking CS -- the only way to get here is a user mode 158 - * trap to a high address, which means that we're in 64-bit user code. 159 - */ 160 124 161 125 if (vsyscall_mode == NONE) { 162 126 warn_bad_vsyscall(KERN_INFO, regs, ··· 252 278 sigsegv: 253 279 force_sig(SIGSEGV); 254 280 return true; 281 + } 282 + 283 + bool emulate_vsyscall_pf(unsigned long error_code, struct pt_regs *regs, 284 + unsigned long address) 285 + { 286 + /* Write faults or kernel-privilege faults never get fixed up. */ 287 + if ((error_code & (X86_PF_WRITE | X86_PF_USER)) != X86_PF_USER) 288 + return false; 289 + 290 + /* 291 + * Assume that faults at regs->ip are because of an instruction 292 + * fetch. Return early and avoid emulation for faults during 293 + * data accesses: 294 + */ 295 + if (address != regs->ip) { 296 + /* Failed vsyscall read */ 297 + if (vsyscall_mode == EMULATE) 298 + return false; 299 + 300 + /* User code tried and failed to read the vsyscall page. */ 301 + warn_bad_vsyscall(KERN_INFO, regs, 302 + "vsyscall read attempt denied -- look up the vsyscall kernel parameter if you need a workaround"); 303 + return false; 304 + } 305 + 306 + /* 307 + * X86_PF_INSTR is only set when NX is supported. When 308 + * available, use it to double-check that the emulation code 309 + * is only being used for instruction fetches: 310 + */ 311 + if (cpu_feature_enabled(X86_FEATURE_NX)) 312 + WARN_ON_ONCE(!(error_code & X86_PF_INSTR)); 313 + 314 + return __emulate_vsyscall(regs, address); 315 + } 316 + 317 + bool emulate_vsyscall_gp(struct pt_regs *regs) 318 + { 319 + /* Without LASS, vsyscall accesses are expected to generate a #PF */ 320 + if (!cpu_feature_enabled(X86_FEATURE_LASS)) 321 + return false; 322 + 323 + /* Emulate only if the RIP points to the vsyscall address */ 324 + if (!is_vsyscall_vaddr(regs->ip)) 325 + return false; 326 + 327 + return __emulate_vsyscall(regs, regs->ip); 255 328 } 256 329 257 330 /*

+9 -4

arch/x86/include/asm/vsyscall.h

··· 14 14 * Called on instruction fetch fault in vsyscall page. 15 15 * Returns true if handled. 16 16 */ 17 - extern bool emulate_vsyscall(unsigned long error_code, 18 - struct pt_regs *regs, unsigned long address); 17 + bool emulate_vsyscall_pf(unsigned long error_code, struct pt_regs *regs, unsigned long address); 18 + bool emulate_vsyscall_gp(struct pt_regs *regs); 19 19 #else 20 20 static inline void map_vsyscall(void) {} 21 - static inline bool emulate_vsyscall(unsigned long error_code, 22 - struct pt_regs *regs, unsigned long address) 21 + static inline bool emulate_vsyscall_pf(unsigned long error_code, 22 + struct pt_regs *regs, unsigned long address) 23 + { 24 + return false; 25 + } 26 + 27 + static inline bool emulate_vsyscall_gp(struct pt_regs *regs) 23 28 { 24 29 return false; 25 30 }

+18 -17

arch/x86/kernel/cpu/common.c

··· 409 409 cr4_clear_bits(X86_CR4_UMIP); 410 410 } 411 411 412 - static __always_inline void setup_lass(struct cpuinfo_x86 *c) 412 + static int enable_lass(unsigned int cpu) 413 + { 414 + cr4_set_bits(X86_CR4_LASS); 415 + 416 + return 0; 417 + } 418 + 419 + /* 420 + * Finalize features that need to be enabled just before entering 421 + * userspace. Note that this only runs on a single CPU. Use appropriate 422 + * callbacks if all the CPUs need to reflect the same change. 423 + */ 424 + static int cpu_finalize_pre_userspace(void) 413 425 { 414 426 if (!cpu_feature_enabled(X86_FEATURE_LASS)) 415 - return; 427 + return 0; 416 428 417 - /* 418 - * Legacy vsyscall page access causes a #GP when LASS is active. 419 - * Disable LASS because the #GP handler doesn't support vsyscall 420 - * emulation. 421 - * 422 - * Also disable LASS when running under EFI, as some runtime and 423 - * boot services rely on 1:1 mappings in the lower half. 424 - */ 425 - if (IS_ENABLED(CONFIG_X86_VSYSCALL_EMULATION) || 426 - IS_ENABLED(CONFIG_EFI)) { 427 - setup_clear_cpu_cap(X86_FEATURE_LASS); 428 - return; 429 - } 429 + /* Runs on all online CPUs and future CPUs that come online. */ 430 + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/lass:enable", enable_lass, NULL); 430 431 431 - cr4_set_bits(X86_CR4_LASS); 432 + return 0; 432 433 } 434 + late_initcall(cpu_finalize_pre_userspace); 433 435 434 436 /* These bits should not change their value after CPU init is finished. */ 435 437 static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | ··· 2063 2061 setup_smep(c); 2064 2062 setup_smap(c); 2065 2063 setup_umip(c); 2066 - setup_lass(c); 2067 2064 2068 2065 /* 2069 2066 * The vendor-specific functions might have changed features.

+7 -5

arch/x86/kernel/traps.c

··· 70 70 #include <asm/tdx.h> 71 71 #include <asm/cfi.h> 72 72 #include <asm/msr.h> 73 + #include <asm/vsyscall.h> 73 74 74 75 #ifdef CONFIG_X86_64 75 76 #include <asm/x86_init.h> ··· 922 921 923 922 cond_local_irq_enable(regs); 924 923 925 - if (static_cpu_has(X86_FEATURE_UMIP)) { 926 - if (user_mode(regs) && fixup_umip_exception(regs)) 927 - goto exit; 928 - } 929 - 930 924 if (v8086_mode(regs)) { 931 925 local_irq_enable(); 932 926 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); ··· 934 938 goto exit; 935 939 936 940 if (fixup_vdso_exception(regs, X86_TRAP_GP, error_code, 0)) 941 + goto exit; 942 + 943 + if (fixup_umip_exception(regs)) 944 + goto exit; 945 + 946 + if (emulate_vsyscall_gp(regs)) 937 947 goto exit; 938 948 939 949 gp_user_force_sig_segv(regs, X86_TRAP_GP, error_code, desc);

+3

arch/x86/kernel/umip.c

··· 354 354 void __user *uaddr; 355 355 struct insn insn; 356 356 357 + if (!cpu_feature_enabled(X86_FEATURE_UMIP)) 358 + return false; 359 + 357 360 if (!regs) 358 361 return false; 359 362

+1 -1

arch/x86/mm/fault.c

··· 1314 1314 * to consider the PF_PK bit. 1315 1315 */ 1316 1316 if (is_vsyscall_vaddr(address)) { 1317 - if (emulate_vsyscall(error_code, regs, address)) 1317 + if (emulate_vsyscall_pf(error_code, regs, address)) 1318 1318 return; 1319 1319 } 1320 1320 #endif

+35

arch/x86/platform/efi/efi_64.c

··· 55 55 */ 56 56 static u64 efi_va = EFI_VA_START; 57 57 static struct mm_struct *efi_prev_mm; 58 + static unsigned long efi_cr4_lass; 58 59 59 60 /* 60 61 * We need our own copy of the higher levels of the page tables ··· 444 443 unuse_temporary_mm(efi_prev_mm); 445 444 } 446 445 446 + /* 447 + * Toggle LASS to allow EFI to access any 1:1 mapped region in the lower 448 + * half. 449 + * 450 + * Disable LASS only after switching to EFI-mm, as userspace is not 451 + * mapped in it. Similar to EFI-mm, these rely on preemption being 452 + * disabled and the calls being serialized. 453 + */ 454 + 455 + static void efi_disable_lass(void) 456 + { 457 + if (!cpu_feature_enabled(X86_FEATURE_LASS)) 458 + return; 459 + 460 + lockdep_assert_preemption_disabled(); 461 + 462 + /* Save current CR4.LASS state */ 463 + efi_cr4_lass = cr4_read_shadow() & X86_CR4_LASS; 464 + cr4_clear_bits(efi_cr4_lass); 465 + } 466 + 467 + static void efi_enable_lass(void) 468 + { 469 + if (!cpu_feature_enabled(X86_FEATURE_LASS)) 470 + return; 471 + 472 + lockdep_assert_preemption_disabled(); 473 + 474 + /* Reprogram CR4.LASS only if it was set earlier */ 475 + cr4_set_bits(efi_cr4_lass); 476 + } 477 + 447 478 void arch_efi_call_virt_setup(void) 448 479 { 449 480 efi_sync_low_kernel_mappings(); 450 481 efi_fpu_begin(); 451 482 firmware_restrict_branch_speculation_start(); 452 483 efi_enter_mm(); 484 + efi_disable_lass(); 453 485 } 454 486 455 487 void arch_efi_call_virt_teardown(void) 456 488 { 489 + efi_enable_lass(); 457 490 efi_leave_mm(); 458 491 firmware_restrict_branch_speculation_end(); 459 492 efi_fpu_end();

+1 -1

sound/soc/intel/Kconfig

··· 95 95 96 96 config SND_SOC_INTEL_AVS 97 97 tristate "Intel AVS driver" 98 - depends on X86 || COMPILE_TEST 98 + depends on X86 99 99 depends on PCI 100 100 depends on COMMON_CLK 101 101 select ACPI_NHLT if ACPI

+26 -12

sound/soc/intel/avs/tgl.c

··· 7 7 // 8 8 9 9 #include <linux/pci.h> 10 + #include <asm/cpuid/api.h> 10 11 #include "avs.h" 11 12 #include "debug.h" 12 13 #include "messages.h" 13 - 14 - #define CPUID_TSC_LEAF 0x15 15 14 16 15 static int avs_tgl_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power) 17 16 { ··· 39 40 return avs_dsp_core_stall(adev, core_mask, stall); 40 41 } 41 42 43 + /* 44 + * Succeed if CPUID(0x15) is not available, or if the nominal core crystal clock 45 + * frequency cannot be enumerated from it. There is nothing to do in both cases. 46 + */ 47 + static int avs_tgl_set_xtal_freq(struct avs_dev *adev) 48 + { 49 + unsigned int freq; 50 + int ret; 51 + 52 + if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) 53 + return 0; 54 + 55 + freq = cpuid_ecx(CPUID_LEAF_TSC); 56 + if (freq) { 57 + ret = avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(freq), &freq); 58 + if (ret) 59 + return AVS_IPC_RET(ret); 60 + } 61 + 62 + return 0; 63 + } 64 + 42 65 static int avs_tgl_config_basefw(struct avs_dev *adev) 43 66 { 44 67 struct pci_dev *pci = adev->base.pci; 45 68 struct avs_bus_hwid hwid; 46 69 int ret; 47 - #ifdef CONFIG_X86 48 - unsigned int ecx; 49 70 50 - #include <asm/cpuid/api.h> 51 - ecx = cpuid_ecx(CPUID_TSC_LEAF); 52 - if (ecx) { 53 - ret = avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(ecx), &ecx); 54 - if (ret) 55 - return AVS_IPC_RET(ret); 56 - } 57 - #endif 71 + ret = avs_tgl_set_xtal_freq(adev); 72 + if (ret) 73 + return ret; 58 74 59 75 hwid.device = pci->device; 60 76 hwid.subsystem = pci->subsystem_vendor | (pci->subsystem_device << 16);

+342 -319

tools/arch/x86/kcpuid/cpuid.csv

··· 1 1 # SPDX-License-Identifier: CC0-1.0 2 - # Generator: x86-cpuid-db v2.4 2 + # Generator: x86-cpuid-db v3.0 3 3 4 4 # 5 5 # Auto-generated file. ··· 10 10 # LEAF, SUBLEAVES, reg, bits, short_name , long_description 11 11 12 12 # Leaf 0H 13 - # Maximum standard leaf number + CPU vendor string 13 + # Maximum standard leaf + CPU vendor string 14 14 15 - 0x0, 0, eax, 31:0, max_std_leaf , Highest standard CPUID leaf supported 15 + 0x0, 0, eax, 31:0, max_std_leaf , Highest standard CPUID leaf 16 16 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3 17 17 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11 18 18 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7 ··· 134 134 0x4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex function) 135 135 136 136 # Leaf 5H 137 - # MONITOR/MWAIT instructions enumeration 137 + # MONITOR/MWAIT instructions 138 138 139 139 0x5, 0, eax, 15:0, min_mon_size , Smallest monitor-line size, in bytes 140 140 0x5, 0, ebx, 15:0, max_mon_size , Largest monitor-line size, in bytes 141 - 0x5, 0, ecx, 0, mwait_ext , Enumeration of MONITOR/MWAIT extensions is supported 142 - 0x5, 0, ecx, 1, mwait_irq_break , Interrupts as a break-event for MWAIT is supported 143 - 0x5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states supported using MWAIT 144 - 0x5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states supported using MWAIT 145 - 0x5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states supported using MWAIT 146 - 0x5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states supported using MWAIT 147 - 0x5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states supported using MWAIT 148 - 0x5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states supported using MWAIT 149 - 0x5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states supported using MWAIT 150 - 0x5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states supported using MWAIT 141 + 0x5, 0, ecx, 0, mwait_ext , MONITOR/MWAIT extensions 142 + 0x5, 0, ecx, 1, mwait_irq_break , Interrupts as a break event for MWAIT 143 + 0x5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states 144 + 0x5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states 145 + 0x5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states 146 + 0x5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states 147 + 0x5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states 148 + 0x5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states 149 + 0x5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states 150 + 0x5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states 151 151 152 152 # Leaf 6H 153 - # Thermal and Power Management enumeration 153 + # Thermal and power management 154 154 155 155 0x6, 0, eax, 0, dtherm , Digital temperature sensor 156 156 0x6, 0, eax, 1, turbo_boost , Intel Turbo Boost ··· 158 158 0x6, 0, eax, 4, pln , Power Limit Notification (PLN) event 159 159 0x6, 0, eax, 5, ecmd , Clock modulation duty cycle extension 160 160 0x6, 0, eax, 6, pts , Package thermal management 161 - 0x6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers are supported 161 + 0x6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers 162 162 0x6, 0, eax, 8, hwp_notify , HWP notification (IA32_HWP_INTERRUPT MSR) 163 - 0x6, 0, eax, 9, hwp_act_window , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported 163 + 0x6, 0, eax, 9, hwp_act_window , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) 164 164 0x6, 0, eax, 10, hwp_epp , HWP Energy Performance Preference 165 165 0x6, 0, eax, 11, hwp_pkg_req , HWP Package Level Request 166 - 0x6, 0, eax, 13, hdc_base_regs , HDC base registers are supported 166 + 0x6, 0, eax, 13, hdc_base_regs , HDC base registers 167 167 0x6, 0, eax, 14, turbo_boost_3_0 , Intel Turbo Boost Max 3.0 168 168 0x6, 0, eax, 15, hwp_capabilities , HWP Highest Performance change 169 169 0x6, 0, eax, 16, hwp_peci_override , HWP PECI override 170 170 0x6, 0, eax, 17, hwp_flexible , Flexible HWP 171 171 0x6, 0, eax, 18, hwp_fast , IA32_HWP_REQUEST MSR fast access mode 172 - 0x6, 0, eax, 19, hfi , HW_FEEDBACK MSRs supported 173 - 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring idle logical CPU HWP req is supported 174 - 0x6, 0, eax, 23, thread_director , Intel thread director support 175 - 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25 is supported 172 + 0x6, 0, eax, 19, hfi , HW_FEEDBACK MSRs 173 + 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring idle logical CPU HWP request is supported 174 + 0x6, 0, eax, 22, hwp_ctl , IA32_HWP_CTL MSR 175 + 0x6, 0, eax, 23, thread_director , Intel thread director 176 + 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25 176 177 0x6, 0, ebx, 3:0, n_therm_thresholds , Digital thermometer thresholds 177 178 0x6, 0, ecx, 0, aperfmperf , MPERF/APERF MSRs (effective frequency interface) 178 - 0x6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR support 179 + 0x6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR 179 180 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number of classes, Intel thread director 180 181 0x6, 0, edx, 0, perfcap_reporting , Performance capability reporting 181 182 0x6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting ··· 184 183 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logical CPU hardware feedback interface index 185 184 186 185 # Leaf 7H 187 - # Extended CPU features enumeration 186 + # Extended CPU features 188 187 189 188 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number of leaf 0x7 subleaves 190 - 0x7, 0, ebx, 0, fsgsbase , FSBASE/GSBASE read/write support 191 - 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR supported 189 + 0x7, 0, ebx, 0, fsgsbase , FSBASE/GSBASE read/write 190 + 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR 192 191 0x7, 0, ebx, 2, sgx , Intel SGX (Software Guard Extensions) 193 192 0x7, 0, ebx, 3, bmi1 , Bit manipulation extensions group 1 194 193 0x7, 0, ebx, 4, hle , Hardware Lock Elision ··· 228 227 0x7, 0, ecx, 7, cet_ss , CET shadow stack features 229 228 0x7, 0, ecx, 8, gfni , Galois field new instructions 230 229 0x7, 0, ecx, 9, vaes , Vector AES instructions 231 - 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction support 230 + 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction 232 231 0x7, 0, ecx, 11, avx512_vnni , Vector neural network instructions 233 232 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 bitwise algorithms 234 233 0x7, 0, ecx, 13, tme , Intel total memory encryption ··· 236 235 0x7, 0, ecx, 16, la57 , 57-bit linear addresses (five-level paging) 237 236 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/BNDSTX MAWAU value in 64-bit mode 238 237 0x7, 0, ecx, 22, rdpid , RDPID instruction 239 - 0x7, 0, ecx, 23, key_locker , Intel key locker support 238 + 0x7, 0, ecx, 23, key_locker , Intel key locker 240 239 0x7, 0, ecx, 24, bus_lock_detect , OS bus-lock detection 241 240 0x7, 0, ecx, 25, cldemote , CLDEMOTE instruction 242 241 0x7, 0, ecx, 27, movdiri , MOVDIRI instruction 243 242 0x7, 0, ecx, 28, movdir64b , MOVDIR64B instruction 244 - 0x7, 0, ecx, 29, enqcmd , Enqueue stores supported (ENQCMD{,S}) 243 + 0x7, 0, ecx, 29, enqcmd , Enqueue stores (ENQCMD{,S}) 245 244 0x7, 0, ecx, 30, sgx_lc , Intel SGX launch configuration 246 245 0x7, 0, ecx, 31, pks , Protection keys for supervisor-mode pages 247 246 0x7, 0, edx, 1, sgx_keys , Intel SGX attestation services 248 247 0x7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions 249 248 0x7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single precision 250 249 0x7, 0, edx, 4, fsrm , Fast short REP MOV 251 - 0x7, 0, edx, 5, uintr , CPU supports user interrupts 250 + 0x7, 0, edx, 5, uintr , User interrupts 252 251 0x7, 0, edx, 8, avx512_vp2intersect , VP2INTERSECT{D,Q} instructions 253 - 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR available 254 - 0x7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode support 252 + 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR 253 + 0x7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode 255 254 0x7, 0, edx, 11, rtm_always_abort , XBEGIN (RTM transaction) always aborts 256 - 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported 255 + 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit 257 256 0x7, 0, edx, 14, serialize , SERIALIZE instruction 258 257 0x7, 0, edx, 15, hybrid_cpu , The CPU is identified as a 'hybrid part' 259 258 0x7, 0, edx, 16, tsxldtrk , TSX suspend/resume load address tracking 260 259 0x7, 0, edx, 18, pconfig , PCONFIG instruction 261 260 0x7, 0, edx, 19, arch_lbr , Intel architectural LBRs 262 261 0x7, 0, edx, 20, ibt , CET indirect branch tracking 263 - 0x7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 support 262 + 0x7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 264 263 0x7, 0, edx, 23, avx512_fp16 , AVX-512 FP16 instructions 265 - 0x7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture support 266 - 0x7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer support 264 + 0x7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture 265 + 0x7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer 267 266 0x7, 0, edx, 26, spec_ctrl , Speculation Control (IBRS/IBPB: indirect branch restrictions) 268 267 0x7, 0, edx, 27, intel_stibp , Single thread indirect branch predictors 269 268 0x7, 0, edx, 28, flush_l1d , FLUSH L1D cache: IA32_FLUSH_CMD MSR ··· 274 273 0x7, 1, eax, 5, avx512_bf16 , AVX-512 bfloat16 instructions 275 274 0x7, 1, eax, 6, lass , Linear address space separation 276 275 0x7, 1, eax, 7, cmpccxadd , CMPccXADD instructions 277 - 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerfmonExt: leaf 0x23 is supported 276 + 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerfmonExt: leaf 0x23 278 277 0x7, 1, eax, 10, fzrm , Fast zero-length REP MOVSB 279 278 0x7, 1, eax, 11, fsrs , Fast short REP STOSB 280 279 0x7, 1, eax, 12, fsrc , Fast Short REP CMPSB/SCASB ··· 283 282 0x7, 1, eax, 19, wrmsrns , WRMSRNS instruction (WRMSR-non-serializing) 284 283 0x7, 1, eax, 20, nmi_src , NMI-source reporting with FRED event data 285 284 0x7, 1, eax, 21, amx_fp16 , AMX-FP16: FP16 tile operations 286 - 0x7, 1, eax, 22, hreset , History reset support 285 + 0x7, 1, eax, 22, hreset , HRESET (Thread director history reset) 287 286 0x7, 1, eax, 23, avx_ifma , Integer fused multiply add 288 287 0x7, 1, eax, 26, lam , Linear address masking 289 288 0x7, 1, eax, 27, rd_wr_msrlist , RDMSRLIST/WRMSRLIST instructions ··· 299 298 0x7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U 300 299 0x7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S 301 300 0x7, 2, edx, 5, mcdt_no , MCDT mitigation not needed 302 - 0x7, 2, edx, 6, uclock_disable , UC-lock disable is supported 301 + 0x7, 2, edx, 6, uclock_disable , UC-lock disable 303 302 304 303 # Leaf 9H 305 - # Intel DCA (Direct Cache Access) enumeration 304 + # Intel DCA (Direct Cache Access) 306 305 307 306 0x9, 0, eax, 0, dca_enabled_in_bios , DCA is enabled in BIOS 308 307 309 308 # Leaf AH 310 - # Intel PMU (Performance Monitoring Unit) enumeration 309 + # Intel PMU (Performance Monitoring Unit) 311 310 312 311 0xa, 0, eax, 7:0, pmu_version , Performance monitoring unit version ID 313 - 0xa, 0, eax, 15:8, pmu_n_gcounters , Number of general PMU counters per logical CPU 314 - 0xa, 0, eax, 23:16, pmu_gcounters_nbits , Bitwidth of PMU general counters 315 - 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length of leaf 0xa EBX bit vector 316 - 0xa, 0, ebx, 0, no_core_cycle_evt , Core cycle event not available 317 - 0xa, 0, ebx, 1, no_insn_retired_evt , Instruction retired event not available 318 - 0xa, 0, ebx, 2, no_refcycle_evt , Reference cycles event not available 319 - 0xa, 0, ebx, 3, no_llc_ref_evt , LLC-reference event not available 320 - 0xa, 0, ebx, 4, no_llc_miss_evt , LLC-misses event not available 321 - 0xa, 0, ebx, 5, no_br_insn_ret_evt , Branch instruction retired event not available 322 - 0xa, 0, ebx, 6, no_br_mispredict_evt , Branch mispredict retired event not available 323 - 0xa, 0, ebx, 7, no_td_slots_evt , Topdown slots event not available 312 + 0xa, 0, eax, 15:8, num_counters_gp , Number of general-purpose PMU counters per logical CPU 313 + 0xa, 0, eax, 23:16, bit_width_gp , Bitwidth of PMU general-purpose counters 314 + 0xa, 0, eax, 31:24, events_mask_len , Length of CPUID(0xa).EBX bit vector 315 + 0xa, 0, ebx, 0, no_core_cycle , Core cycle event not available 316 + 0xa, 0, ebx, 1, no_instruction_retired , Instruction retired event not available 317 + 0xa, 0, ebx, 2, no_reference_cycles , Reference cycles event not available 318 + 0xa, 0, ebx, 3, no_llc_reference , LLC-reference event not available 319 + 0xa, 0, ebx, 4, no_llc_misses , LLC-misses event not available 320 + 0xa, 0, ebx, 5, no_br_insn_retired , Branch instruction retired event not available 321 + 0xa, 0, ebx, 6, no_br_misses_retired , Branch mispredict retired event not available 322 + 0xa, 0, ebx, 7, no_topdown_slots , Topdown slots event not available 323 + 0xa, 0, ebx, 8, no_backend_bound , Topdown backend bound not available 324 + 0xa, 0, ebx, 9, no_bad_speculation , Topdown bad speculation not available 325 + 0xa, 0, ebx, 10, no_frontend_bound , Topdown frontend bound not available 326 + 0xa, 0, ebx, 11, no_retiring , Topdown retiring not available 327 + 0xa, 0, ebx, 12, no_lbr_inserts , LBR inserts not available 324 328 0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-function PMU counters support bitmap 325 - 0xa, 0, edx, 4:0, pmu_n_fcounters , Number of fixed PMU counters 326 - 0xa, 0, edx, 12:5, pmu_fcounters_nbits , Bitwidth of PMU fixed counters 327 - 0xa, 0, edx, 15, anythread_depr , AnyThread deprecation 329 + 0xa, 0, edx, 4:0, num_counters_fixed , Number of fixed PMU counters 330 + 0xa, 0, edx, 12:5, bitwidth_fixed , Bitwidth of PMU fixed counters 331 + 0xa, 0, edx, 15, anythread_deprecation , AnyThread mode deprecation 328 332 329 333 # Leaf BH 330 - # CPUs v1 extended topology enumeration 334 + # CPU extended topology v1 331 335 332 336 0xb, 1:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive) 333 337 0xb, 1:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain ··· 341 335 0xb, 1:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU 342 336 343 337 # Leaf DH 344 - # Processor extended state enumeration 338 + # CPU extended state 345 339 346 - 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87 (bit 0) supported 347 - 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE (bit 1) supported 348 - 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX (bit 2) supported 349 - 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 registers) 350 - 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) 351 - 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 registers) 352 - 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) 353 - 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) 354 - 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKRU (bit 9) supported (XSAVE PKRU registers) 355 - 0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET_U (bit 11) supported (CET user state) 356 - 0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET_S (bit 12) supported (CET supervisor state) 357 - 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG) 358 - 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TILEDATA (bit 18) supported (AMX can manage TILEDATA) 359 - 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XRSTOR area byte size, for XCR0 enabled features 340 + 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87 341 + 0xd, 0, eax, 1, xcr0_sse , XCR0.SSE 342 + 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX 343 + 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS: MPX BND0-BND3 registers 344 + 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BNDCSR: MPX BNDCFGU/BNDSTATUS registers 345 + 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK: AVX-512 k0-k7 registers 346 + 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256: AVX-512 ZMM0->ZMM7/15 registers 347 + 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM: AVX-512 ZMM16->ZMM31 registers 348 + 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKRU: XSAVE PKRU registers 349 + 0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET_U: CET user state 350 + 0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET_S: CET supervisor state 351 + 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TILECONFIG: AMX can manage TILECONFIG 352 + 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TILEDATA: AMX can manage TILEDATA 353 + 0xd, 0, ebx, 31:0, xsave_sz_xcr0 , XSAVE/XRSTOR area byte size, for XCR0 enabled features 360 354 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XRSTOR area max byte size, all CPU features 361 - 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP (bit 62) supported (Light-weight Profiling) 355 + 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP: Light-weight Profiling 362 356 0xd, 1, eax, 0, xsaveopt , XSAVEOPT instruction 363 357 0xd, 1, eax, 1, xsavec , XSAVEC instruction 364 358 0xd, 1, eax, 2, xgetbv1 , XGETBV instruction with ECX = 1 365 359 0xd, 1, eax, 3, xsaves , XSAVES/XRSTORS instructions (and XSS MSR) 366 - 0xd, 1, eax, 4, xfd , Extended feature disable support 367 - 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xmms_enabled, XSAVE area size, all XCR0 and XMMS features enabled 368 - 0xd, 1, ecx, 8, xss_pt , PT state, supported 369 - 0xd, 1, ecx, 10, xss_pasid , PASID state, supported 370 - 0xd, 1, ecx, 11, xss_cet_u , CET user state, supported 371 - 0xd, 1, ecx, 12, xss_cet_p , CET supervisor state, supported 372 - 0xd, 1, ecx, 13, xss_hdc , HDC state, supported 373 - 0xd, 1, ecx, 14, xss_uintr , UINTR state, supported 374 - 0xd, 1, ecx, 15, xss_lbr , LBR state, supported 375 - 0xd, 1, ecx, 16, xss_hwp , HWP state, supported 376 - 0xd, 63:2, eax, 31:0, xsave_sz , Size of save area for subleaf-N feature, in bytes 377 - 0xd, 63:2, ebx, 31:0, xsave_offset , Offset of save area for subleaf-N feature, in bytes 378 - 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf N describes an XSS bit, otherwise XCR0 bit 379 - 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, When compacted, subleaf-N feature XSAVE area is 64-byte aligned 360 + 0xd, 1, eax, 4, xfd , Extended feature disable 361 + 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xss , XSAVES/XSAVEC area byte size, for XCR0|XSS enabled features 362 + 0xd, 1, ecx, 8, xss_pt , PT state 363 + 0xd, 1, ecx, 10, xss_pasid , PASID state 364 + 0xd, 1, ecx, 11, xss_cet_u , CET user state 365 + 0xd, 1, ecx, 12, xss_cet_p , CET supervisor state 366 + 0xd, 1, ecx, 13, xss_hdc , HDC state 367 + 0xd, 1, ecx, 14, xss_uintr , UINTR state 368 + 0xd, 1, ecx, 15, xss_lbr , LBR state 369 + 0xd, 1, ecx, 16, xss_hwp , HWP state 370 + 0xd, 63:2, eax, 31:0, xsave_sz , Subleaf-N feature save area size, in bytes 371 + 0xd, 63:2, ebx, 31:0, xsave_offset , Subleaf-N feature save area offset, in bytes 372 + 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf N describes an XSS bit (otherwise XCR0) 373 + 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, When compacted, subleaf-N XSAVE area is 64-byte aligned 380 374 381 375 # Leaf FH 382 376 # Intel RDT / AMD PQoS resource monitoring 383 377 384 - 0xf, 0, ebx, 31:0, core_rmid_max , RMID max, within this core, all types (0-based) 385 - 0xf, 0, edx, 1, cqm_llc , LLC QoS-monitoring supported 378 + 0xf, 0, ebx, 31:0, core_rmid_max , RMID max within this core (0-based) 379 + 0xf, 0, edx, 1, cqm_llc , LLC QoS-monitoring 386 380 0xf, 1, eax, 7:0, l3c_qm_bitwidth , L3 QoS-monitoring counter bitwidth (24-based) 387 381 0xf, 1, eax, 8, l3c_qm_overflow_bit , QM_CTR MSR bit 61 is an overflow bit 382 + 0xf, 1, eax, 9, io_rdt_cmt , non-CPU agent supporting Intel RDT CMT present 383 + 0xf, 1, eax, 10, io_rdt_mbm , non-CPU agent supporting Intel RDT MBM present 388 384 0xf, 1, ebx, 31:0, l3c_qm_conver_factor , QM_CTR MSR conversion factor to bytes 389 385 0xf, 1, ecx, 31:0, l3c_qm_rmid_max , L3 QoS-monitoring max RMID 390 - 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS occupancy monitoring supported 391 - 0xf, 1, edx, 1, cqm_mbm_total , L3 QoS total bandwidth monitoring supported 392 - 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS local bandwidth monitoring supported 386 + 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS occupancy monitoring 387 + 0xf, 1, edx, 1, cqm_mbm_total , L3 QoS total bandwidth monitoring 388 + 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS local bandwidth monitoring 393 389 394 390 # Leaf 10H 395 - # Intel RDT / AMD PQoS allocation enumeration 391 + # Intel RDT / AMD PQoS allocation 396 392 397 - 0x10, 0, ebx, 1, cat_l3 , L3 Cache Allocation Technology supported 398 - 0x10, 0, ebx, 2, cat_l2 , L2 Cache Allocation Technology supported 399 - 0x10, 0, ebx, 3, mba , Memory Bandwidth Allocation supported 393 + 0x10, 0, ebx, 1, cat_l3 , L3 Cache Allocation Technology 394 + 0x10, 0, ebx, 2, cat_l2 , L2 Cache Allocation Technology 395 + 0x10, 0, ebx, 3, mba , Memory Bandwidth Allocation 400 396 0x10, 2:1, eax, 4:0, cat_cbm_len , L3/L2_CAT capacity bitmask length, minus-one notation 401 - 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CAT bitmap of allocation units 397 + 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CAT allocation units bitmap 402 398 0x10, 2:1, ecx, 1, l3_cat_cos_infreq_updates, L3_CAT COS updates should be infrequent 403 - 0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CAT CDP (Code and Data Prioritization) 404 - 0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CAT non-contiguous 1s value supported 405 - 0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CAT max COS (Class of Service) supported 399 + 0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CAT Code and Data Prioritization 400 + 0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CAT non-contiguous 1s value 401 + 0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CAT max Class of Service 406 402 0x10, 3, eax, 11:0, mba_max_delay , Max MBA throttling value; minus-one notation 407 - 0x10, 3, ecx, 0, per_thread_mba , Per-thread MBA controls are supported 403 + 0x10, 3, ecx, 0, per_thread_mba , Per-thread MBA controls 408 404 0x10, 3, ecx, 2, mba_delay_linear , Delay values are linear 409 - 0x10, 3, edx, 15:0, mba_cos_max , MBA max Class of Service supported 405 + 0x10, 3, edx, 15:0, mba_cos_max , MBA max Class of Service 410 406 411 407 # Leaf 12H 412 - # Intel Software Guard Extensions (SGX) enumeration 408 + # Intel SGX (Software Guard Extensions) 413 409 414 - 0x12, 0, eax, 0, sgx1 , SGX1 leaf functions supported 415 - 0x12, 0, eax, 1, sgx2 , SGX2 leaf functions supported 416 - 0x12, 0, eax, 5, enclv_leaves , ENCLV leaves (E{INC,DEC}VIRTCHILD, ESETCONTEXT) supported 417 - 0x12, 0, eax, 6, encls_leaves , ENCLS leaves (ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC) supported 418 - 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU leaf EVERIFYREPORT2 supported 419 - 0x12, 0, eax, 10, encls_eupdatesvn , ENCLS leaf EUPDATESVN supported 420 - 0x12, 0, eax, 11, sgx_edeccssa , ENCLU leaf EDECCSSA supported 421 - 0x12, 0, ebx, 0, miscselect_exinfo , SSA.MISC frame: reporting #PF and #GP exceptions inside enclave supported 422 - 0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC frame: reporting #CP exceptions inside enclave supported 410 + 0x12, 0, eax, 0, sgx1 , SGX1 leaf functions 411 + 0x12, 0, eax, 1, sgx2 , SGX2 leaf functions 412 + 0x12, 0, eax, 5, enclv_leaves , ENCLV leaves 413 + 0x12, 0, eax, 6, encls_leaves , ENCLS leaves 414 + 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU leaf EVERIFYREPORT2 415 + 0x12, 0, eax, 10, encls_eupdatesvn , ENCLS leaf EUPDATESVN 416 + 0x12, 0, eax, 11, sgx_edeccssa , ENCLU leaf EDECCSSA 417 + 0x12, 0, ebx, 0, miscselect_exinfo , SSA.MISC frame: Enclave #PF and #GP reporting 418 + 0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC frame: Enclave #CP reporting 423 419 0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum enclave size in non-64-bit mode (log2) 424 420 0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum enclave size in 64-bit mode (log2) 425 - 0x12, 1, eax, 0, secs_attr_init , ATTRIBUTES.INIT supported (enclave initialized by EINIT) 426 - 0x12, 1, eax, 1, secs_attr_debug , ATTRIBUTES.DEBUG supported (enclave permits debugger read/write) 427 - 0x12, 1, eax, 2, secs_attr_mode64bit , ATTRIBUTES.MODE64BIT supported (enclave runs in 64-bit mode) 428 - 0x12, 1, eax, 4, secs_attr_provisionkey , ATTRIBUTES.PROVISIONKEY supported (provisioning key available) 429 - 0x12, 1, eax, 5, secs_attr_einittoken_key, ATTRIBUTES.EINITTOKEN_KEY supported (EINIT token key available) 430 - 0x12, 1, eax, 6, secs_attr_cet , ATTRIBUTES.CET supported (enable CET attributes) 431 - 0x12, 1, eax, 7, secs_attr_kss , ATTRIBUTES.KSS supported (Key Separation and Sharing enabled) 432 - 0x12, 1, eax, 10, secs_attr_aexnotify , ATTRIBUTES.AEXNOTIFY supported (enclave threads may get AEX notifications 433 - 0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87 (bit 0) supported 434 - 0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SEE (bit 1) supported 435 - 0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX (bit 2) supported 436 - 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 registers) 437 - 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) 438 - 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 registers) 439 - 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) 440 - 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) 441 - 0x12, 1, ecx, 9, xfrm_pkru , Enclave XFRM.PKRU (bit 9) supported (XSAVE PKRU registers) 442 - 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave XFRM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG) 443 - 0x12, 1, ecx, 18, xfrm_tiledata , Enclave XFRM.TILEDATA (bit 18) supported (AMX can manage TILEDATA) 444 - 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf type (dictates output layout) 421 + 0x12, 1, eax, 0, secs_attr_init , Enclave initialized by EINIT 422 + 0x12, 1, eax, 1, secs_attr_debug , Enclave permits debugger read/write 423 + 0x12, 1, eax, 2, secs_attr_mode64bit , Enclave runs in 64-bit mode 424 + 0x12, 1, eax, 4, secs_attr_provisionkey , Provisioning key 425 + 0x12, 1, eax, 5, secs_attr_einittoken_key, EINIT token key 426 + 0x12, 1, eax, 6, secs_attr_cet , CET attributes 427 + 0x12, 1, eax, 7, secs_attr_kss , Key Separation and Sharing 428 + 0x12, 1, eax, 10, secs_attr_aexnotify , Enclave threads: AEX notifications 429 + 0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87 430 + 0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SEE 431 + 0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX 432 + 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (MPX BND0-BND3 registers) 433 + 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (MPX BNDCFGU/BNDSTATUS registers) 434 + 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave XFRM.OPMASK (AVX-512 k0-k7 registers) 435 + 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave XFRM.ZMM_Hi256 (AVX-512 ZMM0->ZMM7/15 registers) 436 + 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave XFRM.HI16_ZMM (AVX-512 ZMM16->ZMM31 registers) 437 + 0x12, 1, ecx, 9, xfrm_pkru , Enclave XFRM.PKRU (XSAVE PKRU registers) 438 + 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave XFRM.TILECONFIG (AMX can manage TILECONFIG) 439 + 0x12, 1, ecx, 18, xfrm_tiledata , Enclave XFRM.TILEDATA (AMX can manage TILEDATA) 440 + 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf type 445 441 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC section base address, bits[12:31] 446 442 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC section base address, bits[32:51] 447 443 0x12, 31:2, ecx, 3:0, epc_sec_type , EPC section type / property encoding ··· 451 443 0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC section size, bits[32:51] 452 444 453 445 # Leaf 14H 454 - # Intel Processor Trace enumeration 446 + # Intel Processor Trace 455 447 456 448 0x14, 0, eax, 31:0, pt_max_subleaf , Maximum leaf 0x14 subleaf 457 449 0x14, 0, ebx, 0, cr3_filtering , IA32_RTIT_CR3_MATCH is accessible 458 450 0x14, 0, ebx, 1, psb_cyc , Configurable PSB and cycle-accurate mode 459 451 0x14, 0, ebx, 2, ip_filtering , IP/TraceStop filtering; Warm-reset PT MSRs preservation 460 452 0x14, 0, ebx, 3, mtc_timing , MTC timing packet; COFI-based packets suppression 461 - 0x14, 0, ebx, 4, ptwrite , PTWRITE support 462 - 0x14, 0, ebx, 5, power_event_trace , Power Event Trace support 463 - 0x14, 0, ebx, 6, psb_pmi_preserve , PSB and PMI preservation support 464 - 0x14, 0, ebx, 7, event_trace , Event Trace packet generation through IA32_RTIT_CTL.EventEn 465 - 0x14, 0, ebx, 8, tnt_disable , TNT packet generation disable through IA32_RTIT_CTL.DisTNT 466 - 0x14, 0, ecx, 0, topa_output , ToPA output scheme support 453 + 0x14, 0, ebx, 4, ptwrite , PTWRITE instruction 454 + 0x14, 0, ebx, 5, power_event_trace , Power Event Trace 455 + 0x14, 0, ebx, 6, psb_pmi_preserve , PSB and PMI preservation 456 + 0x14, 0, ebx, 7, event_trace , Event Trace packet generation 457 + 0x14, 0, ebx, 8, tnt_disable , TNT packet generation disable 458 + 0x14, 0, ecx, 0, topa_output , ToPA output scheme 467 459 0x14, 0, ecx, 1, topa_multiple_entries , ToPA tables can hold multiple entries 468 - 0x14, 0, ecx, 2, single_range_output , Single-range output scheme supported 469 - 0x14, 0, ecx, 3, trance_transport_output, Trace Transport subsystem output support 460 + 0x14, 0, ecx, 2, single_range_output , Single-range output 461 + 0x14, 0, ecx, 3, trance_transport_output, Trace Transport subsystem output 470 462 0x14, 0, ecx, 31, ip_payloads_lip , IP payloads have LIP values (CS base included) 471 - 0x14, 1, eax, 2:0, num_address_ranges , Filtering number of configurable Address Ranges 472 - 0x14, 1, eax, 31:16, mtc_periods_bmp , Bitmap of supported MTC period encodings 473 - 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Bitmap of supported Cycle Threshold encodings 474 - 0x14, 1, ebx, 31:16, psb_periods_bmp , Bitmap of supported Configurable PSB frequency encodings 463 + 0x14, 1, eax, 2:0, num_address_ranges , Number of configurable Address Ranges 464 + 0x14, 1, eax, 31:16, mtc_periods_bmp , MTC period encodings bitmap 465 + 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Cycle Threshold encodings bitmap 466 + 0x14, 1, ebx, 31:16, psb_periods_bmp , Configurable PSB frequency encodings bitmap 475 467 476 468 # Leaf 15H 477 - # Intel TSC (Time Stamp Counter) enumeration 469 + # Intel TSC (Time Stamp Counter) 478 470 479 471 0x15, 0, eax, 31:0, tsc_denominator , Denominator of the TSC/'core crystal clock' ratio 480 472 0x15, 0, ebx, 31:0, tsc_numerator , Numerator of the TSC/'core crystal clock' ratio 481 473 0x15, 0, ecx, 31:0, cpu_crystal_hz , Core crystal clock nominal frequency, in Hz 482 474 483 475 # Leaf 16H 484 - # Intel processor frequency enumeration 476 + # Intel processor frequency 485 477 486 478 0x16, 0, eax, 15:0, cpu_base_mhz , Processor base frequency, in MHz 487 479 0x16, 0, ebx, 15:0, cpu_max_mhz , Processor max frequency, in MHz 488 480 0x16, 0, ecx, 15:0, bus_mhz , Bus reference frequency, in MHz 489 481 490 482 # Leaf 17H 491 - # Intel SoC vendor attributes enumeration 483 + # Intel SoC vendor attributes 492 484 493 485 0x17, 0, eax, 31:0, soc_max_subleaf , Maximum leaf 0x17 subleaf 494 486 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vendor ID ··· 501 493 0x17, 3:1, edx, 31:0, vendor_brand_d , Vendor Brand ID string, bytes subleaf_nr * (12 -> 15) 502 494 503 495 # Leaf 18H 504 - # Intel determenestic address translation (TLB) parameters 496 + # Intel deterministic address translation (TLB) parameters 505 497 506 498 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Maximum leaf 0x18 subleaf 507 - 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-page entries supported 508 - 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-page entries supported 509 - 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-page entries supported 510 - 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-page entries supported 511 - 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/Soft) partitioning between logical CPUs sharing this structure 499 + 0x18, 31:0, ebx, 0, tlb_4k_page , TLB supports 4KB-page entries 500 + 0x18, 31:0, ebx, 1, tlb_2m_page , TLB supports 2MB-page entries 501 + 0x18, 31:0, ebx, 2, tlb_4m_page , TLB supports 4MB-page entries 502 + 0x18, 31:0, ebx, 3, tlb_1g_page , TLB supports 1GB-page entries 503 + 0x18, 31:0, ebx, 10:8, hard_partitioning , Partitioning between logical CPUs 512 504 0x18, 31:0, ebx, 31:16, n_way_associative , Ways of associativity 513 505 0x18, 31:0, ecx, 31:0, n_sets , Number of sets 514 506 0x18, 31:0, edx, 4:0, tlb_type , Translation cache type (TLB type) 515 507 0x18, 31:0, edx, 7:5, tlb_cache_level , Translation cache level (1-based) 516 - 0x18, 31:0, edx, 8, is_fully_associative , Fully-associative structure 517 - 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max number of addressable IDs for logical CPUs sharing this TLB - 1 508 + 0x18, 31:0, edx, 8, is_fully_associative , Fully-associative 509 + 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max number of addressable IDs - 1 518 510 519 511 # Leaf 19H 520 - # Intel Key Locker enumeration 512 + # Intel key locker 521 513 522 - 0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key Locker restriction supported 523 - 0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction supported 524 - 0x19, 0, eax, 2, kl_no_decrypt , No-decrypt key locker restriction supported 525 - 0x19, 0, ebx, 0, aes_keylocker , AES key locker instructions supported 526 - 0x19, 0, ebx, 2, aes_keylocker_wide , AES wide key locker instructions supported 527 - 0x19, 0, ebx, 4, kl_msr_iwkey , Key locker MSRs and IWKEY backups supported 528 - 0x19, 0, ecx, 0, loadiwkey_no_backup , LOADIWKEY NoBackup parameter supported 529 - 0x19, 0, ecx, 1, iwkey_rand , IWKEY randomization (KeySource encoding 1) supported 514 + 0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key Locker restriction 515 + 0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction 516 + 0x19, 0, eax, 2, kl_no_decrypt , No-decrypt key locker restriction 517 + 0x19, 0, ebx, 0, aes_keylocker , AES key locker instructions 518 + 0x19, 0, ebx, 2, aes_keylocker_wide , AES wide key locker instructions 519 + 0x19, 0, ebx, 4, kl_msr_iwkey , Key locker MSRs and IWKEY backups 520 + 0x19, 0, ecx, 0, loadiwkey_no_backup , LOADIWKEY NoBackup parameter 521 + 0x19, 0, ecx, 1, iwkey_rand , IWKEY randomization 530 522 531 523 # Leaf 1AH 532 524 # Intel hybrid CPUs identification (e.g. Atom, Core) ··· 535 527 0x1a, 0, eax, 31:24, core_type , This core's type 536 528 537 529 # Leaf 1BH 538 - # Intel PCONFIG (Platform configuration) enumeration 530 + # Intel PCONFIG (Platform configuration) 539 531 540 532 0x1b, 31:0, eax, 11:0, pconfig_subleaf_type , CPUID 0x1b subleaf type 541 533 0x1b, 31:0, ebx, 31:0, pconfig_target_id_x , A supported PCONFIG target ID ··· 543 535 0x1b, 31:0, edx, 31:0, pconfig_target_id_z , A supported PCONFIG target ID 544 536 545 537 # Leaf 1CH 546 - # Intel LBR (Last Branch Record) enumeration 538 + # Intel LBR (Last Branch Record) 547 539 548 - 0x1c, 0, eax, 0, lbr_depth_8 , Max stack depth (number of LBR entries) = 8 549 - 0x1c, 0, eax, 1, lbr_depth_16 , Max stack depth (number of LBR entries) = 16 550 - 0x1c, 0, eax, 2, lbr_depth_24 , Max stack depth (number of LBR entries) = 24 551 - 0x1c, 0, eax, 3, lbr_depth_32 , Max stack depth (number of LBR entries) = 32 552 - 0x1c, 0, eax, 4, lbr_depth_40 , Max stack depth (number of LBR entries) = 40 553 - 0x1c, 0, eax, 5, lbr_depth_48 , Max stack depth (number of LBR entries) = 48 554 - 0x1c, 0, eax, 6, lbr_depth_56 , Max stack depth (number of LBR entries) = 56 555 - 0x1c, 0, eax, 7, lbr_depth_64 , Max stack depth (number of LBR entries) = 64 540 + 0x1c, 0, eax, 7:0, lbr_depth_mask , Max LBR stack depth bitmask 556 541 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs maybe cleared on MWAIT C-state > C1 557 - 0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP contain Last IP, otherwise effective IP 558 - 0x1c, 0, ebx, 0, lbr_cpl , CPL filtering (non-zero IA32_LBR_CTL[2:1]) supported 559 - 0x1c, 0, ebx, 1, lbr_branch_filter , Branch filtering (non-zero IA32_LBR_CTL[22:16]) supported 560 - 0x1c, 0, ebx, 2, lbr_call_stack , Call-stack mode (IA32_LBR_CTL[3] = 1) supported 561 - 0x1c, 0, ecx, 0, lbr_mispredict , Branch misprediction bit supported (IA32_LBR_x_INFO[63]) 562 - 0x1c, 0, ecx, 1, lbr_timed_lbr , Timed LBRs (CPU cycles since last LBR entry) supported 563 - 0x1c, 0, ecx, 2, lbr_branch_type , Branch type field (IA32_LBR_INFO_x[59:56]) supported 564 - 0x1c, 0, ecx, 19:16, lbr_events_gpc_bmp , LBR PMU-events logging support; bitmap for first 4 GP (general-purpose) Counters 542 + 0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP contain Last IP (otherwise effective IP) 543 + 0x1c, 0, ebx, 0, lbr_cpl , CPL filtering 544 + 0x1c, 0, ebx, 1, lbr_branch_filter , Branch filtering 545 + 0x1c, 0, ebx, 2, lbr_call_stack , Call-stack mode 546 + 0x1c, 0, ecx, 0, lbr_mispredict , Branch misprediction bit 547 + 0x1c, 0, ecx, 1, lbr_timed_lbr , Timed LBRs (CPU cycles since last LBR entry) 548 + 0x1c, 0, ecx, 2, lbr_branch_type , Branch type field 549 + 0x1c, 0, ecx, 19:16, lbr_events_gpc_bmp , PMU-events logging support 565 550 566 551 # Leaf 1DH 567 552 # Intel AMX (Advanced Matrix Extensions) tile information ··· 567 566 0x1d, 1, ecx, 15:0, amx_tile_nr_rows , AMX tile max number of rows 568 567 569 568 # Leaf 1EH 570 - # Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration 569 + # Intel TMUL (Tile-matrix Multiply) 571 570 572 571 0x1e, 0, ebx, 7:0, tmul_maxk , TMUL unit maximum height, K (rows or columns) 573 572 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL unit maximum SIMD dimension, N (column bytes) 574 573 575 574 # Leaf 1FH 576 - # Intel extended topology enumeration v2 575 + # Intel extended topology v2 577 576 578 577 0x1f, 5:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive) 579 578 0x1f, 5:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain ··· 582 581 0x1f, 5:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU 583 582 584 583 # Leaf 20H 585 - # Intel HRESET (History Reset) enumeration 584 + # Intel HRESET (History Reset) 586 585 587 586 0x20, 0, eax, 31:0, hreset_nr_subleaves , CPUID 0x20 max subleaf + 1 588 - 0x20, 0, ebx, 0, hreset_thread_director , HRESET of Intel thread director is supported 587 + 0x20, 0, ebx, 0, hreset_thread_director , Intel thread director HRESET 589 588 590 589 # Leaf 21H 591 - # Intel TD (Trust Domain) guest execution environment enumeration 590 + # Intel TD (Trust Domain) 592 591 593 592 0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vendor ID string bytes 0 - 3 594 593 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vendor ID string bytes 8 - 11 ··· 597 596 # Leaf 23H 598 597 # Intel Architectural Performance Monitoring Extended (ArchPerfmonExt) 599 598 600 - 0x23, 0, eax, 1, subleaf_1_counters , Subleaf 1, PMU counters bitmaps, is valid 601 - 0x23, 0, eax, 3, subleaf_3_events , Subleaf 3, PMU events bitmaps, is valid 602 - 0x23, 0, ebx, 0, unitmask2 , IA32_PERFEVTSELx MSRs UnitMask2 is supported 603 - 0x23, 0, ebx, 1, zbit , IA32_PERFEVTSELx MSRs Z-bit is supported 604 - 0x23, 1, eax, 31:0, pmu_gp_counters_bitmap , General-purpose PMU counters bitmap 605 - 0x23, 1, ebx, 31:0, pmu_f_counters_bitmap , Fixed PMU counters bitmap 606 - 0x23, 3, eax, 0, core_cycles_evt , Core cycles event supported 607 - 0x23, 3, eax, 1, insn_retired_evt , Instructions retired event supported 608 - 0x23, 3, eax, 2, ref_cycles_evt , Reference cycles event supported 609 - 0x23, 3, eax, 3, llc_refs_evt , Last-level cache references event supported 610 - 0x23, 3, eax, 4, llc_misses_evt , Last-level cache misses event supported 611 - 0x23, 3, eax, 5, br_insn_ret_evt , Branch instruction retired event supported 612 - 0x23, 3, eax, 6, br_mispr_evt , Branch mispredict retired event supported 613 - 0x23, 3, eax, 7, td_slots_evt , Topdown slots event supported 614 - 0x23, 3, eax, 8, td_backend_bound_evt , Topdown backend bound event supported 615 - 0x23, 3, eax, 9, td_bad_spec_evt , Topdown bad speculation event supported 616 - 0x23, 3, eax, 10, td_frontend_bound_evt , Topdown frontend bound event supported 617 - 0x23, 3, eax, 11, td_retiring_evt , Topdown retiring event support 599 + 0x23, 0, eax, 0, subleaf_0 , Subleaf 0, this subleaf 600 + 0x23, 0, eax, 1, counters_subleaf , Subleaf 1, PMU counter bitmaps 601 + 0x23, 0, eax, 2, acr_subleaf , Subleaf 2, Auto Counter Reload bitmaps 602 + 0x23, 0, eax, 3, events_subleaf , Subleaf 3, PMU event bitmaps 603 + 0x23, 0, eax, 4, pebs_caps_subleaf , Subleaf 4, PEBS capabilities 604 + 0x23, 0, eax, 5, pebs_subleaf , Subleaf 5, Arch PEBS bitmaps 605 + 0x23, 0, ebx, 0, unitmask2 , IA32_PERFEVTSELx MSRs UnitMask2 bit 606 + 0x23, 0, ebx, 1, eq , IA32_PERFEVTSELx MSRs EQ bit 607 + 0x23, 0, ebx, 2, rdpmc_user_disable , RDPMC userspace disable 608 + 0x23, 1, eax, 31:0, gp_counters , Bitmap of general-purpose PMU counters 609 + 0x23, 1, ebx, 31:0, fixed_counters , Bitmap of fixed PMU counters 610 + 0x23, 2, eax, 31:0, acr_gp_reload , Bitmap of general-purpose counters that can be reloaded 611 + 0x23, 2, ebx, 31:0, acr_fixed_reload , Bitmap of fixed counters that can be reloaded 612 + 0x23, 2, ecx, 31:0, acr_gp_trigger , Bitmap of general-purpose counters that can trigger reloads 613 + 0x23, 2, edx, 31:0, acr_fixed_trigger , Bitmap of fixed counters that can trigger reloads 614 + 0x23, 3, eax, 0, core_cycles_evt , Core cycles event 615 + 0x23, 3, eax, 1, insn_retired_evt , Instructions retired event 616 + 0x23, 3, eax, 2, ref_cycles_evt , Reference cycles event 617 + 0x23, 3, eax, 3, llc_refs_evt , Last-level cache references event 618 + 0x23, 3, eax, 4, llc_misses_evt , Last-level cache misses event 619 + 0x23, 3, eax, 5, br_insn_ret_evt , Branch instruction retired event 620 + 0x23, 3, eax, 6, br_mispr_evt , Branch mispredict retired event 621 + 0x23, 3, eax, 7, td_slots_evt , Topdown slots event 622 + 0x23, 3, eax, 8, td_backend_bound_evt , Topdown backend bound event 623 + 0x23, 3, eax, 9, td_bad_spec_evt , Topdown bad speculation event 624 + 0x23, 3, eax, 10, td_frontend_bound_evt , Topdown frontend bound event 625 + 0x23, 3, eax, 11, td_retiring_evt , Topdown retiring event 626 + 0x23, 4, ebx, 3, allow_in_record , ALLOW_IN_RECORD bit in MSRs 627 + 0x23, 4, ebx, 4, counters_gp , Counters group sub-group general-purpose counters 628 + 0x23, 4, ebx, 5, counters_fixed , Counters group sub-group fixed-function counters 629 + 0x23, 4, ebx, 6, counters_metrics , Counters group sub-group performance metrics 630 + 0x23, 4, ebx, 9:8, lbr , LBR group 631 + 0x23, 4, ebx, 23:16, xer , XER group 632 + 0x23, 4, ebx, 29, gpr , GPR group 633 + 0x23, 4, ebx, 30, aux , AUX group 634 + 0x23, 5, eax, 31:0, pebs_gp , Architectural PEBS general-purpose counters 635 + 0x23, 5, ebx, 31:0, pebs_pdist_gp , Architectural PEBS PDIST general-purpose counters 636 + 0x23, 5, ecx, 31:0, pebs_fixed , Architectural PEBS fixed counters 637 + 0x23, 5, edx, 31:0, pebs_pdist_fixed , Architectural PEBS PDIST fixed counters 618 638 619 639 # Leaf 40000000H 620 - # Maximum hypervisor standard leaf + hypervisor vendor string 640 + # Maximum hypervisor leaf + hypervisor vendor string 621 641 622 - 0x40000000, 0, eax, 31:0, max_hyp_leaf , Maximum hypervisor standard leaf number 642 + 0x40000000, 0, eax, 31:0, max_hyp_leaf , Maximum hypervisor leaf 623 643 0x40000000, 0, ebx, 31:0, hypervisor_id_0 , Hypervisor ID string bytes 0 - 3 624 644 0x40000000, 0, ecx, 31:0, hypervisor_id_1 , Hypervisor ID string bytes 4 - 7 625 645 0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervisor ID string bytes 8 - 11 626 646 627 647 # Leaf 80000000H 628 - # Maximum extended leaf number + AMD/Transmeta CPU vendor string 648 + # Maximum extended leaf + CPU vendor string 629 649 630 - 0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum extended CPUID leaf supported 650 + 0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum extended CPUID leaf 631 651 0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor ID string bytes 0 - 3 632 652 0x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor ID string bytes 8 - 11 633 653 0x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor ID string bytes 4 - 7 634 654 635 655 # Leaf 80000001H 636 - # Extended CPU feature identifiers 656 + # Extended CPU features 637 657 638 658 0x80000001, 0, eax, 3:0, e_stepping_id , Stepping ID 639 659 0x80000001, 0, eax, 7:4, e_base_model , Base processor model ··· 745 723 0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU brand ID string, bytes 44 - 47 746 724 747 725 # Leaf 80000005H 748 - # AMD/Transmeta L1 cache and L1 TLB enumeration 726 + # AMD/Transmeta L1 cache and TLB 749 727 750 728 0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB #entries, 2M and 4M pages 751 729 0x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB associativity, 2M and 4M pages ··· 765 743 0x80000005, 0, edx, 31:24, l1_icache_size_kb , L1 icache size, in KB 766 744 767 745 # Leaf 80000006H 768 - # (Mostly AMD) L2 TLB, L2 cache, and L3 cache enumeration 746 + # (Mostly AMD) L2/L3 cache and TLB 769 747 770 748 0x80000006, 0, eax, 11:0, l2_itlb_2m_4m_nentries , L2 iTLB #entries, 2M and 4M pages 771 749 0x80000006, 0, eax, 15:12, l2_itlb_2m_4m_assoc , L2 iTLB associativity, 2M and 4M pages ··· 785 763 0x80000006, 0, edx, 31:18, l3_size_range , L3 cache size range 786 764 787 765 # Leaf 80000007H 788 - # CPU power management (mostly AMD) and AMD RAS enumeration 766 + # CPU power management (mostly AMD) and AMD RAS 789 767 790 768 0x80000007, 0, ebx, 0, overflow_recov , MCA overflow conditions not fatal 791 769 0x80000007, 0, ebx, 1, succor , Software containment of uncorrectable errors ··· 814 792 0x80000008, 0, eax, 7:0, phys_addr_bits , Max physical address bits 815 793 0x80000008, 0, eax, 15:8, virt_addr_bits , Max virtual address bits 816 794 0x80000008, 0, eax, 23:16, guest_phys_addr_bits , Max nested-paging guest physical address bits 817 - 0x80000008, 0, ebx, 0, clzero , CLZERO supported 795 + 0x80000008, 0, ebx, 0, clzero , CLZERO instruction 818 796 0x80000008, 0, ebx, 1, irperf , Instruction retired counter MSR 819 797 0x80000008, 0, ebx, 2, xsaveerptr , XSAVE/XRSTOR always saves/restores FPU error pointers 820 - 0x80000008, 0, ebx, 3, invlpgb , INVLPGB broadcasts a TLB invalidate to all threads 821 - 0x80000008, 0, ebx, 4, rdpru , RDPRU (Read Processor Register at User level) supported 798 + 0x80000008, 0, ebx, 3, invlpgb , INVLPGB broadcasts a TLB invalidate 799 + 0x80000008, 0, ebx, 4, rdpru , RDPRU (Read Processor Register at User level) 822 800 0x80000008, 0, ebx, 6, mba , Memory Bandwidth Allocation (AMD bit) 823 - 0x80000008, 0, ebx, 8, mcommit , MCOMMIT (Memory commit) supported 824 - 0x80000008, 0, ebx, 9, wbnoinvd , WBNOINVD supported 801 + 0x80000008, 0, ebx, 8, mcommit , MCOMMIT instruction 802 + 0x80000008, 0, ebx, 9, wbnoinvd , WBNOINVD instruction 825 803 0x80000008, 0, ebx, 12, amd_ibpb , Indirect Branch Prediction Barrier 826 804 0x80000008, 0, ebx, 13, wbinvd_int , Interruptible WBINVD/WBNOINVD 827 805 0x80000008, 0, ebx, 14, amd_ibrs , Indirect Branch Restricted Speculation ··· 830 808 0x80000008, 0, ebx, 17, amd_stibp_always_on , STIBP always-on preferred 831 809 0x80000008, 0, ebx, 18, ibrs_fast , IBRS is preferred over software solution 832 810 0x80000008, 0, ebx, 19, ibrs_same_mode , IBRS provides same mode protection 833 - 0x80000008, 0, ebx, 20, no_efer_lmsle , EFER[LMSLE] bit (Long-Mode Segment Limit Enable) unsupported 834 - 0x80000008, 0, ebx, 21, tlb_flush_nested , INVLPGB RAX[5] bit can be set (nested translations) 811 + 0x80000008, 0, ebx, 20, no_efer_lmsle , Long-Mode Segment Limit Enable unsupported 812 + 0x80000008, 0, ebx, 21, tlb_flush_nested , INVLPGB RAX[5] bit can be set 835 813 0x80000008, 0, ebx, 23, amd_ppin , Protected Processor Inventory Number 836 814 0x80000008, 0, ebx, 24, amd_ssbd , Speculative Store Bypass Disable 837 815 0x80000008, 0, ebx, 25, virt_ssbd , virtualized SSBD (Speculative Store Bypass Disable) ··· 840 818 0x80000008, 0, ebx, 28, amd_psfd , Predictive Store Forward Disable 841 819 0x80000008, 0, ebx, 29, btc_no , CPU not affected by Branch Type Confusion 842 820 0x80000008, 0, ebx, 30, ibpb_ret , IBPB clears RSB/RAS too 843 - 0x80000008, 0, ebx, 31, brs , Branch Sampling supported 821 + 0x80000008, 0, ebx, 31, brs , Branch Sampling 844 822 0x80000008, 0, ecx, 7:0, cpu_nthreads , Number of physical threads - 1 845 823 0x80000008, 0, ecx, 15:12, apicid_coreid_len , Number of thread core ID bits (shift) in APIC ID 846 824 0x80000008, 0, ecx, 17:16, perf_tsc_len , Performance time-stamp counter size ··· 848 826 0x80000008, 0, edx, 31:16, rdpru_max_reg_id , RDPRU max register ID (ECX input) 849 827 850 828 # Leaf 8000000AH 851 - # AMD SVM (Secure Virtual Machine) enumeration 829 + # AMD SVM (Secure Virtual Machine) 852 830 853 831 0x8000000a, 0, eax, 7:0, svm_version , SVM revision number 854 832 0x8000000a, 0, ebx, 31:0, svm_nasid , Number of address space identifiers (ASID) 833 + 0x8000000a, 0, ecx, 4, pml , Page Modification Logging (PML) 855 834 0x8000000a, 0, edx, 0, npt , Nested paging 856 835 0x8000000a, 0, edx, 1, lbrv , LBR virtualization 857 836 0x8000000a, 0, edx, 2, svm_lock , SVM lock ··· 879 856 0x8000000a, 0, edx, 28, svme_addr_chk , Guest SVME address check 880 857 881 858 # Leaf 80000019H 882 - # AMD TLB 1G-pages enumeration 859 + # AMD TLB characteristics for 1GB pages 883 860 884 861 0x80000019, 0, eax, 11:0, l1_itlb_1g_nentries , L1 iTLB #entries, 1G pages 885 862 0x80000019, 0, eax, 15:12, l1_itlb_1g_assoc , L1 iTLB associativity, 1G pages ··· 891 868 0x80000019, 0, ebx, 31:28, l2_dtlb_1g_assoc , L2 dTLB associativity, 1G pages 892 869 893 870 # Leaf 8000001AH 894 - # AMD instruction optimizations enumeration 871 + # AMD instruction optimizations 895 872 896 873 0x8000001a, 0, eax, 0, fp_128 , Internal FP/SIMD exec data path is 128-bits wide 897 874 0x8000001a, 0, eax, 1, movu_preferred , SSE: MOVU* better than MOVL*/MOVH* 898 875 0x8000001a, 0, eax, 2, fp_256 , internal FP/SSE exec data path is 256-bits wide 899 876 900 877 # Leaf 8000001BH 901 - # AMD IBS (Instruction-Based Sampling) enumeration 878 + # AMD IBS (Instruction-Based Sampling) 902 879 903 - 0x8000001b, 0, eax, 0, ibs_flags_valid , IBS feature flags valid 904 - 0x8000001b, 0, eax, 1, ibs_fetch_sampling , IBS fetch sampling supported 905 - 0x8000001b, 0, eax, 2, ibs_op_sampling , IBS execution sampling supported 906 - 0x8000001b, 0, eax, 3, ibs_rdwr_op_counter , IBS read/write of op counter supported 907 - 0x8000001b, 0, eax, 4, ibs_op_count , IBS OP counting mode supported 908 - 0x8000001b, 0, eax, 5, ibs_branch_target , IBS branch target address reporting supported 880 + 0x8000001b, 0, eax, 0, ibs_flags , IBS feature flags 881 + 0x8000001b, 0, eax, 1, ibs_fetch_sampling , IBS fetch sampling 882 + 0x8000001b, 0, eax, 2, ibs_op_sampling , IBS execution sampling 883 + 0x8000001b, 0, eax, 3, ibs_rdwr_op_counter , IBS read/write of op counter 884 + 0x8000001b, 0, eax, 4, ibs_op_count , IBS OP counting mode 885 + 0x8000001b, 0, eax, 5, ibs_branch_target , IBS branch target address reporting 909 886 0x8000001b, 0, eax, 6, ibs_op_counters_ext , IBS IbsOpCurCnt/IbsOpMaxCnt extend by 7 bits 910 - 0x8000001b, 0, eax, 7, ibs_rip_invalid_chk , IBS invalid RIP indication supported 911 - 0x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fused branch micro-op indication supported 912 - 0x8000001b, 0, eax, 9, ibs_fetch_ctl_ext , IBS Fetch Control Extended MSR (0xc001103c) supported 913 - 0x8000001b, 0, eax, 10, ibs_op_data_4 , IBS op data 4 MSR supported 914 - 0x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-miss filtering supported (Zen4+) 887 + 0x8000001b, 0, eax, 7, ibs_rip_invalid_chk , IBS invalid RIP indication 888 + 0x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fused branch micro-op indication 889 + 0x8000001b, 0, eax, 9, ibs_fetch_ctl_ext , IBS Fetch Control Extended MSR 890 + 0x8000001b, 0, eax, 10, ibs_op_data_4 , IBS op data 4 MSR 891 + 0x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-miss filtering (Zen4+) 915 892 916 893 # Leaf 8000001CH 917 894 # AMD LWP (Lightweight Profiling) 918 895 919 - 0x8000001c, 0, eax, 0, os_lwp_avail , LWP is available to application programs (supported by OS) 920 - 0x8000001c, 0, eax, 1, os_lpwval , LWPVAL instruction is supported by OS 921 - 0x8000001c, 0, eax, 2, os_lwp_ire , Instructions Retired Event is supported by OS 922 - 0x8000001c, 0, eax, 3, os_lwp_bre , Branch Retired Event is supported by OS 923 - 0x8000001c, 0, eax, 4, os_lwp_dme , Dcache Miss Event is supported by OS 924 - 0x8000001c, 0, eax, 5, os_lwp_cnh , CPU Clocks Not Halted event is supported by OS 925 - 0x8000001c, 0, eax, 6, os_lwp_rnh , CPU Reference clocks Not Halted event is supported by OS 926 - 0x8000001c, 0, eax, 29, os_lwp_cont , LWP sampling in continuous mode is supported by OS 927 - 0x8000001c, 0, eax, 30, os_lwp_ptsc , Performance Time Stamp Counter in event records is supported by OS 928 - 0x8000001c, 0, eax, 31, os_lwp_int , Interrupt on threshold overflow is supported by OS 929 - 0x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , LWP Control Block size, in quadwords 930 - 0x8000001c, 0, ebx, 15:8, lwp_event_sz , LWP event record size, in bytes 931 - 0x8000001c, 0, ebx, 23:16, lwp_max_events , LWP max supported EventID value (EventID 255 not included) 932 - 0x8000001c, 0, ebx, 31:24, lwp_event_offset , LWP events area offset in the LWP Control Block 933 - 0x8000001c, 0, ecx, 4:0, lwp_latency_max , Number of bits in cache latency counters (10 to 31) 934 - 0x8000001c, 0, ecx, 5, lwp_data_adddr , Cache miss events report the data address of the reference 935 - 0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Amount by which cache latency is rounded 936 - 0x8000001c, 0, ecx, 15:9, lwp_version , LWP implementation version 937 - 0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP event ring buffer min size, in units of 32 event records 896 + 0x8000001c, 0, eax, 0, os_lwp_avail , OS: LWP is available to application programs 897 + 0x8000001c, 0, eax, 1, os_lpwval , OS: LWPVAL instruction 898 + 0x8000001c, 0, eax, 2, os_lwp_ire , OS: Instructions Retired Event 899 + 0x8000001c, 0, eax, 3, os_lwp_bre , OS: Branch Retired Event 900 + 0x8000001c, 0, eax, 4, os_lwp_dme , OS: Dcache Miss Event 901 + 0x8000001c, 0, eax, 5, os_lwp_cnh , OS: CPU Clocks Not Halted event 902 + 0x8000001c, 0, eax, 6, os_lwp_rnh , OS: CPU Reference clocks Not Halted event 903 + 0x8000001c, 0, eax, 29, os_lwp_cont , OS: LWP sampling in continuous mode 904 + 0x8000001c, 0, eax, 30, os_lwp_ptsc , OS: Performance Time Stamp Counter in event records 905 + 0x8000001c, 0, eax, 31, os_lwp_int , OS: Interrupt on threshold overflow 906 + 0x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , Control Block size, in quadwords 907 + 0x8000001c, 0, ebx, 15:8, lwp_event_sz , Event record size, in bytes 908 + 0x8000001c, 0, ebx, 23:16, lwp_max_events , Max EventID supported 909 + 0x8000001c, 0, ebx, 31:24, lwp_event_offset , Control Block events area offset 910 + 0x8000001c, 0, ecx, 4:0, lwp_latency_max , Cache latency counters number of bits 911 + 0x8000001c, 0, ecx, 5, lwp_data_addr , Cache miss events report data cache address 912 + 0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Cache latency rounding amount 913 + 0x8000001c, 0, ecx, 15:9, lwp_version , LWP version 914 + 0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP event ring buffer min size, 32 event records units 938 915 0x8000001c, 0, ecx, 28, lwp_branch_predict , Branches Retired events can be filtered 939 - 0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filtering (IPI, IPF, BaseIP, and LimitIP @ LWPCP) supported 940 - 0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-related events can be filtered by cache level 941 - 0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-related events can be filtered by latency 942 - 0x8000001c, 0, edx, 0, hw_lwp_avail , LWP is available in hardware 943 - 0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL instruction is available in hardware 944 - 0x8000001c, 0, edx, 2, hw_lwp_ire , Instructions Retired Event is available in hardware 945 - 0x8000001c, 0, edx, 3, hw_lwp_bre , Branch Retired Event is available in hardware 946 - 0x8000001c, 0, edx, 4, hw_lwp_dme , Dcache Miss Event is available in hardware 947 - 0x8000001c, 0, edx, 5, hw_lwp_cnh , Clocks Not Halted event is available in hardware 948 - 0x8000001c, 0, edx, 6, hw_lwp_rnh , Reference clocks Not Halted event is available in hardware 949 - 0x8000001c, 0, edx, 29, hw_lwp_cont , LWP sampling in continuous mode is available in hardware 950 - 0x8000001c, 0, edx, 30, hw_lwp_ptsc , Performance Time Stamp Counter in event records is available in hardware 951 - 0x8000001c, 0, edx, 31, hw_lwp_int , Interrupt on threshold overflow is available in hardware 916 + 0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filtering (IPI, IPF, BaseIP, and LimitIP @ LWPCP) 917 + 0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-related events: filter by cache level 918 + 0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-related events: filter by latency 919 + 0x8000001c, 0, edx, 0, hw_lwp_avail , HW: LWP available 920 + 0x8000001c, 0, edx, 1, hw_lpwval , HW: LWPVAL available 921 + 0x8000001c, 0, edx, 2, hw_lwp_ire , HW: Instructions Retired Event 922 + 0x8000001c, 0, edx, 3, hw_lwp_bre , HW: Branch Retired Event 923 + 0x8000001c, 0, edx, 4, hw_lwp_dme , HW: Dcache Miss Event 924 + 0x8000001c, 0, edx, 5, hw_lwp_cnh , HW: Clocks Not Halted event 925 + 0x8000001c, 0, edx, 6, hw_lwp_rnh , HW: Reference clocks Not Halted event 926 + 0x8000001c, 0, edx, 29, hw_lwp_cont , HW: LWP sampling in continuous mode 927 + 0x8000001c, 0, edx, 30, hw_lwp_ptsc , HW: Performance Time Stamp Counter in event records 928 + 0x8000001c, 0, edx, 31, hw_lwp_int , HW: Interrupt on threshold overflow 952 929 953 930 # Leaf 8000001DH 954 931 # AMD deterministic cache parameters ··· 966 943 0x8000001d, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches 967 944 968 945 # Leaf 8000001EH 969 - # AMD CPU topology enumeration 946 + # AMD CPU topology 970 947 971 948 0x8000001e, 0, eax, 31:0, ext_apic_id , Extended APIC ID 972 949 0x8000001e, 0, ebx, 7:0, core_id , Unique per-socket logical core unit ID 973 - 0x8000001e, 0, ebx, 15:8, core_nthreas , #Threads per core (zero-based) 950 + 0x8000001e, 0, ebx, 15:8, core_nthreads , #Threads per core (zero-based) 974 951 0x8000001e, 0, ecx, 7:0, node_id , Node (die) ID of invoking logical CPU 975 952 0x8000001e, 0, ecx, 10:8, nnodes_per_socket , #nodes in invoking logical CPU's package/socket 976 953 977 954 # Leaf 8000001FH 978 - # AMD encrypted memory capabilities enumeration (SME/SEV) 955 + # AMD encrypted memory capabilities (SME/SEV) 979 956 980 - 0x8000001f, 0, eax, 0, sme , Secure Memory Encryption supported 981 - 0x8000001f, 0, eax, 1, sev , Secure Encrypted Virtualization supported 982 - 0x8000001f, 0, eax, 2, vm_page_flush , VM Page Flush MSR (0xc001011e) available 983 - 0x8000001f, 0, eax, 3, sev_es , SEV Encrypted State supported 984 - 0x8000001f, 0, eax, 4, sev_nested_paging , SEV secure nested paging supported 985 - 0x8000001f, 0, eax, 5, vm_permission_levels , VMPL supported 986 - 0x8000001f, 0, eax, 6, rpmquery , RPMQUERY instruction supported 987 - 0x8000001f, 0, eax, 7, vmpl_sss , VMPL supervisor shadow stack supported 988 - 0x8000001f, 0, eax, 8, secure_tsc , Secure TSC supported 957 + 0x8000001f, 0, eax, 0, sme , Secure Memory Encryption 958 + 0x8000001f, 0, eax, 1, sev , Secure Encrypted Virtualization 959 + 0x8000001f, 0, eax, 2, vm_page_flush , VM Page Flush MSR 960 + 0x8000001f, 0, eax, 3, sev_es , SEV Encrypted State 961 + 0x8000001f, 0, eax, 4, sev_nested_paging , SEV secure nested paging 962 + 0x8000001f, 0, eax, 5, vm_permission_levels , VMPL 963 + 0x8000001f, 0, eax, 6, rpmquery , RPMQUERY instruction 964 + 0x8000001f, 0, eax, 7, vmpl_sss , VMPL supervisor shadow stack 965 + 0x8000001f, 0, eax, 8, secure_tsc , Secure TSC 989 966 0x8000001f, 0, eax, 9, v_tsc_aux , Hardware virtualizes TSC_AUX 990 - 0x8000001f, 0, eax, 10, sme_coherent , Cache coherency is enforced across encryption domains 967 + 0x8000001f, 0, eax, 10, sme_coherent , Cache coherency enforcement across encryption domains 991 968 0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV guest mandates 64-bit hypervisor 992 969 0x8000001f, 0, eax, 12, restricted_injection , Restricted Injection supported 993 970 0x8000001f, 0, eax, 13, alternate_injection , Alternate Injection supported 994 - 0x8000001f, 0, eax, 14, debug_swap , SEV-ES: full debug state swap is supported 995 - 0x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: Disallowing IBS use by the host is supported 971 + 0x8000001f, 0, eax, 14, debug_swap , SEV-ES: Full debug state swap 972 + 0x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: Disallowing IBS use by the host 996 973 0x8000001f, 0, eax, 16, virt_transparent_enc , Virtual Transparent Encryption 997 - 0x8000001f, 0, eax, 17, vmgexit_paremeter , VmgexitParameter is supported in SEV_FEATURES 998 - 0x8000001f, 0, eax, 18, virt_tom_msr , Virtual TOM MSR is supported 999 - 0x8000001f, 0, eax, 19, virt_ibs , IBS state virtualization is supported for SEV-ES guests 1000 - 0x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA register protection is supported 1001 - 0x8000001f, 0, eax, 25, smt_protection , SMT protection is supported 1002 - 0x8000001f, 0, eax, 28, svsm_page_msr , SVSM communication page MSR (0xc001f000) is supported 1003 - 0x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMPUPDATE/VIRT_PSMASH MSRs are supported 1004 - 0x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit number used to enable memory encryption 1005 - 0x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reduction of phys address space when encryption is enabled, in bits 1006 - 0x8000001f, 0, ebx, 15:12, vmpl_count , Number of VM permission levels (VMPL) supported 1007 - 0x8000001f, 0, ecx, 31:0, enc_guests_max , Max supported number of simultaneous encrypted guests 974 + 0x8000001f, 0, eax, 17, vmgexit_parameter , SEV_FEATURES: VmgexitParameter 975 + 0x8000001f, 0, eax, 18, virt_tom_msr , Virtual TOM MSR 976 + 0x8000001f, 0, eax, 19, virt_ibs , SEV-ES guests: IBS state virtualization 977 + 0x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA register protection 978 + 0x8000001f, 0, eax, 25, smt_protection , SMT protection 979 + 0x8000001f, 0, eax, 28, svsm_page_msr , SVSM communication page MSR 980 + 0x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMPUPDATE/VIRT_PSMASH MSRs 981 + 0x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit number to enable memory encryption 982 + 0x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reduction of phys address space in bits 983 + 0x8000001f, 0, ebx, 15:12, vmpl_count , Number of VM permission levels (VMPL) 984 + 0x8000001f, 0, ecx, 31:0, enc_guests_max , Max number of simultaneous encrypted guests 1008 985 0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Minimum ASID for SEV-enabled SEV-ES-disabled guest 1009 986 1010 987 # Leaf 80000020H 1011 - # AMD Platform QoS extended feature IDs 988 + # AMD PQoS (Platform QoS) extended features 1012 989 1013 990 0x80000020, 0, ebx, 1, mba , Memory Bandwidth Allocation support 1014 991 0x80000020, 0, ebx, 2, smba , Slow Memory Bandwidth Allocation support ··· 1030 1007 0x80000020, 3, ecx, 6, bmec_all_dirty_victims , Dirty QoS victims to all types of memory can be tracked 1031 1008 1032 1009 # Leaf 80000021H 1033 - # AMD extended features enumeration 2 1010 + # AMD extended CPU features 2 1034 1011 1035 1012 0x80000021, 0, eax, 0, no_nested_data_bp , No nested data breakpoints 1036 1013 0x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing ··· 1039 1016 0x80000021, 0, eax, 6, null_sel_clr_base , Null selector clears base 1040 1017 0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore 1041 1018 0x80000021, 0, eax, 8, autoibrs , EFER MSR Automatic IBRS 1042 - 0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR (0xc0010116) is not available 1019 + 0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR not available 1043 1020 0x80000021, 0, eax, 10, fsrs , Fast Short Rep STOSB 1044 1021 0x80000021, 0, eax, 11, fsrc , Fast Short Rep CMPSB 1045 - 0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR is available 1022 + 0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR 1046 1023 0x80000021, 0, eax, 16, opcode_reclaim , Reserves opcode space 1047 - 0x80000021, 0, eax, 17, user_cpuid_disable , #GP when executing CPUID at CPL > 0 is supported 1024 + 0x80000021, 0, eax, 17, user_cpuid_disable , #GP when executing CPUID at CPL > 0 1048 1025 0x80000021, 0, eax, 18, epsf , Enhanced Predictive Store Forwarding 1049 1026 0x80000021, 0, eax, 22, wl_feedback , Workload-based heuristic feedback to OS 1050 1027 0x80000021, 0, eax, 24, eraps , Enhanced Return Address Predictor Security 1051 1028 0x80000021, 0, eax, 27, sbpb , Selective Branch Predictor Barrier 1052 1029 0x80000021, 0, eax, 28, ibpb_brtype , Branch predictions flushed from CPU branch predictor 1053 - 0x80000021, 0, eax, 29, srso_no , CPU is not subject to the SRSO vulnerability 1054 - 0x80000021, 0, eax, 30, srso_uk_no , CPU is not vulnerable to SRSO at user-kernel boundary 1055 - 0x80000021, 0, eax, 31, srso_msr_fix , Software may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO 1056 - 0x80000021, 0, ebx, 15:0, microcode_patch_size , Size of microcode patch, in 16-byte units 1030 + 0x80000021, 0, eax, 29, srso_no , No SRSO vulnerability 1031 + 0x80000021, 0, eax, 30, srso_uk_no , No SRSO at user-kernel boundary 1032 + 0x80000021, 0, eax, 31, srso_msr_fix , MSR BP_CFG[BpSpecReduce] SRSO mitigation 1033 + 0x80000021, 0, ebx, 15:0, microcode_patch_size , Microcode patch size, in 16-byte units 1057 1034 0x80000021, 0, ebx, 23:16, rap_size , Return Address Predictor size 1058 1035 1059 1036 # Leaf 80000022H 1060 - # AMD Performance Monitoring v2 enumeration 1037 + # AMD extended performance monitoring 1061 1038 1062 - 0x80000022, 0, eax, 0, perfmon_v2 , Performance monitoring v2 supported 1039 + 0x80000022, 0, eax, 0, perfmon_v2 , Performance monitoring v2 1063 1040 0x80000022, 0, eax, 1, lbr_v2 , Last Branch Record v2 extensions (LBR Stack) 1064 - 0x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing core performance counters / LBR Stack supported 1041 + 0x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing core performance counters / LBR Stack 1065 1042 0x80000022, 0, ebx, 3:0, n_pmc_core , Number of core performance counters 1066 - 0x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number of available LBR stack entries 1067 - 0x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number of available northbridge (data fabric) performance counters 1068 - 0x80000022, 0, ebx, 21:16, n_pmc_umc , Number of available UMC performance counters 1043 + 0x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number of LBR stack entries 1044 + 0x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number of northbridge performance counters 1045 + 0x80000022, 0, ebx, 21:16, n_pmc_umc , Number of UMC performance counters 1069 1046 0x80000022, 0, ecx, 31:0, active_umc_bitmask , Active UMCs bitmask 1070 1047 1071 1048 # Leaf 80000023H 1072 - # AMD Secure Multi-key Encryption enumeration 1049 + # AMD multi-key encrypted memory 1073 1050 1074 - 0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK encryption mode is supported 1075 - 0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK mode: total number of available encryption keys 1051 + 0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK encryption mode 1052 + 0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , Total number of available encryption keys 1076 1053 1077 1054 # Leaf 80000026H 1078 - # AMD extended topology enumeration v2 1055 + # AMD extended CPU topology 1079 1056 1080 1057 0x80000026, 3:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive) 1081 1058 0x80000026, 3:0, eax, 29, core_has_pwreff_ranking, This core has a power efficiency ranking ··· 1090 1067 0x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU 1091 1068 1092 1069 # Leaf 80860000H 1093 - # Maximum Transmeta leaf number + CPU vendor ID string 1070 + # Maximum Transmeta leaf + CPU vendor string 1094 1071 1095 - 0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum supported Transmeta leaf number 1072 + 0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum Transmeta leaf 1096 1073 0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmeta Vendor ID string bytes 0 - 3 1097 1074 0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmeta Vendor ID string bytes 8 - 11 1098 1075 0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmeta Vendor ID string bytes 4 - 7 1099 1076 1100 1077 # Leaf 80860001H 1101 - # Transmeta extended CPU information 1078 + # Transmeta extended CPU features 1102 1079 1103 1080 0x80860001, 0, eax, 3:0, stepping , Stepping ID 1104 1081 0x80860001, 0, eax, 7:4, base_model , Base CPU model ID ··· 1114 1091 0x80860001, 0, edx, 3, lrti , LongRun Table Interface 1115 1092 1116 1093 # Leaf 80860002H 1117 - # Transmeta Code Morphing Software (CMS) enumeration 1094 + # Transmeta CMS (Code Morphing Software) 1118 1095 1119 1096 0x80860002, 0, eax, 31:0, cpu_rev_id , CPU revision ID 1120 1097 0x80860002, 0, ebx, 7:0, cms_rev_mask_2 , CMS revision ID, mask component 2 ··· 1164 1141 0x80860007, 0, edx, 31:0, cpu_cur_gate_delay , Current CPU gate delay, in femtoseconds 1165 1142 1166 1143 # Leaf C0000000H 1167 - # Maximum Centaur/Zhaoxin leaf number 1144 + # Maximum Centaur/Zhaoxin leaf 1168 1145 1169 - 0xc0000000, 0, eax, 31:0, max_cntr_leaf , Maximum Centaur/Zhaoxin leaf number 1146 + 0xc0000000, 0, eax, 31:0, max_cntr_leaf , Maximum Centaur/Zhaoxin leaf 1170 1147 1171 1148 # Leaf C0000001H 1172 1149 # Centaur/Zhaoxin extended CPU features

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