Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This has been a semi-quiet cycle. The core framework remains unchanged
this time around.
In terms of shiny new code though, we have support for the SpacemiT K1
SoC, Sophgo SG2044, and T-HEAD TH1520 VO clk drivers joining the usual
silicon players like Qualcomm, Samsung, Allwinner, and Renesas.
Surprisingly, the Qualcomm pile was smaller than usual but that is
likely because they put one SoC support inside a driver for a
different SoC that is very similar.
Other than all those new clk drivers there are the usual clk data
updates to fix parents, frequency tables, and add missing clks along
with some Kconfig changes to make compile testing simpler and even
more DT binding conversions to boot.
The exciting part is still the new SoC support like SpacemiT and
Sophgo support though, which really dominate the diffstat because they
introduce a whole new silicon vendor clk driver.
New Drivers:
- Camera clock controller driver for Qualcomm QCS8300
- DE (display engine) 3.3 clocks on Allwinner H616
- Samsung ExynosAutov920 CPU cluster CL0, CL1 and CL2 clock controllers
- Video Output (VO) subsystem clk controller in the T-HEAD TH1520 SoC
- Clock driver for Sophgo SG2044
- Clock driver for SpacemiT K1 SoC
- Renesas RZ/V2N (R9A09G056) SoC clk driver
Updates:
- Correct data in various SoC clk drivers
- Allow clkaN to be optional in the Qualcomm RPMh clock controller
driver if command db doesn't define it
- Change Kconfig options to not enable by default during compile
testing
- Add missing clks in various SoC clk drivers
- Remove some duplicate clk DT bindings and convert some more to
YAML"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits)
clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks
clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
clk: qcom: rpmh: make clkaN optional
clk: qcom: Add support for Camera Clock Controller on QCS8300
clk: rockchip: rk3528: add slab.h header include
clk: rockchip: rk3576: add missing slab.h include
clk: meson: Do not enable by default during compile testing
clk: meson-g12a: add missing fclk_div2 to spicc
clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz
clk: rockchip: rename gate-grf clk file
clk: rockchip: rename branch_muxgrf to branch_grf_mux
clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
dt-bindings: allwinner: add H616 DE33 clock binding
clk: samsung: correct clock summary for hsi1 block
dt-bindings: clock: add SM6350 QCOM video clock bindings
clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks
clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
clk: rockchip: rk3036: mark ddrphy as critical
clk: rockchip: rk3036: fix implementation of usb480m clock mux
...
+7299
-527
+1
Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
+1
Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
-31
Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt
-31
Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt
···
1
-
Broadcom BCM2835 auxiliary peripheral support
2
-
3
-
This binding uses the common clock binding:
4
-
Documentation/devicetree/bindings/clock/clock-bindings.txt
5
-
6
-
The auxiliary peripherals (UART, SPI1, and SPI2) have a small register
7
-
area controlling clock gating to the peripherals, and providing an IRQ
8
-
status register.
9
-
10
-
Required properties:
11
-
- compatible: Should be "brcm,bcm2835-aux"
12
-
- #clock-cells: Should be <1>. The permitted clock-specifier values can be
13
-
found in include/dt-bindings/clock/bcm2835-aux.h
14
-
- reg: Specifies base physical address and size of the registers
15
-
- clocks: The parent clock phandle
16
-
17
-
Example:
18
-
19
-
clocks: cprman@7e101000 {
20
-
compatible = "brcm,bcm2835-cprman";
21
-
#clock-cells = <1>;
22
-
reg = <0x7e101000 0x2000>;
23
-
clocks = <&clk_osc>;
24
-
};
25
-
26
-
aux: aux@7e215004 {
27
-
compatible = "brcm,bcm2835-aux";
28
-
#clock-cells = <1>;
29
-
reg = <0x7e215000 0x8>;
30
-
clocks = <&clocks BCM2835_CLOCK_VPU>;
31
-
};
+47
Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.yaml
+47
Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/brcm,bcm2835-aux-clock.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Broadcom BCM2835 auxiliary peripheral clock
8
+
9
+
maintainers:
10
+
- Stefan Wahren <wahrenst@gmx.net>
11
+
- Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
12
+
13
+
description:
14
+
The auxiliary peripherals (UART, SPI1, and SPI2) have a small register
15
+
area controlling clock gating to the peripherals, and providing an IRQ
16
+
status register.
17
+
18
+
properties:
19
+
compatible:
20
+
const: brcm,bcm2835-aux
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
"#clock-cells":
26
+
const: 1
27
+
28
+
clocks:
29
+
maxItems: 1
30
+
31
+
required:
32
+
- compatible
33
+
- reg
34
+
- "#clock-cells"
35
+
- clocks
36
+
37
+
additionalProperties: false
38
+
39
+
examples:
40
+
- |
41
+
#include <dt-bindings/clock/bcm2835.h>
42
+
clock@7e215000 {
43
+
compatible = "brcm,bcm2835-aux";
44
+
reg = <0x7e215000 0x8>;
45
+
#clock-cells = <1>;
46
+
clocks = <&clocks BCM2835_CLOCK_VPU>;
47
+
};
+58
Documentation/devicetree/bindings/clock/fsl,vf610-ccm.yaml
+58
Documentation/devicetree/bindings/clock/fsl,vf610-ccm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/fsl,vf610-ccm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Clock for Freescale Vybrid VF610 SOC
8
+
9
+
description:
10
+
The clock consumer should specify the desired clock by having the clock
11
+
ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
12
+
for the full list of VF610 clock IDs
13
+
14
+
maintainers:
15
+
- Frank Li <Frank.Li@nxp.com>
16
+
17
+
properties:
18
+
compatible:
19
+
const: fsl,vf610-ccm
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
'#clock-cells':
25
+
const: 1
26
+
27
+
clocks:
28
+
items:
29
+
- description: external crystal oscillator 32KHz, recommended
30
+
- description: external crystal oscillator 24MHz, recommended
31
+
- description: audio
32
+
- description: enet
33
+
minItems: 2
34
+
35
+
clock-names:
36
+
items:
37
+
- const: sxosc
38
+
- const: fxosc
39
+
- const: enet_ext
40
+
- const: audio_ext
41
+
minItems: 2
42
+
43
+
required:
44
+
- compatible
45
+
- reg
46
+
47
+
additionalProperties: false
48
+
49
+
examples:
50
+
- |
51
+
clock-controller@4006b000 {
52
+
compatible = "fsl,vf610-ccm";
53
+
reg = <0x4006b000 0x1000>;
54
+
#clock-cells = <1>;
55
+
clocks = <&sxosc>, <&fxosc>;
56
+
clock-names = "sxosc", "fxosc";
57
+
};
58
+
-114
Documentation/devicetree/bindings/clock/maxim,max77686.txt
-114
Documentation/devicetree/bindings/clock/maxim,max77686.txt
···
1
-
Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block
2
-
3
-
This is a part of device tree bindings of MAX77686/MAX77802/MAX77620
4
-
multi-function device. More information can be found in MFD DT binding
5
-
doc as follows:
6
-
bindings/mfd/max77686.txt for MAX77686 and
7
-
bindings/mfd/max77802.txt for MAX77802 and
8
-
bindings/mfd/max77620.txt for MAX77620.
9
-
10
-
The MAX77686 contains three 32.768khz clock outputs that can be controlled
11
-
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
12
-
dt-bindings/clock/maxim,max77686.h.
13
-
14
-
15
-
The MAX77802 contains two 32.768khz clock outputs that can be controlled
16
-
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
17
-
dt-bindings/clock/maxim,max77802.h.
18
-
19
-
The MAX77686 contains one 32.768khz clock outputs that can be controlled
20
-
(gated/ungated) over I2C. Clocks are defined as preprocessor macros in
21
-
dt-bindings/clock/maxim,max77620.h.
22
-
23
-
Following properties should be presend in main device node of the MFD chip.
24
-
25
-
Required properties:
26
-
27
-
- #clock-cells: from common clock binding; shall be set to 1.
28
-
29
-
Optional properties:
30
-
- clock-output-names: From common clock binding.
31
-
32
-
Each clock is assigned an identifier and client nodes can use this identifier
33
-
to specify the clock which they consume. Following indices are allowed:
34
-
- 0: 32khz_ap clock (max77686, max77802), 32khz_out0 (max77620)
35
-
- 1: 32khz_cp clock (max77686, max77802),
36
-
- 2: 32khz_pmic clock (max77686).
37
-
38
-
Clocks are defined as preprocessor macros in above dt-binding header for
39
-
respective chips.
40
-
41
-
Example:
42
-
43
-
1. With MAX77686:
44
-
45
-
#include <dt-bindings/clock/maxim,max77686.h>
46
-
/* ... */
47
-
48
-
Node of the MFD chip
49
-
max77686: max77686@9 {
50
-
compatible = "maxim,max77686";
51
-
interrupt-parent = <&wakeup_eint>;
52
-
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
53
-
reg = <0x09>;
54
-
#clock-cells = <1>;
55
-
56
-
/* ... */
57
-
};
58
-
59
-
Clock consumer node
60
-
61
-
foo@0 {
62
-
compatible = "bar,foo";
63
-
/* ... */
64
-
clock-names = "my-clock";
65
-
clocks = <&max77686 MAX77686_CLK_PMIC>;
66
-
};
67
-
68
-
2. With MAX77802:
69
-
70
-
#include <dt-bindings/clock/maxim,max77802.h>
71
-
/* ... */
72
-
73
-
Node of the MFD chip
74
-
max77802: max77802@9 {
75
-
compatible = "maxim,max77802";
76
-
interrupt-parent = <&wakeup_eint>;
77
-
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
78
-
reg = <0x09>;
79
-
#clock-cells = <1>;
80
-
81
-
/* ... */
82
-
};
83
-
84
-
Clock consumer node
85
-
86
-
foo@0 {
87
-
compatible = "bar,foo";
88
-
/* ... */
89
-
clock-names = "my-clock";
90
-
clocks = <&max77802 MAX77802_CLK_32K_AP>;
91
-
};
92
-
93
-
94
-
3. With MAX77620:
95
-
96
-
#include <dt-bindings/clock/maxim,max77620.h>
97
-
/* ... */
98
-
99
-
Node of the MFD chip
100
-
max77620: max77620@3c {
101
-
compatible = "maxim,max77620";
102
-
reg = <0x3c>;
103
-
#clock-cells = <1>;
104
-
/* ... */
105
-
};
106
-
107
-
Clock consumer node
108
-
109
-
foo@0 {
110
-
compatible = "bar,foo";
111
-
/* ... */
112
-
clock-names = "my-clock";
113
-
clocks = <&max77620 MAX77620_CLK_32K_OUT0>;
114
-
};
+20
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
+20
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
···
14
14
domains on Qualcomm SoCs.
15
15
16
16
See also::
17
+
include/dt-bindings/clock/qcom,sm6350-videocc.h
17
18
include/dt-bindings/clock/qcom,videocc-sc7180.h
18
19
include/dt-bindings/clock/qcom,videocc-sc7280.h
19
20
include/dt-bindings/clock/qcom,videocc-sdm845.h
···
27
26
- qcom,sc7180-videocc
28
27
- qcom,sc7280-videocc
29
28
- qcom,sdm845-videocc
29
+
- qcom,sm6350-videocc
30
30
- qcom,sm8150-videocc
31
31
- qcom,sm8250-videocc
32
32
···
88
86
items:
89
87
- const: bi_tcxo
90
88
- const: bi_tcxo_ao
89
+
90
+
- if:
91
+
properties:
92
+
compatible:
93
+
enum:
94
+
- qcom,sm6350-videocc
95
+
then:
96
+
properties:
97
+
clocks:
98
+
items:
99
+
- description: Video AHB clock from GCC
100
+
- description: Board XO source
101
+
- description: Sleep Clock source
102
+
clock-names:
103
+
items:
104
+
- const: iface
105
+
- const: bi_tcxo
106
+
- const: sleep_clk
91
107
92
108
- if:
93
109
properties:
+3
-2
Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
+3
-2
Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
···
4
4
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
7
+
title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
8
8
9
9
maintainers:
10
10
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11
11
12
12
description:
13
-
On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
13
+
On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
14
14
generation and control of clock signals for the IP modules, generation and
15
15
control of resets, and control over booting, low power consumption and power
16
16
supply domains.
···
19
19
compatible:
20
20
enum:
21
21
- renesas,r9a09g047-cpg # RZ/G3E
22
+
- renesas,r9a09g056-cpg # RZ/V2N
22
23
- renesas,r9a09g057-cpg # RZ/V2H
23
24
24
25
reg:
+69
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
+69
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
···
8
8
9
9
maintainers:
10
10
- Sunyeal Hong <sunyeal.hong@samsung.com>
11
+
- Shin Son <shin.son@samsung.com>
11
12
- Chanwoo Choi <cw00.choi@samsung.com>
12
13
- Krzysztof Kozlowski <krzk@kernel.org>
13
14
- Sylwester Nawrocki <s.nawrocki@samsung.com>
···
33
32
compatible:
34
33
enum:
35
34
- samsung,exynosautov920-cmu-top
35
+
- samsung,exynosautov920-cmu-cpucl0
36
+
- samsung,exynosautov920-cmu-cpucl1
37
+
- samsung,exynosautov920-cmu-cpucl2
36
38
- samsung,exynosautov920-cmu-peric0
37
39
- samsung,exynosautov920-cmu-peric1
38
40
- samsung,exynosautov920-cmu-misc
···
72
68
clock-names:
73
69
items:
74
70
- const: oscclk
71
+
72
+
- if:
73
+
properties:
74
+
compatible:
75
+
contains:
76
+
enum:
77
+
- samsung,exynosautov920-cmu-cpucl0
78
+
79
+
then:
80
+
properties:
81
+
clocks:
82
+
items:
83
+
- description: External reference clock (38.4 MHz)
84
+
- description: CMU_CPUCL0 SWITCH clock (from CMU_TOP)
85
+
- description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP)
86
+
- description: CMU_CPUCL0 DBG clock (from CMU_TOP)
87
+
88
+
clock-names:
89
+
items:
90
+
- const: oscclk
91
+
- const: switch
92
+
- const: cluster
93
+
- const: dbg
94
+
95
+
- if:
96
+
properties:
97
+
compatible:
98
+
contains:
99
+
enum:
100
+
- samsung,exynosautov920-cmu-cpucl1
101
+
102
+
then:
103
+
properties:
104
+
clocks:
105
+
items:
106
+
- description: External reference clock (38.4 MHz)
107
+
- description: CMU_CPUCL1 SWITCH clock (from CMU_TOP)
108
+
- description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP)
109
+
110
+
clock-names:
111
+
items:
112
+
- const: oscclk
113
+
- const: switch
114
+
- const: cluster
115
+
116
+
- if:
117
+
properties:
118
+
compatible:
119
+
contains:
120
+
enum:
121
+
- samsung,exynosautov920-cmu-cpucl2
122
+
123
+
then:
124
+
properties:
125
+
clocks:
126
+
items:
127
+
- description: External reference clock (38.4 MHz)
128
+
- description: CMU_CPUCL2 SWITCH clock (from CMU_TOP)
129
+
- description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP)
130
+
131
+
clock-names:
132
+
items:
133
+
- const: oscclk
134
+
- const: switch
135
+
- const: cluster
75
136
76
137
- if:
77
138
properties:
+12
-4
Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml
+12
-4
Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml
···
11
11
12
12
properties:
13
13
compatible:
14
-
enum:
15
-
- sophgo,cv1800-clk
16
-
- sophgo,cv1810-clk
17
-
- sophgo,sg2000-clk
14
+
oneOf:
15
+
- enum:
16
+
- sophgo,cv1800b-clk
17
+
- sophgo,cv1812h-clk
18
+
- sophgo,sg2000-clk
19
+
- items:
20
+
- const: sophgo,sg2002-clk
21
+
- const: sophgo,sg2000-clk
22
+
- const: sophgo,cv1800-clk
23
+
deprecated: true
24
+
- const: sophgo,cv1810-clk
25
+
deprecated: true
18
26
19
27
reg:
20
28
maxItems: 1
+99
Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml
+99
Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/sophgo,sg2044-clk.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Sophgo SG2044 Clock Controller
8
+
9
+
maintainers:
10
+
- Inochi Amaoto <inochiama@gmail.com>
11
+
12
+
description: |
13
+
The Sophgo SG2044 clock controller requires an external oscillator
14
+
as input clock.
15
+
16
+
All available clocks are defined as preprocessor macros in
17
+
include/dt-bindings/clock/sophgo,sg2044-clk.h
18
+
19
+
properties:
20
+
compatible:
21
+
const: sophgo,sg2044-clk
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
items:
28
+
- description: fpll0
29
+
- description: fpll1
30
+
- description: fpll2
31
+
- description: dpll0
32
+
- description: dpll1
33
+
- description: dpll2
34
+
- description: dpll3
35
+
- description: dpll4
36
+
- description: dpll5
37
+
- description: dpll6
38
+
- description: dpll7
39
+
- description: mpll0
40
+
- description: mpll1
41
+
- description: mpll2
42
+
- description: mpll3
43
+
- description: mpll4
44
+
- description: mpll5
45
+
46
+
clock-names:
47
+
items:
48
+
- const: fpll0
49
+
- const: fpll1
50
+
- const: fpll2
51
+
- const: dpll0
52
+
- const: dpll1
53
+
- const: dpll2
54
+
- const: dpll3
55
+
- const: dpll4
56
+
- const: dpll5
57
+
- const: dpll6
58
+
- const: dpll7
59
+
- const: mpll0
60
+
- const: mpll1
61
+
- const: mpll2
62
+
- const: mpll3
63
+
- const: mpll4
64
+
- const: mpll5
65
+
66
+
'#clock-cells':
67
+
const: 1
68
+
69
+
required:
70
+
- compatible
71
+
- reg
72
+
- clocks
73
+
- '#clock-cells'
74
+
75
+
additionalProperties: false
76
+
77
+
examples:
78
+
- |
79
+
#include <dt-bindings/clock/sophgo,sg2044-pll.h>
80
+
81
+
clock-controller@50002000 {
82
+
compatible = "sophgo,sg2044-clk";
83
+
reg = <0x50002000 0x1000>;
84
+
#clock-cells = <1>;
85
+
clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,
86
+
<&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,
87
+
<&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,
88
+
<&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,
89
+
<&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,
90
+
<&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,
91
+
<&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,
92
+
<&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,
93
+
<&syscon CLK_MPLL5>;
94
+
clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
95
+
"dpll1", "dpll2", "dpll3", "dpll4",
96
+
"dpll5", "dpll6", "dpll7", "mpll0",
97
+
"mpll1", "mpll2", "mpll3", "mpll4",
98
+
"mpll5";
99
+
};
+50
Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml
+50
Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: SpacemiT K1 PLL
8
+
9
+
maintainers:
10
+
- Haylen Chu <heylenay@4d2.org>
11
+
12
+
properties:
13
+
compatible:
14
+
const: spacemit,k1-pll
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
clocks:
20
+
description: External 24MHz oscillator
21
+
22
+
spacemit,mpmu:
23
+
$ref: /schemas/types.yaml#/definitions/phandle
24
+
description:
25
+
Phandle to the "Main PMU (MPMU)" syscon. It is used to check PLL
26
+
lock status.
27
+
28
+
"#clock-cells":
29
+
const: 1
30
+
description:
31
+
See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
32
+
33
+
required:
34
+
- compatible
35
+
- reg
36
+
- clocks
37
+
- spacemit,mpmu
38
+
- "#clock-cells"
39
+
40
+
additionalProperties: false
41
+
42
+
examples:
43
+
- |
44
+
clock-controller@d4090000 {
45
+
compatible = "spacemit,k1-pll";
46
+
reg = <0xd4090000 0x1000>;
47
+
clocks = <&vctcxo_24m>;
48
+
spacemit,mpmu = <&sysctl_mpmu>;
49
+
#clock-cells = <1>;
50
+
};
-71
Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt
-71
Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt
···
1
-
STMicroelectronics STM32H7 Reset and Clock Controller
2
-
=====================================================
3
-
4
-
The RCC IP is both a reset and a clock controller.
5
-
6
-
Please refer to clock-bindings.txt for common clock controller binding usage.
7
-
Please also refer to reset.txt for common reset controller binding usage.
8
-
9
-
Required properties:
10
-
- compatible: Should be:
11
-
"st,stm32h743-rcc"
12
-
13
-
- reg: should be register base and length as documented in the
14
-
datasheet
15
-
16
-
- #reset-cells: 1, see below
17
-
18
-
- #clock-cells : from common clock binding; shall be set to 1
19
-
20
-
- clocks: External oscillator clock phandle
21
-
- high speed external clock signal (HSE)
22
-
- low speed external clock signal (LSE)
23
-
- external I2S clock (I2S_CKIN)
24
-
25
-
Optional properties:
26
-
- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
27
-
write protection (RTC clock).
28
-
29
-
Example:
30
-
31
-
rcc: reset-clock-controller@58024400 {
32
-
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
33
-
reg = <0x58024400 0x400>;
34
-
#reset-cells = <1>;
35
-
#clock-cells = <1>;
36
-
clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
37
-
38
-
st,syscfg = <&pwrcfg>;
39
-
};
40
-
41
-
The peripheral clock consumer should specify the desired clock by
42
-
having the clock ID in its "clocks" phandle cell.
43
-
44
-
Example:
45
-
46
-
timer5: timer@40000c00 {
47
-
compatible = "st,stm32-timer";
48
-
reg = <0x40000c00 0x400>;
49
-
interrupts = <50>;
50
-
clocks = <&rcc TIM5_CK>;
51
-
};
52
-
53
-
Specifying softreset control of devices
54
-
=======================================
55
-
56
-
Device nodes should specify the reset channel required in their "resets"
57
-
property, containing a phandle to the reset device node and an index specifying
58
-
which channel to use.
59
-
The index is the bit number within the RCC registers bank, starting from RCC
60
-
base address.
61
-
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
62
-
Where bit_offset is the bit offset within the register.
63
-
64
-
For example, for CRC reset:
65
-
crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
66
-
67
-
Example:
68
-
69
-
timer2 {
70
-
resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
71
-
};
+14
-3
Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
+14
-3
Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
···
8
8
9
9
description: |
10
10
The T-HEAD TH1520 AP sub-system clock controller configures the
11
-
CPU, DPU, GMAC and TEE PLLs.
11
+
CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures
12
+
the clock gates for the HDMI, MIPI and the GPU.
12
13
13
14
SoC reference manual
14
15
https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
···
21
20
22
21
properties:
23
22
compatible:
24
-
const: thead,th1520-clk-ap
23
+
enum:
24
+
- thead,th1520-clk-ap
25
+
- thead,th1520-clk-vo
25
26
26
27
reg:
27
28
maxItems: 1
28
29
29
30
clocks:
30
31
items:
31
-
- description: main oscillator (24MHz)
32
+
- description: |
33
+
One input clock:
34
+
- For "thead,th1520-clk-ap": the clock input must be the 24 MHz
35
+
main oscillator.
36
+
- For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL,
37
+
which is configured by the AP clock controller. According to the
38
+
TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL
39
+
(integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with
40
+
a maximum FOUTVCO of 2376 MHz.
32
41
33
42
"#clock-cells":
34
43
const: 1
-41
Documentation/devicetree/bindings/clock/vf610-clock.txt
-41
Documentation/devicetree/bindings/clock/vf610-clock.txt
···
1
-
* Clock bindings for Freescale Vybrid VF610 SOC
2
-
3
-
Required properties:
4
-
- compatible: Should be "fsl,vf610-ccm"
5
-
- reg: Address and length of the register set
6
-
- #clock-cells: Should be <1>
7
-
8
-
Optional properties:
9
-
- clocks: list of clock identifiers which are external input clocks to the
10
-
given clock controller. Please refer the next section to find
11
-
the input clocks for a given controller.
12
-
- clock-names: list of names of clocks which are external input clocks to the
13
-
given clock controller.
14
-
15
-
Input clocks for top clock controller:
16
-
- sxosc (external crystal oscillator 32KHz, recommended)
17
-
- fxosc (external crystal oscillator 24MHz, recommended)
18
-
- audio_ext
19
-
- enet_ext
20
-
21
-
The clock consumer should specify the desired clock by having the clock
22
-
ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
23
-
for the full list of VF610 clock IDs.
24
-
25
-
Examples:
26
-
27
-
clks: ccm@4006b000 {
28
-
compatible = "fsl,vf610-ccm";
29
-
reg = <0x4006b000 0x1000>;
30
-
#clock-cells = <1>;
31
-
clocks = <&sxosc>, <&fxosc>;
32
-
clock-names = "sxosc", "fxosc";
33
-
};
34
-
35
-
uart1: serial@40028000 {
36
-
compatible = "fsl,vf610-uart";
37
-
reg = <0x40028000 0x1000>;
38
-
interrupts = <0 62 0x04>;
39
-
clocks = <&clks VF610_CLK_UART1>;
40
-
clock-names = "ipg";
41
-
};
+2
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+2
Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
···
27
27
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
28
28
- renesas,r9a08g045-pinctrl # RZ/G3S
29
29
- renesas,r9a09g047-pinctrl # RZ/G3E
30
+
- renesas,r9a09g056-pinctrl # RZ/V2N
30
31
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
31
32
32
33
- items:
···
146
145
contains:
147
146
enum:
148
147
- renesas,r9a09g047-pinctrl
148
+
- renesas,r9a09g056-pinctrl
149
149
- renesas,r9a09g057-pinctrl
150
150
then:
151
151
properties:
+1
Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
+1
Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
+15
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+15
Documentation/devicetree/bindings/soc/renesas/renesas.yaml
···
551
551
- renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
552
552
- const: renesas,r9a09g047
553
553
554
+
- description: RZ/V2N (R9A09G056)
555
+
items:
556
+
- enum:
557
+
- renesas,rzv2n-evk # RZ/V2N EVK (RTK0EF0186C03000BJ)
558
+
- enum:
559
+
- renesas,r9a09g056n41 # RZ/V2N
560
+
- renesas,r9a09g056n42 # RZ/V2N with Mali-G31 support
561
+
- renesas,r9a09g056n43 # RZ/V2N with Mali-C55 support
562
+
- renesas,r9a09g056n44 # RZ/V2N with Mali-G31 + Mali-C55 support
563
+
- renesas,r9a09g056n45 # RZ/V2N with cryptographic extension support
564
+
- renesas,r9a09g056n46 # RZ/V2N with Mali-G31 + cryptographic extension support
565
+
- renesas,r9a09g056n47 # RZ/V2N with Mali-C55 + cryptographic extension support
566
+
- renesas,r9a09g056n48 # RZ/V2N with Mali-G31 + Mali-C55 + cryptographic extension support
567
+
- const: renesas,r9a09g056
568
+
554
569
- description: RZ/V2H(P) (R9A09G057)
555
570
items:
556
571
- enum:
+49
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml
+49
Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2044-top-syscon.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Sophgo SG2044 SoC TOP system controller
8
+
9
+
maintainers:
10
+
- Inochi Amaoto <inochiama@gmail.com>
11
+
12
+
description:
13
+
The Sophgo SG2044 TOP system controller is a hardware block grouping
14
+
multiple small functions, such as clocks and some other internal
15
+
function.
16
+
17
+
properties:
18
+
compatible:
19
+
items:
20
+
- const: sophgo,sg2044-top-syscon
21
+
- const: syscon
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
maxItems: 1
28
+
29
+
'#clock-cells':
30
+
const: 1
31
+
description:
32
+
See <dt-bindings/clock/sophgo,sg2044-pll.h> for valid clock.
33
+
34
+
required:
35
+
- compatible
36
+
- reg
37
+
- clocks
38
+
- '#clock-cells'
39
+
40
+
additionalProperties: false
41
+
42
+
examples:
43
+
- |
44
+
syscon@50000000 {
45
+
compatible = "sophgo,sg2044-top-syscon", "syscon";
46
+
reg = <0x50000000 0x1000>;
47
+
#clock-cells = <1>;
48
+
clocks = <&osc>;
49
+
};
+80
Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
+80
Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: SpacemiT K1 SoC System Controller
8
+
9
+
maintainers:
10
+
- Haylen Chu <heylenay@4d2.org>
11
+
12
+
description:
13
+
System controllers found on SpacemiT K1 SoC, which are capable of
14
+
clock, reset and power-management functions.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- spacemit,k1-syscon-apbc
20
+
- spacemit,k1-syscon-apmu
21
+
- spacemit,k1-syscon-mpmu
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
maxItems: 4
28
+
29
+
clock-names:
30
+
items:
31
+
- const: osc
32
+
- const: vctcxo_1m
33
+
- const: vctcxo_3m
34
+
- const: vctcxo_24m
35
+
36
+
"#clock-cells":
37
+
const: 1
38
+
description:
39
+
See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
40
+
41
+
"#power-domain-cells":
42
+
const: 1
43
+
44
+
"#reset-cells":
45
+
const: 1
46
+
47
+
required:
48
+
- compatible
49
+
- reg
50
+
- clocks
51
+
- clock-names
52
+
- "#clock-cells"
53
+
- "#reset-cells"
54
+
55
+
allOf:
56
+
- if:
57
+
properties:
58
+
compatible:
59
+
contains:
60
+
const: spacemit,k1-syscon-apbc
61
+
then:
62
+
properties:
63
+
"#power-domain-cells": false
64
+
else:
65
+
required:
66
+
- "#power-domain-cells"
67
+
68
+
additionalProperties: false
69
+
70
+
examples:
71
+
- |
72
+
system-controller@d4050000 {
73
+
compatible = "spacemit,k1-syscon-mpmu";
74
+
reg = <0xd4050000 0x209c>;
75
+
clocks = <&osc>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
76
+
clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
77
+
#clock-cells = <1>;
78
+
#power-domain-cells = <1>;
79
+
#reset-cells = <1>;
80
+
};
-1
MAINTAINERS
-1
MAINTAINERS
···
14765
14765
F: Documentation/devicetree/bindings/*/maxim,max77693.yaml
14766
14766
F: Documentation/devicetree/bindings/*/maxim,max77705*.yaml
14767
14767
F: Documentation/devicetree/bindings/*/maxim,max77843.yaml
14768
-
F: Documentation/devicetree/bindings/clock/maxim,max77686.txt
14769
14768
F: drivers/leds/leds-max77705.c
14770
14769
F: drivers/*/*max77843.c
14771
14770
F: drivers/*/max14577*.c
+1
drivers/clk/Kconfig
+1
drivers/clk/Kconfig
···
517
517
source "drivers/clk/sifive/Kconfig"
518
518
source "drivers/clk/socfpga/Kconfig"
519
519
source "drivers/clk/sophgo/Kconfig"
520
+
source "drivers/clk/spacemit/Kconfig"
520
521
source "drivers/clk/sprd/Kconfig"
521
522
source "drivers/clk/starfive/Kconfig"
522
523
source "drivers/clk/sunxi/Kconfig"
+1
drivers/clk/Makefile
+1
drivers/clk/Makefile
-18
drivers/clk/bcm/clk-kona.c
-18
drivers/clk/bcm/clk-kona.c
···
53
53
return (u64)reg_div + ((u64)1 << div->u.s.frac_width);
54
54
}
55
55
56
-
/*
57
-
* Build a scaled divider value as close as possible to the
58
-
* given whole part (div_value) and fractional part (expressed
59
-
* in billionths).
60
-
*/
61
-
u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths)
62
-
{
63
-
u64 combined;
64
-
65
-
BUG_ON(!div_value);
66
-
BUG_ON(billionths >= BILLION);
67
-
68
-
combined = (u64)div_value * BILLION + billionths;
69
-
combined <<= div->u.s.frac_width;
70
-
71
-
return DIV_ROUND_CLOSEST_ULL(combined, BILLION);
72
-
}
73
-
74
56
/* The scaled minimum divisor representable by a divider */
75
57
static inline u64
76
58
scaled_div_min(struct bcm_clk_div *div)
-2
drivers/clk/bcm/clk-kona.h
-2
drivers/clk/bcm/clk-kona.h
···
492
492
/* Externally visible functions */
493
493
494
494
extern u64 scaled_div_max(struct bcm_clk_div *div);
495
-
extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value,
496
-
u32 billionths);
497
495
498
496
extern void __init kona_dt_ccu_setup(struct ccu_data *ccu,
499
497
struct device_node *node);
+2
-1
drivers/clk/bcm/clk-raspberrypi.c
+2
-1
drivers/clk/bcm/clk-raspberrypi.c
···
286
286
init.name = devm_kasprintf(rpi->dev, GFP_KERNEL,
287
287
"fw-clk-%s",
288
288
rpi_firmware_clk_names[id]);
289
+
if (!init.name)
290
+
return ERR_PTR(-ENOMEM);
289
291
init.ops = &raspberrypi_firmware_clk_ops;
290
292
init.flags = CLK_GET_RATE_NOCACHE;
291
293
···
482
480
MODULE_AUTHOR("Nicolas Saenz Julienne <nsaenzjulienne@suse.de>");
483
481
MODULE_DESCRIPTION("Raspberry Pi firmware clock driver");
484
482
MODULE_LICENSE("GPL");
485
-
MODULE_ALIAS("platform:raspberrypi-clk");
+15
-13
drivers/clk/davinci/pll.c
+15
-13
drivers/clk/davinci/pll.c
···
763
763
return PTR_ERR(clk);
764
764
}
765
765
766
-
child = of_get_child_by_name(node, "pllout");
767
-
if (of_device_is_available(child))
766
+
child = of_get_available_child_by_name(node, "pllout");
767
+
if (child) {
768
768
of_clk_add_provider(child, of_clk_src_simple_get, clk);
769
-
of_node_put(child);
769
+
of_node_put(child);
770
+
}
770
771
771
-
child = of_get_child_by_name(node, "sysclk");
772
-
if (of_device_is_available(child)) {
772
+
child = of_get_available_child_by_name(node, "sysclk");
773
+
if (child) {
773
774
struct clk_onecell_data *clk_data;
774
775
struct clk **clks;
775
776
int n_clks = max_sysclk_id + 1;
···
804
803
clks[(*div_info)->id] = clk;
805
804
}
806
805
of_clk_add_provider(child, of_clk_src_onecell_get, clk_data);
806
+
of_node_put(child);
807
807
}
808
-
of_node_put(child);
809
808
810
-
child = of_get_child_by_name(node, "auxclk");
811
-
if (of_device_is_available(child)) {
809
+
child = of_get_available_child_by_name(node, "auxclk");
810
+
if (child) {
812
811
char child_name[MAX_NAME_SIZE];
813
812
814
813
snprintf(child_name, MAX_NAME_SIZE, "%s_auxclk", info->name);
···
819
818
child_name, PTR_ERR(clk));
820
819
else
821
820
of_clk_add_provider(child, of_clk_src_simple_get, clk);
822
-
}
823
-
of_node_put(child);
824
821
825
-
child = of_get_child_by_name(node, "obsclk");
826
-
if (of_device_is_available(child)) {
822
+
of_node_put(child);
823
+
}
824
+
825
+
child = of_get_available_child_by_name(node, "obsclk");
826
+
if (child) {
827
827
if (obsclk_info)
828
828
clk = davinci_pll_obsclk_register(dev, obsclk_info, base);
829
829
else
···
835
833
PTR_ERR(clk));
836
834
else
837
835
of_clk_add_provider(child, of_clk_src_simple_get, clk);
836
+
of_node_put(child);
838
837
}
839
-
of_node_put(child);
840
838
841
839
return 0;
842
840
}
+8
-8
drivers/clk/meson/Kconfig
+8
-8
drivers/clk/meson/Kconfig
···
55
55
config COMMON_CLK_MESON8B
56
56
bool "Meson8 SoC Clock controller support"
57
57
depends on ARM
58
-
default y
58
+
default ARCH_MESON
59
59
select COMMON_CLK_MESON_REGMAP
60
60
select COMMON_CLK_MESON_CLKC_UTILS
61
61
select COMMON_CLK_MESON_MPLL
···
70
70
config COMMON_CLK_GXBB
71
71
tristate "GXBB and GXL SoC clock controllers support"
72
72
depends on ARM64
73
-
default y
73
+
default ARCH_MESON
74
74
select COMMON_CLK_MESON_REGMAP
75
75
select COMMON_CLK_MESON_DUALDIV
76
76
select COMMON_CLK_MESON_VID_PLL_DIV
···
86
86
config COMMON_CLK_AXG
87
87
tristate "AXG SoC clock controllers support"
88
88
depends on ARM64
89
-
default y
89
+
default ARCH_MESON
90
90
select COMMON_CLK_MESON_REGMAP
91
91
select COMMON_CLK_MESON_DUALDIV
92
92
select COMMON_CLK_MESON_MPLL
···
136
136
config COMMON_CLK_C3_PLL
137
137
tristate "Amlogic C3 PLL clock controller"
138
138
depends on ARM64
139
-
default y
139
+
default ARCH_MESON
140
140
select COMMON_CLK_MESON_REGMAP
141
141
select COMMON_CLK_MESON_PLL
142
142
select COMMON_CLK_MESON_CLKC_UTILS
···
149
149
config COMMON_CLK_C3_PERIPHERALS
150
150
tristate "Amlogic C3 peripherals clock controller"
151
151
depends on ARM64
152
-
default y
152
+
default ARCH_MESON
153
153
select COMMON_CLK_MESON_REGMAP
154
154
select COMMON_CLK_MESON_DUALDIV
155
155
select COMMON_CLK_MESON_CLKC_UTILS
···
163
163
config COMMON_CLK_G12A
164
164
tristate "G12 and SM1 SoC clock controllers support"
165
165
depends on ARM64
166
-
default y
166
+
default ARCH_MESON
167
167
select COMMON_CLK_MESON_REGMAP
168
168
select COMMON_CLK_MESON_DUALDIV
169
169
select COMMON_CLK_MESON_MPLL
···
181
181
config COMMON_CLK_S4_PLL
182
182
tristate "S4 SoC PLL clock controllers support"
183
183
depends on ARM64
184
-
default y
184
+
default ARCH_MESON
185
185
select COMMON_CLK_MESON_CLKC_UTILS
186
186
select COMMON_CLK_MESON_MPLL
187
187
select COMMON_CLK_MESON_PLL
···
194
194
config COMMON_CLK_S4_PERIPHERALS
195
195
tristate "S4 SoC peripherals clock controllers support"
196
196
depends on ARM64
197
-
default y
197
+
default ARCH_MESON
198
198
select COMMON_CLK_MESON_CLKC_UTILS
199
199
select COMMON_CLK_MESON_REGMAP
200
200
select COMMON_CLK_MESON_DUALDIV
+1
drivers/clk/meson/g12a.c
+1
drivers/clk/meson/g12a.c
+5
-1
drivers/clk/qcom/apcs-sdx55.c
+5
-1
drivers/clk/qcom/apcs-sdx55.c
···
111
111
* driver, there seems to be no better place to do this. So do it here!
112
112
*/
113
113
cpu_dev = get_cpu_device(0);
114
-
dev_pm_domain_attach(cpu_dev, true);
114
+
ret = dev_pm_domain_attach(cpu_dev, true);
115
+
if (ret) {
116
+
dev_err_probe(dev, ret, "can't get PM domain: %d\n", ret);
117
+
goto err;
118
+
}
115
119
116
120
return 0;
117
121
+98
-5
drivers/clk/qcom/camcc-sa8775p.c
+98
-5
drivers/clk/qcom/camcc-sa8775p.c
···
10
10
#include <linux/pm_runtime.h>
11
11
#include <linux/regmap.h>
12
12
13
-
#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
13
+
#include <dt-bindings/clock/qcom,qcs8300-camcc.h>
14
14
15
15
#include "clk-alpha-pll.h"
16
16
#include "clk-branch.h"
···
1681
1681
},
1682
1682
};
1683
1683
1684
+
static struct clk_branch cam_cc_titan_top_accu_shift_clk = {
1685
+
.halt_reg = 0x131f0,
1686
+
.halt_check = BRANCH_HALT_VOTED,
1687
+
.clkr = {
1688
+
.enable_reg = 0x131f0,
1689
+
.enable_mask = BIT(0),
1690
+
.hw.init = &(const struct clk_init_data) {
1691
+
.name = "cam_cc_titan_top_accu_shift_clk",
1692
+
.parent_hws = (const struct clk_hw*[]) {
1693
+
&cam_cc_xo_clk_src.clkr.hw,
1694
+
},
1695
+
.num_parents = 1,
1696
+
.flags = CLK_SET_RATE_PARENT,
1697
+
.ops = &clk_branch2_ops,
1698
+
},
1699
+
},
1700
+
};
1701
+
1684
1702
static struct gdsc cam_cc_titan_top_gdsc = {
1685
1703
.gdscr = 0x131bc,
1686
1704
.en_rest_wait_val = 0x2,
···
1793
1775
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
1794
1776
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
1795
1777
[CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr,
1778
+
[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL,
1796
1779
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
1797
1780
[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
1798
1781
};
···
1830
1811
};
1831
1812
1832
1813
static const struct of_device_id cam_cc_sa8775p_match_table[] = {
1814
+
{ .compatible = "qcom,qcs8300-camcc" },
1833
1815
{ .compatible = "qcom,sa8775p-camcc" },
1834
1816
{ }
1835
1817
};
···
1861
1841
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
1862
1842
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
1863
1843
1864
-
/* Keep some clocks always enabled */
1865
-
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
1866
-
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
1867
-
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
1844
+
if (device_is_compatible(&pdev->dev, "qcom,qcs8300-camcc")) {
1845
+
cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154;
1846
+
cam_cc_camnoc_axi_clk.halt_reg = 0x1316c;
1847
+
cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c;
1848
+
cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174;
1849
+
cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174;
1850
+
1851
+
cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054;
1852
+
cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078;
1853
+
cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098;
1854
+
cam_cc_csid_clk_src.cmd_rcgr = 0x13134;
1855
+
1856
+
cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000;
1857
+
cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c;
1858
+
cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038;
1859
+
1860
+
cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104;
1861
+
cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c;
1862
+
cam_cc_xo_clk_src.cmd_rcgr = 0x131b8;
1863
+
cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4;
1864
+
1865
+
cam_cc_core_ahb_clk.halt_reg = 0x131b4;
1866
+
cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4;
1867
+
1868
+
cam_cc_cpas_ahb_clk.halt_reg = 0x130f4;
1869
+
cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4;
1870
+
cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc;
1871
+
cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc;
1872
+
1873
+
cam_cc_csi0phytimer_clk.halt_reg = 0x1506c;
1874
+
cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c;
1875
+
cam_cc_csi1phytimer_clk.halt_reg = 0x15090;
1876
+
cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090;
1877
+
cam_cc_csi2phytimer_clk.halt_reg = 0x150b0;
1878
+
cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0;
1879
+
cam_cc_csid_clk.halt_reg = 0x1314c;
1880
+
cam_cc_csid_clk.clkr.enable_reg = 0x1314c;
1881
+
cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074;
1882
+
cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074;
1883
+
cam_cc_csiphy0_clk.halt_reg = 0x15070;
1884
+
cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070;
1885
+
cam_cc_csiphy1_clk.halt_reg = 0x15094;
1886
+
cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094;
1887
+
cam_cc_csiphy2_clk.halt_reg = 0x150b4;
1888
+
cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4;
1889
+
1890
+
cam_cc_mclk0_clk.halt_reg = 0x15018;
1891
+
cam_cc_mclk0_clk.clkr.enable_reg = 0x15018;
1892
+
cam_cc_mclk1_clk.halt_reg = 0x15034;
1893
+
cam_cc_mclk1_clk.clkr.enable_reg = 0x15034;
1894
+
cam_cc_mclk2_clk.halt_reg = 0x15050;
1895
+
cam_cc_mclk2_clk.clkr.enable_reg = 0x15050;
1896
+
cam_cc_qdss_debug_xo_clk.halt_reg = 0x1319c;
1897
+
cam_cc_qdss_debug_xo_clk.clkr.enable_reg = 0x1319c;
1898
+
1899
+
cam_cc_titan_top_gdsc.gdscr = 0x131a0;
1900
+
1901
+
cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL;
1902
+
cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL;
1903
+
cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL;
1904
+
cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL;
1905
+
cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL;
1906
+
cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL;
1907
+
cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL;
1908
+
cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =
1909
+
&cam_cc_titan_top_accu_shift_clk.clkr;
1910
+
1911
+
/* Keep some clocks always enabled */
1912
+
qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */
1913
+
qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */
1914
+
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */
1915
+
} else {
1916
+
/* Keep some clocks always enabled */
1917
+
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
1918
+
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
1919
+
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
1920
+
}
1868
1921
1869
1922
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap);
1870
1923
+18
drivers/clk/qcom/camcc-sm6350.c
+18
drivers/clk/qcom/camcc-sm6350.c
···
1695
1695
1696
1696
static struct gdsc bps_gdsc = {
1697
1697
.gdscr = 0x6004,
1698
+
.en_rest_wait_val = 0x2,
1699
+
.en_few_wait_val = 0x2,
1700
+
.clk_dis_wait_val = 0xf,
1698
1701
.pd = {
1699
1702
.name = "bps_gdsc",
1700
1703
},
···
1707
1704
1708
1705
static struct gdsc ipe_0_gdsc = {
1709
1706
.gdscr = 0x7004,
1707
+
.en_rest_wait_val = 0x2,
1708
+
.en_few_wait_val = 0x2,
1709
+
.clk_dis_wait_val = 0xf,
1710
1710
.pd = {
1711
1711
.name = "ipe_0_gdsc",
1712
1712
},
···
1719
1713
1720
1714
static struct gdsc ife_0_gdsc = {
1721
1715
.gdscr = 0x9004,
1716
+
.en_rest_wait_val = 0x2,
1717
+
.en_few_wait_val = 0x2,
1718
+
.clk_dis_wait_val = 0xf,
1722
1719
.pd = {
1723
1720
.name = "ife_0_gdsc",
1724
1721
},
···
1730
1721
1731
1722
static struct gdsc ife_1_gdsc = {
1732
1723
.gdscr = 0xa004,
1724
+
.en_rest_wait_val = 0x2,
1725
+
.en_few_wait_val = 0x2,
1726
+
.clk_dis_wait_val = 0xf,
1733
1727
.pd = {
1734
1728
.name = "ife_1_gdsc",
1735
1729
},
···
1741
1729
1742
1730
static struct gdsc ife_2_gdsc = {
1743
1731
.gdscr = 0xb004,
1732
+
.en_rest_wait_val = 0x2,
1733
+
.en_few_wait_val = 0x2,
1734
+
.clk_dis_wait_val = 0xf,
1744
1735
.pd = {
1745
1736
.name = "ife_2_gdsc",
1746
1737
},
···
1752
1737
1753
1738
static struct gdsc titan_top_gdsc = {
1754
1739
.gdscr = 0x14004,
1740
+
.en_rest_wait_val = 0x2,
1741
+
.en_few_wait_val = 0x2,
1742
+
.clk_dis_wait_val = 0xf,
1755
1743
.pd = {
1756
1744
.name = "titan_top_gdsc",
1757
1745
},
+11
drivers/clk/qcom/clk-rpmh.c
+11
drivers/clk/qcom/clk-rpmh.c
···
66
66
struct clk_rpmh_desc {
67
67
struct clk_hw **clks;
68
68
size_t num_clks;
69
+
/* RPMh clock clkaN are optional for this platform */
70
+
bool clka_optional;
69
71
};
70
72
71
73
static DEFINE_MUTEX(rpmh_clk_lock);
···
650
648
static const struct clk_rpmh_desc clk_rpmh_sm8550 = {
651
649
.clks = sm8550_rpmh_clocks,
652
650
.num_clks = ARRAY_SIZE(sm8550_rpmh_clocks),
651
+
.clka_optional = true,
653
652
};
654
653
655
654
static struct clk_hw *sm8650_rpmh_clocks[] = {
···
682
679
static const struct clk_rpmh_desc clk_rpmh_sm8650 = {
683
680
.clks = sm8650_rpmh_clocks,
684
681
.num_clks = ARRAY_SIZE(sm8650_rpmh_clocks),
682
+
.clka_optional = true,
685
683
};
686
684
687
685
static struct clk_hw *sc7280_rpmh_clocks[] = {
···
851
847
static const struct clk_rpmh_desc clk_rpmh_sm8750 = {
852
848
.clks = sm8750_rpmh_clocks,
853
849
.num_clks = ARRAY_SIZE(sm8750_rpmh_clocks),
850
+
.clka_optional = true,
854
851
};
855
852
856
853
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
···
895
890
rpmh_clk = to_clk_rpmh(hw_clks[i]);
896
891
res_addr = cmd_db_read_addr(rpmh_clk->res_name);
897
892
if (!res_addr) {
893
+
hw_clks[i] = NULL;
894
+
895
+
if (desc->clka_optional &&
896
+
!strncmp(rpmh_clk->res_name, "clka", sizeof("clka") - 1))
897
+
continue;
898
+
898
899
dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
899
900
rpmh_clk->res_name);
900
901
return -ENODEV;
+3
drivers/clk/qcom/dispcc-sm6350.c
+3
drivers/clk/qcom/dispcc-sm6350.c
+2
-2
drivers/clk/qcom/gcc-msm8939.c
+2
-2
drivers/clk/qcom/gcc-msm8939.c
···
432
432
{ P_XO, 0 },
433
433
{ P_GPLL0, 1 },
434
434
{ P_GPLL1_AUX, 2 },
435
-
{ P_GPLL6, 2 },
435
+
{ P_GPLL6, 3 },
436
436
{ P_SLEEP_CLK, 6 },
437
437
};
438
438
···
1113
1113
};
1114
1114
1115
1115
static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk[] = {
1116
-
F(24000000, P_GPLL0, 1, 1, 45),
1116
+
F(24000000, P_GPLL6, 1, 1, 45),
1117
1117
F(66670000, P_GPLL0, 12, 0, 0),
1118
1118
{ }
1119
1119
};
+6
drivers/clk/qcom/gcc-sm6350.c
+6
drivers/clk/qcom/gcc-sm6350.c
···
2320
2320
2321
2321
static struct gdsc usb30_prim_gdsc = {
2322
2322
.gdscr = 0x1a004,
2323
+
.en_rest_wait_val = 0x2,
2324
+
.en_few_wait_val = 0x2,
2325
+
.clk_dis_wait_val = 0xf,
2323
2326
.pd = {
2324
2327
.name = "usb30_prim_gdsc",
2325
2328
},
···
2331
2328
2332
2329
static struct gdsc ufs_phy_gdsc = {
2333
2330
.gdscr = 0x3a004,
2331
+
.en_rest_wait_val = 0x2,
2332
+
.en_few_wait_val = 0x2,
2333
+
.clk_dis_wait_val = 0xf,
2334
2334
.pd = {
2335
2335
.name = "ufs_phy_gdsc",
2336
2336
},
+2
drivers/clk/qcom/gcc-sm8650.c
+2
drivers/clk/qcom/gcc-sm8650.c
···
3817
3817
qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */
3818
3818
qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */
3819
3819
3820
+
/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
3820
3821
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
3822
+
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
3821
3823
3822
3824
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
3823
3825
regmap_write(regmap, 0x52150, 0x0);
+2
-1
drivers/clk/qcom/gcc-sm8750.c
+2
-1
drivers/clk/qcom/gcc-sm8750.c
···
3244
3244
regmap_update_bits(regmap, 0x52010, BIT(20), BIT(20));
3245
3245
regmap_update_bits(regmap, 0x52010, BIT(21), BIT(21));
3246
3246
3247
-
/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3247
+
/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
3248
3248
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
3249
+
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
3249
3250
3250
3251
return qcom_cc_really_probe(&pdev->dev, &gcc_sm8750_desc, regmap);
3251
3252
}
+4
drivers/clk/qcom/gcc-x1e80100.c
+4
drivers/clk/qcom/gcc-x1e80100.c
···
6753
6753
/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
6754
6754
regmap_write(regmap, 0x52224, 0x0);
6755
6755
6756
+
/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
6757
+
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
6758
+
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
6759
+
6756
6760
return qcom_cc_really_probe(&pdev->dev, &gcc_x1e80100_desc, regmap);
6757
6761
}
6758
6762
+6
drivers/clk/qcom/gpucc-sm6350.c
+6
drivers/clk/qcom/gpucc-sm6350.c
···
413
413
static struct gdsc gpu_cx_gdsc = {
414
414
.gdscr = 0x106c,
415
415
.gds_hw_ctrl = 0x1540,
416
+
.en_rest_wait_val = 0x2,
417
+
.en_few_wait_val = 0x2,
418
+
.clk_dis_wait_val = 0x8,
416
419
.pd = {
417
420
.name = "gpu_cx_gdsc",
418
421
},
···
426
423
static struct gdsc gpu_gx_gdsc = {
427
424
.gdscr = 0x100c,
428
425
.clamp_io_ctrl = 0x1508,
426
+
.en_rest_wait_val = 0x2,
427
+
.en_few_wait_val = 0x2,
428
+
.clk_dis_wait_val = 0x2,
429
429
.pd = {
430
430
.name = "gpu_gx_gdsc",
431
431
.power_on = gdsc_gx_do_nothing_enable,
+5
drivers/clk/renesas/Kconfig
+5
drivers/clk/renesas/Kconfig
···
41
41
select CLK_R9A08G045 if ARCH_R9A08G045
42
42
select CLK_R9A09G011 if ARCH_R9A09G011
43
43
select CLK_R9A09G047 if ARCH_R9A09G047
44
+
select CLK_R9A09G056 if ARCH_R9A09G056
44
45
select CLK_R9A09G057 if ARCH_R9A09G057
45
46
select CLK_SH73A0 if ARCH_SH73A0
46
47
···
198
197
199
198
config CLK_R9A09G047
200
199
bool "RZ/G3E clock support" if COMPILE_TEST
200
+
select CLK_RZV2H
201
+
202
+
config CLK_R9A09G056
203
+
bool "RZ/V2N clock support" if COMPILE_TEST
201
204
select CLK_RZV2H
202
205
203
206
config CLK_R9A09G057
+1
drivers/clk/renesas/Makefile
+1
drivers/clk/renesas/Makefile
···
38
38
obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
39
39
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
40
40
obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
41
+
obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o
41
42
obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
42
43
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
43
44
+50
-2
drivers/clk/renesas/r9a09g047-cpg.c
+50
-2
drivers/clk/renesas/r9a09g047-cpg.c
···
16
16
17
17
enum clk_ids {
18
18
/* Core Clock Outputs exported to DT */
19
-
LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK,
19
+
LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
20
20
21
21
/* External Input Clocks */
22
22
CLK_AUDIO_EXTAL,
···
31
31
CLK_PLLVDO,
32
32
33
33
/* Internal Core Clocks */
34
+
CLK_PLLCM33_DIV3,
35
+
CLK_PLLCM33_DIV4,
36
+
CLK_PLLCM33_DIV5,
34
37
CLK_PLLCM33_DIV16,
38
+
CLK_PLLCM33_GEAR,
39
+
CLK_SMUX2_XSPI_CLK0,
40
+
CLK_SMUX2_XSPI_CLK1,
41
+
CLK_PLLCM33_XSPI,
35
42
CLK_PLLCLN_DIV2,
36
43
CLK_PLLCLN_DIV8,
37
44
CLK_PLLCLN_DIV16,
···
48
41
CLK_PLLDTY_ACPU_DIV4,
49
42
CLK_PLLDTY_DIV16,
50
43
CLK_PLLVDO_CRU0,
44
+
CLK_PLLVDO_GPU,
51
45
52
46
/* Module Clocks */
53
47
MOD_CLK_BASE,
···
68
60
{0, 0},
69
61
};
70
62
63
+
static const struct clk_div_table dtable_2_16[] = {
64
+
{0, 2},
65
+
{1, 4},
66
+
{2, 8},
67
+
{3, 16},
68
+
{0, 0},
69
+
};
70
+
71
71
static const struct clk_div_table dtable_2_64[] = {
72
72
{0, 2},
73
73
{1, 4},
···
84
68
{4, 64},
85
69
{0, 0},
86
70
};
71
+
72
+
/* Mux clock tables */
73
+
static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" };
74
+
static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" };
87
75
88
76
static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
89
77
/* External Clock Inputs */
···
99
79
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
100
80
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
101
81
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
102
-
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
82
+
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
103
83
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
104
84
105
85
/* Internal Core Clocks */
86
+
DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
87
+
DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
88
+
DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5),
106
89
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
107
90
91
+
DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
92
+
93
+
DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0),
94
+
DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
95
+
DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
96
+
dtable_2_16),
108
97
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
109
98
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
110
99
DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),
···
125
96
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
126
97
127
98
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
99
+
DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
128
100
129
101
/* Core Clocks */
130
102
DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
···
138
108
DEF_DDIV("ca55_0_coreclk3", R9A09G047_CA55_0_CORECLK3, CLK_PLLCA55,
139
109
CDDIV1_DIVCTL3, dtable_1_8),
140
110
DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
111
+
DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
141
112
};
142
113
143
114
static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
···
184
153
BUS_MSTOP(10, BIT(14))),
185
154
DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30,
186
155
BUS_MSTOP(10, BIT(14))),
156
+
DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
157
+
BUS_MSTOP(4, BIT(5))),
158
+
DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0,
159
+
BUS_MSTOP(4, BIT(5))),
160
+
DEF_MOD_NO_PM("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2,
161
+
BUS_MSTOP(4, BIT(5))),
187
162
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
188
163
BUS_MSTOP(8, BIT(2))),
189
164
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
···
220
183
BUS_MSTOP(9, BIT(4))),
221
184
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
222
185
BUS_MSTOP(9, BIT(4))),
186
+
DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,
187
+
BUS_MSTOP(3, BIT(4))),
188
+
DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
189
+
BUS_MSTOP(3, BIT(4))),
190
+
DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
191
+
BUS_MSTOP(3, BIT(4))),
223
192
DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
224
193
BUS_MSTOP(2, BIT(15))),
225
194
};
···
250
207
DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */
251
208
DEF_RST(10, 1, 4, 18), /* CANFD_0_RSTP_N */
252
209
DEF_RST(10, 2, 4, 19), /* CANFD_0_RSTC_N */
210
+
DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
211
+
DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */
253
212
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
254
213
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
255
214
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
256
215
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
257
216
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
258
217
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
218
+
DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */
219
+
DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */
220
+
DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */
259
221
DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
260
222
};
261
223
+152
drivers/clk/renesas/r9a09g056-cpg.c
+152
drivers/clk/renesas/r9a09g056-cpg.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Renesas RZ/V2N CPG driver
4
+
*
5
+
* Copyright (C) 2025 Renesas Electronics Corp.
6
+
*/
7
+
8
+
#include <linux/clk-provider.h>
9
+
#include <linux/device.h>
10
+
#include <linux/init.h>
11
+
#include <linux/kernel.h>
12
+
13
+
#include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
14
+
15
+
#include "rzv2h-cpg.h"
16
+
17
+
enum clk_ids {
18
+
/* Core Clock Outputs exported to DT */
19
+
LAST_DT_CORE_CLK = R9A09G056_GBETH_1_CLK_PTP_REF_I,
20
+
21
+
/* External Input Clocks */
22
+
CLK_AUDIO_EXTAL,
23
+
CLK_RTXIN,
24
+
CLK_QEXTAL,
25
+
26
+
/* PLL Clocks */
27
+
CLK_PLLCM33,
28
+
CLK_PLLCLN,
29
+
CLK_PLLDTY,
30
+
CLK_PLLCA55,
31
+
32
+
/* Internal Core Clocks */
33
+
CLK_PLLCM33_DIV16,
34
+
CLK_PLLCLN_DIV2,
35
+
CLK_PLLCLN_DIV8,
36
+
CLK_PLLDTY_ACPU,
37
+
CLK_PLLDTY_ACPU_DIV4,
38
+
39
+
/* Module Clocks */
40
+
MOD_CLK_BASE,
41
+
};
42
+
43
+
static const struct clk_div_table dtable_1_8[] = {
44
+
{0, 1},
45
+
{1, 2},
46
+
{2, 4},
47
+
{3, 8},
48
+
{0, 0},
49
+
};
50
+
51
+
static const struct clk_div_table dtable_2_64[] = {
52
+
{0, 2},
53
+
{1, 4},
54
+
{2, 8},
55
+
{3, 16},
56
+
{4, 64},
57
+
{0, 0},
58
+
};
59
+
60
+
static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
61
+
/* External Clock Inputs */
62
+
DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
63
+
DEF_INPUT("rtxin", CLK_RTXIN),
64
+
DEF_INPUT("qextal", CLK_QEXTAL),
65
+
66
+
/* PLL Clocks */
67
+
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
68
+
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
69
+
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
70
+
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
71
+
72
+
/* Internal Core Clocks */
73
+
DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
74
+
75
+
DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
76
+
DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
77
+
78
+
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
79
+
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
80
+
81
+
/* Core Clocks */
82
+
DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
83
+
DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55,
84
+
CDDIV1_DIVCTL0, dtable_1_8),
85
+
DEF_DDIV("ca55_0_coreclk1", R9A09G056_CA55_0_CORE_CLK1, CLK_PLLCA55,
86
+
CDDIV1_DIVCTL1, dtable_1_8),
87
+
DEF_DDIV("ca55_0_coreclk2", R9A09G056_CA55_0_CORE_CLK2, CLK_PLLCA55,
88
+
CDDIV1_DIVCTL2, dtable_1_8),
89
+
DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55,
90
+
CDDIV1_DIVCTL3, dtable_1_8),
91
+
DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
92
+
};
93
+
94
+
static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
95
+
DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
96
+
BUS_MSTOP(3, BIT(5))),
97
+
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
98
+
BUS_MSTOP(3, BIT(14))),
99
+
DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
100
+
BUS_MSTOP(8, BIT(2))),
101
+
DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4,
102
+
BUS_MSTOP(8, BIT(2))),
103
+
DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5,
104
+
BUS_MSTOP(8, BIT(2))),
105
+
DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
106
+
BUS_MSTOP(8, BIT(2))),
107
+
DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7,
108
+
BUS_MSTOP(8, BIT(3))),
109
+
DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8,
110
+
BUS_MSTOP(8, BIT(3))),
111
+
DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
112
+
BUS_MSTOP(8, BIT(3))),
113
+
DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
114
+
BUS_MSTOP(8, BIT(3))),
115
+
DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
116
+
BUS_MSTOP(8, BIT(4))),
117
+
DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12,
118
+
BUS_MSTOP(8, BIT(4))),
119
+
DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13,
120
+
BUS_MSTOP(8, BIT(4))),
121
+
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
122
+
BUS_MSTOP(8, BIT(4))),
123
+
};
124
+
125
+
static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
126
+
DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
127
+
DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
128
+
DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
129
+
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
130
+
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
131
+
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
132
+
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
133
+
};
134
+
135
+
const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {
136
+
/* Core Clocks */
137
+
.core_clks = r9a09g056_core_clks,
138
+
.num_core_clks = ARRAY_SIZE(r9a09g056_core_clks),
139
+
.last_dt_core_clk = LAST_DT_CORE_CLK,
140
+
.num_total_core_clks = MOD_CLK_BASE,
141
+
142
+
/* Module Clocks */
143
+
.mod_clks = r9a09g056_mod_clks,
144
+
.num_mod_clks = ARRAY_SIZE(r9a09g056_mod_clks),
145
+
.num_hw_mod_clks = 25 * 16,
146
+
147
+
/* Resets */
148
+
.resets = r9a09g056_resets,
149
+
.num_resets = ARRAY_SIZE(r9a09g056_resets),
150
+
151
+
.num_mstop_bits = 192,
152
+
};
+34
-2
drivers/clk/renesas/r9a09g057-cpg.c
+34
-2
drivers/clk/renesas/r9a09g057-cpg.c
···
16
16
17
17
enum clk_ids {
18
18
/* Core Clock Outputs exported to DT */
19
-
LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK,
19
+
LAST_DT_CORE_CLK = R9A09G057_GBETH_1_CLK_PTP_REF_I,
20
20
21
21
/* External Input Clocks */
22
22
CLK_AUDIO_EXTAL,
···
29
29
CLK_PLLDTY,
30
30
CLK_PLLCA55,
31
31
CLK_PLLVDO,
32
+
CLK_PLLGPU,
32
33
33
34
/* Internal Core Clocks */
34
35
CLK_PLLCM33_DIV4,
···
41
40
CLK_PLLDTY_ACPU,
42
41
CLK_PLLDTY_ACPU_DIV2,
43
42
CLK_PLLDTY_ACPU_DIV4,
43
+
CLK_PLLDTY_DIV8,
44
44
CLK_PLLDTY_DIV16,
45
45
CLK_PLLDTY_RCPU,
46
46
CLK_PLLDTY_RCPU_DIV4,
···
49
47
CLK_PLLVDO_CRU1,
50
48
CLK_PLLVDO_CRU2,
51
49
CLK_PLLVDO_CRU3,
50
+
CLK_PLLGPU_GEAR,
52
51
53
52
/* Module Clocks */
54
53
MOD_CLK_BASE,
···
88
85
DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
89
86
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
90
87
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
91
-
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
88
+
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
92
89
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
90
+
DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
93
91
94
92
/* Internal Core Clocks */
95
93
DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4),
···
105
101
DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
106
102
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
107
103
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
104
+
DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
108
105
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
109
106
DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64),
110
107
DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4),
···
114
109
DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
115
110
DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4),
116
111
DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4),
112
+
113
+
DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
117
114
118
115
/* Core Clocks */
119
116
DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
···
128
121
DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55,
129
122
CDDIV1_DIVCTL3, dtable_1_8),
130
123
DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
124
+
DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
125
+
DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
131
126
};
132
127
133
128
static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
···
223
214
BUS_MSTOP(8, BIT(4))),
224
215
DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
225
216
BUS_MSTOP(8, BIT(4))),
217
+
DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
218
+
BUS_MSTOP(7, BIT(7))),
219
+
DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
220
+
BUS_MSTOP(7, BIT(8))),
221
+
DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
222
+
BUS_MSTOP(7, BIT(9))),
223
+
DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
224
+
BUS_MSTOP(7, BIT(10))),
225
+
DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
226
+
BUS_MSTOP(7, BIT(11))),
226
227
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
227
228
BUS_MSTOP(9, BIT(4))),
228
229
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
···
257
238
BUS_MSTOP(9, BIT(7))),
258
239
DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29,
259
240
BUS_MSTOP(9, BIT(7))),
241
+
DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
242
+
BUS_MSTOP(3, BIT(4))),
243
+
DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
244
+
BUS_MSTOP(3, BIT(4))),
245
+
DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
246
+
BUS_MSTOP(3, BIT(4))),
260
247
};
261
248
262
249
static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
···
300
275
DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */
301
276
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
302
277
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
278
+
DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
279
+
DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
280
+
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
281
+
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
303
282
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
304
283
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
305
284
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
···
316
287
DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */
317
288
DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */
318
289
DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */
290
+
DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
291
+
DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
292
+
DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */
319
293
};
320
294
321
295
const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = {
+2
-1
drivers/clk/renesas/renesas-cpg-mssr.c
+2
-1
drivers/clk/renesas/renesas-cpg-mssr.c
···
27
27
#include <linux/psci.h>
28
28
#include <linux/reset-controller.h>
29
29
#include <linux/slab.h>
30
+
#include <linux/string_choices.h>
30
31
31
32
#include <dt-bindings/clock/renesas-cpg-mssr.h>
32
33
···
205
204
int error;
206
205
207
206
dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
208
-
enable ? "ON" : "OFF");
207
+
str_on_off(enable));
209
208
spin_lock_irqsave(&priv->rmw_lock, flags);
210
209
211
210
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
+2
-1
drivers/clk/renesas/rzg2l-cpg.c
+2
-1
drivers/clk/renesas/rzg2l-cpg.c
···
27
27
#include <linux/pm_domain.h>
28
28
#include <linux/reset-controller.h>
29
29
#include <linux/slab.h>
30
+
#include <linux/string_choices.h>
30
31
#include <linux/units.h>
31
32
32
33
#include <dt-bindings/clock/renesas-cpg-mssr.h>
···
1218
1217
}
1219
1218
1220
1219
dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", CLK_ON_R(reg), hw->clk,
1221
-
enable ? "ON" : "OFF");
1220
+
str_on_off(enable));
1222
1221
1223
1222
value = bitmask << 16;
1224
1223
if (enable)
+135
-51
drivers/clk/renesas/rzv2h-cpg.c
+135
-51
drivers/clk/renesas/rzv2h-cpg.c
···
25
25
#include <linux/pm_domain.h>
26
26
#include <linux/refcount.h>
27
27
#include <linux/reset-controller.h>
28
+
#include <linux/string_choices.h>
28
29
29
30
#include <dt-bindings/clock/renesas-cpg-mssr.h>
30
31
···
45
44
#define CPG_BUS_1_MSTOP (0xd00)
46
45
#define CPG_BUS_MSTOP(m) (CPG_BUS_1_MSTOP + ((m) - 1) * 4)
47
46
48
-
#define KDIV(val) ((s16)FIELD_GET(GENMASK(31, 16), (val)))
49
-
#define MDIV(val) FIELD_GET(GENMASK(15, 6), (val))
50
-
#define PDIV(val) FIELD_GET(GENMASK(5, 0), (val))
51
-
#define SDIV(val) FIELD_GET(GENMASK(2, 0), (val))
47
+
#define CPG_PLL_STBY(x) ((x))
48
+
#define CPG_PLL_STBY_RESETB BIT(0)
49
+
#define CPG_PLL_STBY_RESETB_WEN BIT(16)
50
+
#define CPG_PLL_CLK1(x) ((x) + 0x004)
51
+
#define CPG_PLL_CLK1_KDIV(x) ((s16)FIELD_GET(GENMASK(31, 16), (x)))
52
+
#define CPG_PLL_CLK1_MDIV(x) FIELD_GET(GENMASK(15, 6), (x))
53
+
#define CPG_PLL_CLK1_PDIV(x) FIELD_GET(GENMASK(5, 0), (x))
54
+
#define CPG_PLL_CLK2(x) ((x) + 0x008)
55
+
#define CPG_PLL_CLK2_SDIV(x) FIELD_GET(GENMASK(2, 0), (x))
56
+
#define CPG_PLL_MON(x) ((x) + 0x010)
57
+
#define CPG_PLL_MON_RESETB BIT(0)
58
+
#define CPG_PLL_MON_LOCK BIT(4)
52
59
53
60
#define DDIV_DIVCTL_WEN(shift) BIT((shift) + 16)
54
61
···
103
94
struct rzv2h_cpg_priv *priv;
104
95
void __iomem *base;
105
96
struct clk_hw hw;
106
-
unsigned int conf;
107
-
unsigned int type;
97
+
struct pll pll;
108
98
};
109
99
110
100
#define to_pll(_hw) container_of(_hw, struct pll_clk, hw)
···
118
110
* @on_index: register offset
119
111
* @on_bit: ON/MON bit
120
112
* @mon_index: monitor register offset
121
-
* @mon_bit: montor bit
113
+
* @mon_bit: monitor bit
122
114
*/
123
115
struct mod_clock {
124
116
struct rzv2h_cpg_priv *priv;
···
148
140
149
141
#define to_ddiv_clock(_div) container_of(_div, struct ddiv_clk, div)
150
142
143
+
static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw)
144
+
{
145
+
struct pll_clk *pll_clk = to_pll(hw);
146
+
struct rzv2h_cpg_priv *priv = pll_clk->priv;
147
+
u32 val = readl(priv->base + CPG_PLL_MON(pll_clk->pll.offset));
148
+
149
+
/* Ensure both RESETB and LOCK bits are set */
150
+
return (val & (CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK)) ==
151
+
(CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK);
152
+
}
153
+
154
+
static int rzv2h_cpg_pll_clk_enable(struct clk_hw *hw)
155
+
{
156
+
struct pll_clk *pll_clk = to_pll(hw);
157
+
struct rzv2h_cpg_priv *priv = pll_clk->priv;
158
+
struct pll pll = pll_clk->pll;
159
+
u32 stby_offset;
160
+
u32 mon_offset;
161
+
u32 val;
162
+
int ret;
163
+
164
+
if (rzv2h_cpg_pll_clk_is_enabled(hw))
165
+
return 0;
166
+
167
+
stby_offset = CPG_PLL_STBY(pll.offset);
168
+
mon_offset = CPG_PLL_MON(pll.offset);
169
+
170
+
writel(CPG_PLL_STBY_RESETB_WEN | CPG_PLL_STBY_RESETB,
171
+
priv->base + stby_offset);
172
+
173
+
/*
174
+
* Ensure PLL enters into normal mode
175
+
*
176
+
* Note: There is no HW information about the worst case latency.
177
+
*
178
+
* Since this latency might depend on external crystal or PLL rate,
179
+
* use a "super" safe timeout value.
180
+
*/
181
+
ret = readl_poll_timeout_atomic(priv->base + mon_offset, val,
182
+
(val & (CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK)) ==
183
+
(CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK), 200, 2000);
184
+
if (ret)
185
+
dev_err(priv->dev, "Failed to enable PLL 0x%x/%pC\n",
186
+
stby_offset, hw->clk);
187
+
188
+
return ret;
189
+
}
190
+
151
191
static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
152
192
unsigned long parent_rate)
153
193
{
154
194
struct pll_clk *pll_clk = to_pll(hw);
155
195
struct rzv2h_cpg_priv *priv = pll_clk->priv;
196
+
struct pll pll = pll_clk->pll;
156
197
unsigned int clk1, clk2;
157
198
u64 rate;
158
199
159
-
if (!PLL_CLK_ACCESS(pll_clk->conf))
200
+
if (!pll.has_clkn)
160
201
return 0;
161
202
162
-
clk1 = readl(priv->base + PLL_CLK1_OFFSET(pll_clk->conf));
163
-
clk2 = readl(priv->base + PLL_CLK2_OFFSET(pll_clk->conf));
203
+
clk1 = readl(priv->base + CPG_PLL_CLK1(pll.offset));
204
+
clk2 = readl(priv->base + CPG_PLL_CLK2(pll.offset));
164
205
165
-
rate = mul_u64_u32_shr(parent_rate, (MDIV(clk1) << 16) + KDIV(clk1),
166
-
16 + SDIV(clk2));
206
+
rate = mul_u64_u32_shr(parent_rate, (CPG_PLL_CLK1_MDIV(clk1) << 16) +
207
+
CPG_PLL_CLK1_KDIV(clk1), 16 + CPG_PLL_CLK2_SDIV(clk2));
167
208
168
-
return DIV_ROUND_CLOSEST_ULL(rate, PDIV(clk1));
209
+
return DIV_ROUND_CLOSEST_ULL(rate, CPG_PLL_CLK1_PDIV(clk1));
169
210
}
170
211
171
212
static const struct clk_ops rzv2h_cpg_pll_ops = {
213
+
.is_enabled = rzv2h_cpg_pll_clk_is_enabled,
214
+
.enable = rzv2h_cpg_pll_clk_enable,
172
215
.recalc_rate = rzv2h_cpg_pll_clk_recalc_rate,
173
216
};
174
217
···
252
193
init.num_parents = 1;
253
194
254
195
pll_clk->hw.init = &init;
255
-
pll_clk->conf = core->cfg.conf;
196
+
pll_clk->pll = core->cfg.pll;
256
197
pll_clk->base = base;
257
198
pll_clk->priv = priv;
258
-
pll_clk->type = core->type;
259
199
260
200
ret = devm_clk_hw_register(dev, &pll_clk->hw);
261
201
if (ret)
···
299
241
u32 bitmask = BIT(mon);
300
242
u32 val;
301
243
244
+
if (mon == CSDIV_NO_MON)
245
+
return 0;
246
+
302
247
return readl_poll_timeout_atomic(base + CPG_CLKSTATUS0, val, !(val & bitmask), 10, 200);
303
248
}
304
249
···
333
272
writel(val, divider->reg);
334
273
335
274
ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);
336
-
if (ret)
337
-
goto ddiv_timeout;
338
-
339
-
spin_unlock_irqrestore(divider->lock, flags);
340
-
341
-
return 0;
342
275
343
276
ddiv_timeout:
344
277
spin_unlock_irqrestore(divider->lock, flags);
···
375
320
return ERR_PTR(-ENOMEM);
376
321
377
322
init.name = core->name;
378
-
init.ops = &rzv2h_ddiv_clk_divider_ops;
323
+
if (cfg_ddiv.no_rmw)
324
+
init.ops = &clk_divider_ops;
325
+
else
326
+
init.ops = &rzv2h_ddiv_clk_divider_ops;
379
327
init.parent_names = &parent_name;
380
328
init.num_parents = 1;
381
329
···
398
340
return ERR_PTR(ret);
399
341
400
342
return div->hw.clk;
343
+
}
344
+
345
+
static struct clk * __init
346
+
rzv2h_cpg_mux_clk_register(const struct cpg_core_clk *core,
347
+
struct rzv2h_cpg_priv *priv)
348
+
{
349
+
struct smuxed mux = core->cfg.smux;
350
+
const struct clk_hw *clk_hw;
351
+
352
+
clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
353
+
core->parent_names, core->num_parents,
354
+
core->flag, priv->base + mux.offset,
355
+
mux.shift, mux.width,
356
+
core->mux_flags, &priv->rmw_lock);
357
+
if (IS_ERR(clk_hw))
358
+
return ERR_CAST(clk_hw);
359
+
360
+
return clk_hw->clk;
401
361
}
402
362
403
363
static struct clk
···
502
426
case CLK_TYPE_DDIV:
503
427
clk = rzv2h_cpg_ddiv_clk_register(core, priv);
504
428
break;
429
+
case CLK_TYPE_SMUX:
430
+
clk = rzv2h_cpg_mux_clk_register(core, priv);
431
+
break;
505
432
default:
506
433
goto fail;
507
434
}
···
573
494
if (clock->mon_index >= 0) {
574
495
offset = GET_CLK_MON_OFFSET(clock->mon_index);
575
496
bitmask = BIT(clock->mon_bit);
576
-
} else {
577
-
offset = GET_CLK_ON_OFFSET(clock->on_index);
578
-
bitmask = BIT(clock->on_bit);
497
+
498
+
if (!(readl(priv->base + offset) & bitmask))
499
+
return 0;
579
500
}
501
+
502
+
offset = GET_CLK_ON_OFFSET(clock->on_index);
503
+
bitmask = BIT(clock->on_bit);
580
504
581
505
return readl(priv->base + offset) & bitmask;
582
506
}
···
596
514
int error;
597
515
598
516
dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,
599
-
enable ? "ON" : "OFF");
517
+
str_on_off(enable));
600
518
601
519
if (enabled == enable)
602
520
return 0;
···
740
658
mod->name, PTR_ERR(clk));
741
659
}
742
660
743
-
static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
744
-
unsigned long id)
661
+
static int __rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
662
+
unsigned long id, bool assert)
745
663
{
746
664
struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
747
665
unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
···
749
667
u8 monbit = priv->resets[id].mon_bit;
750
668
u32 value = mask << 16;
751
669
752
-
dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, reg);
670
+
dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",
671
+
assert ? "assert" : "deassert", id, reg);
753
672
673
+
if (!assert)
674
+
value |= mask;
754
675
writel(value, priv->base + reg);
755
676
756
677
reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
757
678
mask = BIT(monbit);
758
679
759
680
return readl_poll_timeout_atomic(priv->base + reg, value,
760
-
value & mask, 10, 200);
681
+
assert ? (value & mask) : !(value & mask),
682
+
10, 200);
683
+
}
684
+
685
+
static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
686
+
unsigned long id)
687
+
{
688
+
return __rzv2h_cpg_assert(rcdev, id, true);
761
689
}
762
690
763
691
static int rzv2h_cpg_deassert(struct reset_controller_dev *rcdev,
764
692
unsigned long id)
765
693
{
766
-
struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
767
-
unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);
768
-
u32 mask = BIT(priv->resets[id].reset_bit);
769
-
u8 monbit = priv->resets[id].mon_bit;
770
-
u32 value = (mask << 16) | mask;
771
-
772
-
dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, reg);
773
-
774
-
writel(value, priv->base + reg);
775
-
776
-
reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);
777
-
mask = BIT(monbit);
778
-
779
-
return readl_poll_timeout_atomic(priv->base + reg, value,
780
-
!(value & mask), 10, 200);
694
+
return __rzv2h_cpg_assert(rcdev, id, false);
781
695
}
782
696
783
697
static int rzv2h_cpg_reset(struct reset_controller_dev *rcdev,
···
1045
967
}
1046
968
1047
969
static const struct of_device_id rzv2h_cpg_match[] = {
1048
-
#ifdef CONFIG_CLK_R9A09G057
1049
-
{
1050
-
.compatible = "renesas,r9a09g057-cpg",
1051
-
.data = &r9a09g057_cpg_info,
1052
-
},
1053
-
#endif
1054
970
#ifdef CONFIG_CLK_R9A09G047
1055
971
{
1056
972
.compatible = "renesas,r9a09g047-cpg",
1057
973
.data = &r9a09g047_cpg_info,
974
+
},
975
+
#endif
976
+
#ifdef CONFIG_CLK_R9A09G056
977
+
{
978
+
.compatible = "renesas,r9a09g056-cpg",
979
+
.data = &r9a09g056_cpg_info,
980
+
},
981
+
#endif
982
+
#ifdef CONFIG_CLK_R9A09G057
983
+
{
984
+
.compatible = "renesas,r9a09g057-cpg",
985
+
.data = &r9a09g057_cpg_info,
1058
986
},
1059
987
#endif
1060
988
{ /* sentinel */ }
+86
-8
drivers/clk/renesas/rzv2h-cpg.h
+86
-8
drivers/clk/renesas/rzv2h-cpg.h
···
11
11
#include <linux/bitfield.h>
12
12
13
13
/**
14
+
* struct pll - Structure for PLL configuration
15
+
*
16
+
* @offset: STBY register offset
17
+
* @has_clkn: Flag to indicate if CLK1/2 are accessible or not
18
+
*/
19
+
struct pll {
20
+
unsigned int offset:9;
21
+
unsigned int has_clkn:1;
22
+
};
23
+
24
+
#define PLL_PACK(_offset, _has_clkn) \
25
+
((struct pll){ \
26
+
.offset = _offset, \
27
+
.has_clkn = _has_clkn \
28
+
})
29
+
30
+
#define PLLCA55 PLL_PACK(0x60, 1)
31
+
#define PLLGPU PLL_PACK(0x120, 1)
32
+
33
+
/**
14
34
* struct ddiv - Structure for dynamic switching divider
15
35
*
16
36
* @offset: register offset
17
37
* @shift: position of the divider bit
18
38
* @width: width of the divider
19
39
* @monbit: monitor bit in CPG_CLKSTATUS0 register
40
+
* @no_rmw: flag to indicate if the register is read-modify-write
41
+
* (1: no RMW, 0: RMW)
20
42
*/
21
43
struct ddiv {
22
44
unsigned int offset:11;
23
45
unsigned int shift:4;
24
46
unsigned int width:4;
25
47
unsigned int monbit:5;
48
+
unsigned int no_rmw:1;
26
49
};
50
+
51
+
/*
52
+
* On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits,
53
+
* while on RZ/G3E, it supports up to 16 monitor bits. Use the maximum value
54
+
* `0x1f` to indicate that monitor bits are not supported for static divider
55
+
* clocks.
56
+
*/
57
+
#define CSDIV_NO_MON (0x1f)
27
58
28
59
#define DDIV_PACK(_offset, _shift, _width, _monbit) \
29
60
((struct ddiv){ \
···
64
33
.monbit = _monbit \
65
34
})
66
35
36
+
#define DDIV_PACK_NO_RMW(_offset, _shift, _width, _monbit) \
37
+
((struct ddiv){ \
38
+
.offset = (_offset), \
39
+
.shift = (_shift), \
40
+
.width = (_width), \
41
+
.monbit = (_monbit), \
42
+
.no_rmw = 1 \
43
+
})
44
+
45
+
/**
46
+
* struct smuxed - Structure for static muxed clocks
47
+
*
48
+
* @offset: register offset
49
+
* @shift: position of the divider field
50
+
* @width: width of the divider field
51
+
*/
52
+
struct smuxed {
53
+
unsigned int offset:11;
54
+
unsigned int shift:4;
55
+
unsigned int width:4;
56
+
};
57
+
58
+
#define SMUX_PACK(_offset, _shift, _width) \
59
+
((struct smuxed){ \
60
+
.offset = (_offset), \
61
+
.shift = (_shift), \
62
+
.width = (_width), \
63
+
})
64
+
65
+
#define CPG_SSEL1 (0x304)
67
66
#define CPG_CDDIV0 (0x400)
68
67
#define CPG_CDDIV1 (0x404)
69
68
#define CPG_CDDIV3 (0x40C)
70
69
#define CPG_CDDIV4 (0x410)
70
+
#define CPG_CSDIV0 (0x500)
71
71
72
72
#define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1)
73
73
#define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2)
···
106
44
#define CDDIV1_DIVCTL1 DDIV_PACK(CPG_CDDIV1, 4, 2, 5)
107
45
#define CDDIV1_DIVCTL2 DDIV_PACK(CPG_CDDIV1, 8, 2, 6)
108
46
#define CDDIV1_DIVCTL3 DDIV_PACK(CPG_CDDIV1, 12, 2, 7)
47
+
#define CDDIV3_DIVCTL1 DDIV_PACK(CPG_CDDIV3, 4, 3, 13)
109
48
#define CDDIV3_DIVCTL2 DDIV_PACK(CPG_CDDIV3, 8, 3, 14)
110
49
#define CDDIV3_DIVCTL3 DDIV_PACK(CPG_CDDIV3, 12, 1, 15)
111
50
#define CDDIV4_DIVCTL0 DDIV_PACK(CPG_CDDIV4, 0, 1, 16)
112
51
#define CDDIV4_DIVCTL1 DDIV_PACK(CPG_CDDIV4, 4, 1, 17)
113
52
#define CDDIV4_DIVCTL2 DDIV_PACK(CPG_CDDIV4, 8, 1, 18)
53
+
54
+
#define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
55
+
56
+
#define SSEL1_SELCTL2 SMUX_PACK(CPG_SSEL1, 8, 1)
57
+
#define SSEL1_SELCTL3 SMUX_PACK(CPG_SSEL1, 12, 1)
114
58
115
59
#define BUS_MSTOP_IDX_MASK GENMASK(31, 16)
116
60
#define BUS_MSTOP_BITS_MASK GENMASK(15, 0)
···
142
74
union {
143
75
unsigned int conf;
144
76
struct ddiv ddiv;
77
+
struct pll pll;
78
+
struct smuxed smux;
145
79
} cfg;
146
80
const struct clk_div_table *dtable;
81
+
const char * const *parent_names;
82
+
unsigned int num_parents;
83
+
u8 mux_flags;
147
84
u32 flag;
148
85
};
149
86
···
158
85
CLK_TYPE_FF, /* Fixed Factor Clock */
159
86
CLK_TYPE_PLL,
160
87
CLK_TYPE_DDIV, /* Dynamic Switching Divider */
88
+
CLK_TYPE_SMUX, /* Static Mux */
161
89
};
162
-
163
-
/* BIT(31) indicates if CLK1/2 are accessible or not */
164
-
#define PLL_CONF(n) (BIT(31) | ((n) & ~GENMASK(31, 16)))
165
-
#define PLL_CLK_ACCESS(n) ((n) & BIT(31) ? 1 : 0)
166
-
#define PLL_CLK1_OFFSET(n) ((n) & ~GENMASK(31, 16))
167
-
#define PLL_CLK2_OFFSET(n) (((n) & ~GENMASK(31, 16)) + (0x4))
168
90
169
91
#define DEF_TYPE(_name, _id, _type...) \
170
92
{ .name = _name, .id = _id, .type = _type }
171
93
#define DEF_BASE(_name, _id, _type, _parent...) \
172
94
DEF_TYPE(_name, _id, _type, .parent = _parent)
173
-
#define DEF_PLL(_name, _id, _parent, _conf) \
174
-
DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.conf = _conf)
95
+
#define DEF_PLL(_name, _id, _parent, _pll_packed) \
96
+
DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .cfg.pll = _pll_packed)
175
97
#define DEF_INPUT(_name, _id) \
176
98
DEF_TYPE(_name, _id, CLK_TYPE_IN)
177
99
#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
···
177
109
.parent = _parent, \
178
110
.dtable = _dtable, \
179
111
.flag = CLK_DIVIDER_HIWORD_MASK)
112
+
#define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
113
+
DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable)
114
+
#define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \
115
+
DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \
116
+
.cfg.smux = _smux_packed, \
117
+
.parent_names = _parent_names, \
118
+
.num_parents = ARRAY_SIZE(_parent_names), \
119
+
.flag = CLK_SET_RATE_PARENT, \
120
+
.mux_flags = CLK_MUX_HIWORD_MASK)
180
121
181
122
/**
182
123
* struct rzv2h_mod_clk - Module Clocks definitions
···
298
221
};
299
222
300
223
extern const struct rzv2h_cpg_info r9a09g047_cpg_info;
224
+
extern const struct rzv2h_cpg_info r9a09g056_cpg_info;
301
225
extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
302
226
303
227
#endif /* __RENESAS_RZV2H_CPG_H__ */
+1
drivers/clk/rockchip/Makefile
+1
drivers/clk/rockchip/Makefile
+105
drivers/clk/rockchip/clk-gate-grf.c
+105
drivers/clk/rockchip/clk-gate-grf.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Copyright (c) 2025 Collabora Ltd.
4
+
* Author: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
5
+
*
6
+
* Certain clocks on Rockchip are "gated" behind an additional register bit
7
+
* write in a GRF register, such as the SAI MCLKs on RK3576. This code
8
+
* implements a clock driver for these types of gates, based on regmaps.
9
+
*/
10
+
11
+
#include <linux/clk.h>
12
+
#include <linux/clk-provider.h>
13
+
#include <linux/regmap.h>
14
+
#include <linux/slab.h>
15
+
#include "clk.h"
16
+
17
+
struct rockchip_gate_grf {
18
+
struct clk_hw hw;
19
+
struct regmap *regmap;
20
+
unsigned int reg;
21
+
unsigned int shift;
22
+
u8 flags;
23
+
};
24
+
25
+
#define to_gate_grf(_hw) container_of(_hw, struct rockchip_gate_grf, hw)
26
+
27
+
static int rockchip_gate_grf_enable(struct clk_hw *hw)
28
+
{
29
+
struct rockchip_gate_grf *gate = to_gate_grf(hw);
30
+
u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? BIT(gate->shift) : 0;
31
+
u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16);
32
+
int ret;
33
+
34
+
ret = regmap_update_bits(gate->regmap, gate->reg,
35
+
hiword | BIT(gate->shift), hiword | val);
36
+
37
+
return ret;
38
+
}
39
+
40
+
static void rockchip_gate_grf_disable(struct clk_hw *hw)
41
+
{
42
+
struct rockchip_gate_grf *gate = to_gate_grf(hw);
43
+
u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : BIT(gate->shift);
44
+
u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16);
45
+
46
+
regmap_update_bits(gate->regmap, gate->reg,
47
+
hiword | BIT(gate->shift), hiword | val);
48
+
}
49
+
50
+
static int rockchip_gate_grf_is_enabled(struct clk_hw *hw)
51
+
{
52
+
struct rockchip_gate_grf *gate = to_gate_grf(hw);
53
+
bool invert = !!(gate->flags & CLK_GATE_SET_TO_DISABLE);
54
+
int ret;
55
+
56
+
ret = regmap_test_bits(gate->regmap, gate->reg, BIT(gate->shift));
57
+
if (ret < 0)
58
+
ret = 0;
59
+
60
+
return invert ? 1 - ret : ret;
61
+
62
+
}
63
+
64
+
static const struct clk_ops rockchip_gate_grf_ops = {
65
+
.enable = rockchip_gate_grf_enable,
66
+
.disable = rockchip_gate_grf_disable,
67
+
.is_enabled = rockchip_gate_grf_is_enabled,
68
+
};
69
+
70
+
struct clk *rockchip_clk_register_gate_grf(const char *name,
71
+
const char *parent_name, unsigned long flags,
72
+
struct regmap *regmap, unsigned int reg, unsigned int shift,
73
+
u8 gate_flags)
74
+
{
75
+
struct rockchip_gate_grf *gate;
76
+
struct clk_init_data init;
77
+
struct clk *clk;
78
+
79
+
if (IS_ERR(regmap)) {
80
+
pr_err("%s: regmap not available\n", __func__);
81
+
return ERR_PTR(-EOPNOTSUPP);
82
+
}
83
+
84
+
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
85
+
if (!gate)
86
+
return ERR_PTR(-ENOMEM);
87
+
88
+
init.name = name;
89
+
init.flags = flags;
90
+
init.num_parents = parent_name ? 1 : 0;
91
+
init.parent_names = parent_name ? &parent_name : NULL;
92
+
init.ops = &rockchip_gate_grf_ops;
93
+
94
+
gate->hw.init = &init;
95
+
gate->regmap = regmap;
96
+
gate->reg = reg;
97
+
gate->shift = shift;
98
+
gate->flags = gate_flags;
99
+
100
+
clk = clk_register(NULL, &gate->hw);
101
+
if (IS_ERR(clk))
102
+
kfree(gate);
103
+
104
+
return clk;
105
+
}
+20
-4
drivers/clk/rockchip/clk-mmc-phase.c
+20
-4
drivers/clk/rockchip/clk-mmc-phase.c
···
9
9
#include <linux/clk-provider.h>
10
10
#include <linux/io.h>
11
11
#include <linux/kernel.h>
12
+
#include <linux/regmap.h>
12
13
#include "clk.h"
13
14
14
15
struct rockchip_mmc_clock {
15
16
struct clk_hw hw;
16
17
void __iomem *reg;
18
+
struct regmap *grf;
19
+
int grf_reg;
17
20
int shift;
18
21
int cached_phase;
19
22
struct notifier_block clk_rate_change_nb;
···
57
54
if (!rate)
58
55
return 0;
59
56
60
-
raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
57
+
if (mmc_clock->grf)
58
+
regmap_read(mmc_clock->grf, mmc_clock->grf_reg, &raw_value);
59
+
else
60
+
raw_value = readl(mmc_clock->reg);
61
+
62
+
raw_value >>= mmc_clock->shift;
61
63
62
64
degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
63
65
···
142
134
raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
143
135
raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
144
136
raw_value |= nineties;
145
-
writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),
146
-
mmc_clock->reg);
137
+
raw_value = HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift);
138
+
139
+
if (mmc_clock->grf)
140
+
regmap_write(mmc_clock->grf, mmc_clock->grf_reg, raw_value);
141
+
else
142
+
writel(raw_value, mmc_clock->reg);
147
143
148
144
pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
149
145
clk_hw_get_name(hw), degrees, delay_num,
···
201
189
202
190
struct clk *rockchip_clk_register_mmc(const char *name,
203
191
const char *const *parent_names, u8 num_parents,
204
-
void __iomem *reg, int shift)
192
+
void __iomem *reg,
193
+
struct regmap *grf, int grf_reg,
194
+
int shift)
205
195
{
206
196
struct clk_init_data init;
207
197
struct rockchip_mmc_clock *mmc_clock;
···
222
208
223
209
mmc_clock->hw.init = &init;
224
210
mmc_clock->reg = reg;
211
+
mmc_clock->grf = grf;
212
+
mmc_clock->grf_reg = grf_reg;
225
213
mmc_clock->shift = shift;
226
214
227
215
clk = clk_register(NULL, &mmc_clock->hw);
-11
drivers/clk/rockchip/clk-pll.c
-11
drivers/clk/rockchip/clk-pll.c
···
1027
1027
return !(pllcon & RK3588_PLLCON1_PWRDOWN);
1028
1028
}
1029
1029
1030
-
static int rockchip_rk3588_pll_init(struct clk_hw *hw)
1031
-
{
1032
-
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
1033
-
1034
-
if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
1035
-
return 0;
1036
-
1037
-
return 0;
1038
-
}
1039
-
1040
1030
static const struct clk_ops rockchip_rk3588_pll_clk_norate_ops = {
1041
1031
.recalc_rate = rockchip_rk3588_pll_recalc_rate,
1042
1032
.enable = rockchip_rk3588_pll_enable,
···
1041
1051
.enable = rockchip_rk3588_pll_enable,
1042
1052
.disable = rockchip_rk3588_pll_disable,
1043
1053
.is_enabled = rockchip_rk3588_pll_is_enabled,
1044
-
.init = rockchip_rk3588_pll_init,
1045
1054
};
1046
1055
1047
1056
/*
+5
-6
drivers/clk/rockchip/clk-rk3036.c
+5
-6
drivers/clk/rockchip/clk-rk3036.c
···
123
123
PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
124
124
PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" };
125
125
126
+
PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
126
127
PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
127
128
PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
128
129
PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
···
424
423
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
425
424
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
426
425
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
426
+
427
+
MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
428
+
RK2928_MISC_CON, 15, 1, MFLAGS),
427
429
};
428
430
429
431
static const char *const rk3036_critical_clocks[] __initconst = {
···
435
431
"hclk_peri",
436
432
"pclk_peri",
437
433
"pclk_ddrupctl",
434
+
"ddrphy",
438
435
};
439
436
440
437
static void __init rk3036_clk_init(struct device_node *np)
···
443
438
struct rockchip_clk_provider *ctx;
444
439
unsigned long clk_nr_clks;
445
440
void __iomem *reg_base;
446
-
struct clk *clk;
447
441
448
442
reg_base = of_iomap(np, 0);
449
443
if (!reg_base) {
···
465
461
iounmap(reg_base);
466
462
return;
467
463
}
468
-
469
-
clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
470
-
if (IS_ERR(clk))
471
-
pr_warn("%s: could not register clock usb480m: %ld\n",
472
-
__func__, PTR_ERR(clk));
473
464
474
465
rockchip_clk_register_plls(ctx, rk3036_pll_clks,
475
466
ARRAY_SIZE(rk3036_pll_clks),
+1
-1
drivers/clk/rockchip/clk-rk3288.c
+1
-1
drivers/clk/rockchip/clk-rk3288.c
···
418
418
RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
419
419
RK3288_CLKGATE_CON(3), 11, GFLAGS),
420
420
MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT,
421
-
RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS),
421
+
RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS, grf_type_sys),
422
422
GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
423
423
RK3288_CLKGATE_CON(9), 0, GFLAGS),
424
424
+3
-3
drivers/clk/rockchip/clk-rk3328.c
+3
-3
drivers/clk/rockchip/clk-rk3328.c
···
677
677
RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,
678
678
RK3328_CLKGATE_CON(3), 5, GFLAGS),
679
679
MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT,
680
-
RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),
680
+
RK3328_GRF_MAC_CON1, 10, 1, MFLAGS, grf_type_sys),
681
681
MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT,
682
-
RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),
682
+
RK3328_GRF_SOC_CON4, 14, 1, MFLAGS, grf_type_sys),
683
683
684
684
COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,
685
685
RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
···
692
692
RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,
693
693
RK3328_CLKGATE_CON(9), 2, GFLAGS),
694
694
MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT,
695
-
RK3328_GRF_MAC_CON2, 10, 1, MFLAGS),
695
+
RK3328_GRF_MAC_CON2, 10, 1, MFLAGS, grf_type_sys),
696
696
697
697
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
698
698
+77
-6
drivers/clk/rockchip/clk-rk3528.c
+77
-6
drivers/clk/rockchip/clk-rk3528.c
···
10
10
#include <linux/of.h>
11
11
#include <linux/of_device.h>
12
12
#include <linux/platform_device.h>
13
+
#include <linux/mfd/syscon.h>
14
+
#include <linux/minmax.h>
15
+
#include <linux/slab.h>
13
16
14
17
#include <dt-bindings/clock/rockchip,rk3528-cru.h>
15
18
···
1064
1061
0, 1, 1),
1065
1062
};
1066
1063
1064
+
static struct rockchip_clk_branch rk3528_vo_clk_branches[] __initdata = {
1065
+
MMC_GRF(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc0",
1066
+
RK3528_SDMMC_CON(0), 1, grf_type_vo),
1067
+
MMC_GRF(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc0",
1068
+
RK3528_SDMMC_CON(1), 1, grf_type_vo),
1069
+
};
1070
+
1071
+
static struct rockchip_clk_branch rk3528_vpu_clk_branches[] __initdata = {
1072
+
MMC_GRF(SCLK_SDIO0_DRV, "sdio0_drv", "cclk_src_sdio0",
1073
+
RK3528_SDIO0_CON(0), 1, grf_type_vpu),
1074
+
MMC_GRF(SCLK_SDIO0_SAMPLE, "sdio0_sample", "cclk_src_sdio0",
1075
+
RK3528_SDIO0_CON(1), 1, grf_type_vpu),
1076
+
MMC_GRF(SCLK_SDIO1_DRV, "sdio1_drv", "cclk_src_sdio1",
1077
+
RK3528_SDIO1_CON(0), 1, grf_type_vpu),
1078
+
MMC_GRF(SCLK_SDIO1_SAMPLE, "sdio1_sample", "cclk_src_sdio1",
1079
+
RK3528_SDIO1_CON(1), 1, grf_type_vpu),
1080
+
};
1081
+
1067
1082
static int __init clk_rk3528_probe(struct platform_device *pdev)
1068
1083
{
1069
-
struct rockchip_clk_provider *ctx;
1084
+
unsigned long nr_vpu_branches = ARRAY_SIZE(rk3528_vpu_clk_branches);
1085
+
unsigned long nr_vo_branches = ARRAY_SIZE(rk3528_vo_clk_branches);
1086
+
unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches);
1087
+
unsigned long nr_clks, nr_vo_clks, nr_vpu_clks;
1088
+
struct rockchip_aux_grf *vo_grf_e, *vpu_grf_e;
1089
+
struct regmap *vo_grf, *vpu_grf;
1070
1090
struct device *dev = &pdev->dev;
1071
1091
struct device_node *np = dev->of_node;
1072
-
unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches);
1073
-
unsigned long nr_clks;
1092
+
struct rockchip_clk_provider *ctx;
1074
1093
void __iomem *reg_base;
1075
-
1076
-
nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches,
1077
-
nr_branches) + 1;
1078
1094
1079
1095
reg_base = devm_platform_ioremap_resource(pdev, 0);
1080
1096
if (IS_ERR(reg_base))
1081
1097
return dev_err_probe(dev, PTR_ERR(reg_base),
1082
1098
"could not map cru region");
1099
+
1100
+
nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches,
1101
+
nr_branches) + 1;
1102
+
1103
+
vo_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3528-vo-grf");
1104
+
if (!IS_ERR(vo_grf)) {
1105
+
nr_vo_clks = rockchip_clk_find_max_clk_id(rk3528_vo_clk_branches,
1106
+
nr_vo_branches) + 1;
1107
+
nr_clks = max(nr_clks, nr_vo_clks);
1108
+
} else if (PTR_ERR(vo_grf) != -ENODEV) {
1109
+
return dev_err_probe(dev, PTR_ERR(vo_grf),
1110
+
"failed to look up VO GRF\n");
1111
+
}
1112
+
1113
+
vpu_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3528-vpu-grf");
1114
+
if (!IS_ERR(vpu_grf)) {
1115
+
nr_vpu_clks = rockchip_clk_find_max_clk_id(rk3528_vpu_clk_branches,
1116
+
nr_vpu_branches) + 1;
1117
+
nr_clks = max(nr_clks, nr_vpu_clks);
1118
+
} else if (PTR_ERR(vpu_grf) != -ENODEV) {
1119
+
return dev_err_probe(dev, PTR_ERR(vpu_grf),
1120
+
"failed to look up VPU GRF\n");
1121
+
}
1083
1122
1084
1123
ctx = rockchip_clk_init(np, reg_base, nr_clks);
1085
1124
if (IS_ERR(ctx))
···
1136
1091
&rk3528_cpuclk_data, rk3528_cpuclk_rates,
1137
1092
ARRAY_SIZE(rk3528_cpuclk_rates));
1138
1093
rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches);
1094
+
1095
+
if (!IS_ERR(vo_grf)) {
1096
+
vo_grf_e = devm_kzalloc(dev, sizeof(*vo_grf_e), GFP_KERNEL);
1097
+
if (!vo_grf_e)
1098
+
return -ENOMEM;
1099
+
1100
+
vo_grf_e->grf = vo_grf;
1101
+
vo_grf_e->type = grf_type_vo;
1102
+
hash_add(ctx->aux_grf_table, &vo_grf_e->node, grf_type_vo);
1103
+
1104
+
rockchip_clk_register_branches(ctx, rk3528_vo_clk_branches,
1105
+
nr_vo_branches);
1106
+
}
1107
+
1108
+
if (!IS_ERR(vpu_grf)) {
1109
+
vpu_grf_e = devm_kzalloc(dev, sizeof(*vpu_grf_e), GFP_KERNEL);
1110
+
if (!vpu_grf_e)
1111
+
return -ENOMEM;
1112
+
1113
+
vpu_grf_e->grf = vpu_grf;
1114
+
vpu_grf_e->type = grf_type_vpu;
1115
+
hash_add(ctx->aux_grf_table, &vpu_grf_e->node, grf_type_vpu);
1116
+
1117
+
rockchip_clk_register_branches(ctx, rk3528_vpu_clk_branches,
1118
+
nr_vpu_branches);
1119
+
}
1139
1120
1140
1121
rk3528_rst_init(np, reg_base);
1141
1122
+2
-1
drivers/clk/rockchip/clk-rk3568.c
+2
-1
drivers/clk/rockchip/clk-rk3568.c
···
89
89
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
90
90
RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
91
91
RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
92
+
RK3036_PLL_RATE(33300000, 4, 111, 5, 4, 1, 0),
92
93
{ /* sentinel */ },
93
94
};
94
95
···
591
590
RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
592
591
RK3568_CLKGATE_CON(4), 0, GFLAGS),
593
592
MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT,
594
-
RK3568_CLKSEL_CON(9), 15, 1, MFLAGS),
593
+
RK3568_CLKSEL_CON(9), 15, 1, MFLAGS, grf_type_sys),
595
594
596
595
COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED,
597
596
RK3568_CLKSEL_CON(10), 0, 2, DFLAGS,
+50
-10
drivers/clk/rockchip/clk-rk3576.c
+50
-10
drivers/clk/rockchip/clk-rk3576.c
···
10
10
#include <linux/platform_device.h>
11
11
#include <linux/syscore_ops.h>
12
12
#include <linux/mfd/syscon.h>
13
+
#include <linux/slab.h>
13
14
#include <dt-bindings/clock/rockchip,rk3576-cru.h>
14
15
#include "clk.h"
15
16
16
17
#define RK3576_GRF_SOC_STATUS0 0x600
17
18
#define RK3576_PMU0_GRF_OSC_CON6 0x18
19
+
#define RK3576_VCCIO_IOC_MISC_CON0 0x6400
18
20
19
21
enum rk3576_plls {
20
22
bpll, lpll, vpll, aupll, cpll, gpll, ppll,
···
1483
1481
RK3576_CLKGATE_CON(10), 0, GFLAGS),
1484
1482
GATE(CLK_SAI0_MCLKOUT, "clk_sai0_mclkout", "mclk_sai0_8ch", 0,
1485
1483
RK3576_CLKGATE_CON(10), 1, GFLAGS),
1484
+
GATE_GRF(CLK_SAI0_MCLKOUT_TO_IO, "mclk_sai0_to_io", "clk_sai0_mclkout",
1485
+
0, RK3576_VCCIO_IOC_MISC_CON0, 0, GFLAGS, grf_type_ioc),
1486
+
GATE_GRF(CLK_SAI1_MCLKOUT_TO_IO, "mclk_sai1_to_io", "clk_sai1_mclkout",
1487
+
0, RK3576_VCCIO_IOC_MISC_CON0, 1, GFLAGS, grf_type_ioc),
1488
+
GATE_GRF(CLK_SAI2_MCLKOUT_TO_IO, "mclk_sai2_to_io", "clk_sai2_mclkout",
1489
+
0, RK3576_VCCIO_IOC_MISC_CON0, 2, GFLAGS, grf_type_ioc),
1490
+
GATE_GRF(CLK_SAI3_MCLKOUT_TO_IO, "mclk_sai3_to_io", "clk_sai3_mclkout",
1491
+
0, RK3576_VCCIO_IOC_MISC_CON0, 3, GFLAGS, grf_type_ioc),
1486
1492
1487
1493
/* sdgmac */
1488
1494
COMPOSITE_NODIV(HCLK_SDGMAC_ROOT, "hclk_sdgmac_root", mux_200m_100m_50m_24m_p, 0,
···
1688
1678
1689
1679
/* phy ref */
1690
1680
MUXGRF(CLK_PHY_REF_SRC, "clk_phy_ref_src", clk_phy_ref_src_p, 0,
1691
-
RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS),
1681
+
RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS, grf_type_pmu0),
1692
1682
MUXGRF(CLK_USBPHY_REF_SRC, "clk_usbphy_ref_src", clk_usbphy_ref_src_p, 0,
1693
-
RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS),
1683
+
RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS, grf_type_pmu0),
1694
1684
MUXGRF(CLK_CPLL_REF_SRC, "clk_cpll_ref_src", clk_cpll_ref_src_p, 0,
1695
-
RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS),
1685
+
RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS, grf_type_pmu0),
1696
1686
MUXGRF(CLK_AUPLL_REF_SRC, "clk_aupll_ref_src", clk_aupll_ref_src_p, 0,
1697
-
RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS),
1687
+
RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS, grf_type_pmu0),
1698
1688
1699
1689
/* secure ns */
1700
1690
COMPOSITE_NODIV(ACLK_SECURE_NS, "aclk_secure_ns", mux_350m_175m_116m_24m_p, CLK_IS_CRITICAL,
···
1737
1727
struct rockchip_clk_provider *ctx;
1738
1728
unsigned long clk_nr_clks;
1739
1729
void __iomem *reg_base;
1740
-
struct regmap *grf;
1730
+
struct rockchip_aux_grf *ioc_grf_e;
1731
+
struct rockchip_aux_grf *pmu0_grf_e;
1732
+
struct regmap *ioc_grf;
1733
+
struct regmap *pmu0_grf;
1741
1734
1742
1735
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3576_clk_branches,
1743
1736
ARRAY_SIZE(rk3576_clk_branches)) + 1;
1744
1737
1745
-
grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-pmu0-grf");
1746
-
if (IS_ERR(grf)) {
1738
+
pmu0_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-pmu0-grf");
1739
+
if (IS_ERR(pmu0_grf)) {
1747
1740
pr_err("%s: could not get PMU0 GRF syscon\n", __func__);
1741
+
return;
1742
+
}
1743
+
1744
+
ioc_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-ioc-grf");
1745
+
if (IS_ERR(ioc_grf)) {
1746
+
pr_err("%s: could not get IOC GRF syscon\n", __func__);
1748
1747
return;
1749
1748
}
1750
1749
···
1766
1747
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
1767
1748
if (IS_ERR(ctx)) {
1768
1749
pr_err("%s: rockchip clk init failed\n", __func__);
1769
-
iounmap(reg_base);
1770
-
return;
1750
+
goto err_unmap;
1771
1751
}
1772
1752
1773
-
ctx->grf = grf;
1753
+
pmu0_grf_e = kzalloc(sizeof(*pmu0_grf_e), GFP_KERNEL);
1754
+
if (!pmu0_grf_e)
1755
+
goto err_unmap;
1756
+
1757
+
pmu0_grf_e->grf = pmu0_grf;
1758
+
pmu0_grf_e->type = grf_type_pmu0;
1759
+
hash_add(ctx->aux_grf_table, &pmu0_grf_e->node, grf_type_pmu0);
1760
+
1761
+
ioc_grf_e = kzalloc(sizeof(*ioc_grf_e), GFP_KERNEL);
1762
+
if (!ioc_grf_e)
1763
+
goto err_free_pmu0;
1764
+
1765
+
ioc_grf_e->grf = ioc_grf;
1766
+
ioc_grf_e->type = grf_type_ioc;
1767
+
hash_add(ctx->aux_grf_table, &ioc_grf_e->node, grf_type_ioc);
1774
1768
1775
1769
rockchip_clk_register_plls(ctx, rk3576_pll_clks,
1776
1770
ARRAY_SIZE(rk3576_pll_clks),
···
1806
1774
rockchip_register_restart_notifier(ctx, RK3576_GLB_SRST_FST, NULL);
1807
1775
1808
1776
rockchip_clk_of_add_provider(np, ctx);
1777
+
1778
+
return;
1779
+
1780
+
err_free_pmu0:
1781
+
kfree(pmu0_grf_e);
1782
+
err_unmap:
1783
+
iounmap(reg_base);
1784
+
return;
1809
1785
}
1810
1786
1811
1787
CLK_OF_DECLARE(rk3576_cru, "rockchip,rk3576-cru", rk3576_clk_init);
+1
drivers/clk/rockchip/clk-rk3588.c
+1
drivers/clk/rockchip/clk-rk3588.c
···
64
64
RK3588_PLL_RATE(1560000000, 2, 260, 1, 0),
65
65
RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),
66
66
RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
67
+
RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),
67
68
RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),
68
69
RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),
69
70
RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),
+1
-1
drivers/clk/rockchip/clk-rv1126.c
+1
-1
drivers/clk/rockchip/clk-rv1126.c
···
857
857
RV1126_GMAC_CON, 5, 1, MFLAGS),
858
858
MUXGRF(CLK_GMAC_SRC, "clk_gmac_src", mux_clk_gmac_src_p, CLK_SET_RATE_PARENT |
859
859
CLK_SET_RATE_NO_REPARENT,
860
-
RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS),
860
+
RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS, grf_type_sys),
861
861
862
862
GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0,
863
863
RV1126_CLKGATE_CON(20), 7, GFLAGS),
+36
-2
drivers/clk/rockchip/clk.c
+36
-2
drivers/clk/rockchip/clk.c
···
382
382
ctx->cru_node = np;
383
383
spin_lock_init(&ctx->lock);
384
384
385
+
hash_init(ctx->aux_grf_table);
386
+
385
387
ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
386
388
"rockchip,grf");
387
389
···
498
496
struct rockchip_clk_branch *list,
499
497
unsigned int nr_clk)
500
498
{
499
+
struct regmap *grf = ctx->grf;
500
+
struct rockchip_aux_grf *agrf;
501
501
struct clk *clk;
502
502
unsigned int idx;
503
503
unsigned long flags;
···
507
503
for (idx = 0; idx < nr_clk; idx++, list++) {
508
504
flags = list->flags;
509
505
clk = NULL;
506
+
507
+
/* for GRF-dependent branches, choose the right grf first */
508
+
if ((list->branch_type == branch_grf_mux ||
509
+
list->branch_type == branch_grf_gate ||
510
+
list->branch_type == branch_grf_mmc) &&
511
+
list->grf_type != grf_type_sys) {
512
+
hash_for_each_possible(ctx->aux_grf_table, agrf, node, list->grf_type) {
513
+
if (agrf->type == list->grf_type) {
514
+
grf = agrf->grf;
515
+
break;
516
+
}
517
+
}
518
+
}
510
519
511
520
/* catch simple muxes */
512
521
switch (list->branch_type) {
···
540
523
list->mux_shift, list->mux_width,
541
524
list->mux_flags, &ctx->lock);
542
525
break;
543
-
case branch_muxgrf:
526
+
case branch_grf_mux:
544
527
clk = rockchip_clk_register_muxgrf(list->name,
545
528
list->parent_names, list->num_parents,
546
-
flags, ctx->grf, list->muxdiv_offset,
529
+
flags, grf, list->muxdiv_offset,
547
530
list->mux_shift, list->mux_width,
548
531
list->mux_flags);
549
532
break;
···
590
573
ctx->reg_base + list->gate_offset,
591
574
list->gate_shift, list->gate_flags, &ctx->lock);
592
575
break;
576
+
case branch_grf_gate:
577
+
flags |= CLK_SET_RATE_PARENT;
578
+
clk = rockchip_clk_register_gate_grf(list->name,
579
+
list->parent_names[0], flags, grf,
580
+
list->gate_offset, list->gate_shift,
581
+
list->gate_flags);
582
+
break;
593
583
case branch_composite:
594
584
clk = rockchip_clk_register_branch(list->name,
595
585
list->parent_names, list->num_parents,
···
614
590
list->name,
615
591
list->parent_names, list->num_parents,
616
592
ctx->reg_base + list->muxdiv_offset,
593
+
NULL, 0,
594
+
list->div_shift
595
+
);
596
+
break;
597
+
case branch_grf_mmc:
598
+
clk = rockchip_clk_register_mmc(
599
+
list->name,
600
+
list->parent_names, list->num_parents,
601
+
NULL,
602
+
grf, list->muxdiv_offset,
617
603
list->div_shift
618
604
);
619
605
break;
+71
-4
drivers/clk/rockchip/clk.h
+71
-4
drivers/clk/rockchip/clk.h
···
19
19
20
20
#include <linux/io.h>
21
21
#include <linux/clk-provider.h>
22
+
#include <linux/hashtable.h>
22
23
23
24
struct clk;
24
25
···
218
217
#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
219
218
#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
220
219
#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
220
+
#define RK3528_SDMMC_CON(x) ((x) * 0x4 + 0x24)
221
+
#define RK3528_SDIO0_CON(x) ((x) * 0x4 + 0x4)
222
+
#define RK3528_SDIO1_CON(x) ((x) * 0x4 + 0xc)
221
223
#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
222
224
#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
223
225
#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
···
444
440
.k = _k, \
445
441
}
446
442
443
+
enum rockchip_grf_type {
444
+
grf_type_sys = 0,
445
+
grf_type_pmu0,
446
+
grf_type_pmu1,
447
+
grf_type_ioc,
448
+
grf_type_vo,
449
+
grf_type_vpu,
450
+
};
451
+
452
+
/* ceil(sqrt(enums in rockchip_grf_type - 1)) */
453
+
#define GRF_HASH_ORDER 2
454
+
455
+
/**
456
+
* struct rockchip_aux_grf - entry for the aux_grf_table hashtable
457
+
* @grf: pointer to the grf this entry references
458
+
* @type: what type of GRF this is
459
+
* @node: hlist node
460
+
*/
461
+
struct rockchip_aux_grf {
462
+
struct regmap *grf;
463
+
enum rockchip_grf_type type;
464
+
struct hlist_node node;
465
+
};
466
+
447
467
/**
448
468
* struct rockchip_clk_provider - information about clock provider
449
469
* @reg_base: virtual address for the register base.
450
470
* @clk_data: holds clock related data like clk* and number of clocks.
451
471
* @cru_node: device-node of the clock-provider
452
472
* @grf: regmap of the general-register-files syscon
473
+
* @aux_grf_table: hashtable of auxiliary GRF regmaps, indexed by grf_type
453
474
* @lock: maintains exclusion between callbacks for a given clock-provider.
454
475
*/
455
476
struct rockchip_clk_provider {
···
482
453
struct clk_onecell_data clk_data;
483
454
struct device_node *cru_node;
484
455
struct regmap *grf;
456
+
DECLARE_HASHTABLE(aux_grf_table, GRF_HASH_ORDER);
485
457
spinlock_t lock;
486
458
};
487
459
···
624
594
625
595
struct clk *rockchip_clk_register_mmc(const char *name,
626
596
const char *const *parent_names, u8 num_parents,
627
-
void __iomem *reg, int shift);
597
+
void __iomem *reg,
598
+
struct regmap *grf, int grf_reg,
599
+
int shift);
628
600
629
601
/*
630
602
* DDRCLK flags, including method of setting the rate
···
654
622
int flags, struct regmap *grf, int reg,
655
623
int shift, int width, int mux_flags);
656
624
625
+
struct clk *rockchip_clk_register_gate_grf(const char *name,
626
+
const char *parent_name, unsigned long flags,
627
+
struct regmap *regmap, unsigned int reg,
628
+
unsigned int shift, u8 gate_flags);
629
+
657
630
#define PNAME(x) static const char *const x[] __initconst
658
631
659
632
enum rockchip_clk_branch_type {
660
633
branch_composite,
661
634
branch_mux,
662
-
branch_muxgrf,
635
+
branch_grf_mux,
663
636
branch_divider,
664
637
branch_fraction_divider,
665
638
branch_gate,
639
+
branch_grf_gate,
666
640
branch_linked_gate,
667
641
branch_mmc,
642
+
branch_grf_mmc,
668
643
branch_inverter,
669
644
branch_factor,
670
645
branch_ddrclk,
···
699
660
u8 gate_shift;
700
661
u8 gate_flags;
701
662
unsigned int linked_clk_id;
663
+
enum rockchip_grf_type grf_type;
702
664
struct rockchip_clk_branch *child;
703
665
};
704
666
···
940
900
.mux_table = mt, \
941
901
}
942
902
943
-
#define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
903
+
#define MUXGRF(_id, cname, pnames, f, o, s, w, mf, gt) \
944
904
{ \
945
905
.id = _id, \
946
-
.branch_type = branch_muxgrf, \
906
+
.branch_type = branch_grf_mux, \
947
907
.name = cname, \
948
908
.parent_names = pnames, \
949
909
.num_parents = ARRAY_SIZE(pnames), \
···
953
913
.mux_width = w, \
954
914
.mux_flags = mf, \
955
915
.gate_offset = -1, \
916
+
.grf_type = gt, \
956
917
}
957
918
958
919
#define DIV(_id, cname, pname, f, o, s, w, df) \
···
999
958
.gate_flags = gf, \
1000
959
}
1001
960
961
+
#define GATE_GRF(_id, cname, pname, f, o, b, gf, gt) \
962
+
{ \
963
+
.id = _id, \
964
+
.branch_type = branch_grf_gate, \
965
+
.name = cname, \
966
+
.parent_names = (const char *[]){ pname }, \
967
+
.num_parents = 1, \
968
+
.flags = f, \
969
+
.gate_offset = o, \
970
+
.gate_shift = b, \
971
+
.gate_flags = gf, \
972
+
.grf_type = gt, \
973
+
}
974
+
1002
975
#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
1003
976
{ \
1004
977
.id = _id, \
···
1036
981
.num_parents = 1, \
1037
982
.muxdiv_offset = offset, \
1038
983
.div_shift = shift, \
984
+
}
985
+
986
+
#define MMC_GRF(_id, cname, pname, offset, shift, grftype) \
987
+
{ \
988
+
.id = _id, \
989
+
.branch_type = branch_grf_mmc, \
990
+
.name = cname, \
991
+
.parent_names = (const char *[]){ pname }, \
992
+
.num_parents = 1, \
993
+
.muxdiv_offset = offset, \
994
+
.div_shift = shift, \
995
+
.grf_type = grftype, \
1039
996
}
1040
997
1041
998
#define INVERTER(_id, cname, pname, io, is, if) \
+42
-32
drivers/clk/samsung/clk-exynos4.c
+42
-32
drivers/clk/samsung/clk-exynos4.c
···
1269
1269
CPUCLK_LAYOUT_E4210, e4412_armclk_d),
1270
1270
};
1271
1271
1272
+
static const struct samsung_cmu_info cmu_info_exynos4 __initconst = {
1273
+
.mux_clks = exynos4_mux_clks,
1274
+
.nr_mux_clks = ARRAY_SIZE(exynos4_mux_clks),
1275
+
.div_clks = exynos4_div_clks,
1276
+
.nr_div_clks = ARRAY_SIZE(exynos4_div_clks),
1277
+
.gate_clks = exynos4_gate_clks,
1278
+
.nr_gate_clks = ARRAY_SIZE(exynos4_gate_clks),
1279
+
.fixed_factor_clks = exynos4_fixed_factor_clks,
1280
+
.nr_fixed_factor_clks = ARRAY_SIZE(exynos4_fixed_factor_clks),
1281
+
.fixed_clks = exynos4_fixed_rate_clks,
1282
+
.nr_fixed_clks = ARRAY_SIZE(exynos4_fixed_rate_clks),
1283
+
};
1284
+
1285
+
static const struct samsung_cmu_info cmu_info_exynos4210 __initconst = {
1286
+
.mux_clks = exynos4210_mux_clks,
1287
+
.nr_mux_clks = ARRAY_SIZE(exynos4210_mux_clks),
1288
+
.div_clks = exynos4210_div_clks,
1289
+
.nr_div_clks = ARRAY_SIZE(exynos4210_div_clks),
1290
+
.gate_clks = exynos4210_gate_clks,
1291
+
.nr_gate_clks = ARRAY_SIZE(exynos4210_gate_clks),
1292
+
.fixed_factor_clks = exynos4210_fixed_factor_clks,
1293
+
.nr_fixed_factor_clks = ARRAY_SIZE(exynos4210_fixed_factor_clks),
1294
+
.fixed_clks = exynos4210_fixed_rate_clks,
1295
+
.nr_fixed_clks = ARRAY_SIZE(exynos4210_fixed_rate_clks),
1296
+
.cpu_clks = exynos4210_cpu_clks,
1297
+
.nr_cpu_clks = ARRAY_SIZE(exynos4210_cpu_clks),
1298
+
};
1299
+
1300
+
static const struct samsung_cmu_info cmu_info_exynos4x12 __initconst = {
1301
+
.mux_clks = exynos4x12_mux_clks,
1302
+
.nr_mux_clks = ARRAY_SIZE(exynos4x12_mux_clks),
1303
+
.div_clks = exynos4x12_div_clks,
1304
+
.nr_div_clks = ARRAY_SIZE(exynos4x12_div_clks),
1305
+
.gate_clks = exynos4x12_gate_clks,
1306
+
.nr_gate_clks = ARRAY_SIZE(exynos4x12_gate_clks),
1307
+
.fixed_factor_clks = exynos4x12_fixed_factor_clks,
1308
+
.nr_fixed_factor_clks = ARRAY_SIZE(exynos4x12_fixed_factor_clks),
1309
+
};
1310
+
1272
1311
/* register exynos4 clocks */
1273
1312
static void __init exynos4_clk_init(struct device_node *np,
1274
1313
enum exynos4_soc soc)
···
1361
1322
ARRAY_SIZE(exynos4x12_plls));
1362
1323
}
1363
1324
1364
-
samsung_clk_register_fixed_rate(ctx, exynos4_fixed_rate_clks,
1365
-
ARRAY_SIZE(exynos4_fixed_rate_clks));
1366
-
samsung_clk_register_mux(ctx, exynos4_mux_clks,
1367
-
ARRAY_SIZE(exynos4_mux_clks));
1368
-
samsung_clk_register_div(ctx, exynos4_div_clks,
1369
-
ARRAY_SIZE(exynos4_div_clks));
1370
-
samsung_clk_register_gate(ctx, exynos4_gate_clks,
1371
-
ARRAY_SIZE(exynos4_gate_clks));
1372
-
samsung_clk_register_fixed_factor(ctx, exynos4_fixed_factor_clks,
1373
-
ARRAY_SIZE(exynos4_fixed_factor_clks));
1325
+
samsung_cmu_register_clocks(ctx, &cmu_info_exynos4);
1374
1326
1375
1327
if (exynos4_soc == EXYNOS4210) {
1376
-
samsung_clk_register_fixed_rate(ctx, exynos4210_fixed_rate_clks,
1377
-
ARRAY_SIZE(exynos4210_fixed_rate_clks));
1378
-
samsung_clk_register_mux(ctx, exynos4210_mux_clks,
1379
-
ARRAY_SIZE(exynos4210_mux_clks));
1380
-
samsung_clk_register_div(ctx, exynos4210_div_clks,
1381
-
ARRAY_SIZE(exynos4210_div_clks));
1382
-
samsung_clk_register_gate(ctx, exynos4210_gate_clks,
1383
-
ARRAY_SIZE(exynos4210_gate_clks));
1384
-
samsung_clk_register_fixed_factor(ctx,
1385
-
exynos4210_fixed_factor_clks,
1386
-
ARRAY_SIZE(exynos4210_fixed_factor_clks));
1387
-
samsung_clk_register_cpu(ctx, exynos4210_cpu_clks,
1388
-
ARRAY_SIZE(exynos4210_cpu_clks));
1328
+
samsung_cmu_register_clocks(ctx, &cmu_info_exynos4210);
1389
1329
} else {
1390
-
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1391
-
ARRAY_SIZE(exynos4x12_mux_clks));
1392
-
samsung_clk_register_div(ctx, exynos4x12_div_clks,
1393
-
ARRAY_SIZE(exynos4x12_div_clks));
1394
-
samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
1395
-
ARRAY_SIZE(exynos4x12_gate_clks));
1396
-
samsung_clk_register_fixed_factor(ctx,
1397
-
exynos4x12_fixed_factor_clks,
1398
-
ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1330
+
samsung_cmu_register_clocks(ctx, &cmu_info_exynos4x12);
1399
1331
if (soc == EXYNOS4412)
1400
1332
samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
1401
1333
ARRAY_SIZE(exynos4412_cpu_clks));
+337
-1
drivers/clk/samsung/clk-exynosautov920.c
+337
-1
drivers/clk/samsung/clk-exynosautov920.c
···
18
18
19
19
/* NOTE: Must be equal to the last clock ID increased by one */
20
20
#define CLKS_NR_TOP (DOUT_CLKCMU_TAA_NOC + 1)
21
+
#define CLKS_NR_CPUCL0 (CLK_DOUT_CPUCL0_NOCP + 1)
22
+
#define CLKS_NR_CPUCL1 (CLK_DOUT_CPUCL1_NOCP + 1)
23
+
#define CLKS_NR_CPUCL2 (CLK_DOUT_CPUCL2_NOCP + 1)
21
24
#define CLKS_NR_PERIC0 (CLK_DOUT_PERIC0_I3C + 1)
22
25
#define CLKS_NR_PERIC1 (CLK_DOUT_PERIC1_I3C + 1)
23
26
#define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1)
···
1008
1005
CLK_OF_DECLARE(exynosautov920_cmu_top, "samsung,exynosautov920-cmu-top",
1009
1006
exynosautov920_cmu_top_init);
1010
1007
1008
+
/* ---- CMU_CPUCL0 --------------------------------------------------------- */
1009
+
1010
+
/* Register Offset definitions for CMU_CPUCL0 (0x1EC00000) */
1011
+
#define PLL_LOCKTIME_PLL_CPUCL0 0x0000
1012
+
#define PLL_CON0_PLL_CPUCL0 0x0100
1013
+
#define PLL_CON1_PLL_CPUCL0 0x0104
1014
+
#define PLL_CON3_PLL_CPUCL0 0x010c
1015
+
#define PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER 0x0600
1016
+
#define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0610
1017
+
#define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0620
1018
+
1019
+
#define CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER 0x1000
1020
+
#define CLK_CON_MUX_MUX_CLK_CPUCL0_CORE 0x1004
1021
+
1022
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
1023
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1804
1024
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK 0x1808
1025
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK 0x180c
1026
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
1027
+
#define CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC 0x181c
1028
+
#define CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG 0x1820
1029
+
#define CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP 0x1824
1030
+
1031
+
static const unsigned long cpucl0_clk_regs[] __initconst = {
1032
+
PLL_LOCKTIME_PLL_CPUCL0,
1033
+
PLL_CON0_PLL_CPUCL0,
1034
+
PLL_CON1_PLL_CPUCL0,
1035
+
PLL_CON3_PLL_CPUCL0,
1036
+
PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER,
1037
+
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
1038
+
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
1039
+
CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER,
1040
+
CLK_CON_MUX_MUX_CLK_CPUCL0_CORE,
1041
+
CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
1042
+
CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
1043
+
CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK,
1044
+
CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK,
1045
+
CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
1046
+
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC,
1047
+
CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG,
1048
+
CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP,
1049
+
};
1050
+
1051
+
/* List of parent clocks for Muxes in CMU_CPUCL0 */
1052
+
PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" };
1053
+
PNAME(mout_cpucl0_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl0_cluster" };
1054
+
PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_clkcmu_cpucl0_dbg" };
1055
+
PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl0_switch" };
1056
+
PNAME(mout_cpucl0_cluster_p) = { "oscclk", "mout_cpucl0_cluster_user",
1057
+
"mout_cpucl0_switch_user"};
1058
+
PNAME(mout_cpucl0_core_p) = { "oscclk", "mout_pll_cpucl0",
1059
+
"mout_cpucl0_switch_user"};
1060
+
1061
+
static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = {
1062
+
PLL_35XX_RATE(38400000U, 2400000000U, 250, 4, 0),
1063
+
PLL_35XX_RATE(38400000U, 2304000000U, 240, 4, 0),
1064
+
PLL_35XX_RATE(38400000U, 2208000000U, 230, 4, 0),
1065
+
PLL_35XX_RATE(38400000U, 2112000000U, 220, 4, 0),
1066
+
PLL_35XX_RATE(38400000U, 2016000000U, 210, 4, 0),
1067
+
PLL_35XX_RATE(38400000U, 1824000000U, 190, 4, 0),
1068
+
PLL_35XX_RATE(38400000U, 1680000000U, 175, 4, 0),
1069
+
PLL_35XX_RATE(38400000U, 1344000000U, 140, 4, 0),
1070
+
PLL_35XX_RATE(38400000U, 1152000000U, 120, 4, 0),
1071
+
PLL_35XX_RATE(38400000U, 576000000U, 120, 4, 1),
1072
+
PLL_35XX_RATE(38400000U, 288000000U, 120, 4, 2),
1073
+
};
1074
+
1075
+
static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
1076
+
/* CMU_CPUCL0_PURECLKCOMP */
1077
+
PLL(pll_531x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
1078
+
PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates),
1079
+
};
1080
+
1081
+
static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
1082
+
MUX(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p,
1083
+
PLL_CON0_PLL_CPUCL0, 4, 1),
1084
+
MUX(CLK_MOUT_CPUCL0_CLUSTER_USER, "mout_cpucl0_cluster_user", mout_cpucl0_cluster_user_p,
1085
+
PLL_CON0_MUX_CLKCMU_CPUCL0_CLUSTER_USER, 4, 1),
1086
+
MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user", mout_cpucl0_dbg_user_p,
1087
+
PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
1088
+
MUX(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user", mout_cpucl0_switch_user_p,
1089
+
PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1),
1090
+
MUX(CLK_MOUT_CPUCL0_CLUSTER, "mout_cpucl0_cluster", mout_cpucl0_cluster_p,
1091
+
CLK_CON_MUX_MUX_CLK_CPUCL0_CLUSTER, 0, 2),
1092
+
MUX(CLK_MOUT_CPUCL0_CORE, "mout_cpucl0_core", mout_cpucl0_core_p,
1093
+
CLK_CON_MUX_MUX_CLK_CPUCL0_CORE, 0, 2),
1094
+
};
1095
+
1096
+
static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
1097
+
DIV(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk",
1098
+
"mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4),
1099
+
DIV(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk",
1100
+
"mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4),
1101
+
DIV(CLK_DOUT_CLUSTER0_MPCLK, "dout_cluster0_mpclk",
1102
+
"mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_MPCLK, 0, 4),
1103
+
DIV(CLK_DOUT_CLUSTER0_PCLK, "dout_cluster0_pclk",
1104
+
"mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLK, 0, 4),
1105
+
DIV(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk",
1106
+
"mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4),
1107
+
DIV(CLK_DOUT_CPUCL0_DBG_NOC, "dout_cpucl0_dbg_noc",
1108
+
"mout_cpucl0_dbg_user", CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC, 0, 3),
1109
+
DIV(CLK_DOUT_CPUCL0_DBG_PCLKDBG, "dout_cpucl0_dbg_pclkdbg",
1110
+
"mout_cpucl0_dbg_user", CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0, 3),
1111
+
DIV(CLK_DOUT_CPUCL0_NOCP, "dout_cpucl0_nocp",
1112
+
"mout_cpucl0_cluster", CLK_CON_DIV_DIV_CLK_CPUCL0_NOCP, 0, 4),
1113
+
};
1114
+
1115
+
static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
1116
+
.pll_clks = cpucl0_pll_clks,
1117
+
.nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
1118
+
.mux_clks = cpucl0_mux_clks,
1119
+
.nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
1120
+
.div_clks = cpucl0_div_clks,
1121
+
.nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
1122
+
.nr_clk_ids = CLKS_NR_CPUCL0,
1123
+
.clk_regs = cpucl0_clk_regs,
1124
+
.nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
1125
+
.clk_name = "cpucl0",
1126
+
};
1127
+
1128
+
static void __init exynosautov920_cmu_cpucl0_init(struct device_node *np)
1129
+
{
1130
+
exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
1131
+
}
1132
+
1133
+
/* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */
1134
+
CLK_OF_DECLARE(exynosautov920_cmu_cpucl0, "samsung,exynosautov920-cmu-cpucl0",
1135
+
exynosautov920_cmu_cpucl0_init);
1136
+
1137
+
/* ---- CMU_CPUCL1 --------------------------------------------------------- */
1138
+
1139
+
/* Register Offset definitions for CMU_CPUCL1 (0x1ED00000) */
1140
+
#define PLL_LOCKTIME_PLL_CPUCL1 0x0000
1141
+
#define PLL_CON0_PLL_CPUCL1 0x0100
1142
+
#define PLL_CON1_PLL_CPUCL1 0x0104
1143
+
#define PLL_CON3_PLL_CPUCL1 0x010c
1144
+
#define PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER 0x0600
1145
+
#define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
1146
+
1147
+
#define CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER 0x1000
1148
+
#define CLK_CON_MUX_MUX_CLK_CPUCL1_CORE 0x1004
1149
+
1150
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
1151
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1804
1152
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK 0x1808
1153
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK 0x180c
1154
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
1155
+
#define CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP 0x181c
1156
+
1157
+
static const unsigned long cpucl1_clk_regs[] __initconst = {
1158
+
PLL_LOCKTIME_PLL_CPUCL1,
1159
+
PLL_CON0_PLL_CPUCL1,
1160
+
PLL_CON1_PLL_CPUCL1,
1161
+
PLL_CON3_PLL_CPUCL1,
1162
+
PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER,
1163
+
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
1164
+
CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER,
1165
+
CLK_CON_MUX_MUX_CLK_CPUCL1_CORE,
1166
+
CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
1167
+
CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
1168
+
CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK,
1169
+
CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK,
1170
+
CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
1171
+
CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP,
1172
+
};
1173
+
1174
+
/* List of parent clocks for Muxes in CMU_CPUCL1 */
1175
+
PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
1176
+
PNAME(mout_cpucl1_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl1_cluster" };
1177
+
PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl1_switch" };
1178
+
PNAME(mout_cpucl1_cluster_p) = { "oscclk", "mout_cpucl1_cluster_user",
1179
+
"mout_cpucl1_switch_user"};
1180
+
PNAME(mout_cpucl1_core_p) = { "oscclk", "mout_pll_cpucl1",
1181
+
"mout_cpucl1_switch_user"};
1182
+
1183
+
static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
1184
+
/* CMU_CPUCL1_PURECLKCOMP */
1185
+
PLL(pll_531x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
1186
+
PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
1187
+
};
1188
+
1189
+
static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
1190
+
MUX(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
1191
+
PLL_CON0_PLL_CPUCL1, 4, 1),
1192
+
MUX(CLK_MOUT_CPUCL1_CLUSTER_USER, "mout_cpucl1_cluster_user", mout_cpucl1_cluster_user_p,
1193
+
PLL_CON0_MUX_CLKCMU_CPUCL1_CLUSTER_USER, 4, 1),
1194
+
MUX(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user", mout_cpucl1_switch_user_p,
1195
+
PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1),
1196
+
MUX(CLK_MOUT_CPUCL1_CLUSTER, "mout_cpucl1_cluster", mout_cpucl1_cluster_p,
1197
+
CLK_CON_MUX_MUX_CLK_CPUCL1_CLUSTER, 0, 2),
1198
+
MUX(CLK_MOUT_CPUCL1_CORE, "mout_cpucl1_core", mout_cpucl1_core_p,
1199
+
CLK_CON_MUX_MUX_CLK_CPUCL1_CORE, 0, 2),
1200
+
};
1201
+
1202
+
static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
1203
+
DIV(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk",
1204
+
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4),
1205
+
DIV(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
1206
+
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4),
1207
+
DIV(CLK_DOUT_CLUSTER1_MPCLK, "dout_cluster1_mpclk",
1208
+
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_MPCLK, 0, 4),
1209
+
DIV(CLK_DOUT_CLUSTER1_PCLK, "dout_cluster1_pclk",
1210
+
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLK, 0, 4),
1211
+
DIV(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
1212
+
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4),
1213
+
DIV(CLK_DOUT_CPUCL1_NOCP, "dout_cpucl1_nocp",
1214
+
"mout_cpucl1_cluster", CLK_CON_DIV_DIV_CLK_CPUCL1_NOCP, 0, 4),
1215
+
};
1216
+
1217
+
static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
1218
+
.pll_clks = cpucl1_pll_clks,
1219
+
.nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
1220
+
.mux_clks = cpucl1_mux_clks,
1221
+
.nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
1222
+
.div_clks = cpucl1_div_clks,
1223
+
.nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
1224
+
.nr_clk_ids = CLKS_NR_CPUCL1,
1225
+
.clk_regs = cpucl1_clk_regs,
1226
+
.nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
1227
+
.clk_name = "cpucl1",
1228
+
};
1229
+
1230
+
static void __init exynosautov920_cmu_cpucl1_init(struct device_node *np)
1231
+
{
1232
+
exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
1233
+
}
1234
+
1235
+
/* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
1236
+
CLK_OF_DECLARE(exynosautov920_cmu_cpucl1, "samsung,exynosautov920-cmu-cpucl1",
1237
+
exynosautov920_cmu_cpucl1_init);
1238
+
1239
+
/* ---- CMU_CPUCL2 --------------------------------------------------------- */
1240
+
1241
+
/* Register Offset definitions for CMU_CPUCL2 (0x1EE00000) */
1242
+
#define PLL_LOCKTIME_PLL_CPUCL2 0x0000
1243
+
#define PLL_CON0_PLL_CPUCL2 0x0100
1244
+
#define PLL_CON1_PLL_CPUCL2 0x0104
1245
+
#define PLL_CON3_PLL_CPUCL2 0x010c
1246
+
#define PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER 0x0600
1247
+
#define PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER 0x0610
1248
+
1249
+
#define CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER 0x1000
1250
+
#define CLK_CON_MUX_MUX_CLK_CPUCL2_CORE 0x1004
1251
+
1252
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK 0x1800
1253
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK 0x1804
1254
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK 0x1808
1255
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK 0x180c
1256
+
#define CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK 0x1810
1257
+
#define CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP 0x181c
1258
+
1259
+
static const unsigned long cpucl2_clk_regs[] __initconst = {
1260
+
PLL_LOCKTIME_PLL_CPUCL2,
1261
+
PLL_CON0_PLL_CPUCL2,
1262
+
PLL_CON1_PLL_CPUCL2,
1263
+
PLL_CON3_PLL_CPUCL2,
1264
+
PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER,
1265
+
PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER,
1266
+
CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER,
1267
+
CLK_CON_MUX_MUX_CLK_CPUCL2_CORE,
1268
+
CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK,
1269
+
CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK,
1270
+
CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK,
1271
+
CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK,
1272
+
CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK,
1273
+
CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP,
1274
+
};
1275
+
1276
+
/* List of parent clocks for Muxes in CMU_CPUCL2 */
1277
+
PNAME(mout_pll_cpucl2_p) = { "oscclk", "fout_cpucl2_pll" };
1278
+
PNAME(mout_cpucl2_cluster_user_p) = { "oscclk", "dout_clkcmu_cpucl2_cluster" };
1279
+
PNAME(mout_cpucl2_switch_user_p) = { "oscclk", "dout_clkcmu_cpucl2_switch" };
1280
+
PNAME(mout_cpucl2_cluster_p) = { "oscclk", "mout_cpucl2_cluster_user",
1281
+
"mout_cpucl2_switch_user"};
1282
+
PNAME(mout_cpucl2_core_p) = { "oscclk", "mout_pll_cpucl2",
1283
+
"mout_cpucl2_switch_user"};
1284
+
1285
+
static const struct samsung_pll_clock cpucl2_pll_clks[] __initconst = {
1286
+
/* CMU_CPUCL2_PURECLKCOMP */
1287
+
PLL(pll_531x, CLK_FOUT_CPUCL2_PLL, "fout_cpucl2_pll", "oscclk",
1288
+
PLL_LOCKTIME_PLL_CPUCL2, PLL_CON3_PLL_CPUCL2, cpu_pll_rates),
1289
+
};
1290
+
1291
+
static const struct samsung_mux_clock cpucl2_mux_clks[] __initconst = {
1292
+
MUX(CLK_MOUT_PLL_CPUCL2, "mout_pll_cpucl2", mout_pll_cpucl2_p,
1293
+
PLL_CON0_PLL_CPUCL2, 4, 1),
1294
+
MUX(CLK_MOUT_CPUCL2_CLUSTER_USER, "mout_cpucl2_cluster_user", mout_cpucl2_cluster_user_p,
1295
+
PLL_CON0_MUX_CLKCMU_CPUCL2_CLUSTER_USER, 4, 1),
1296
+
MUX(CLK_MOUT_CPUCL2_SWITCH_USER, "mout_cpucl2_switch_user", mout_cpucl2_switch_user_p,
1297
+
PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, 4, 1),
1298
+
MUX(CLK_MOUT_CPUCL2_CLUSTER, "mout_cpucl2_cluster", mout_cpucl2_cluster_p,
1299
+
CLK_CON_MUX_MUX_CLK_CPUCL2_CLUSTER, 0, 2),
1300
+
MUX(CLK_MOUT_CPUCL2_CORE, "mout_cpucl2_core", mout_cpucl2_core_p,
1301
+
CLK_CON_MUX_MUX_CLK_CPUCL2_CORE, 0, 2),
1302
+
};
1303
+
1304
+
static const struct samsung_div_clock cpucl2_div_clks[] __initconst = {
1305
+
DIV(CLK_DOUT_CLUSTER2_ACLK, "dout_cluster2_aclk",
1306
+
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ACLK, 0, 4),
1307
+
DIV(CLK_DOUT_CLUSTER2_ATCLK, "dout_cluster2_atclk",
1308
+
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_ATCLK, 0, 4),
1309
+
DIV(CLK_DOUT_CLUSTER2_MPCLK, "dout_cluster2_mpclk",
1310
+
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_MPCLK, 0, 4),
1311
+
DIV(CLK_DOUT_CLUSTER2_PCLK, "dout_cluster2_pclk",
1312
+
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PCLK, 0, 4),
1313
+
DIV(CLK_DOUT_CLUSTER2_PERIPHCLK, "dout_cluster2_periphclk",
1314
+
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CLUSTER2_PERIPHCLK, 0, 4),
1315
+
DIV(CLK_DOUT_CPUCL2_NOCP, "dout_cpucl2_nocp",
1316
+
"mout_cpucl2_cluster", CLK_CON_DIV_DIV_CLK_CPUCL2_NOCP, 0, 4),
1317
+
};
1318
+
1319
+
static const struct samsung_cmu_info cpucl2_cmu_info __initconst = {
1320
+
.pll_clks = cpucl2_pll_clks,
1321
+
.nr_pll_clks = ARRAY_SIZE(cpucl2_pll_clks),
1322
+
.mux_clks = cpucl2_mux_clks,
1323
+
.nr_mux_clks = ARRAY_SIZE(cpucl2_mux_clks),
1324
+
.div_clks = cpucl2_div_clks,
1325
+
.nr_div_clks = ARRAY_SIZE(cpucl2_div_clks),
1326
+
.nr_clk_ids = CLKS_NR_CPUCL2,
1327
+
.clk_regs = cpucl2_clk_regs,
1328
+
.nr_clk_regs = ARRAY_SIZE(cpucl2_clk_regs),
1329
+
.clk_name = "cpucl2",
1330
+
};
1331
+
1332
+
static void __init exynosautov920_cmu_cpucl2_init(struct device_node *np)
1333
+
{
1334
+
exynos_arm64_register_cmu(NULL, np, &cpucl2_cmu_info);
1335
+
}
1336
+
1337
+
/* Register CMU_CPUCL2 early, as CPU clocks should be available ASAP */
1338
+
CLK_OF_DECLARE(exynosautov920_cmu_cpucl2, "samsung,exynosautov920-cmu-cpucl2",
1339
+
exynosautov920_cmu_cpucl2_init);
1340
+
1011
1341
/* ---- CMU_PERIC0 --------------------------------------------------------- */
1012
1342
1013
1343
/* Register Offset definitions for CMU_PERIC0 (0x10800000) */
···
1729
1393
/* List of parent clocks for Muxes in CMU_HSI1 */
1730
1394
PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"};
1731
1395
PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };
1732
-
PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" };
1396
+
PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_hsi1_usbdrd" };
1733
1397
PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" };
1734
1398
1735
1399
static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {
+3
-3
drivers/clk/socfpga/clk-pll-s10.c
+3
-3
drivers/clk/socfpga/clk-pll-s10.c
···
83
83
unsigned long parent_rate)
84
84
{
85
85
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
86
-
unsigned long mdiv;
87
-
unsigned long refdiv;
88
-
unsigned long reg;
86
+
u32 mdiv;
87
+
u32 refdiv;
88
+
u32 reg;
89
89
unsigned long long vco_freq;
90
90
91
91
/* read VCO1 reg for numerator and denominator */
+2
-2
drivers/clk/socfpga/clk-pll.c
+2
-2
drivers/clk/socfpga/clk-pll.c
···
39
39
unsigned long parent_rate)
40
40
{
41
41
struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk);
42
-
unsigned long divf, divq, reg;
42
+
u32 divf, divq, reg;
43
43
unsigned long long vco_freq;
44
-
unsigned long bypass;
44
+
u32 bypass;
45
45
46
46
reg = readl(socfpgaclk->hw.reg);
47
47
bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
+19
drivers/clk/sophgo/Kconfig
+19
drivers/clk/sophgo/Kconfig
···
37
37
This clock IP depends on SG2042 Clock Generator because it uses
38
38
clock from Clock Generator IP as input.
39
39
This driver provides Gate function for RP.
40
+
41
+
config CLK_SOPHGO_SG2044
42
+
tristate "Sophgo SG2044 clock controller support"
43
+
depends on ARCH_SOPHGO || COMPILE_TEST
44
+
help
45
+
This driver supports the clock controller on the Sophgo SG2044
46
+
SoC. This controller requires mulitple PLL clock as input.
47
+
This clock control provides PLL clocks and common clock function
48
+
for various IPs on the SoC.
49
+
50
+
config CLK_SOPHGO_SG2044_PLL
51
+
tristate "Sophgo SG2044 PLL clock controller support"
52
+
depends on ARCH_SOPHGO || COMPILE_TEST
53
+
select MFD_SYSCON
54
+
select REGMAP_MMIO
55
+
help
56
+
This driver supports the PLL clock controller on the Sophgo
57
+
SG2044 SoC. This controller requires 25M oscillator as input.
58
+
This clock control provides PLL clocks on the SoC.
+2
drivers/clk/sophgo/Makefile
+2
drivers/clk/sophgo/Makefile
···
9
9
obj-$(CONFIG_CLK_SOPHGO_SG2042_CLKGEN) += clk-sg2042-clkgen.o
10
10
obj-$(CONFIG_CLK_SOPHGO_SG2042_PLL) += clk-sg2042-pll.o
11
11
obj-$(CONFIG_CLK_SOPHGO_SG2042_RPGATE) += clk-sg2042-rpgate.o
12
+
obj-$(CONFIG_CLK_SOPHGO_SG2044) += clk-sg2044.o
13
+
obj-$(CONFIG_CLK_SOPHGO_SG2044_PLL) += clk-sg2044-pll.o
+2
drivers/clk/sophgo/clk-cv1800.c
+2
drivers/clk/sophgo/clk-cv1800.c
···
1519
1519
1520
1520
static const struct of_device_id cv1800_clk_ids[] = {
1521
1521
{ .compatible = "sophgo,cv1800-clk", .data = &cv1800_desc },
1522
+
{ .compatible = "sophgo,cv1800b-clk", .data = &cv1800_desc },
1522
1523
{ .compatible = "sophgo,cv1810-clk", .data = &cv1810_desc },
1524
+
{ .compatible = "sophgo,cv1812h-clk", .data = &cv1810_desc },
1523
1525
{ .compatible = "sophgo,sg2000-clk", .data = &sg2000_desc },
1524
1526
{ }
1525
1527
};
+628
drivers/clk/sophgo/clk-sg2044-pll.c
+628
drivers/clk/sophgo/clk-sg2044-pll.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo SG2044 PLL clock controller driver
4
+
*
5
+
* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
6
+
*/
7
+
8
+
#include <linux/array_size.h>
9
+
#include <linux/bitfield.h>
10
+
#include <linux/bits.h>
11
+
#include <linux/cleanup.h>
12
+
#include <linux/clk.h>
13
+
#include <linux/clk-provider.h>
14
+
#include <linux/io.h>
15
+
#include <linux/iopoll.h>
16
+
#include <linux/math64.h>
17
+
#include <linux/mfd/syscon.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/regmap.h>
20
+
#include <linux/spinlock.h>
21
+
22
+
#include <dt-bindings/clock/sophgo,sg2044-pll.h>
23
+
24
+
/* Low Control part */
25
+
#define PLL_VCOSEL_MASK GENMASK(17, 16)
26
+
27
+
/* High Control part */
28
+
#define PLL_FBDIV_MASK GENMASK(11, 0)
29
+
#define PLL_REFDIV_MASK GENMASK(17, 12)
30
+
#define PLL_POSTDIV1_MASK GENMASK(20, 18)
31
+
#define PLL_POSTDIV2_MASK GENMASK(23, 21)
32
+
33
+
#define PLL_CALIBRATE_EN BIT(24)
34
+
#define PLL_CALIBRATE_MASK GENMASK(29, 27)
35
+
#define PLL_CALIBRATE_DEFAULT FIELD_PREP(PLL_CALIBRATE_MASK, 2)
36
+
#define PLL_UPDATE_EN BIT(30)
37
+
38
+
#define PLL_HIGH_CTRL_MASK \
39
+
(PLL_FBDIV_MASK | PLL_REFDIV_MASK | \
40
+
PLL_POSTDIV1_MASK | PLL_POSTDIV2_MASK | \
41
+
PLL_CALIBRATE_EN | PLL_CALIBRATE_MASK | \
42
+
PLL_UPDATE_EN)
43
+
44
+
#define PLL_HIGH_CTRL_OFFSET 4
45
+
46
+
#define PLL_VCOSEL_1G6 0x2
47
+
#define PLL_VCOSEL_2G4 0x3
48
+
49
+
#define PLL_LIMIT_FOUTVCO 0
50
+
#define PLL_LIMIT_FOUT 1
51
+
#define PLL_LIMIT_REFDIV 2
52
+
#define PLL_LIMIT_FBDIV 3
53
+
#define PLL_LIMIT_POSTDIV1 4
54
+
#define PLL_LIMIT_POSTDIV2 5
55
+
56
+
#define for_each_pll_limit_range(_var, _limit) \
57
+
for (_var = (_limit)->min; _var <= (_limit)->max; _var++)
58
+
59
+
struct sg2044_pll_limit {
60
+
u64 min;
61
+
u64 max;
62
+
};
63
+
64
+
struct sg2044_pll_internal {
65
+
u32 ctrl_offset;
66
+
u32 status_offset;
67
+
u32 enable_offset;
68
+
69
+
u8 status_lock_bit;
70
+
u8 status_updating_bit;
71
+
u8 enable_bit;
72
+
73
+
const struct sg2044_pll_limit *limits;
74
+
};
75
+
76
+
struct sg2044_clk_common {
77
+
struct clk_hw hw;
78
+
struct regmap *regmap;
79
+
spinlock_t *lock;
80
+
unsigned int id;
81
+
};
82
+
83
+
struct sg2044_pll {
84
+
struct sg2044_clk_common common;
85
+
struct sg2044_pll_internal pll;
86
+
unsigned int syscon_offset;
87
+
};
88
+
89
+
struct sg2044_pll_desc_data {
90
+
struct sg2044_clk_common * const *pll;
91
+
u16 num_pll;
92
+
};
93
+
94
+
#define SG2044_SYSCON_PLL_OFFSET 0x98
95
+
96
+
struct sg2044_pll_ctrl {
97
+
spinlock_t lock;
98
+
struct clk_hw_onecell_data data;
99
+
};
100
+
101
+
#define hw_to_sg2044_clk_common(_hw) \
102
+
container_of((_hw), struct sg2044_clk_common, hw)
103
+
104
+
static inline bool sg2044_clk_fit_limit(u64 value,
105
+
const struct sg2044_pll_limit *limit)
106
+
{
107
+
return value >= limit->min && value <= limit->max;
108
+
}
109
+
110
+
static inline struct sg2044_pll *hw_to_sg2044_pll(struct clk_hw *hw)
111
+
{
112
+
return container_of(hw_to_sg2044_clk_common(hw),
113
+
struct sg2044_pll, common);
114
+
}
115
+
116
+
static unsigned long sg2044_pll_calc_vco_rate(unsigned long parent_rate,
117
+
unsigned long refdiv,
118
+
unsigned long fbdiv)
119
+
{
120
+
u64 numerator = parent_rate * fbdiv;
121
+
122
+
return div64_ul(numerator, refdiv);
123
+
}
124
+
125
+
static unsigned long sg2044_pll_calc_rate(unsigned long parent_rate,
126
+
unsigned long refdiv,
127
+
unsigned long fbdiv,
128
+
unsigned long postdiv1,
129
+
unsigned long postdiv2)
130
+
{
131
+
u64 numerator, denominator;
132
+
133
+
numerator = parent_rate * fbdiv;
134
+
denominator = refdiv * (postdiv1 + 1) * (postdiv2 + 1);
135
+
136
+
return div64_u64(numerator, denominator);
137
+
}
138
+
139
+
static unsigned long sg2044_pll_recalc_rate(struct clk_hw *hw,
140
+
unsigned long parent_rate)
141
+
{
142
+
struct sg2044_pll *pll = hw_to_sg2044_pll(hw);
143
+
u32 value;
144
+
int ret;
145
+
146
+
ret = regmap_read(pll->common.regmap,
147
+
pll->syscon_offset + pll->pll.ctrl_offset + PLL_HIGH_CTRL_OFFSET,
148
+
&value);
149
+
if (ret < 0)
150
+
return 0;
151
+
152
+
return sg2044_pll_calc_rate(parent_rate,
153
+
FIELD_GET(PLL_REFDIV_MASK, value),
154
+
FIELD_GET(PLL_FBDIV_MASK, value),
155
+
FIELD_GET(PLL_POSTDIV1_MASK, value),
156
+
FIELD_GET(PLL_POSTDIV2_MASK, value));
157
+
}
158
+
159
+
static bool pll_is_better_rate(unsigned long target, unsigned long now,
160
+
unsigned long best)
161
+
{
162
+
return abs_diff(target, now) < abs_diff(target, best);
163
+
}
164
+
165
+
static int sg2042_pll_compute_postdiv(const struct sg2044_pll_limit *limits,
166
+
unsigned long target,
167
+
unsigned long parent_rate,
168
+
unsigned int refdiv,
169
+
unsigned int fbdiv,
170
+
unsigned int *postdiv1,
171
+
unsigned int *postdiv2)
172
+
{
173
+
unsigned int div1, div2;
174
+
unsigned long tmp, best_rate = 0;
175
+
unsigned int best_div1 = 0, best_div2 = 0;
176
+
177
+
for_each_pll_limit_range(div2, &limits[PLL_LIMIT_POSTDIV2]) {
178
+
for_each_pll_limit_range(div1, &limits[PLL_LIMIT_POSTDIV1]) {
179
+
tmp = sg2044_pll_calc_rate(parent_rate,
180
+
refdiv, fbdiv,
181
+
div1, div2);
182
+
183
+
if (tmp > target)
184
+
continue;
185
+
186
+
if (pll_is_better_rate(target, tmp, best_rate)) {
187
+
best_div1 = div1;
188
+
best_div2 = div2;
189
+
best_rate = tmp;
190
+
191
+
if (tmp == target)
192
+
goto find;
193
+
}
194
+
}
195
+
}
196
+
197
+
find:
198
+
if (best_rate) {
199
+
*postdiv1 = best_div1;
200
+
*postdiv2 = best_div2;
201
+
return 0;
202
+
}
203
+
204
+
return -EINVAL;
205
+
}
206
+
207
+
static int sg2044_compute_pll_setting(const struct sg2044_pll_limit *limits,
208
+
unsigned long req_rate,
209
+
unsigned long parent_rate,
210
+
unsigned int *value)
211
+
{
212
+
unsigned int refdiv, fbdiv, postdiv1, postdiv2;
213
+
unsigned int best_refdiv, best_fbdiv, best_postdiv1, best_postdiv2;
214
+
unsigned long tmp, best_rate = 0;
215
+
int ret;
216
+
217
+
for_each_pll_limit_range(fbdiv, &limits[PLL_LIMIT_FBDIV]) {
218
+
for_each_pll_limit_range(refdiv, &limits[PLL_LIMIT_REFDIV]) {
219
+
u64 vco = sg2044_pll_calc_vco_rate(parent_rate,
220
+
refdiv, fbdiv);
221
+
if (!sg2044_clk_fit_limit(vco, &limits[PLL_LIMIT_FOUTVCO]))
222
+
continue;
223
+
224
+
ret = sg2042_pll_compute_postdiv(limits,
225
+
req_rate, parent_rate,
226
+
refdiv, fbdiv,
227
+
&postdiv1, &postdiv2);
228
+
if (ret)
229
+
continue;
230
+
231
+
tmp = sg2044_pll_calc_rate(parent_rate,
232
+
refdiv, fbdiv,
233
+
postdiv1, postdiv2);
234
+
235
+
if (pll_is_better_rate(req_rate, tmp, best_rate)) {
236
+
best_refdiv = refdiv;
237
+
best_fbdiv = fbdiv;
238
+
best_postdiv1 = postdiv1;
239
+
best_postdiv2 = postdiv2;
240
+
best_rate = tmp;
241
+
242
+
if (tmp == req_rate)
243
+
goto find;
244
+
}
245
+
}
246
+
}
247
+
248
+
find:
249
+
if (best_rate) {
250
+
*value = FIELD_PREP(PLL_REFDIV_MASK, best_refdiv) |
251
+
FIELD_PREP(PLL_FBDIV_MASK, best_fbdiv) |
252
+
FIELD_PREP(PLL_POSTDIV1_MASK, best_postdiv1) |
253
+
FIELD_PREP(PLL_POSTDIV2_MASK, best_postdiv2);
254
+
return 0;
255
+
}
256
+
257
+
return -EINVAL;
258
+
}
259
+
260
+
static int sg2044_pll_determine_rate(struct clk_hw *hw,
261
+
struct clk_rate_request *req)
262
+
{
263
+
struct sg2044_pll *pll = hw_to_sg2044_pll(hw);
264
+
unsigned int value;
265
+
u64 target;
266
+
int ret;
267
+
268
+
target = clamp(req->rate, pll->pll.limits[PLL_LIMIT_FOUT].min,
269
+
pll->pll.limits[PLL_LIMIT_FOUT].max);
270
+
271
+
ret = sg2044_compute_pll_setting(pll->pll.limits, target,
272
+
req->best_parent_rate, &value);
273
+
if (ret < 0)
274
+
return ret;
275
+
276
+
req->rate = sg2044_pll_calc_rate(req->best_parent_rate,
277
+
FIELD_GET(PLL_REFDIV_MASK, value),
278
+
FIELD_GET(PLL_FBDIV_MASK, value),
279
+
FIELD_GET(PLL_POSTDIV1_MASK, value),
280
+
FIELD_GET(PLL_POSTDIV2_MASK, value));
281
+
282
+
return 0;
283
+
}
284
+
285
+
static int sg2044_pll_poll_update(struct sg2044_pll *pll)
286
+
{
287
+
int ret;
288
+
unsigned int value;
289
+
290
+
ret = regmap_read_poll_timeout_atomic(pll->common.regmap,
291
+
pll->syscon_offset + pll->pll.status_offset,
292
+
value,
293
+
(value & BIT(pll->pll.status_lock_bit)),
294
+
1, 100000);
295
+
if (ret)
296
+
return ret;
297
+
298
+
return regmap_read_poll_timeout_atomic(pll->common.regmap,
299
+
pll->syscon_offset + pll->pll.status_offset,
300
+
value,
301
+
(!(value & BIT(pll->pll.status_updating_bit))),
302
+
1, 100000);
303
+
}
304
+
305
+
static int sg2044_pll_enable(struct sg2044_pll *pll, bool en)
306
+
{
307
+
if (en) {
308
+
if (sg2044_pll_poll_update(pll) < 0)
309
+
pr_warn("%s: fail to lock pll\n", clk_hw_get_name(&pll->common.hw));
310
+
311
+
return regmap_set_bits(pll->common.regmap,
312
+
pll->syscon_offset + pll->pll.enable_offset,
313
+
BIT(pll->pll.enable_bit));
314
+
}
315
+
316
+
return regmap_clear_bits(pll->common.regmap,
317
+
pll->syscon_offset + pll->pll.enable_offset,
318
+
BIT(pll->pll.enable_bit));
319
+
}
320
+
321
+
static int sg2044_pll_update_vcosel(struct sg2044_pll *pll, u64 rate)
322
+
{
323
+
unsigned int sel;
324
+
325
+
if (rate < U64_C(2400000000))
326
+
sel = PLL_VCOSEL_1G6;
327
+
else
328
+
sel = PLL_VCOSEL_2G4;
329
+
330
+
return regmap_write_bits(pll->common.regmap,
331
+
pll->syscon_offset + pll->pll.ctrl_offset,
332
+
PLL_VCOSEL_MASK,
333
+
FIELD_PREP(PLL_VCOSEL_MASK, sel));
334
+
}
335
+
336
+
static int sg2044_pll_set_rate(struct clk_hw *hw,
337
+
unsigned long rate, unsigned long parent_rate)
338
+
{
339
+
struct sg2044_pll *pll = hw_to_sg2044_pll(hw);
340
+
unsigned int value;
341
+
u64 vco;
342
+
int ret;
343
+
344
+
ret = sg2044_compute_pll_setting(pll->pll.limits, rate,
345
+
parent_rate, &value);
346
+
if (ret < 0)
347
+
return ret;
348
+
349
+
vco = sg2044_pll_calc_vco_rate(parent_rate,
350
+
FIELD_GET(PLL_REFDIV_MASK, value),
351
+
FIELD_GET(PLL_FBDIV_MASK, value));
352
+
353
+
value |= PLL_CALIBRATE_EN;
354
+
value |= PLL_CALIBRATE_DEFAULT;
355
+
value |= PLL_UPDATE_EN;
356
+
357
+
guard(spinlock_irqsave)(pll->common.lock);
358
+
359
+
ret = sg2044_pll_enable(pll, false);
360
+
if (ret)
361
+
return ret;
362
+
363
+
sg2044_pll_update_vcosel(pll, vco);
364
+
365
+
regmap_write_bits(pll->common.regmap,
366
+
pll->syscon_offset + pll->pll.ctrl_offset +
367
+
PLL_HIGH_CTRL_OFFSET,
368
+
PLL_HIGH_CTRL_MASK, value);
369
+
370
+
sg2044_pll_enable(pll, true);
371
+
372
+
return ret;
373
+
}
374
+
375
+
static const struct clk_ops sg2044_pll_ops = {
376
+
.recalc_rate = sg2044_pll_recalc_rate,
377
+
.determine_rate = sg2044_pll_determine_rate,
378
+
.set_rate = sg2044_pll_set_rate,
379
+
};
380
+
381
+
static const struct clk_ops sg2044_pll_ro_ops = {
382
+
.recalc_rate = sg2044_pll_recalc_rate,
383
+
};
384
+
385
+
#define SG2044_CLK_COMMON_PDATA(_id, _name, _parents, _op, _flags) \
386
+
{ \
387
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parents, \
388
+
_op, (_flags)), \
389
+
.id = (_id), \
390
+
}
391
+
392
+
#define DEFINE_SG2044_PLL(_id, _name, _parent, _flags, \
393
+
_ctrl_offset, \
394
+
_status_offset, _status_lock_bit, \
395
+
_status_updating_bit, \
396
+
_enable_offset, _enable_bit, \
397
+
_limits) \
398
+
struct sg2044_pll _name = { \
399
+
.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
400
+
&sg2044_pll_ops, \
401
+
(_flags)), \
402
+
.pll = { \
403
+
.ctrl_offset = (_ctrl_offset), \
404
+
.status_offset = (_status_offset), \
405
+
.enable_offset = (_enable_offset), \
406
+
.status_lock_bit = (_status_lock_bit), \
407
+
.status_updating_bit = (_status_updating_bit), \
408
+
.enable_bit = (_enable_bit), \
409
+
.limits = (_limits), \
410
+
}, \
411
+
}
412
+
413
+
#define DEFINE_SG2044_PLL_RO(_id, _name, _parent, _flags, \
414
+
_ctrl_offset, \
415
+
_status_offset, _status_lock_bit, \
416
+
_status_updating_bit, \
417
+
_enable_offset, _enable_bit, \
418
+
_limits) \
419
+
struct sg2044_pll _name = { \
420
+
.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
421
+
&sg2044_pll_ro_ops, \
422
+
(_flags)), \
423
+
.pll = { \
424
+
.ctrl_offset = (_ctrl_offset), \
425
+
.status_offset = (_status_offset), \
426
+
.enable_offset = (_enable_offset), \
427
+
.status_lock_bit = (_status_lock_bit), \
428
+
.status_updating_bit = (_status_updating_bit), \
429
+
.enable_bit = (_enable_bit), \
430
+
.limits = (_limits), \
431
+
}, \
432
+
}
433
+
434
+
static const struct clk_parent_data osc_parents[] = {
435
+
{ .index = 0 },
436
+
};
437
+
438
+
static const struct sg2044_pll_limit pll_limits[] = {
439
+
[PLL_LIMIT_FOUTVCO] = {
440
+
.min = U64_C(1600000000),
441
+
.max = U64_C(3200000000),
442
+
},
443
+
[PLL_LIMIT_FOUT] = {
444
+
.min = U64_C(25000),
445
+
.max = U64_C(3200000000),
446
+
},
447
+
[PLL_LIMIT_REFDIV] = {
448
+
.min = U64_C(1),
449
+
.max = U64_C(63),
450
+
},
451
+
[PLL_LIMIT_FBDIV] = {
452
+
.min = U64_C(8),
453
+
.max = U64_C(1066),
454
+
},
455
+
[PLL_LIMIT_POSTDIV1] = {
456
+
.min = U64_C(0),
457
+
.max = U64_C(7),
458
+
},
459
+
[PLL_LIMIT_POSTDIV2] = {
460
+
.min = U64_C(0),
461
+
.max = U64_C(7),
462
+
},
463
+
};
464
+
465
+
static DEFINE_SG2044_PLL_RO(CLK_FPLL0, clk_fpll0, osc_parents, CLK_IS_CRITICAL,
466
+
0x58, 0x00, 22, 6,
467
+
0x04, 6, pll_limits);
468
+
469
+
static DEFINE_SG2044_PLL_RO(CLK_FPLL1, clk_fpll1, osc_parents, CLK_IS_CRITICAL,
470
+
0x60, 0x00, 23, 7,
471
+
0x04, 7, pll_limits);
472
+
473
+
static DEFINE_SG2044_PLL_RO(CLK_FPLL2, clk_fpll2, osc_parents, CLK_IS_CRITICAL,
474
+
0x20, 0x08, 16, 0,
475
+
0x0c, 0, pll_limits);
476
+
477
+
static DEFINE_SG2044_PLL_RO(CLK_DPLL0, clk_dpll0, osc_parents, CLK_IS_CRITICAL,
478
+
0x68, 0x00, 24, 8,
479
+
0x04, 8, pll_limits);
480
+
481
+
static DEFINE_SG2044_PLL_RO(CLK_DPLL1, clk_dpll1, osc_parents, CLK_IS_CRITICAL,
482
+
0x70, 0x00, 25, 9,
483
+
0x04, 9, pll_limits);
484
+
485
+
static DEFINE_SG2044_PLL_RO(CLK_DPLL2, clk_dpll2, osc_parents, CLK_IS_CRITICAL,
486
+
0x78, 0x00, 26, 10,
487
+
0x04, 10, pll_limits);
488
+
489
+
static DEFINE_SG2044_PLL_RO(CLK_DPLL3, clk_dpll3, osc_parents, CLK_IS_CRITICAL,
490
+
0x80, 0x00, 27, 11,
491
+
0x04, 11, pll_limits);
492
+
493
+
static DEFINE_SG2044_PLL_RO(CLK_DPLL4, clk_dpll4, osc_parents, CLK_IS_CRITICAL,
494
+
0x88, 0x00, 28, 12,
495
+
0x04, 12, pll_limits);
496
+
497
+
static DEFINE_SG2044_PLL_RO(CLK_DPLL5, clk_dpll5, osc_parents, CLK_IS_CRITICAL,
498
+
0x90, 0x00, 29, 13,
499
+
0x04, 13, pll_limits);
500
+
501
+
static DEFINE_SG2044_PLL_RO(CLK_DPLL6, clk_dpll6, osc_parents, CLK_IS_CRITICAL,
502
+
0x98, 0x00, 30, 14,
503
+
0x04, 14, pll_limits);
504
+
505
+
static DEFINE_SG2044_PLL_RO(CLK_DPLL7, clk_dpll7, osc_parents, CLK_IS_CRITICAL,
506
+
0xa0, 0x00, 31, 15,
507
+
0x04, 15, pll_limits);
508
+
509
+
static DEFINE_SG2044_PLL(CLK_MPLL0, clk_mpll0, osc_parents, CLK_IS_CRITICAL,
510
+
0x28, 0x00, 16, 0,
511
+
0x04, 0, pll_limits);
512
+
513
+
static DEFINE_SG2044_PLL(CLK_MPLL1, clk_mpll1, osc_parents, CLK_IS_CRITICAL,
514
+
0x30, 0x00, 17, 1,
515
+
0x04, 1, pll_limits);
516
+
517
+
static DEFINE_SG2044_PLL(CLK_MPLL2, clk_mpll2, osc_parents, CLK_IS_CRITICAL,
518
+
0x38, 0x00, 18, 2,
519
+
0x04, 2, pll_limits);
520
+
521
+
static DEFINE_SG2044_PLL(CLK_MPLL3, clk_mpll3, osc_parents, CLK_IS_CRITICAL,
522
+
0x40, 0x00, 19, 3,
523
+
0x04, 3, pll_limits);
524
+
525
+
static DEFINE_SG2044_PLL(CLK_MPLL4, clk_mpll4, osc_parents, CLK_IS_CRITICAL,
526
+
0x48, 0x00, 20, 4,
527
+
0x04, 4, pll_limits);
528
+
529
+
static DEFINE_SG2044_PLL(CLK_MPLL5, clk_mpll5, osc_parents, CLK_IS_CRITICAL,
530
+
0x50, 0x00, 21, 5,
531
+
0x04, 5, pll_limits);
532
+
533
+
static struct sg2044_clk_common * const sg2044_pll_commons[] = {
534
+
&clk_fpll0.common,
535
+
&clk_fpll1.common,
536
+
&clk_fpll2.common,
537
+
&clk_dpll0.common,
538
+
&clk_dpll1.common,
539
+
&clk_dpll2.common,
540
+
&clk_dpll3.common,
541
+
&clk_dpll4.common,
542
+
&clk_dpll5.common,
543
+
&clk_dpll6.common,
544
+
&clk_dpll7.common,
545
+
&clk_mpll0.common,
546
+
&clk_mpll1.common,
547
+
&clk_mpll2.common,
548
+
&clk_mpll3.common,
549
+
&clk_mpll4.common,
550
+
&clk_mpll5.common,
551
+
};
552
+
553
+
static int sg2044_pll_init_ctrl(struct device *dev, struct regmap *regmap,
554
+
struct sg2044_pll_ctrl *ctrl,
555
+
const struct sg2044_pll_desc_data *desc)
556
+
{
557
+
int ret, i;
558
+
559
+
spin_lock_init(&ctrl->lock);
560
+
561
+
for (i = 0; i < desc->num_pll; i++) {
562
+
struct sg2044_clk_common *common = desc->pll[i];
563
+
struct sg2044_pll *pll = hw_to_sg2044_pll(&common->hw);
564
+
565
+
common->lock = &ctrl->lock;
566
+
common->regmap = regmap;
567
+
pll->syscon_offset = SG2044_SYSCON_PLL_OFFSET;
568
+
569
+
ret = devm_clk_hw_register(dev, &common->hw);
570
+
if (ret)
571
+
return ret;
572
+
573
+
ctrl->data.hws[common->id] = &common->hw;
574
+
}
575
+
576
+
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
577
+
&ctrl->data);
578
+
}
579
+
580
+
static int sg2044_pll_probe(struct platform_device *pdev)
581
+
{
582
+
struct device *dev = &pdev->dev;
583
+
struct sg2044_pll_ctrl *ctrl;
584
+
const struct sg2044_pll_desc_data *desc;
585
+
struct regmap *regmap;
586
+
587
+
regmap = device_node_to_regmap(pdev->dev.parent->of_node);
588
+
if (IS_ERR(regmap))
589
+
return dev_err_probe(dev, PTR_ERR(regmap),
590
+
"fail to get the regmap for PLL\n");
591
+
592
+
desc = (const struct sg2044_pll_desc_data *)platform_get_device_id(pdev)->driver_data;
593
+
if (!desc)
594
+
return dev_err_probe(dev, -EINVAL, "no match data for platform\n");
595
+
596
+
ctrl = devm_kzalloc(dev, struct_size(ctrl, data.hws, desc->num_pll), GFP_KERNEL);
597
+
if (!ctrl)
598
+
return -ENOMEM;
599
+
600
+
ctrl->data.num = desc->num_pll;
601
+
602
+
return sg2044_pll_init_ctrl(dev, regmap, ctrl, desc);
603
+
}
604
+
605
+
static const struct sg2044_pll_desc_data sg2044_pll_desc_data = {
606
+
.pll = sg2044_pll_commons,
607
+
.num_pll = ARRAY_SIZE(sg2044_pll_commons),
608
+
};
609
+
610
+
static const struct platform_device_id sg2044_pll_match[] = {
611
+
{ .name = "sg2044-pll",
612
+
.driver_data = (unsigned long)&sg2044_pll_desc_data },
613
+
{ /* sentinel */ }
614
+
};
615
+
MODULE_DEVICE_TABLE(platform, sg2044_pll_match);
616
+
617
+
static struct platform_driver sg2044_clk_driver = {
618
+
.probe = sg2044_pll_probe,
619
+
.driver = {
620
+
.name = "sg2044-pll",
621
+
},
622
+
.id_table = sg2044_pll_match,
623
+
};
624
+
module_platform_driver(sg2044_clk_driver);
625
+
626
+
MODULE_AUTHOR("Inochi Amaoto <inochiama@gmail.com>");
627
+
MODULE_DESCRIPTION("Sophgo SG2044 pll clock driver");
628
+
MODULE_LICENSE("GPL");
+1812
drivers/clk/sophgo/clk-sg2044.c
+1812
drivers/clk/sophgo/clk-sg2044.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo SG2044 clock controller driver
4
+
*
5
+
* Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
6
+
*/
7
+
8
+
#include <linux/array_size.h>
9
+
#include <linux/bitfield.h>
10
+
#include <linux/bits.h>
11
+
#include <linux/cleanup.h>
12
+
#include <linux/clk.h>
13
+
#include <linux/clk-provider.h>
14
+
#include <linux/io.h>
15
+
#include <linux/iopoll.h>
16
+
#include <linux/math64.h>
17
+
#include <linux/mfd/syscon.h>
18
+
#include <linux/platform_device.h>
19
+
#include <linux/regmap.h>
20
+
#include <linux/spinlock.h>
21
+
22
+
#include <dt-bindings/clock/sophgo,sg2044-clk.h>
23
+
24
+
#define DIV_ASSERT BIT(0)
25
+
#define DIV_FACTOR_REG_SOURCE BIT(3)
26
+
#define DIV_BRANCH_EN BIT(4)
27
+
28
+
#define DIV_ASSERT_TIME 2
29
+
30
+
struct sg2044_div_internal {
31
+
u32 offset;
32
+
u32 initval;
33
+
u8 shift;
34
+
u8 width;
35
+
u16 flags;
36
+
};
37
+
38
+
struct sg2044_mux_internal {
39
+
const u32 *table;
40
+
u32 offset;
41
+
u16 shift;
42
+
u16 flags;
43
+
};
44
+
45
+
struct sg2044_gate_internal {
46
+
u32 offset;
47
+
u16 shift;
48
+
u16 flags;
49
+
};
50
+
51
+
struct sg2044_clk_common {
52
+
struct clk_hw hw;
53
+
void __iomem *base;
54
+
spinlock_t *lock;
55
+
unsigned int id;
56
+
};
57
+
58
+
struct sg2044_div {
59
+
struct sg2044_clk_common common;
60
+
struct sg2044_div_internal div;
61
+
};
62
+
63
+
struct sg2044_mux {
64
+
struct sg2044_clk_common common;
65
+
struct sg2044_mux_internal mux;
66
+
struct notifier_block nb;
67
+
u8 saved_parent;
68
+
};
69
+
70
+
struct sg2044_gate {
71
+
struct sg2044_clk_common common;
72
+
struct sg2044_gate_internal gate;
73
+
};
74
+
75
+
struct sg2044_clk_ctrl {
76
+
spinlock_t lock;
77
+
struct clk_hw_onecell_data data;
78
+
};
79
+
80
+
struct sg2044_clk_desc_data {
81
+
struct sg2044_clk_common * const *pll;
82
+
struct sg2044_clk_common * const *div;
83
+
struct sg2044_clk_common * const *mux;
84
+
struct sg2044_clk_common * const *gate;
85
+
u16 num_pll;
86
+
u16 num_div;
87
+
u16 num_mux;
88
+
u16 num_gate;
89
+
};
90
+
91
+
#define hw_to_sg2044_clk_common(_hw) \
92
+
container_of((_hw), struct sg2044_clk_common, hw)
93
+
94
+
static inline struct sg2044_div *hw_to_sg2044_div(struct clk_hw *hw)
95
+
{
96
+
return container_of(hw_to_sg2044_clk_common(hw),
97
+
struct sg2044_div, common);
98
+
}
99
+
100
+
static u32 sg2044_div_get_reg_div(u32 reg, struct sg2044_div_internal *div)
101
+
{
102
+
if ((reg & DIV_FACTOR_REG_SOURCE))
103
+
return (reg >> div->shift) & clk_div_mask(div->width);
104
+
105
+
return div->initval == 0 ? 1 : div->initval;
106
+
}
107
+
108
+
static unsigned long _sg2044_div_recalc_rate(struct sg2044_clk_common *common,
109
+
struct sg2044_div_internal *div,
110
+
unsigned long parent_rate)
111
+
{
112
+
u32 reg = readl(common->base + div->offset);
113
+
u32 val = sg2044_div_get_reg_div(reg, div);
114
+
115
+
return divider_recalc_rate(&common->hw, parent_rate, val, NULL,
116
+
div->flags, div->width);
117
+
}
118
+
119
+
static unsigned long sg2044_div_recalc_rate(struct clk_hw *hw,
120
+
unsigned long parent_rate)
121
+
{
122
+
struct sg2044_div *div = hw_to_sg2044_div(hw);
123
+
124
+
return _sg2044_div_recalc_rate(&div->common, &div->div,
125
+
parent_rate);
126
+
}
127
+
128
+
static int _sg2044_div_determine_rate(struct sg2044_clk_common *common,
129
+
struct sg2044_div_internal *div,
130
+
struct clk_rate_request *req)
131
+
{
132
+
if (div->flags & CLK_DIVIDER_READ_ONLY) {
133
+
u32 reg = readl(common->base + div->offset);
134
+
u32 val = sg2044_div_get_reg_div(reg, div);
135
+
136
+
return divider_ro_determine_rate(&common->hw, req, NULL,
137
+
div->width, div->flags,
138
+
val);
139
+
}
140
+
141
+
return divider_determine_rate(&common->hw, req, NULL,
142
+
div->width, div->flags);
143
+
}
144
+
145
+
static int sg2044_div_determine_rate(struct clk_hw *hw,
146
+
struct clk_rate_request *req)
147
+
{
148
+
struct sg2044_div *div = hw_to_sg2044_div(hw);
149
+
150
+
return _sg2044_div_determine_rate(&div->common, &div->div, req);
151
+
}
152
+
153
+
static void sg2044_div_set_reg_div(struct sg2044_clk_common *common,
154
+
struct sg2044_div_internal *div,
155
+
u32 value)
156
+
{
157
+
void __iomem *addr = common->base + div->offset;
158
+
u32 reg;
159
+
160
+
reg = readl(addr);
161
+
162
+
/* assert */
163
+
reg &= ~DIV_ASSERT;
164
+
writel(reg, addr);
165
+
166
+
/* set value */
167
+
reg = readl(addr);
168
+
reg &= ~(clk_div_mask(div->width) << div->shift);
169
+
reg |= (value << div->shift) | DIV_FACTOR_REG_SOURCE;
170
+
writel(reg, addr);
171
+
172
+
/* de-assert */
173
+
reg |= DIV_ASSERT;
174
+
writel(reg, addr);
175
+
}
176
+
177
+
static int sg2044_div_set_rate(struct clk_hw *hw,
178
+
unsigned long rate, unsigned long parent_rate)
179
+
{
180
+
struct sg2044_div *div = hw_to_sg2044_div(hw);
181
+
u32 value;
182
+
183
+
value = divider_get_val(rate, parent_rate, NULL,
184
+
div->div.width, div->div.flags);
185
+
186
+
guard(spinlock_irqsave)(div->common.lock);
187
+
188
+
sg2044_div_set_reg_div(&div->common, &div->div, value);
189
+
190
+
return 0;
191
+
}
192
+
193
+
static int sg2044_div_enable(struct clk_hw *hw)
194
+
{
195
+
struct sg2044_div *div = hw_to_sg2044_div(hw);
196
+
void __iomem *addr = div->common.base + div->div.offset;
197
+
u32 value;
198
+
199
+
guard(spinlock_irqsave)(div->common.lock);
200
+
201
+
value = readl(addr);
202
+
value |= DIV_BRANCH_EN;
203
+
writel(value, addr);
204
+
205
+
return 0;
206
+
}
207
+
208
+
static void sg2044_div_disable(struct clk_hw *hw)
209
+
{
210
+
struct sg2044_div *div = hw_to_sg2044_div(hw);
211
+
void __iomem *addr = div->common.base + div->div.offset;
212
+
u32 value;
213
+
214
+
guard(spinlock_irqsave)(div->common.lock);
215
+
216
+
value = readl(addr);
217
+
value &= ~DIV_BRANCH_EN;
218
+
writel(value, addr);
219
+
}
220
+
221
+
static int sg2044_div_is_enabled(struct clk_hw *hw)
222
+
{
223
+
struct sg2044_div *div = hw_to_sg2044_div(hw);
224
+
225
+
return readl(div->common.base + div->div.offset) & DIV_BRANCH_EN;
226
+
}
227
+
228
+
static const struct clk_ops sg2044_gateable_div_ops = {
229
+
.enable = sg2044_div_enable,
230
+
.disable = sg2044_div_disable,
231
+
.is_enabled = sg2044_div_is_enabled,
232
+
.recalc_rate = sg2044_div_recalc_rate,
233
+
.determine_rate = sg2044_div_determine_rate,
234
+
.set_rate = sg2044_div_set_rate,
235
+
};
236
+
237
+
static const struct clk_ops sg2044_div_ops = {
238
+
.recalc_rate = sg2044_div_recalc_rate,
239
+
.determine_rate = sg2044_div_determine_rate,
240
+
.set_rate = sg2044_div_set_rate,
241
+
};
242
+
243
+
static const struct clk_ops sg2044_div_ro_ops = {
244
+
.recalc_rate = sg2044_div_recalc_rate,
245
+
.determine_rate = sg2044_div_determine_rate,
246
+
};
247
+
248
+
static inline struct sg2044_mux *hw_to_sg2044_mux(struct clk_hw *hw)
249
+
{
250
+
return container_of(hw_to_sg2044_clk_common(hw),
251
+
struct sg2044_mux, common);
252
+
}
253
+
254
+
static inline struct sg2044_mux *nb_to_sg2044_mux(struct notifier_block *nb)
255
+
{
256
+
return container_of(nb, struct sg2044_mux, nb);
257
+
}
258
+
259
+
static const u32 sg2044_mux_table[] = {0, 1};
260
+
261
+
static int sg2044_mux_notifier_cb(struct notifier_block *nb,
262
+
unsigned long event,
263
+
void *data)
264
+
{
265
+
struct sg2044_mux *mux = nb_to_sg2044_mux(nb);
266
+
const struct clk_ops *ops = &clk_mux_ops;
267
+
struct clk_notifier_data *ndata = data;
268
+
struct clk_hw *hw = __clk_get_hw(ndata->clk);
269
+
int ret = 0;
270
+
271
+
if (event == PRE_RATE_CHANGE) {
272
+
mux->saved_parent = ops->get_parent(hw);
273
+
if (mux->saved_parent)
274
+
ret = ops->set_parent(hw, 0);
275
+
} else if (event == POST_RATE_CHANGE) {
276
+
ret = ops->set_parent(hw, mux->saved_parent);
277
+
}
278
+
279
+
return notifier_from_errno(ret);
280
+
}
281
+
282
+
static inline struct sg2044_gate *hw_to_sg2044_gate(struct clk_hw *hw)
283
+
{
284
+
return container_of(hw_to_sg2044_clk_common(hw),
285
+
struct sg2044_gate, common);
286
+
}
287
+
288
+
#define SG2044_CLK_COMMON_PDATA(_id, _name, _parents, _op, _flags) \
289
+
{ \
290
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parents, \
291
+
_op, (_flags)), \
292
+
.id = (_id), \
293
+
}
294
+
295
+
#define SG2044_CLK_COMMON_PHWS(_id, _name, _parents, _op, _flags) \
296
+
{ \
297
+
.hw.init = CLK_HW_INIT_PARENTS_HW(_name, _parents, \
298
+
_op, (_flags)), \
299
+
.id = (_id), \
300
+
}
301
+
302
+
#define DEFINE_SG2044_GATEABLE_DIV(_id, _name, _parent, _flags, \
303
+
_div_offset, _div_shift, _div_width, \
304
+
_div_flags, _div_initval) \
305
+
struct sg2044_div _name = { \
306
+
.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
307
+
&sg2044_gateable_div_ops,\
308
+
(_flags)), \
309
+
.div = { \
310
+
.offset = (_div_offset), \
311
+
.initval = (_div_initval), \
312
+
.shift = (_div_shift), \
313
+
.width = (_div_width), \
314
+
.flags = (_div_flags), \
315
+
}, \
316
+
}
317
+
318
+
#define DEFINE_SG2044_DIV(_id, _name, _parent, _flags, \
319
+
_div_offset, _div_shift, _div_width, \
320
+
_div_flags, _div_initval) \
321
+
struct sg2044_div _name = { \
322
+
.common = SG2044_CLK_COMMON_PHWS(_id, #_name, _parent, \
323
+
&sg2044_div_ops, \
324
+
(_flags)), \
325
+
.div = { \
326
+
.offset = (_div_offset), \
327
+
.initval = (_div_initval), \
328
+
.shift = (_div_shift), \
329
+
.width = (_div_width), \
330
+
.flags = (_div_flags), \
331
+
}, \
332
+
}
333
+
334
+
#define DEFINE_SG2044_DIV_PDATA(_id, _name, _parent, _flags, \
335
+
_div_offset, _div_shift, _div_width, \
336
+
_div_flags, _div_initval) \
337
+
struct sg2044_div _name = { \
338
+
.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
339
+
&sg2044_div_ops, \
340
+
(_flags)), \
341
+
.div = { \
342
+
.offset = (_div_offset), \
343
+
.initval = (_div_initval), \
344
+
.shift = (_div_shift), \
345
+
.width = (_div_width), \
346
+
.flags = (_div_flags), \
347
+
}, \
348
+
}
349
+
350
+
#define DEFINE_SG2044_DIV_RO(_id, _name, _parent, _flags, \
351
+
_div_offset, _div_shift, _div_width, \
352
+
_div_flags, _div_initval) \
353
+
struct sg2044_div _name = { \
354
+
.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
355
+
&sg2044_div_ro_ops, \
356
+
(_flags)), \
357
+
.div = { \
358
+
.offset = (_div_offset), \
359
+
.initval = (_div_initval), \
360
+
.shift = (_div_shift), \
361
+
.width = (_div_width), \
362
+
.flags = (_div_flags) | CLK_DIVIDER_READ_ONLY,\
363
+
}, \
364
+
}
365
+
366
+
#define DEFINE_SG2044_MUX(_id, _name, _parent, _flags, \
367
+
_mux_offset, _mux_shift, \
368
+
_mux_table, _mux_flags) \
369
+
struct sg2044_mux _name = { \
370
+
.common = SG2044_CLK_COMMON_PDATA(_id, #_name, _parent, \
371
+
&clk_mux_ops, (_flags)),\
372
+
.mux = { \
373
+
.table = (_mux_table), \
374
+
.offset = (_mux_offset), \
375
+
.shift = (_mux_shift), \
376
+
.flags = (_mux_flags), \
377
+
}, \
378
+
}
379
+
380
+
#define DEFINE_SG2044_GATE(_id, _name, _parent, _flags, \
381
+
_gate_offset, _gate_shift, _gate_flags) \
382
+
struct sg2044_gate _name = { \
383
+
.common = SG2044_CLK_COMMON_PHWS(_id, #_name, _parent, \
384
+
&clk_gate_ops, (_flags)),\
385
+
.gate = { \
386
+
.offset = (_gate_offset), \
387
+
.shift = (_gate_shift), \
388
+
.flags = (_gate_flags), \
389
+
}, \
390
+
}
391
+
392
+
static const struct clk_parent_data clk_fpll0_parent[] = {
393
+
{ .fw_name = "fpll0" },
394
+
};
395
+
396
+
static const struct clk_parent_data clk_fpll1_parent[] = {
397
+
{ .fw_name = "fpll1" },
398
+
};
399
+
400
+
static const struct clk_parent_data clk_fpll2_parent[] = {
401
+
{ .fw_name = "fpll2" },
402
+
};
403
+
404
+
static const struct clk_parent_data clk_dpll0_parent[] = {
405
+
{ .fw_name = "dpll0" },
406
+
};
407
+
408
+
static const struct clk_parent_data clk_dpll1_parent[] = {
409
+
{ .fw_name = "dpll1" },
410
+
};
411
+
412
+
static const struct clk_parent_data clk_dpll2_parent[] = {
413
+
{ .fw_name = "dpll2" },
414
+
};
415
+
416
+
static const struct clk_parent_data clk_dpll3_parent[] = {
417
+
{ .fw_name = "dpll3" },
418
+
};
419
+
420
+
static const struct clk_parent_data clk_dpll4_parent[] = {
421
+
{ .fw_name = "dpll4" },
422
+
};
423
+
424
+
static const struct clk_parent_data clk_dpll5_parent[] = {
425
+
{ .fw_name = "dpll5" },
426
+
};
427
+
428
+
static const struct clk_parent_data clk_dpll6_parent[] = {
429
+
{ .fw_name = "dpll6" },
430
+
};
431
+
432
+
static const struct clk_parent_data clk_dpll7_parent[] = {
433
+
{ .fw_name = "dpll7" },
434
+
};
435
+
436
+
static const struct clk_parent_data clk_mpll0_parent[] = {
437
+
{ .fw_name = "mpll0" },
438
+
};
439
+
440
+
static const struct clk_parent_data clk_mpll1_parent[] = {
441
+
{ .fw_name = "mpll1" },
442
+
};
443
+
444
+
static const struct clk_parent_data clk_mpll2_parent[] = {
445
+
{ .fw_name = "mpll2" },
446
+
};
447
+
448
+
static const struct clk_parent_data clk_mpll3_parent[] = {
449
+
{ .fw_name = "mpll3" },
450
+
};
451
+
452
+
static const struct clk_parent_data clk_mpll4_parent[] = {
453
+
{ .fw_name = "mpll4" },
454
+
};
455
+
456
+
static const struct clk_parent_data clk_mpll5_parent[] = {
457
+
{ .fw_name = "mpll5" },
458
+
};
459
+
460
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_AP_SYS_FIXED, clk_div_ap_sys_fixed,
461
+
clk_fpll0_parent, 0,
462
+
0x044, 16, 8,
463
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
464
+
CLK_IS_CRITICAL,
465
+
1);
466
+
467
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_AP_SYS_MAIN, clk_div_ap_sys_main,
468
+
clk_mpll0_parent, 0,
469
+
0x040, 16, 8,
470
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
471
+
CLK_IS_CRITICAL,
472
+
1);
473
+
474
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_RP_SYS_FIXED, clk_div_rp_sys_fixed,
475
+
clk_fpll0_parent, 0,
476
+
0x050, 16, 8,
477
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
478
+
CLK_IS_CRITICAL,
479
+
1);
480
+
481
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_RP_SYS_MAIN, clk_div_rp_sys_main,
482
+
clk_mpll1_parent, 0,
483
+
0x04c, 16, 8,
484
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
485
+
CLK_IS_CRITICAL,
486
+
1);
487
+
488
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_TPU_SYS_FIXED, clk_div_tpu_sys_fixed,
489
+
clk_fpll0_parent, 0,
490
+
0x058, 16, 8,
491
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
492
+
CLK_IS_CRITICAL,
493
+
2);
494
+
495
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_TPU_SYS_MAIN, clk_div_tpu_sys_main,
496
+
clk_mpll2_parent, 0,
497
+
0x054, 16, 8,
498
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
499
+
CLK_IS_CRITICAL,
500
+
1);
501
+
502
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_NOC_SYS_FIXED, clk_div_noc_sys_fixed,
503
+
clk_fpll0_parent, 0,
504
+
0x070, 16, 8,
505
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
506
+
CLK_IS_CRITICAL,
507
+
1);
508
+
509
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_NOC_SYS_MAIN, clk_div_noc_sys_main,
510
+
clk_mpll3_parent, 0,
511
+
0x06c, 16, 8,
512
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
513
+
CLK_IS_CRITICAL,
514
+
1);
515
+
516
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_VC_SRC0_FIXED, clk_div_vc_src0_fixed,
517
+
clk_fpll0_parent, 0,
518
+
0x078, 16, 8,
519
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
520
+
CLK_IS_CRITICAL,
521
+
2);
522
+
523
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_VC_SRC0_MAIN, clk_div_vc_src0_main,
524
+
clk_mpll4_parent, 0,
525
+
0x074, 16, 8,
526
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
527
+
CLK_IS_CRITICAL,
528
+
1);
529
+
530
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_VC_SRC1_FIXED, clk_div_vc_src1_fixed,
531
+
clk_fpll0_parent, 0,
532
+
0x080, 16, 8,
533
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
534
+
CLK_IS_CRITICAL,
535
+
3);
536
+
537
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_VC_SRC1_MAIN, clk_div_vc_src1_main,
538
+
clk_mpll5_parent, 0,
539
+
0x07c, 16, 8,
540
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
541
+
CLK_IS_CRITICAL,
542
+
1);
543
+
544
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_CXP_MAC_FIXED, clk_div_cxp_mac_fixed,
545
+
clk_fpll0_parent, 0,
546
+
0x088, 16, 8,
547
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
548
+
CLK_IS_CRITICAL,
549
+
2);
550
+
551
+
static DEFINE_SG2044_GATEABLE_DIV(CLK_DIV_CXP_MAC_MAIN, clk_div_cxp_mac_main,
552
+
clk_fpll1_parent, 0,
553
+
0x084, 16, 8,
554
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO |
555
+
CLK_IS_CRITICAL,
556
+
1);
557
+
558
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR0_FIXED, clk_div_ddr0_fixed,
559
+
clk_fpll0_parent, 0,
560
+
0x124, 16, 8,
561
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
562
+
2);
563
+
564
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR0_MAIN, clk_div_ddr0_main,
565
+
clk_dpll0_parent, 0,
566
+
0x120, 16, 8,
567
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
568
+
1);
569
+
570
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR1_FIXED, clk_div_ddr1_fixed,
571
+
clk_fpll0_parent, 0,
572
+
0x12c, 16, 8,
573
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
574
+
2);
575
+
576
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR1_MAIN, clk_div_ddr1_main,
577
+
clk_dpll1_parent, 0,
578
+
0x128, 16, 8,
579
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
580
+
1);
581
+
582
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR2_FIXED, clk_div_ddr2_fixed,
583
+
clk_fpll0_parent, 0,
584
+
0x134, 16, 8,
585
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
586
+
2);
587
+
588
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR2_MAIN, clk_div_ddr2_main,
589
+
clk_dpll2_parent, 0,
590
+
0x130, 16, 8,
591
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
592
+
1);
593
+
594
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR3_FIXED, clk_div_ddr3_fixed,
595
+
clk_fpll0_parent, 0,
596
+
0x13c, 16, 8,
597
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
598
+
2);
599
+
600
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR3_MAIN, clk_div_ddr3_main,
601
+
clk_dpll3_parent, 0,
602
+
0x138, 16, 8,
603
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
604
+
1);
605
+
606
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR4_FIXED, clk_div_ddr4_fixed,
607
+
clk_fpll0_parent, 0,
608
+
0x144, 16, 8,
609
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
610
+
2);
611
+
612
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR4_MAIN, clk_div_ddr4_main,
613
+
clk_dpll4_parent, 0,
614
+
0x140, 16, 8,
615
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
616
+
1);
617
+
618
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR5_FIXED, clk_div_ddr5_fixed,
619
+
clk_fpll0_parent, 0,
620
+
0x14c, 16, 8,
621
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
622
+
2);
623
+
624
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR5_MAIN, clk_div_ddr5_main,
625
+
clk_dpll5_parent, 0,
626
+
0x148, 16, 8,
627
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
628
+
1);
629
+
630
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR6_FIXED, clk_div_ddr6_fixed,
631
+
clk_fpll0_parent, 0,
632
+
0x154, 16, 8,
633
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
634
+
2);
635
+
636
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR6_MAIN, clk_div_ddr6_main,
637
+
clk_dpll6_parent, 0,
638
+
0x150, 16, 8,
639
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
640
+
1);
641
+
642
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR7_FIXED, clk_div_ddr7_fixed,
643
+
clk_fpll0_parent, 0,
644
+
0x15c, 16, 8,
645
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
646
+
2);
647
+
648
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_DDR7_MAIN, clk_div_ddr7_main,
649
+
clk_dpll7_parent, 0,
650
+
0x158, 16, 8,
651
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
652
+
1);
653
+
654
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_TOP_50M, clk_div_top_50m,
655
+
clk_fpll0_parent, 0,
656
+
0x048, 16, 8,
657
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
658
+
40);
659
+
660
+
static const struct clk_hw *clk_div_top_50m_parent[] = {
661
+
&clk_div_top_50m.common.hw,
662
+
};
663
+
664
+
static DEFINE_SG2044_DIV_RO(CLK_DIV_TOP_AXI0, clk_div_top_axi0,
665
+
clk_fpll0_parent, 0,
666
+
0x118, 16, 8,
667
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
668
+
20);
669
+
670
+
static const struct clk_hw *clk_div_top_axi0_parent[] = {
671
+
&clk_div_top_axi0.common.hw,
672
+
};
673
+
674
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_TOP_AXI_HSPERI, clk_div_top_axi_hsperi,
675
+
clk_fpll0_parent, 0,
676
+
0x11c, 16, 8,
677
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
678
+
8);
679
+
680
+
static const struct clk_hw *clk_div_top_axi_hsperi_parent[] = {
681
+
&clk_div_top_axi_hsperi.common.hw,
682
+
};
683
+
684
+
static DEFINE_SG2044_DIV(CLK_DIV_TIMER0, clk_div_timer0,
685
+
clk_div_top_50m_parent, 0,
686
+
0x0d0, 16, 16,
687
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
688
+
1);
689
+
690
+
static DEFINE_SG2044_DIV(CLK_DIV_TIMER1, clk_div_timer1,
691
+
clk_div_top_50m_parent, 0,
692
+
0x0d4, 16, 16,
693
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
694
+
1);
695
+
696
+
static DEFINE_SG2044_DIV(CLK_DIV_TIMER2, clk_div_timer2,
697
+
clk_div_top_50m_parent, 0,
698
+
0x0d8, 16, 16,
699
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
700
+
1);
701
+
702
+
static DEFINE_SG2044_DIV(CLK_DIV_TIMER3, clk_div_timer3,
703
+
clk_div_top_50m_parent, 0,
704
+
0x0dc, 16, 16,
705
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
706
+
1);
707
+
708
+
static DEFINE_SG2044_DIV(CLK_DIV_TIMER4, clk_div_timer4,
709
+
clk_div_top_50m_parent, 0,
710
+
0x0e0, 16, 16,
711
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
712
+
1);
713
+
714
+
static DEFINE_SG2044_DIV(CLK_DIV_TIMER5, clk_div_timer5,
715
+
clk_div_top_50m_parent, 0,
716
+
0x0e4, 16, 16,
717
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
718
+
1);
719
+
720
+
static DEFINE_SG2044_DIV(CLK_DIV_TIMER6, clk_div_timer6,
721
+
clk_div_top_50m_parent, 0,
722
+
0x0e8, 16, 16,
723
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
724
+
1);
725
+
726
+
static DEFINE_SG2044_DIV(CLK_DIV_TIMER7, clk_div_timer7,
727
+
clk_div_top_50m_parent, 0,
728
+
0x0ec, 16, 16,
729
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
730
+
1);
731
+
732
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_CXP_TEST_PHY, clk_div_cxp_test_phy,
733
+
clk_fpll0_parent, 0,
734
+
0x064, 16, 8,
735
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
736
+
1);
737
+
738
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_CXP_TEST_ETH_PHY, clk_div_cxp_test_eth_phy,
739
+
clk_fpll2_parent, 0,
740
+
0x068, 16, 8,
741
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
742
+
1);
743
+
744
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_C2C0_TEST_PHY, clk_div_c2c0_test_phy,
745
+
clk_fpll0_parent, 0,
746
+
0x05c, 16, 8,
747
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
748
+
1);
749
+
750
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_C2C1_TEST_PHY, clk_div_c2c1_test_phy,
751
+
clk_fpll0_parent, 0,
752
+
0x060, 16, 8,
753
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
754
+
1);
755
+
756
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_PCIE_1G, clk_div_pcie_1g,
757
+
clk_fpll1_parent, 0,
758
+
0x160, 16, 8,
759
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
760
+
1);
761
+
762
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_UART_500M, clk_div_uart_500m,
763
+
clk_fpll0_parent, 0,
764
+
0x0cc, 16, 8,
765
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
766
+
4);
767
+
768
+
static DEFINE_SG2044_DIV(CLK_DIV_GPIO_DB, clk_div_gpio_db,
769
+
clk_div_top_axi0_parent, 0,
770
+
0x0f8, 16, 16,
771
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
772
+
1000);
773
+
774
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_SD, clk_div_sd,
775
+
clk_fpll0_parent, 0,
776
+
0x110, 16, 16,
777
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
778
+
5);
779
+
780
+
static DEFINE_SG2044_DIV(CLK_DIV_SD_100K, clk_div_sd_100k,
781
+
clk_div_top_axi0_parent, 0,
782
+
0x114, 16, 16,
783
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
784
+
1000);
785
+
786
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_EMMC, clk_div_emmc,
787
+
clk_fpll0_parent, 0,
788
+
0x108, 16, 16,
789
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
790
+
5);
791
+
792
+
static DEFINE_SG2044_DIV(CLK_DIV_EMMC_100K, clk_div_emmc_100k,
793
+
clk_div_top_axi0_parent, 0,
794
+
0x10c, 16, 16,
795
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
796
+
1000);
797
+
798
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_EFUSE, clk_div_efuse,
799
+
clk_fpll0_parent, 0,
800
+
0x0f4, 16, 8,
801
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
802
+
80);
803
+
804
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_TX_ETH0, clk_div_tx_eth0,
805
+
clk_fpll0_parent, 0,
806
+
0x0fc, 16, 8,
807
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
808
+
16);
809
+
810
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_PTP_REF_I_ETH0, clk_div_ptp_ref_i_eth0,
811
+
clk_fpll0_parent, 0,
812
+
0x100, 16, 8,
813
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
814
+
40);
815
+
816
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_REF_ETH0, clk_div_ref_eth0,
817
+
clk_fpll0_parent, 0,
818
+
0x104, 16, 8,
819
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
820
+
80);
821
+
822
+
static DEFINE_SG2044_DIV_PDATA(CLK_DIV_PKA, clk_div_pka,
823
+
clk_fpll0_parent, 0,
824
+
0x0f0, 16, 8,
825
+
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
826
+
2);
827
+
828
+
static const struct clk_parent_data clk_mux_ddr0_parents[] = {
829
+
{ .hw = &clk_div_ddr0_fixed.common.hw },
830
+
{ .hw = &clk_div_ddr0_main.common.hw },
831
+
};
832
+
833
+
static DEFINE_SG2044_MUX(CLK_MUX_DDR0, clk_mux_ddr0,
834
+
clk_mux_ddr0_parents,
835
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
836
+
0x020, 7, sg2044_mux_table, CLK_MUX_READ_ONLY);
837
+
838
+
static const struct clk_parent_data clk_mux_ddr1_parents[] = {
839
+
{ .hw = &clk_div_ddr1_fixed.common.hw },
840
+
{ .hw = &clk_div_ddr1_main.common.hw },
841
+
};
842
+
843
+
static DEFINE_SG2044_MUX(CLK_MUX_DDR1, clk_mux_ddr1,
844
+
clk_mux_ddr1_parents,
845
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
846
+
0x020, 8, sg2044_mux_table, CLK_MUX_READ_ONLY);
847
+
848
+
static const struct clk_parent_data clk_mux_ddr2_parents[] = {
849
+
{ .hw = &clk_div_ddr2_fixed.common.hw },
850
+
{ .hw = &clk_div_ddr2_main.common.hw },
851
+
};
852
+
853
+
static DEFINE_SG2044_MUX(CLK_MUX_DDR2, clk_mux_ddr2,
854
+
clk_mux_ddr2_parents,
855
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
856
+
0x020, 9, sg2044_mux_table, CLK_MUX_READ_ONLY);
857
+
858
+
static const struct clk_parent_data clk_mux_ddr3_parents[] = {
859
+
{ .hw = &clk_div_ddr3_fixed.common.hw },
860
+
{ .hw = &clk_div_ddr3_main.common.hw },
861
+
};
862
+
863
+
static DEFINE_SG2044_MUX(CLK_MUX_DDR3, clk_mux_ddr3,
864
+
clk_mux_ddr3_parents,
865
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
866
+
0x020, 10, sg2044_mux_table, CLK_MUX_READ_ONLY);
867
+
868
+
static const struct clk_parent_data clk_mux_ddr4_parents[] = {
869
+
{ .hw = &clk_div_ddr4_fixed.common.hw },
870
+
{ .hw = &clk_div_ddr4_main.common.hw },
871
+
};
872
+
873
+
static DEFINE_SG2044_MUX(CLK_MUX_DDR4, clk_mux_ddr4,
874
+
clk_mux_ddr4_parents,
875
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
876
+
0x020, 11, sg2044_mux_table, CLK_MUX_READ_ONLY);
877
+
878
+
static const struct clk_parent_data clk_mux_ddr5_parents[] = {
879
+
{ .hw = &clk_div_ddr5_fixed.common.hw },
880
+
{ .hw = &clk_div_ddr5_main.common.hw },
881
+
};
882
+
883
+
static DEFINE_SG2044_MUX(CLK_MUX_DDR5, clk_mux_ddr5,
884
+
clk_mux_ddr5_parents,
885
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
886
+
0x020, 12, sg2044_mux_table, CLK_MUX_READ_ONLY);
887
+
888
+
static const struct clk_parent_data clk_mux_ddr6_parents[] = {
889
+
{ .hw = &clk_div_ddr6_fixed.common.hw },
890
+
{ .hw = &clk_div_ddr6_main.common.hw },
891
+
};
892
+
893
+
static DEFINE_SG2044_MUX(CLK_MUX_DDR6, clk_mux_ddr6,
894
+
clk_mux_ddr6_parents,
895
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
896
+
0x020, 13, sg2044_mux_table, CLK_MUX_READ_ONLY);
897
+
898
+
static const struct clk_parent_data clk_mux_ddr7_parents[] = {
899
+
{ .hw = &clk_div_ddr7_fixed.common.hw },
900
+
{ .hw = &clk_div_ddr7_main.common.hw },
901
+
};
902
+
903
+
static DEFINE_SG2044_MUX(CLK_MUX_DDR7, clk_mux_ddr7,
904
+
clk_mux_ddr7_parents,
905
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
906
+
0x020, 14, sg2044_mux_table, CLK_MUX_READ_ONLY);
907
+
908
+
static const struct clk_parent_data clk_mux_noc_sys_parents[] = {
909
+
{ .hw = &clk_div_noc_sys_fixed.common.hw },
910
+
{ .hw = &clk_div_noc_sys_main.common.hw },
911
+
};
912
+
913
+
static DEFINE_SG2044_MUX(CLK_MUX_NOC_SYS, clk_mux_noc_sys,
914
+
clk_mux_noc_sys_parents,
915
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
916
+
0x020, 3, sg2044_mux_table, 0);
917
+
918
+
static const struct clk_parent_data clk_mux_tpu_sys_parents[] = {
919
+
{ .hw = &clk_div_tpu_sys_fixed.common.hw },
920
+
{ .hw = &clk_div_tpu_sys_main.common.hw },
921
+
};
922
+
923
+
static DEFINE_SG2044_MUX(CLK_MUX_TPU_SYS, clk_mux_tpu_sys,
924
+
clk_mux_tpu_sys_parents,
925
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
926
+
0x020, 2, sg2044_mux_table, 0);
927
+
928
+
static const struct clk_parent_data clk_mux_rp_sys_parents[] = {
929
+
{ .hw = &clk_div_rp_sys_fixed.common.hw },
930
+
{ .hw = &clk_div_rp_sys_main.common.hw },
931
+
};
932
+
933
+
static DEFINE_SG2044_MUX(CLK_MUX_RP_SYS, clk_mux_rp_sys,
934
+
clk_mux_rp_sys_parents,
935
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
936
+
0x020, 1, sg2044_mux_table, 0);
937
+
938
+
static const struct clk_parent_data clk_mux_ap_sys_parents[] = {
939
+
{ .hw = &clk_div_ap_sys_fixed.common.hw },
940
+
{ .hw = &clk_div_ap_sys_main.common.hw },
941
+
};
942
+
943
+
static DEFINE_SG2044_MUX(CLK_MUX_AP_SYS, clk_mux_ap_sys,
944
+
clk_mux_ap_sys_parents,
945
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
946
+
0x020, 0, sg2044_mux_table, 0);
947
+
948
+
static const struct clk_parent_data clk_mux_vc_src0_parents[] = {
949
+
{ .hw = &clk_div_vc_src0_fixed.common.hw },
950
+
{ .hw = &clk_div_vc_src0_main.common.hw },
951
+
};
952
+
953
+
static DEFINE_SG2044_MUX(CLK_MUX_VC_SRC0, clk_mux_vc_src0,
954
+
clk_mux_vc_src0_parents,
955
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
956
+
0x020, 4, sg2044_mux_table, 0);
957
+
958
+
static const struct clk_parent_data clk_mux_vc_src1_parents[] = {
959
+
{ .hw = &clk_div_vc_src1_fixed.common.hw },
960
+
{ .hw = &clk_div_vc_src1_main.common.hw },
961
+
};
962
+
963
+
static DEFINE_SG2044_MUX(CLK_MUX_VC_SRC1, clk_mux_vc_src1,
964
+
clk_mux_vc_src1_parents,
965
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
966
+
0x020, 5, sg2044_mux_table, 0);
967
+
968
+
static const struct clk_parent_data clk_mux_cxp_mac_parents[] = {
969
+
{ .hw = &clk_div_cxp_mac_fixed.common.hw },
970
+
{ .hw = &clk_div_cxp_mac_main.common.hw },
971
+
};
972
+
973
+
static DEFINE_SG2044_MUX(CLK_MUX_CXP_MAC, clk_mux_cxp_mac,
974
+
clk_mux_cxp_mac_parents,
975
+
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
976
+
0x020, 6, sg2044_mux_table, 0);
977
+
978
+
static const struct clk_hw *clk_gate_ap_sys_parent[] = {
979
+
&clk_mux_ap_sys.common.hw,
980
+
};
981
+
982
+
static DEFINE_SG2044_GATE(CLK_GATE_AP_SYS, clk_gate_ap_sys,
983
+
clk_gate_ap_sys_parent,
984
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
985
+
0x000, 0, 0);
986
+
987
+
static const struct clk_hw *clk_gate_rp_sys_parent[] = {
988
+
&clk_mux_rp_sys.common.hw,
989
+
};
990
+
991
+
static DEFINE_SG2044_GATE(CLK_GATE_RP_SYS, clk_gate_rp_sys,
992
+
clk_gate_rp_sys_parent,
993
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
994
+
0x000, 2, 0);
995
+
996
+
static const struct clk_hw *clk_gate_tpu_sys_parent[] = {
997
+
&clk_mux_tpu_sys.common.hw,
998
+
};
999
+
1000
+
static DEFINE_SG2044_GATE(CLK_GATE_TPU_SYS, clk_gate_tpu_sys,
1001
+
clk_gate_tpu_sys_parent,
1002
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1003
+
0x000, 3, 0);
1004
+
1005
+
static const struct clk_hw *clk_gate_noc_sys_parent[] = {
1006
+
&clk_mux_noc_sys.common.hw,
1007
+
};
1008
+
1009
+
static DEFINE_SG2044_GATE(CLK_GATE_NOC_SYS, clk_gate_noc_sys,
1010
+
clk_gate_noc_sys_parent,
1011
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1012
+
0x000, 8, 0);
1013
+
1014
+
static const struct clk_hw *clk_gate_vc_src0_parent[] = {
1015
+
&clk_mux_vc_src0.common.hw,
1016
+
};
1017
+
1018
+
static DEFINE_SG2044_GATE(CLK_GATE_VC_SRC0, clk_gate_vc_src0,
1019
+
clk_gate_vc_src0_parent,
1020
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1021
+
0x000, 9, 0);
1022
+
1023
+
static const struct clk_hw *clk_gate_vc_src1_parent[] = {
1024
+
&clk_mux_vc_src1.common.hw,
1025
+
};
1026
+
1027
+
static DEFINE_SG2044_GATE(CLK_GATE_VC_SRC1, clk_gate_vc_src1,
1028
+
clk_gate_vc_src1_parent,
1029
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1030
+
0x000, 10, 0);
1031
+
1032
+
static const struct clk_hw *clk_gate_ddr0_parent[] = {
1033
+
&clk_mux_ddr0.common.hw,
1034
+
};
1035
+
1036
+
static DEFINE_SG2044_GATE(CLK_GATE_DDR0, clk_gate_ddr0,
1037
+
clk_gate_ddr0_parent,
1038
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1039
+
0x008, 7, 0);
1040
+
1041
+
static const struct clk_hw *clk_gate_ddr1_parent[] = {
1042
+
&clk_mux_ddr1.common.hw,
1043
+
};
1044
+
1045
+
static DEFINE_SG2044_GATE(CLK_GATE_DDR1, clk_gate_ddr1,
1046
+
clk_gate_ddr1_parent,
1047
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1048
+
0x008, 8, 0);
1049
+
1050
+
static const struct clk_hw *clk_gate_ddr2_parent[] = {
1051
+
&clk_mux_ddr2.common.hw,
1052
+
};
1053
+
1054
+
static DEFINE_SG2044_GATE(CLK_GATE_DDR2, clk_gate_ddr2,
1055
+
clk_gate_ddr2_parent,
1056
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1057
+
0x008, 9, 0);
1058
+
1059
+
static const struct clk_hw *clk_gate_ddr3_parent[] = {
1060
+
&clk_mux_ddr3.common.hw,
1061
+
};
1062
+
1063
+
static DEFINE_SG2044_GATE(CLK_GATE_DDR3, clk_gate_ddr3,
1064
+
clk_gate_ddr3_parent,
1065
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1066
+
0x008, 10, 0);
1067
+
1068
+
static const struct clk_hw *clk_gate_ddr4_parent[] = {
1069
+
&clk_mux_ddr4.common.hw,
1070
+
};
1071
+
1072
+
static DEFINE_SG2044_GATE(CLK_GATE_DDR4, clk_gate_ddr4,
1073
+
clk_gate_ddr4_parent,
1074
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1075
+
0x008, 11, 0);
1076
+
1077
+
static const struct clk_hw *clk_gate_ddr5_parent[] = {
1078
+
&clk_mux_ddr5.common.hw,
1079
+
};
1080
+
1081
+
static DEFINE_SG2044_GATE(CLK_GATE_DDR5, clk_gate_ddr5,
1082
+
clk_gate_ddr5_parent,
1083
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1084
+
0x008, 12, 0);
1085
+
1086
+
static const struct clk_hw *clk_gate_ddr6_parent[] = {
1087
+
&clk_mux_ddr6.common.hw,
1088
+
};
1089
+
1090
+
static DEFINE_SG2044_GATE(CLK_GATE_DDR6, clk_gate_ddr6,
1091
+
clk_gate_ddr6_parent,
1092
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1093
+
0x008, 13, 0);
1094
+
1095
+
static const struct clk_hw *clk_gate_ddr7_parent[] = {
1096
+
&clk_mux_ddr7.common.hw,
1097
+
};
1098
+
1099
+
static DEFINE_SG2044_GATE(CLK_GATE_DDR7, clk_gate_ddr7,
1100
+
clk_gate_ddr7_parent,
1101
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1102
+
0x008, 14, 0);
1103
+
1104
+
static const struct clk_hw *clk_gate_top_50m_parent[] = {
1105
+
&clk_div_top_50m.common.hw,
1106
+
};
1107
+
1108
+
static DEFINE_SG2044_GATE(CLK_GATE_TOP_50M, clk_gate_top_50m,
1109
+
clk_gate_top_50m_parent,
1110
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1111
+
0x000, 1, 0);
1112
+
1113
+
static const struct clk_hw *clk_gate_sc_rx_parent[] = {
1114
+
&clk_div_top_50m.common.hw,
1115
+
};
1116
+
1117
+
static DEFINE_SG2044_GATE(CLK_GATE_SC_RX, clk_gate_sc_rx,
1118
+
clk_gate_sc_rx_parent,
1119
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1120
+
0x000, 12, 0);
1121
+
1122
+
static const struct clk_hw *clk_gate_sc_rx_x0y1_parent[] = {
1123
+
&clk_div_top_50m.common.hw,
1124
+
};
1125
+
1126
+
static DEFINE_SG2044_GATE(CLK_GATE_SC_RX_X0Y1, clk_gate_sc_rx_x0y1,
1127
+
clk_gate_sc_rx_x0y1_parent,
1128
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1129
+
0x000, 13, 0);
1130
+
1131
+
static DEFINE_SG2044_GATE(CLK_GATE_TOP_AXI0, clk_gate_top_axi0,
1132
+
clk_div_top_axi0_parent,
1133
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1134
+
0x008, 5, 0);
1135
+
1136
+
static const struct clk_hw *clk_gate_mailbox_intc_parent[] = {
1137
+
&clk_gate_top_axi0.common.hw,
1138
+
};
1139
+
1140
+
static DEFINE_SG2044_GATE(CLK_GATE_INTC0, clk_gate_intc0,
1141
+
clk_gate_mailbox_intc_parent,
1142
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1143
+
0x020, 20, 0);
1144
+
1145
+
static DEFINE_SG2044_GATE(CLK_GATE_INTC1, clk_gate_intc1,
1146
+
clk_gate_mailbox_intc_parent,
1147
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1148
+
0x020, 21, 0);
1149
+
1150
+
static DEFINE_SG2044_GATE(CLK_GATE_INTC2, clk_gate_intc2,
1151
+
clk_gate_mailbox_intc_parent,
1152
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1153
+
0x020, 22, 0);
1154
+
1155
+
static DEFINE_SG2044_GATE(CLK_GATE_INTC3, clk_gate_intc3,
1156
+
clk_gate_mailbox_intc_parent,
1157
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1158
+
0x020, 23, 0);
1159
+
1160
+
static DEFINE_SG2044_GATE(CLK_GATE_MAILBOX0, clk_gate_mailbox0,
1161
+
clk_gate_mailbox_intc_parent,
1162
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1163
+
0x020, 16, 0);
1164
+
1165
+
static DEFINE_SG2044_GATE(CLK_GATE_MAILBOX1, clk_gate_mailbox1,
1166
+
clk_gate_mailbox_intc_parent,
1167
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1168
+
0x020, 17, 0);
1169
+
1170
+
static DEFINE_SG2044_GATE(CLK_GATE_MAILBOX2, clk_gate_mailbox2,
1171
+
clk_gate_mailbox_intc_parent,
1172
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1173
+
0x020, 18, 0);
1174
+
1175
+
static DEFINE_SG2044_GATE(CLK_GATE_MAILBOX3, clk_gate_mailbox3,
1176
+
clk_gate_mailbox_intc_parent,
1177
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1178
+
0x020, 19, 0);
1179
+
1180
+
static DEFINE_SG2044_GATE(CLK_GATE_TOP_AXI_HSPERI, clk_gate_top_axi_hsperi,
1181
+
clk_div_top_axi_hsperi_parent,
1182
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1183
+
0x008, 6, 0);
1184
+
1185
+
static DEFINE_SG2044_GATE(CLK_GATE_APB_TIMER, clk_gate_apb_timer,
1186
+
clk_div_top_axi0_parent,
1187
+
CLK_SET_RATE_PARENT,
1188
+
0x004, 7, 0);
1189
+
1190
+
static const struct clk_hw *clk_gate_timer0_parent[] = {
1191
+
&clk_div_timer0.common.hw,
1192
+
};
1193
+
1194
+
static DEFINE_SG2044_GATE(CLK_GATE_TIMER0, clk_gate_timer0,
1195
+
clk_gate_timer0_parent,
1196
+
CLK_SET_RATE_PARENT,
1197
+
0x004, 8, 0);
1198
+
1199
+
static const struct clk_hw *clk_gate_timer1_parent[] = {
1200
+
&clk_div_timer1.common.hw,
1201
+
};
1202
+
1203
+
static DEFINE_SG2044_GATE(CLK_GATE_TIMER1, clk_gate_timer1,
1204
+
clk_gate_timer1_parent,
1205
+
CLK_SET_RATE_PARENT,
1206
+
0x004, 9, 0);
1207
+
1208
+
static const struct clk_hw *clk_gate_timer2_parent[] = {
1209
+
&clk_div_timer2.common.hw,
1210
+
};
1211
+
1212
+
static DEFINE_SG2044_GATE(CLK_GATE_TIMER2, clk_gate_timer2,
1213
+
clk_gate_timer2_parent,
1214
+
CLK_SET_RATE_PARENT,
1215
+
0x004, 10, 0);
1216
+
1217
+
static const struct clk_hw *clk_gate_timer3_parent[] = {
1218
+
&clk_div_timer3.common.hw,
1219
+
};
1220
+
1221
+
static DEFINE_SG2044_GATE(CLK_GATE_TIMER3, clk_gate_timer3,
1222
+
clk_gate_timer3_parent,
1223
+
CLK_SET_RATE_PARENT,
1224
+
0x004, 11, 0);
1225
+
1226
+
static const struct clk_hw *clk_gate_timer4_parent[] = {
1227
+
&clk_div_timer4.common.hw,
1228
+
};
1229
+
1230
+
static DEFINE_SG2044_GATE(CLK_GATE_TIMER4, clk_gate_timer4,
1231
+
clk_gate_timer4_parent,
1232
+
CLK_SET_RATE_PARENT,
1233
+
0x004, 12, 0);
1234
+
1235
+
static const struct clk_hw *clk_gate_timer5_parent[] = {
1236
+
&clk_div_timer5.common.hw,
1237
+
};
1238
+
1239
+
static DEFINE_SG2044_GATE(CLK_GATE_TIMER5, clk_gate_timer5,
1240
+
clk_gate_timer5_parent,
1241
+
CLK_SET_RATE_PARENT,
1242
+
0x004, 13, 0);
1243
+
1244
+
static const struct clk_hw *clk_gate_timer6_parent[] = {
1245
+
&clk_div_timer6.common.hw,
1246
+
};
1247
+
1248
+
static DEFINE_SG2044_GATE(CLK_GATE_TIMER6, clk_gate_timer6,
1249
+
clk_gate_timer6_parent,
1250
+
CLK_SET_RATE_PARENT,
1251
+
0x004, 14, 0);
1252
+
1253
+
static const struct clk_hw *clk_gate_timer7_parent[] = {
1254
+
&clk_div_timer7.common.hw,
1255
+
};
1256
+
1257
+
static DEFINE_SG2044_GATE(CLK_GATE_TIMER7, clk_gate_timer7,
1258
+
clk_gate_timer7_parent,
1259
+
CLK_SET_RATE_PARENT,
1260
+
0x004, 15, 0);
1261
+
1262
+
static DEFINE_SG2044_GATE(CLK_GATE_CXP_CFG, clk_gate_cxp_cfg,
1263
+
clk_div_top_axi0_parent,
1264
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1265
+
0x000, 15, 0);
1266
+
1267
+
static const struct clk_hw *clk_gate_cxp_mac_parent[] = {
1268
+
&clk_mux_cxp_mac.common.hw,
1269
+
};
1270
+
1271
+
static DEFINE_SG2044_GATE(CLK_GATE_CXP_MAC, clk_gate_cxp_mac,
1272
+
clk_gate_cxp_mac_parent,
1273
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1274
+
0x000, 14, 0);
1275
+
1276
+
static const struct clk_hw *clk_gate_cxp_test_phy_parent[] = {
1277
+
&clk_div_cxp_test_phy.common.hw,
1278
+
};
1279
+
1280
+
static DEFINE_SG2044_GATE(CLK_GATE_CXP_TEST_PHY, clk_gate_cxp_test_phy,
1281
+
clk_gate_cxp_test_phy_parent,
1282
+
CLK_SET_RATE_PARENT,
1283
+
0x000, 6, 0);
1284
+
1285
+
static const struct clk_hw *clk_gate_cxp_test_eth_phy_parent[] = {
1286
+
&clk_div_cxp_test_eth_phy.common.hw,
1287
+
};
1288
+
1289
+
static DEFINE_SG2044_GATE(CLK_GATE_CXP_TEST_ETH_PHY, clk_gate_cxp_test_eth_phy,
1290
+
clk_gate_cxp_test_eth_phy_parent,
1291
+
CLK_SET_RATE_PARENT,
1292
+
0x000, 7, 0);
1293
+
1294
+
static const struct clk_hw *clk_gate_pcie_1g_parent[] = {
1295
+
&clk_div_pcie_1g.common.hw,
1296
+
};
1297
+
1298
+
static DEFINE_SG2044_GATE(CLK_GATE_PCIE_1G, clk_gate_pcie_1g,
1299
+
clk_gate_pcie_1g_parent,
1300
+
CLK_SET_RATE_PARENT,
1301
+
0x008, 15, 0);
1302
+
1303
+
static const struct clk_hw *clk_gate_c2c0_test_phy_parent[] = {
1304
+
&clk_div_c2c0_test_phy.common.hw,
1305
+
};
1306
+
1307
+
static DEFINE_SG2044_GATE(CLK_GATE_C2C0_TEST_PHY, clk_gate_c2c0_test_phy,
1308
+
clk_gate_c2c0_test_phy_parent,
1309
+
CLK_SET_RATE_PARENT,
1310
+
0x000, 4, 0);
1311
+
1312
+
static const struct clk_hw *clk_gate_c2c1_test_phy_parent[] = {
1313
+
&clk_div_c2c1_test_phy.common.hw,
1314
+
};
1315
+
1316
+
static DEFINE_SG2044_GATE(CLK_GATE_C2C1_TEST_PHY, clk_gate_c2c1_test_phy,
1317
+
clk_gate_c2c1_test_phy_parent,
1318
+
CLK_SET_RATE_PARENT,
1319
+
0x000, 5, 0);
1320
+
1321
+
static const struct clk_hw *clk_gate_uart_500m_parent[] = {
1322
+
&clk_div_uart_500m.common.hw,
1323
+
};
1324
+
1325
+
static DEFINE_SG2044_GATE(CLK_GATE_UART_500M, clk_gate_uart_500m,
1326
+
clk_gate_uart_500m_parent,
1327
+
CLK_SET_RATE_PARENT,
1328
+
0x004, 1, 0);
1329
+
1330
+
static DEFINE_SG2044_GATE(CLK_GATE_APB_UART, clk_gate_apb_uart,
1331
+
clk_div_top_axi_hsperi_parent,
1332
+
CLK_SET_RATE_PARENT,
1333
+
0x004, 2, 0);
1334
+
1335
+
static DEFINE_SG2044_GATE(CLK_GATE_APB_SPI, clk_gate_apb_spi,
1336
+
clk_div_top_axi_hsperi_parent,
1337
+
CLK_SET_RATE_PARENT,
1338
+
0x004, 22, 0);
1339
+
1340
+
static DEFINE_SG2044_GATE(CLK_GATE_AHB_SPIFMC, clk_gate_ahb_spifmc,
1341
+
clk_div_top_axi0_parent,
1342
+
CLK_SET_RATE_PARENT,
1343
+
0x004, 5, 0);
1344
+
1345
+
static DEFINE_SG2044_GATE(CLK_GATE_APB_I2C, clk_gate_apb_i2c,
1346
+
clk_div_top_axi0_parent,
1347
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1348
+
0x004, 23, 0);
1349
+
1350
+
static DEFINE_SG2044_GATE(CLK_GATE_AXI_DBG_I2C, clk_gate_axi_dbg_i2c,
1351
+
clk_div_top_axi_hsperi_parent,
1352
+
CLK_SET_RATE_PARENT,
1353
+
0x004, 3, 0);
1354
+
1355
+
static const struct clk_hw *clk_gate_gpio_db_parent[] = {
1356
+
&clk_div_gpio_db.common.hw,
1357
+
};
1358
+
1359
+
static DEFINE_SG2044_GATE(CLK_GATE_GPIO_DB, clk_gate_gpio_db,
1360
+
clk_gate_gpio_db_parent,
1361
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1362
+
0x004, 21, 0);
1363
+
1364
+
static DEFINE_SG2044_GATE(CLK_GATE_APB_GPIO_INTR, clk_gate_apb_gpio_intr,
1365
+
clk_div_top_axi0_parent,
1366
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1367
+
0x004, 20, 0);
1368
+
1369
+
static DEFINE_SG2044_GATE(CLK_GATE_APB_GPIO, clk_gate_apb_gpio,
1370
+
clk_div_top_axi0_parent,
1371
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1372
+
0x004, 19, 0);
1373
+
1374
+
static const struct clk_hw *clk_gate_sd_parent[] = {
1375
+
&clk_div_sd.common.hw,
1376
+
};
1377
+
1378
+
static DEFINE_SG2044_GATE(CLK_GATE_SD, clk_gate_sd,
1379
+
clk_gate_sd_parent,
1380
+
CLK_SET_RATE_PARENT,
1381
+
0x008, 3, 0);
1382
+
1383
+
static DEFINE_SG2044_GATE(CLK_GATE_AXI_SD, clk_gate_axi_sd,
1384
+
clk_div_top_axi_hsperi_parent,
1385
+
CLK_SET_RATE_PARENT,
1386
+
0x008, 2, 0);
1387
+
1388
+
static const struct clk_hw *clk_gate_sd_100k_parent[] = {
1389
+
&clk_div_sd_100k.common.hw,
1390
+
};
1391
+
1392
+
static DEFINE_SG2044_GATE(CLK_GATE_SD_100K, clk_gate_sd_100k,
1393
+
clk_gate_sd_100k_parent,
1394
+
CLK_SET_RATE_PARENT,
1395
+
0x008, 4, 0);
1396
+
1397
+
static const struct clk_hw *clk_gate_emmc_parent[] = {
1398
+
&clk_div_emmc.common.hw,
1399
+
};
1400
+
1401
+
static DEFINE_SG2044_GATE(CLK_GATE_EMMC, clk_gate_emmc,
1402
+
clk_gate_emmc_parent,
1403
+
CLK_SET_RATE_PARENT,
1404
+
0x008, 0, 0);
1405
+
1406
+
static DEFINE_SG2044_GATE(CLK_GATE_AXI_EMMC, clk_gate_axi_emmc,
1407
+
clk_div_top_axi_hsperi_parent,
1408
+
CLK_SET_RATE_PARENT,
1409
+
0x004, 31, 0);
1410
+
1411
+
static const struct clk_hw *clk_gate_emmc_100k_parent[] = {
1412
+
&clk_div_emmc_100k.common.hw,
1413
+
};
1414
+
1415
+
static DEFINE_SG2044_GATE(CLK_GATE_EMMC_100K, clk_gate_emmc_100k,
1416
+
clk_gate_emmc_100k_parent,
1417
+
CLK_SET_RATE_PARENT,
1418
+
0x008, 1, 0);
1419
+
1420
+
static const struct clk_hw *clk_gate_efuse_parent[] = {
1421
+
&clk_div_efuse.common.hw,
1422
+
};
1423
+
1424
+
static DEFINE_SG2044_GATE(CLK_GATE_EFUSE, clk_gate_efuse,
1425
+
clk_gate_efuse_parent,
1426
+
CLK_SET_RATE_PARENT,
1427
+
0x004, 17, 0);
1428
+
1429
+
static DEFINE_SG2044_GATE(CLK_GATE_APB_EFUSE, clk_gate_apb_efuse,
1430
+
clk_div_top_axi0_parent,
1431
+
CLK_SET_RATE_PARENT,
1432
+
0x004, 18, 0);
1433
+
1434
+
static DEFINE_SG2044_GATE(CLK_GATE_SYSDMA_AXI, clk_gate_sysdma_axi,
1435
+
clk_div_top_axi_hsperi_parent,
1436
+
CLK_SET_RATE_PARENT,
1437
+
0x004, 0, 0);
1438
+
1439
+
static const struct clk_hw *clk_gate_tx_eth0_parent[] = {
1440
+
&clk_div_tx_eth0.common.hw,
1441
+
};
1442
+
1443
+
static DEFINE_SG2044_GATE(CLK_GATE_TX_ETH0, clk_gate_tx_eth0,
1444
+
clk_gate_tx_eth0_parent,
1445
+
CLK_SET_RATE_PARENT,
1446
+
0x004, 27, 0);
1447
+
1448
+
static DEFINE_SG2044_GATE(CLK_GATE_AXI_ETH0, clk_gate_axi_eth0,
1449
+
clk_div_top_axi_hsperi_parent,
1450
+
CLK_SET_RATE_PARENT,
1451
+
0x004, 28, 0);
1452
+
1453
+
static const struct clk_hw *clk_gate_ptp_ref_i_eth0_parent[] = {
1454
+
&clk_div_ptp_ref_i_eth0.common.hw,
1455
+
};
1456
+
1457
+
static DEFINE_SG2044_GATE(CLK_GATE_PTP_REF_I_ETH0, clk_gate_ptp_ref_i_eth0,
1458
+
clk_gate_ptp_ref_i_eth0_parent,
1459
+
CLK_SET_RATE_PARENT,
1460
+
0x004, 29, 0);
1461
+
1462
+
static const struct clk_hw *clk_gate_ref_eth0_parent[] = {
1463
+
&clk_div_ref_eth0.common.hw,
1464
+
};
1465
+
1466
+
static DEFINE_SG2044_GATE(CLK_GATE_REF_ETH0, clk_gate_ref_eth0,
1467
+
clk_gate_ref_eth0_parent,
1468
+
CLK_SET_RATE_PARENT,
1469
+
0x004, 30, 0);
1470
+
1471
+
static DEFINE_SG2044_GATE(CLK_GATE_APB_RTC, clk_gate_apb_rtc,
1472
+
clk_div_top_axi0_parent,
1473
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1474
+
0x004, 26, 0);
1475
+
1476
+
static DEFINE_SG2044_GATE(CLK_GATE_APB_PWM, clk_gate_apb_pwm,
1477
+
clk_div_top_axi0_parent,
1478
+
CLK_SET_RATE_PARENT,
1479
+
0x004, 25, 0);
1480
+
1481
+
static DEFINE_SG2044_GATE(CLK_GATE_APB_WDT, clk_gate_apb_wdt,
1482
+
clk_div_top_axi0_parent,
1483
+
CLK_SET_RATE_PARENT,
1484
+
0x004, 24, 0);
1485
+
1486
+
static DEFINE_SG2044_GATE(CLK_GATE_AXI_SRAM, clk_gate_axi_sram,
1487
+
clk_div_top_axi0_parent,
1488
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1489
+
0x004, 6, 0);
1490
+
1491
+
static DEFINE_SG2044_GATE(CLK_GATE_AHB_ROM, clk_gate_ahb_rom,
1492
+
clk_div_top_axi0_parent,
1493
+
CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1494
+
0x004, 4, 0);
1495
+
1496
+
static const struct clk_hw *clk_gate_pka_parent[] = {
1497
+
&clk_div_pka.common.hw,
1498
+
};
1499
+
1500
+
static DEFINE_SG2044_GATE(CLK_GATE_PKA, clk_gate_pka,
1501
+
clk_gate_pka_parent,
1502
+
CLK_SET_RATE_PARENT,
1503
+
0x004, 16, 0);
1504
+
1505
+
static struct sg2044_clk_common * const sg2044_div_commons[] = {
1506
+
&clk_div_ap_sys_fixed.common,
1507
+
&clk_div_ap_sys_main.common,
1508
+
&clk_div_rp_sys_fixed.common,
1509
+
&clk_div_rp_sys_main.common,
1510
+
&clk_div_tpu_sys_fixed.common,
1511
+
&clk_div_tpu_sys_main.common,
1512
+
&clk_div_noc_sys_fixed.common,
1513
+
&clk_div_noc_sys_main.common,
1514
+
&clk_div_vc_src0_fixed.common,
1515
+
&clk_div_vc_src0_main.common,
1516
+
&clk_div_vc_src1_fixed.common,
1517
+
&clk_div_vc_src1_main.common,
1518
+
&clk_div_cxp_mac_fixed.common,
1519
+
&clk_div_cxp_mac_main.common,
1520
+
&clk_div_ddr0_fixed.common,
1521
+
&clk_div_ddr0_main.common,
1522
+
&clk_div_ddr1_fixed.common,
1523
+
&clk_div_ddr1_main.common,
1524
+
&clk_div_ddr2_fixed.common,
1525
+
&clk_div_ddr2_main.common,
1526
+
&clk_div_ddr3_fixed.common,
1527
+
&clk_div_ddr3_main.common,
1528
+
&clk_div_ddr4_fixed.common,
1529
+
&clk_div_ddr4_main.common,
1530
+
&clk_div_ddr5_fixed.common,
1531
+
&clk_div_ddr5_main.common,
1532
+
&clk_div_ddr6_fixed.common,
1533
+
&clk_div_ddr6_main.common,
1534
+
&clk_div_ddr7_fixed.common,
1535
+
&clk_div_ddr7_main.common,
1536
+
&clk_div_top_50m.common,
1537
+
&clk_div_top_axi0.common,
1538
+
&clk_div_top_axi_hsperi.common,
1539
+
&clk_div_timer0.common,
1540
+
&clk_div_timer1.common,
1541
+
&clk_div_timer2.common,
1542
+
&clk_div_timer3.common,
1543
+
&clk_div_timer4.common,
1544
+
&clk_div_timer5.common,
1545
+
&clk_div_timer6.common,
1546
+
&clk_div_timer7.common,
1547
+
&clk_div_cxp_test_phy.common,
1548
+
&clk_div_cxp_test_eth_phy.common,
1549
+
&clk_div_c2c0_test_phy.common,
1550
+
&clk_div_c2c1_test_phy.common,
1551
+
&clk_div_pcie_1g.common,
1552
+
&clk_div_uart_500m.common,
1553
+
&clk_div_gpio_db.common,
1554
+
&clk_div_sd.common,
1555
+
&clk_div_sd_100k.common,
1556
+
&clk_div_emmc.common,
1557
+
&clk_div_emmc_100k.common,
1558
+
&clk_div_efuse.common,
1559
+
&clk_div_tx_eth0.common,
1560
+
&clk_div_ptp_ref_i_eth0.common,
1561
+
&clk_div_ref_eth0.common,
1562
+
&clk_div_pka.common,
1563
+
};
1564
+
1565
+
static struct sg2044_clk_common * const sg2044_mux_commons[] = {
1566
+
&clk_mux_ddr0.common,
1567
+
&clk_mux_ddr1.common,
1568
+
&clk_mux_ddr2.common,
1569
+
&clk_mux_ddr3.common,
1570
+
&clk_mux_ddr4.common,
1571
+
&clk_mux_ddr5.common,
1572
+
&clk_mux_ddr6.common,
1573
+
&clk_mux_ddr7.common,
1574
+
&clk_mux_noc_sys.common,
1575
+
&clk_mux_tpu_sys.common,
1576
+
&clk_mux_rp_sys.common,
1577
+
&clk_mux_ap_sys.common,
1578
+
&clk_mux_vc_src0.common,
1579
+
&clk_mux_vc_src1.common,
1580
+
&clk_mux_cxp_mac.common,
1581
+
};
1582
+
1583
+
static struct sg2044_clk_common * const sg2044_gate_commons[] = {
1584
+
&clk_gate_ap_sys.common,
1585
+
&clk_gate_rp_sys.common,
1586
+
&clk_gate_tpu_sys.common,
1587
+
&clk_gate_noc_sys.common,
1588
+
&clk_gate_vc_src0.common,
1589
+
&clk_gate_vc_src1.common,
1590
+
&clk_gate_ddr0.common,
1591
+
&clk_gate_ddr1.common,
1592
+
&clk_gate_ddr2.common,
1593
+
&clk_gate_ddr3.common,
1594
+
&clk_gate_ddr4.common,
1595
+
&clk_gate_ddr5.common,
1596
+
&clk_gate_ddr6.common,
1597
+
&clk_gate_ddr7.common,
1598
+
&clk_gate_top_50m.common,
1599
+
&clk_gate_sc_rx.common,
1600
+
&clk_gate_sc_rx_x0y1.common,
1601
+
&clk_gate_top_axi0.common,
1602
+
&clk_gate_intc0.common,
1603
+
&clk_gate_intc1.common,
1604
+
&clk_gate_intc2.common,
1605
+
&clk_gate_intc3.common,
1606
+
&clk_gate_mailbox0.common,
1607
+
&clk_gate_mailbox1.common,
1608
+
&clk_gate_mailbox2.common,
1609
+
&clk_gate_mailbox3.common,
1610
+
&clk_gate_top_axi_hsperi.common,
1611
+
&clk_gate_apb_timer.common,
1612
+
&clk_gate_timer0.common,
1613
+
&clk_gate_timer1.common,
1614
+
&clk_gate_timer2.common,
1615
+
&clk_gate_timer3.common,
1616
+
&clk_gate_timer4.common,
1617
+
&clk_gate_timer5.common,
1618
+
&clk_gate_timer6.common,
1619
+
&clk_gate_timer7.common,
1620
+
&clk_gate_cxp_cfg.common,
1621
+
&clk_gate_cxp_mac.common,
1622
+
&clk_gate_cxp_test_phy.common,
1623
+
&clk_gate_cxp_test_eth_phy.common,
1624
+
&clk_gate_pcie_1g.common,
1625
+
&clk_gate_c2c0_test_phy.common,
1626
+
&clk_gate_c2c1_test_phy.common,
1627
+
&clk_gate_uart_500m.common,
1628
+
&clk_gate_apb_uart.common,
1629
+
&clk_gate_apb_spi.common,
1630
+
&clk_gate_ahb_spifmc.common,
1631
+
&clk_gate_apb_i2c.common,
1632
+
&clk_gate_axi_dbg_i2c.common,
1633
+
&clk_gate_gpio_db.common,
1634
+
&clk_gate_apb_gpio_intr.common,
1635
+
&clk_gate_apb_gpio.common,
1636
+
&clk_gate_sd.common,
1637
+
&clk_gate_axi_sd.common,
1638
+
&clk_gate_sd_100k.common,
1639
+
&clk_gate_emmc.common,
1640
+
&clk_gate_axi_emmc.common,
1641
+
&clk_gate_emmc_100k.common,
1642
+
&clk_gate_efuse.common,
1643
+
&clk_gate_apb_efuse.common,
1644
+
&clk_gate_sysdma_axi.common,
1645
+
&clk_gate_tx_eth0.common,
1646
+
&clk_gate_axi_eth0.common,
1647
+
&clk_gate_ptp_ref_i_eth0.common,
1648
+
&clk_gate_ref_eth0.common,
1649
+
&clk_gate_apb_rtc.common,
1650
+
&clk_gate_apb_pwm.common,
1651
+
&clk_gate_apb_wdt.common,
1652
+
&clk_gate_axi_sram.common,
1653
+
&clk_gate_ahb_rom.common,
1654
+
&clk_gate_pka.common,
1655
+
};
1656
+
1657
+
static void sg2044_clk_fix_init_parent(struct clk_hw **pdata,
1658
+
const struct clk_init_data *init,
1659
+
struct clk_hw_onecell_data *data)
1660
+
{
1661
+
u8 i;
1662
+
const struct clk_hw *hw;
1663
+
const struct sg2044_clk_common *common;
1664
+
1665
+
for (i = 0; i < init->num_parents; i++) {
1666
+
hw = init->parent_hws[i];
1667
+
common = hw_to_sg2044_clk_common(hw);
1668
+
1669
+
WARN(!data->hws[common->id], "clk %u is not register\n",
1670
+
common->id);
1671
+
pdata[i] = data->hws[common->id];
1672
+
}
1673
+
}
1674
+
1675
+
static int sg2044_clk_init_ctrl(struct device *dev, void __iomem *reg,
1676
+
struct sg2044_clk_ctrl *ctrl,
1677
+
const struct sg2044_clk_desc_data *desc)
1678
+
{
1679
+
int ret, i;
1680
+
struct clk_hw *hw;
1681
+
1682
+
spin_lock_init(&ctrl->lock);
1683
+
1684
+
for (i = 0; i < desc->num_div; i++) {
1685
+
struct sg2044_clk_common *common = desc->div[i];
1686
+
1687
+
common->lock = &ctrl->lock;
1688
+
common->base = reg;
1689
+
1690
+
ret = devm_clk_hw_register(dev, &common->hw);
1691
+
if (ret)
1692
+
return ret;
1693
+
1694
+
ctrl->data.hws[common->id] = &common->hw;
1695
+
}
1696
+
1697
+
for (i = 0; i < desc->num_mux; i++) {
1698
+
struct sg2044_clk_common *common = desc->mux[i];
1699
+
struct sg2044_mux *mux = hw_to_sg2044_mux(&common->hw);
1700
+
const struct clk_init_data *init = common->hw.init;
1701
+
1702
+
common->lock = &ctrl->lock;
1703
+
common->base = reg;
1704
+
1705
+
hw = devm_clk_hw_register_mux_parent_data_table(dev,
1706
+
init->name,
1707
+
init->parent_data,
1708
+
init->num_parents,
1709
+
init->flags,
1710
+
reg + mux->mux.offset,
1711
+
mux->mux.shift,
1712
+
1,
1713
+
mux->mux.flags,
1714
+
mux->mux.table,
1715
+
&ctrl->lock);
1716
+
if (IS_ERR(hw))
1717
+
return PTR_ERR(hw);
1718
+
1719
+
if (!(mux->mux.flags & CLK_MUX_READ_ONLY)) {
1720
+
mux->nb.notifier_call = sg2044_mux_notifier_cb;
1721
+
ret = devm_clk_notifier_register(dev, hw->clk,
1722
+
&mux->nb);
1723
+
if (ret < 0)
1724
+
return dev_err_probe(dev, ret,
1725
+
"%s: failed to register notifier\n",
1726
+
clk_hw_get_name(hw));
1727
+
}
1728
+
1729
+
ctrl->data.hws[common->id] = hw;
1730
+
}
1731
+
1732
+
for (i = 0; i < desc->num_gate; i++) {
1733
+
struct sg2044_clk_common *common = desc->gate[i];
1734
+
struct sg2044_gate *gate = hw_to_sg2044_gate(&common->hw);
1735
+
const struct clk_init_data *init = common->hw.init;
1736
+
struct clk_hw *parent_hws[1] = { };
1737
+
1738
+
sg2044_clk_fix_init_parent(parent_hws, init, &ctrl->data);
1739
+
common->lock = &ctrl->lock;
1740
+
common->base = reg;
1741
+
1742
+
hw = devm_clk_hw_register_gate_parent_hw(dev, init->name,
1743
+
parent_hws[0],
1744
+
init->flags,
1745
+
reg + gate->gate.offset,
1746
+
gate->gate.shift,
1747
+
gate->gate.flags,
1748
+
&ctrl->lock);
1749
+
if (IS_ERR(hw))
1750
+
return PTR_ERR(hw);
1751
+
1752
+
ctrl->data.hws[common->id] = hw;
1753
+
}
1754
+
1755
+
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1756
+
&ctrl->data);
1757
+
}
1758
+
1759
+
static int sg2044_clk_probe(struct platform_device *pdev)
1760
+
{
1761
+
struct device *dev = &pdev->dev;
1762
+
struct sg2044_clk_ctrl *ctrl;
1763
+
const struct sg2044_clk_desc_data *desc;
1764
+
void __iomem *reg;
1765
+
u32 num_clks;
1766
+
1767
+
reg = devm_platform_ioremap_resource(pdev, 0);
1768
+
if (IS_ERR(reg))
1769
+
return PTR_ERR(reg);
1770
+
1771
+
desc = device_get_match_data(dev);
1772
+
if (!desc)
1773
+
return dev_err_probe(dev, -EINVAL, "no match data for platform\n");
1774
+
1775
+
num_clks = desc->num_div + desc->num_gate + desc->num_mux;
1776
+
1777
+
ctrl = devm_kzalloc(dev, struct_size(ctrl, data.hws, num_clks), GFP_KERNEL);
1778
+
if (!ctrl)
1779
+
return -ENOMEM;
1780
+
1781
+
ctrl->data.num = num_clks;
1782
+
1783
+
return sg2044_clk_init_ctrl(dev, reg, ctrl, desc);
1784
+
}
1785
+
1786
+
static const struct sg2044_clk_desc_data sg2044_clk_desc_data = {
1787
+
.div = sg2044_div_commons,
1788
+
.mux = sg2044_mux_commons,
1789
+
.gate = sg2044_gate_commons,
1790
+
.num_div = ARRAY_SIZE(sg2044_div_commons),
1791
+
.num_mux = ARRAY_SIZE(sg2044_mux_commons),
1792
+
.num_gate = ARRAY_SIZE(sg2044_gate_commons),
1793
+
};
1794
+
1795
+
static const struct of_device_id sg2044_clk_match[] = {
1796
+
{ .compatible = "sophgo,sg2044-clk", .data = &sg2044_clk_desc_data },
1797
+
{ /* sentinel */ }
1798
+
};
1799
+
MODULE_DEVICE_TABLE(of, sg2044_clk_match);
1800
+
1801
+
static struct platform_driver sg2044_clk_driver = {
1802
+
.probe = sg2044_clk_probe,
1803
+
.driver = {
1804
+
.name = "sg2044-clk",
1805
+
.of_match_table = sg2044_clk_match,
1806
+
},
1807
+
};
1808
+
module_platform_driver(sg2044_clk_driver);
1809
+
1810
+
MODULE_AUTHOR("Inochi Amaoto <inochiama@gmail.com>");
1811
+
MODULE_DESCRIPTION("Sophgo SG2044 clock driver");
1812
+
MODULE_LICENSE("GPL");
+18
drivers/clk/spacemit/Kconfig
+18
drivers/clk/spacemit/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
config SPACEMIT_CCU
4
+
tristate "Clock support for SpacemiT SoCs"
5
+
depends on ARCH_SPACEMIT || COMPILE_TEST
6
+
select MFD_SYSCON
7
+
help
8
+
Say Y to enable clock controller unit support for SpacemiT SoCs.
9
+
10
+
if SPACEMIT_CCU
11
+
12
+
config SPACEMIT_K1_CCU
13
+
tristate "Support for SpacemiT K1 SoC"
14
+
depends on ARCH_SPACEMIT || COMPILE_TEST
15
+
help
16
+
Support for clock controller unit in SpacemiT K1 SoC.
17
+
18
+
endif
+5
drivers/clk/spacemit/Makefile
+5
drivers/clk/spacemit/Makefile
+1164
drivers/clk/spacemit/ccu-k1.c
+1164
drivers/clk/spacemit/ccu-k1.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2024 SpacemiT Technology Co. Ltd
4
+
* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
5
+
*/
6
+
7
+
#include <linux/array_size.h>
8
+
#include <linux/clk-provider.h>
9
+
#include <linux/delay.h>
10
+
#include <linux/mfd/syscon.h>
11
+
#include <linux/minmax.h>
12
+
#include <linux/module.h>
13
+
#include <linux/platform_device.h>
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+
15
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#include "ccu_common.h"
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#include "ccu_pll.h"
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#include "ccu_mix.h"
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#include "ccu_ddn.h"
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#include <dt-bindings/clock/spacemit,k1-syscon.h>
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22
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/* APBS register offset */
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#define APBS_PLL1_SWCR1 0x100
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#define APBS_PLL1_SWCR2 0x104
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#define APBS_PLL1_SWCR3 0x108
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#define APBS_PLL2_SWCR1 0x118
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#define APBS_PLL2_SWCR2 0x11c
28
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#define APBS_PLL2_SWCR3 0x120
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#define APBS_PLL3_SWCR1 0x124
30
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#define APBS_PLL3_SWCR2 0x128
31
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#define APBS_PLL3_SWCR3 0x12c
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+
33
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/* MPMU register offset */
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#define MPMU_POSR 0x0010
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#define POSR_PLL1_LOCK BIT(27)
36
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#define POSR_PLL2_LOCK BIT(28)
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#define POSR_PLL3_LOCK BIT(29)
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#define MPMU_SUCCR 0x0014
39
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#define MPMU_ISCCR 0x0044
40
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#define MPMU_WDTPCR 0x0200
41
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#define MPMU_RIPCCR 0x0210
42
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#define MPMU_ACGR 0x1024
43
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#define MPMU_APBCSCR 0x1050
44
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#define MPMU_SUCCR_1 0x10b0
45
+
46
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/* APBC register offset */
47
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#define APBC_UART1_CLK_RST 0x00
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#define APBC_UART2_CLK_RST 0x04
49
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#define APBC_GPIO_CLK_RST 0x08
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+
#define APBC_PWM0_CLK_RST 0x0c
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#define APBC_PWM1_CLK_RST 0x10
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#define APBC_PWM2_CLK_RST 0x14
53
+
#define APBC_PWM3_CLK_RST 0x18
54
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#define APBC_TWSI8_CLK_RST 0x20
55
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#define APBC_UART3_CLK_RST 0x24
56
+
#define APBC_RTC_CLK_RST 0x28
57
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#define APBC_TWSI0_CLK_RST 0x2c
58
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#define APBC_TWSI1_CLK_RST 0x30
59
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#define APBC_TIMERS1_CLK_RST 0x34
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#define APBC_TWSI2_CLK_RST 0x38
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#define APBC_AIB_CLK_RST 0x3c
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#define APBC_TWSI4_CLK_RST 0x40
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#define APBC_TIMERS2_CLK_RST 0x44
64
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#define APBC_ONEWIRE_CLK_RST 0x48
65
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#define APBC_TWSI5_CLK_RST 0x4c
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#define APBC_DRO_CLK_RST 0x58
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#define APBC_IR_CLK_RST 0x5c
68
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#define APBC_TWSI6_CLK_RST 0x60
69
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#define APBC_COUNTER_CLK_SEL 0x64
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#define APBC_TWSI7_CLK_RST 0x68
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#define APBC_TSEN_CLK_RST 0x6c
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#define APBC_UART4_CLK_RST 0x70
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#define APBC_UART5_CLK_RST 0x74
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#define APBC_UART6_CLK_RST 0x78
75
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#define APBC_SSP3_CLK_RST 0x7c
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#define APBC_SSPA0_CLK_RST 0x80
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#define APBC_SSPA1_CLK_RST 0x84
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#define APBC_IPC_AP2AUD_CLK_RST 0x90
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#define APBC_UART7_CLK_RST 0x94
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#define APBC_UART8_CLK_RST 0x98
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#define APBC_UART9_CLK_RST 0x9c
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#define APBC_CAN0_CLK_RST 0xa0
83
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#define APBC_PWM4_CLK_RST 0xa8
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#define APBC_PWM5_CLK_RST 0xac
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#define APBC_PWM6_CLK_RST 0xb0
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#define APBC_PWM7_CLK_RST 0xb4
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#define APBC_PWM8_CLK_RST 0xb8
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#define APBC_PWM9_CLK_RST 0xbc
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#define APBC_PWM10_CLK_RST 0xc0
90
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#define APBC_PWM11_CLK_RST 0xc4
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#define APBC_PWM12_CLK_RST 0xc8
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#define APBC_PWM13_CLK_RST 0xcc
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#define APBC_PWM14_CLK_RST 0xd0
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#define APBC_PWM15_CLK_RST 0xd4
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#define APBC_PWM16_CLK_RST 0xd8
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#define APBC_PWM17_CLK_RST 0xdc
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#define APBC_PWM18_CLK_RST 0xe0
98
+
#define APBC_PWM19_CLK_RST 0xe4
99
+
100
+
/* APMU register offset */
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#define APMU_JPG_CLK_RES_CTRL 0x020
102
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#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024
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#define APMU_ISP_CLK_RES_CTRL 0x038
104
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#define APMU_LCD_CLK_RES_CTRL1 0x044
105
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#define APMU_LCD_SPI_CLK_RES_CTRL 0x048
106
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#define APMU_LCD_CLK_RES_CTRL2 0x04c
107
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#define APMU_CCIC_CLK_RES_CTRL 0x050
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#define APMU_SDH0_CLK_RES_CTRL 0x054
109
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#define APMU_SDH1_CLK_RES_CTRL 0x058
110
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#define APMU_USB_CLK_RES_CTRL 0x05c
111
+
#define APMU_QSPI_CLK_RES_CTRL 0x060
112
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#define APMU_DMA_CLK_RES_CTRL 0x064
113
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#define APMU_AES_CLK_RES_CTRL 0x068
114
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#define APMU_VPU_CLK_RES_CTRL 0x0a4
115
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#define APMU_GPU_CLK_RES_CTRL 0x0cc
116
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#define APMU_SDH2_CLK_RES_CTRL 0x0e0
117
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#define APMU_PMUA_MC_CTRL 0x0e8
118
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#define APMU_PMU_CC2_AP 0x100
119
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#define APMU_PMUA_EM_CLK_RES_CTRL 0x104
120
+
#define APMU_AUDIO_CLK_RES_CTRL 0x14c
121
+
#define APMU_HDMI_CLK_RES_CTRL 0x1b8
122
+
#define APMU_CCI550_CLK_CTRL 0x300
123
+
#define APMU_ACLK_CLK_CTRL 0x388
124
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#define APMU_CPU_C0_CLK_CTRL 0x38C
125
+
#define APMU_CPU_C1_CLK_CTRL 0x390
126
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#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc
127
+
#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4
128
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#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc
129
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#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
130
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#define APMU_EMAC1_CLK_RES_CTRL 0x3ec
131
+
132
+
struct spacemit_ccu_data {
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struct clk_hw **hws;
134
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size_t num;
135
+
};
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+
137
+
/* APBS clocks start, APBS region contains and only contains all PLL clocks */
138
+
139
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/*
140
+
* PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for
141
+
* peripherals.
142
+
*/
143
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static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = {
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CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd),
145
+
};
146
+
147
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static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
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CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000),
149
+
};
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+
151
+
static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
152
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CCU_PLL_RATE(1600000000UL, 0x0050cd61, 0x43eaaaab),
153
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CCU_PLL_RATE(1800000000UL, 0x0050cd61, 0x4b000000),
154
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CCU_PLL_RATE(2000000000UL, 0x0050dd62, 0x2aeaaaab),
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CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd),
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CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000),
157
+
CCU_PLL_RATE(3200000000UL, 0x0050dd67, 0x43eaaaab),
158
+
};
159
+
160
+
CCU_PLL_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR3, MPMU_POSR, POSR_PLL1_LOCK,
161
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CLK_SET_RATE_GATE);
162
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CCU_PLL_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR3, MPMU_POSR, POSR_PLL2_LOCK,
163
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CLK_SET_RATE_GATE);
164
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CCU_PLL_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR3, MPMU_POSR, POSR_PLL3_LOCK,
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+
CLK_SET_RATE_GATE);
166
+
167
+
CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1);
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CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1);
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CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1);
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CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1);
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CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1);
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CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1);
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CCU_FACTOR_GATE_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1);
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CCU_FACTOR_GATE_DEFINE(pll1_d11_223p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(15), 11, 1);
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CCU_FACTOR_GATE_DEFINE(pll1_d13_189, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(16), 13, 1);
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CCU_FACTOR_GATE_DEFINE(pll1_d23_106p8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(20), 23, 1);
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CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(0), 64, 1);
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CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(10), 10, 1);
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CCU_FACTOR_GATE_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(11), 100, 1);
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CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1);
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CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1);
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CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1);
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CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1);
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CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1);
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CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1);
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CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1);
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CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1);
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+
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CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(0), 1, 1);
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CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(1), 2, 1);
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CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(2), 3, 1);
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CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(3), 4, 1);
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CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(4), 5, 1);
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CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(5), 6, 1);
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CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(6), 7, 1);
197
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CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(7), 8, 1);
198
+
199
+
CCU_FACTOR_DEFINE(pll3_20, CCU_PARENT_HW(pll3_d8), 20, 1);
200
+
CCU_FACTOR_DEFINE(pll3_40, CCU_PARENT_HW(pll3_d8), 10, 1);
201
+
CCU_FACTOR_DEFINE(pll3_80, CCU_PARENT_HW(pll3_d8), 5, 1);
202
+
203
+
/* APBS clocks end */
204
+
205
+
/* MPMU clocks start */
206
+
CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13), 0);
207
+
208
+
CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1);
209
+
210
+
CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1);
211
+
212
+
CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1);
213
+
CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(12), 3, 1);
214
+
CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(7), 6, 1);
215
+
CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(11), 6, 1);
216
+
CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(8), 16, 3);
217
+
CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(4), 12, 1);
218
+
CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(3), 24, 1);
219
+
CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(19), 24, 1);
220
+
CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(2), 48, 1);
221
+
222
+
CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1);
223
+
CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1);
224
+
CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1);
225
+
226
+
CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0);
227
+
CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1);
228
+
229
+
CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0);
230
+
CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1);
231
+
232
+
CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0);
233
+
CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(10), 13, 1);
234
+
CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6), 39, 2);
235
+
236
+
CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0);
237
+
238
+
CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0);
239
+
240
+
CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED);
241
+
CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 0);
242
+
CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 0);
243
+
244
+
CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0);
245
+
246
+
CCU_FACTOR_GATE_DEFINE(i2s_sysclk, CCU_PARENT_HW(pll1_d16_153p6), MPMU_ISCCR, BIT(31), 50, 1);
247
+
CCU_FACTOR_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_sysclk), MPMU_ISCCR, BIT(29), 1, 1);
248
+
249
+
static const struct clk_parent_data apb_parents[] = {
250
+
CCU_PARENT_HW(pll1_d96_25p6),
251
+
CCU_PARENT_HW(pll1_d48_51p2),
252
+
CCU_PARENT_HW(pll1_d96_25p6),
253
+
CCU_PARENT_HW(pll1_d24_102p4),
254
+
};
255
+
CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0);
256
+
257
+
CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), 0);
258
+
259
+
CCU_GATE_DEFINE(ripc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, 0x1, 0);
260
+
/* MPMU clocks end */
261
+
262
+
/* APBC clocks start */
263
+
static const struct clk_parent_data uart_clk_parents[] = {
264
+
CCU_PARENT_HW(pll1_m3d128_57p6),
265
+
CCU_PARENT_HW(slow_uart1_14p74),
266
+
CCU_PARENT_HW(slow_uart2_48),
267
+
};
268
+
CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART1_CLK_RST, 4, 3, BIT(1), 0);
269
+
CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3, BIT(1), 0);
270
+
CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3, BIT(1), 0);
271
+
CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3, BIT(1), 0);
272
+
CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3, BIT(1), 0);
273
+
CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3, BIT(1), 0);
274
+
CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3, BIT(1), 0);
275
+
CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3, BIT(1), 0);
276
+
CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3, BIT(1), 0);
277
+
278
+
CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0);
279
+
280
+
static const struct clk_parent_data pwm_parents[] = {
281
+
CCU_PARENT_HW(pll1_d192_12p8),
282
+
CCU_PARENT_NAME(osc),
283
+
};
284
+
CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0);
285
+
CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0);
286
+
CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0);
287
+
CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0);
288
+
CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0);
289
+
CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0);
290
+
CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0);
291
+
CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0);
292
+
CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0);
293
+
CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0);
294
+
CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0);
295
+
CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0);
296
+
CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0);
297
+
CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0);
298
+
CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0);
299
+
CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0);
300
+
CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0);
301
+
CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0);
302
+
CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0);
303
+
CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0);
304
+
305
+
static const struct clk_parent_data ssp_parents[] = {
306
+
CCU_PARENT_HW(pll1_d384_6p4),
307
+
CCU_PARENT_HW(pll1_d192_12p8),
308
+
CCU_PARENT_HW(pll1_d96_25p6),
309
+
CCU_PARENT_HW(pll1_d48_51p2),
310
+
CCU_PARENT_HW(pll1_d768_3p2),
311
+
CCU_PARENT_HW(pll1_d1536_1p6),
312
+
CCU_PARENT_HW(pll1_d3072_0p8),
313
+
};
314
+
CCU_MUX_GATE_DEFINE(ssp3_clk, ssp_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0);
315
+
316
+
CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc), APBC_RTC_CLK_RST,
317
+
BIT(7) | BIT(1), 0);
318
+
319
+
static const struct clk_parent_data twsi_parents[] = {
320
+
CCU_PARENT_HW(pll1_d78_31p5),
321
+
CCU_PARENT_HW(pll1_d48_51p2),
322
+
CCU_PARENT_HW(pll1_d40_61p44),
323
+
};
324
+
CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0);
325
+
CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0);
326
+
CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0);
327
+
CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0);
328
+
CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0);
329
+
CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0);
330
+
CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents, APBC_TWSI7_CLK_RST, 4, 3, BIT(1), 0);
331
+
/*
332
+
* APBC_TWSI8_CLK_RST has a quirk that reading always results in zero.
333
+
* Combine functional and bus bits together as a gate to avoid sharing the
334
+
* write-only register between different clock hardwares.
335
+
*/
336
+
CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5), APBC_TWSI8_CLK_RST, BIT(1) | BIT(0), 0);
337
+
338
+
static const struct clk_parent_data timer_parents[] = {
339
+
CCU_PARENT_HW(pll1_d192_12p8),
340
+
CCU_PARENT_NAME(osc),
341
+
CCU_PARENT_HW(pll1_d384_6p4),
342
+
CCU_PARENT_NAME(vctcxo_3m),
343
+
CCU_PARENT_NAME(vctcxo_1m),
344
+
};
345
+
CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0);
346
+
CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0);
347
+
348
+
CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0);
349
+
350
+
CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0);
351
+
352
+
static const struct clk_parent_data sspa_parents[] = {
353
+
CCU_PARENT_HW(pll1_d384_6p4),
354
+
CCU_PARENT_HW(pll1_d192_12p8),
355
+
CCU_PARENT_HW(pll1_d96_25p6),
356
+
CCU_PARENT_HW(pll1_d48_51p2),
357
+
CCU_PARENT_HW(pll1_d768_3p2),
358
+
CCU_PARENT_HW(pll1_d1536_1p6),
359
+
CCU_PARENT_HW(pll1_d3072_0p8),
360
+
CCU_PARENT_HW(i2s_bclk),
361
+
};
362
+
CCU_MUX_GATE_DEFINE(sspa0_clk, sspa_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0);
363
+
CCU_MUX_GATE_DEFINE(sspa1_clk, sspa_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0);
364
+
CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0);
365
+
CCU_GATE_DEFINE(ir_clk, CCU_PARENT_HW(apb_clk), APBC_IR_CLK_RST, BIT(1), 0);
366
+
CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0);
367
+
CCU_GATE_DEFINE(ipc_ap2aud_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0);
368
+
369
+
static const struct clk_parent_data can_parents[] = {
370
+
CCU_PARENT_HW(pll3_20),
371
+
CCU_PARENT_HW(pll3_40),
372
+
CCU_PARENT_HW(pll3_80),
373
+
};
374
+
CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0);
375
+
CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_CAN0_CLK_RST, BIT(0), 0);
376
+
377
+
CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART1_CLK_RST, BIT(0), 0);
378
+
CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST, BIT(0), 0);
379
+
CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST, BIT(0), 0);
380
+
CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST, BIT(0), 0);
381
+
CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST, BIT(0), 0);
382
+
CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST, BIT(0), 0);
383
+
CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST, BIT(0), 0);
384
+
CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST, BIT(0), 0);
385
+
CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST, BIT(0), 0);
386
+
387
+
CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, BIT(0), 0);
388
+
389
+
CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, BIT(0), 0);
390
+
CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, BIT(0), 0);
391
+
CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, BIT(0), 0);
392
+
CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, BIT(0), 0);
393
+
CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, BIT(0), 0);
394
+
CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, BIT(0), 0);
395
+
CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, BIT(0), 0);
396
+
CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, BIT(0), 0);
397
+
CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, BIT(0), 0);
398
+
CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, BIT(0), 0);
399
+
CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST, BIT(0), 0);
400
+
CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST, BIT(0), 0);
401
+
CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST, BIT(0), 0);
402
+
CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST, BIT(0), 0);
403
+
CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST, BIT(0), 0);
404
+
CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST, BIT(0), 0);
405
+
CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST, BIT(0), 0);
406
+
CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST, BIT(0), 0);
407
+
CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST, BIT(0), 0);
408
+
CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST, BIT(0), 0);
409
+
410
+
CCU_GATE_DEFINE(ssp3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, BIT(0), 0);
411
+
412
+
CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT(0), 0);
413
+
414
+
CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST, BIT(0), 0);
415
+
CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST, BIT(0), 0);
416
+
CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST, BIT(0), 0);
417
+
CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0), 0);
418
+
CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0);
419
+
CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0);
420
+
CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI7_CLK_RST, BIT(0), 0);
421
+
/* Placeholder to workaround quirk of the register */
422
+
CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), 1, 1);
423
+
424
+
CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0);
425
+
CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0);
426
+
427
+
CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT(0), 0);
428
+
429
+
CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_RST, BIT(0), 0);
430
+
431
+
CCU_GATE_DEFINE(sspa0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, BIT(0), 0);
432
+
CCU_GATE_DEFINE(sspa1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, BIT(0), 0);
433
+
434
+
CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(0), 0);
435
+
436
+
CCU_GATE_DEFINE(ipc_ap2aud_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0);
437
+
/* APBC clocks end */
438
+
439
+
/* APMU clocks start */
440
+
static const struct clk_parent_data pmua_aclk_parents[] = {
441
+
CCU_PARENT_HW(pll1_d10_245p76),
442
+
CCU_PARENT_HW(pll1_d8_307p2),
443
+
};
444
+
CCU_MUX_DIV_FC_DEFINE(pmua_aclk, pmua_aclk_parents, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), 0, 1, 0);
445
+
446
+
static const struct clk_parent_data cci550_clk_parents[] = {
447
+
CCU_PARENT_HW(pll1_d5_491p52),
448
+
CCU_PARENT_HW(pll1_d4_614p4),
449
+
CCU_PARENT_HW(pll1_d3_819p2),
450
+
CCU_PARENT_HW(pll2_d3),
451
+
};
452
+
CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL, 8, 3, BIT(12), 0, 2,
453
+
CLK_IS_CRITICAL);
454
+
455
+
static const struct clk_parent_data cpu_c0_hi_clk_parents[] = {
456
+
CCU_PARENT_HW(pll3_d2),
457
+
CCU_PARENT_HW(pll3_d1),
458
+
};
459
+
CCU_MUX_DEFINE(cpu_c0_hi_clk, cpu_c0_hi_clk_parents, APMU_CPU_C0_CLK_CTRL, 13, 1, 0);
460
+
static const struct clk_parent_data cpu_c0_clk_parents[] = {
461
+
CCU_PARENT_HW(pll1_d4_614p4),
462
+
CCU_PARENT_HW(pll1_d3_819p2),
463
+
CCU_PARENT_HW(pll1_d6_409p6),
464
+
CCU_PARENT_HW(pll1_d5_491p52),
465
+
CCU_PARENT_HW(pll1_d2_1228p8),
466
+
CCU_PARENT_HW(pll3_d3),
467
+
CCU_PARENT_HW(pll2_d3),
468
+
CCU_PARENT_HW(cpu_c0_hi_clk),
469
+
};
470
+
CCU_MUX_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL, BIT(12), 0, 3,
471
+
CLK_IS_CRITICAL);
472
+
CCU_DIV_DEFINE(cpu_c0_ace_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 6, 3,
473
+
CLK_IS_CRITICAL);
474
+
CCU_DIV_DEFINE(cpu_c0_tcm_clk, CCU_PARENT_HW(cpu_c0_core_clk), APMU_CPU_C0_CLK_CTRL, 9, 3,
475
+
CLK_IS_CRITICAL);
476
+
477
+
static const struct clk_parent_data cpu_c1_hi_clk_parents[] = {
478
+
CCU_PARENT_HW(pll3_d2),
479
+
CCU_PARENT_HW(pll3_d1),
480
+
};
481
+
CCU_MUX_DEFINE(cpu_c1_hi_clk, cpu_c1_hi_clk_parents, APMU_CPU_C1_CLK_CTRL, 13, 1, 0);
482
+
static const struct clk_parent_data cpu_c1_clk_parents[] = {
483
+
CCU_PARENT_HW(pll1_d4_614p4),
484
+
CCU_PARENT_HW(pll1_d3_819p2),
485
+
CCU_PARENT_HW(pll1_d6_409p6),
486
+
CCU_PARENT_HW(pll1_d5_491p52),
487
+
CCU_PARENT_HW(pll1_d2_1228p8),
488
+
CCU_PARENT_HW(pll3_d3),
489
+
CCU_PARENT_HW(pll2_d3),
490
+
CCU_PARENT_HW(cpu_c1_hi_clk),
491
+
};
492
+
CCU_MUX_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL, BIT(12), 0, 3,
493
+
CLK_IS_CRITICAL);
494
+
CCU_DIV_DEFINE(cpu_c1_ace_clk, CCU_PARENT_HW(cpu_c1_core_clk), APMU_CPU_C1_CLK_CTRL, 6, 3,
495
+
CLK_IS_CRITICAL);
496
+
497
+
static const struct clk_parent_data jpg_parents[] = {
498
+
CCU_PARENT_HW(pll1_d4_614p4),
499
+
CCU_PARENT_HW(pll1_d6_409p6),
500
+
CCU_PARENT_HW(pll1_d5_491p52),
501
+
CCU_PARENT_HW(pll1_d3_819p2),
502
+
CCU_PARENT_HW(pll1_d2_1228p8),
503
+
CCU_PARENT_HW(pll2_d4),
504
+
CCU_PARENT_HW(pll2_d3),
505
+
};
506
+
CCU_MUX_DIV_GATE_FC_DEFINE(jpg_clk, jpg_parents, APMU_JPG_CLK_RES_CTRL, 5, 3, BIT(15), 2, 3,
507
+
BIT(1), 0);
508
+
509
+
static const struct clk_parent_data ccic2phy_parents[] = {
510
+
CCU_PARENT_HW(pll1_d24_102p4),
511
+
CCU_PARENT_HW(pll1_d48_51p2_ap),
512
+
};
513
+
CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0);
514
+
515
+
static const struct clk_parent_data ccic3phy_parents[] = {
516
+
CCU_PARENT_HW(pll1_d24_102p4),
517
+
CCU_PARENT_HW(pll1_d48_51p2_ap),
518
+
};
519
+
CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0);
520
+
521
+
static const struct clk_parent_data csi_parents[] = {
522
+
CCU_PARENT_HW(pll1_d5_491p52),
523
+
CCU_PARENT_HW(pll1_d6_409p6),
524
+
CCU_PARENT_HW(pll1_d4_614p4),
525
+
CCU_PARENT_HW(pll1_d3_819p2),
526
+
CCU_PARENT_HW(pll2_d2),
527
+
CCU_PARENT_HW(pll2_d3),
528
+
CCU_PARENT_HW(pll2_d4),
529
+
CCU_PARENT_HW(pll1_d2_1228p8),
530
+
};
531
+
CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15),
532
+
16, 3, BIT(4), 0);
533
+
534
+
static const struct clk_parent_data camm_parents[] = {
535
+
CCU_PARENT_HW(pll1_d8_307p2),
536
+
CCU_PARENT_HW(pll2_d5),
537
+
CCU_PARENT_HW(pll1_d6_409p6),
538
+
CCU_PARENT_NAME(vctcxo_24m),
539
+
};
540
+
CCU_MUX_DIV_GATE_DEFINE(camm0_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2,
541
+
BIT(28), 0);
542
+
CCU_MUX_DIV_GATE_DEFINE(camm1_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2,
543
+
BIT(6), 0);
544
+
CCU_MUX_DIV_GATE_DEFINE(camm2_clk, camm_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 23, 4, 8, 2,
545
+
BIT(3), 0);
546
+
547
+
static const struct clk_parent_data isp_cpp_parents[] = {
548
+
CCU_PARENT_HW(pll1_d8_307p2),
549
+
CCU_PARENT_HW(pll1_d6_409p6),
550
+
};
551
+
CCU_MUX_DIV_GATE_DEFINE(isp_cpp_clk, isp_cpp_parents, APMU_ISP_CLK_RES_CTRL, 24, 2, 26, 1,
552
+
BIT(28), 0);
553
+
static const struct clk_parent_data isp_bus_parents[] = {
554
+
CCU_PARENT_HW(pll1_d6_409p6),
555
+
CCU_PARENT_HW(pll1_d5_491p52),
556
+
CCU_PARENT_HW(pll1_d8_307p2),
557
+
CCU_PARENT_HW(pll1_d10_245p76),
558
+
};
559
+
CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23),
560
+
21, 2, BIT(17), 0);
561
+
static const struct clk_parent_data isp_parents[] = {
562
+
CCU_PARENT_HW(pll1_d6_409p6),
563
+
CCU_PARENT_HW(pll1_d5_491p52),
564
+
CCU_PARENT_HW(pll1_d4_614p4),
565
+
CCU_PARENT_HW(pll1_d8_307p2),
566
+
};
567
+
CCU_MUX_DIV_GATE_FC_DEFINE(isp_clk, isp_parents, APMU_ISP_CLK_RES_CTRL, 4, 3, BIT(7), 8, 2,
568
+
BIT(1), 0);
569
+
570
+
static const struct clk_parent_data dpumclk_parents[] = {
571
+
CCU_PARENT_HW(pll1_d6_409p6),
572
+
CCU_PARENT_HW(pll1_d5_491p52),
573
+
CCU_PARENT_HW(pll1_d4_614p4),
574
+
CCU_PARENT_HW(pll1_d8_307p2),
575
+
};
576
+
CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dpu_mclk, dpumclk_parents, APMU_LCD_CLK_RES_CTRL2,
577
+
APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0);
578
+
579
+
static const struct clk_parent_data dpuesc_parents[] = {
580
+
CCU_PARENT_HW(pll1_d48_51p2_ap),
581
+
CCU_PARENT_HW(pll1_d52_47p26),
582
+
CCU_PARENT_HW(pll1_d96_25p6),
583
+
CCU_PARENT_HW(pll1_d32_76p8),
584
+
};
585
+
CCU_MUX_GATE_DEFINE(dpu_esc_clk, dpuesc_parents, APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0);
586
+
587
+
static const struct clk_parent_data dpubit_parents[] = {
588
+
CCU_PARENT_HW(pll1_d3_819p2),
589
+
CCU_PARENT_HW(pll2_d2),
590
+
CCU_PARENT_HW(pll2_d3),
591
+
CCU_PARENT_HW(pll1_d2_1228p8),
592
+
CCU_PARENT_HW(pll2_d4),
593
+
CCU_PARENT_HW(pll2_d5),
594
+
CCU_PARENT_HW(pll2_d7),
595
+
CCU_PARENT_HW(pll2_d8),
596
+
};
597
+
CCU_MUX_DIV_GATE_FC_DEFINE(dpu_bit_clk, dpubit_parents, APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(31),
598
+
20, 3, BIT(16), 0);
599
+
600
+
static const struct clk_parent_data dpupx_parents[] = {
601
+
CCU_PARENT_HW(pll1_d6_409p6),
602
+
CCU_PARENT_HW(pll1_d5_491p52),
603
+
CCU_PARENT_HW(pll1_d4_614p4),
604
+
CCU_PARENT_HW(pll1_d8_307p2),
605
+
CCU_PARENT_HW(pll2_d7),
606
+
CCU_PARENT_HW(pll2_d8),
607
+
};
608
+
CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dpu_pxclk, dpupx_parents, APMU_LCD_CLK_RES_CTRL2,
609
+
APMU_LCD_CLK_RES_CTRL1, 17, 4, BIT(30), 21, 3, BIT(16), 0);
610
+
611
+
CCU_GATE_DEFINE(dpu_hclk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_CLK_RES_CTRL1,
612
+
BIT(5), 0);
613
+
614
+
static const struct clk_parent_data dpu_spi_parents[] = {
615
+
CCU_PARENT_HW(pll1_d8_307p2),
616
+
CCU_PARENT_HW(pll1_d6_409p6),
617
+
CCU_PARENT_HW(pll1_d10_245p76),
618
+
CCU_PARENT_HW(pll1_d11_223p4),
619
+
CCU_PARENT_HW(pll1_d13_189),
620
+
CCU_PARENT_HW(pll1_d23_106p8),
621
+
CCU_PARENT_HW(pll2_d3),
622
+
CCU_PARENT_HW(pll2_d5),
623
+
};
624
+
CCU_MUX_DIV_GATE_FC_DEFINE(dpu_spi_clk, dpu_spi_parents, APMU_LCD_SPI_CLK_RES_CTRL, 8, 3,
625
+
BIT(7), 12, 3, BIT(1), 0);
626
+
CCU_GATE_DEFINE(dpu_spi_hbus_clk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(3), 0);
627
+
CCU_GATE_DEFINE(dpu_spi_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(5), 0);
628
+
CCU_GATE_DEFINE(dpu_spi_aclk, CCU_PARENT_HW(pmua_aclk), APMU_LCD_SPI_CLK_RES_CTRL, BIT(6), 0);
629
+
630
+
static const struct clk_parent_data v2d_parents[] = {
631
+
CCU_PARENT_HW(pll1_d5_491p52),
632
+
CCU_PARENT_HW(pll1_d6_409p6),
633
+
CCU_PARENT_HW(pll1_d8_307p2),
634
+
CCU_PARENT_HW(pll1_d4_614p4),
635
+
};
636
+
CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28), 12, 2,
637
+
BIT(8), 0);
638
+
639
+
static const struct clk_parent_data ccic_4x_parents[] = {
640
+
CCU_PARENT_HW(pll1_d5_491p52),
641
+
CCU_PARENT_HW(pll1_d6_409p6),
642
+
CCU_PARENT_HW(pll1_d4_614p4),
643
+
CCU_PARENT_HW(pll1_d3_819p2),
644
+
CCU_PARENT_HW(pll2_d2),
645
+
CCU_PARENT_HW(pll2_d3),
646
+
CCU_PARENT_HW(pll2_d4),
647
+
CCU_PARENT_HW(pll1_d2_1228p8),
648
+
};
649
+
CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES_CTRL, 18, 3,
650
+
BIT(15), 23, 2, BIT(4), 0);
651
+
652
+
static const struct clk_parent_data ccic1phy_parents[] = {
653
+
CCU_PARENT_HW(pll1_d24_102p4),
654
+
CCU_PARENT_HW(pll1_d48_51p2_ap),
655
+
};
656
+
CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0);
657
+
658
+
CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(pmua_aclk), APMU_SDH0_CLK_RES_CTRL, BIT(3), 0);
659
+
static const struct clk_parent_data sdh01_parents[] = {
660
+
CCU_PARENT_HW(pll1_d6_409p6),
661
+
CCU_PARENT_HW(pll1_d4_614p4),
662
+
CCU_PARENT_HW(pll2_d8),
663
+
CCU_PARENT_HW(pll2_d5),
664
+
CCU_PARENT_HW(pll1_d11_223p4),
665
+
CCU_PARENT_HW(pll1_d13_189),
666
+
CCU_PARENT_HW(pll1_d23_106p8),
667
+
};
668
+
CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3,
669
+
BIT(4), 0);
670
+
CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3,
671
+
BIT(4), 0);
672
+
static const struct clk_parent_data sdh2_parents[] = {
673
+
CCU_PARENT_HW(pll1_d6_409p6),
674
+
CCU_PARENT_HW(pll1_d4_614p4),
675
+
CCU_PARENT_HW(pll2_d8),
676
+
CCU_PARENT_HW(pll1_d3_819p2),
677
+
CCU_PARENT_HW(pll1_d11_223p4),
678
+
CCU_PARENT_HW(pll1_d13_189),
679
+
CCU_PARENT_HW(pll1_d23_106p8),
680
+
};
681
+
CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3, BIT(11), 5, 3,
682
+
BIT(4), 0);
683
+
684
+
CCU_GATE_DEFINE(usb_axi_clk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(1), 0);
685
+
CCU_GATE_DEFINE(usb_p1_aclk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(5), 0);
686
+
CCU_GATE_DEFINE(usb30_clk, CCU_PARENT_HW(pmua_aclk), APMU_USB_CLK_RES_CTRL, BIT(8), 0);
687
+
688
+
static const struct clk_parent_data qspi_parents[] = {
689
+
CCU_PARENT_HW(pll1_d6_409p6),
690
+
CCU_PARENT_HW(pll2_d8),
691
+
CCU_PARENT_HW(pll1_d8_307p2),
692
+
CCU_PARENT_HW(pll1_d10_245p76),
693
+
CCU_PARENT_HW(pll1_d11_223p4),
694
+
CCU_PARENT_HW(pll1_d23_106p8),
695
+
CCU_PARENT_HW(pll1_d5_491p52),
696
+
CCU_PARENT_HW(pll1_d13_189),
697
+
};
698
+
CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL, 9, 3, BIT(12), 6, 3,
699
+
BIT(4), 0);
700
+
CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_QSPI_CLK_RES_CTRL, BIT(3), 0);
701
+
CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(pmua_aclk), APMU_DMA_CLK_RES_CTRL, BIT(3), 0);
702
+
703
+
static const struct clk_parent_data aes_parents[] = {
704
+
CCU_PARENT_HW(pll1_d12_204p8),
705
+
CCU_PARENT_HW(pll1_d24_102p4),
706
+
};
707
+
CCU_MUX_GATE_DEFINE(aes_clk, aes_parents, APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0);
708
+
709
+
static const struct clk_parent_data vpu_parents[] = {
710
+
CCU_PARENT_HW(pll1_d4_614p4),
711
+
CCU_PARENT_HW(pll1_d5_491p52),
712
+
CCU_PARENT_HW(pll1_d3_819p2),
713
+
CCU_PARENT_HW(pll1_d6_409p6),
714
+
CCU_PARENT_HW(pll3_d6),
715
+
CCU_PARENT_HW(pll2_d3),
716
+
CCU_PARENT_HW(pll2_d4),
717
+
CCU_PARENT_HW(pll2_d5),
718
+
};
719
+
CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13, 3, BIT(21), 10, 3,
720
+
BIT(3), 0);
721
+
722
+
static const struct clk_parent_data gpu_parents[] = {
723
+
CCU_PARENT_HW(pll1_d4_614p4),
724
+
CCU_PARENT_HW(pll1_d5_491p52),
725
+
CCU_PARENT_HW(pll1_d3_819p2),
726
+
CCU_PARENT_HW(pll1_d6_409p6),
727
+
CCU_PARENT_HW(pll3_d6),
728
+
CCU_PARENT_HW(pll2_d3),
729
+
CCU_PARENT_HW(pll2_d4),
730
+
CCU_PARENT_HW(pll2_d5),
731
+
};
732
+
CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12, 3, BIT(15), 18, 3,
733
+
BIT(4), 0);
734
+
735
+
static const struct clk_parent_data emmc_parents[] = {
736
+
CCU_PARENT_HW(pll1_d6_409p6),
737
+
CCU_PARENT_HW(pll1_d4_614p4),
738
+
CCU_PARENT_HW(pll1_d52_47p26),
739
+
CCU_PARENT_HW(pll1_d3_819p2),
740
+
};
741
+
CCU_MUX_DIV_GATE_FC_DEFINE(emmc_clk, emmc_parents, APMU_PMUA_EM_CLK_RES_CTRL, 8, 3, BIT(11),
742
+
6, 2, BIT(4), 0);
743
+
CCU_DIV_GATE_DEFINE(emmc_x_clk, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMUA_EM_CLK_RES_CTRL, 12,
744
+
3, BIT(15), 0);
745
+
746
+
static const struct clk_parent_data audio_parents[] = {
747
+
CCU_PARENT_HW(pll1_aud_245p7),
748
+
CCU_PARENT_HW(pll1_d8_307p2),
749
+
CCU_PARENT_HW(pll1_d6_409p6),
750
+
};
751
+
CCU_MUX_DIV_GATE_FC_DEFINE(audio_clk, audio_parents, APMU_AUDIO_CLK_RES_CTRL, 4, 3, BIT(15),
752
+
7, 3, BIT(12), 0);
753
+
754
+
static const struct clk_parent_data hdmi_parents[] = {
755
+
CCU_PARENT_HW(pll1_d6_409p6),
756
+
CCU_PARENT_HW(pll1_d5_491p52),
757
+
CCU_PARENT_HW(pll1_d4_614p4),
758
+
CCU_PARENT_HW(pll1_d8_307p2),
759
+
};
760
+
CCU_MUX_DIV_GATE_FC_DEFINE(hdmi_mclk, hdmi_parents, APMU_HDMI_CLK_RES_CTRL, 1, 4, BIT(29), 5,
761
+
3, BIT(0), 0);
762
+
763
+
CCU_GATE_DEFINE(pcie0_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(2), 0);
764
+
CCU_GATE_DEFINE(pcie0_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(1), 0);
765
+
CCU_GATE_DEFINE(pcie0_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_0, BIT(0), 0);
766
+
767
+
CCU_GATE_DEFINE(pcie1_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(2), 0);
768
+
CCU_GATE_DEFINE(pcie1_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(1), 0);
769
+
CCU_GATE_DEFINE(pcie1_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_1, BIT(0), 0);
770
+
771
+
CCU_GATE_DEFINE(pcie2_master_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(2), 0);
772
+
CCU_GATE_DEFINE(pcie2_slave_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(1), 0);
773
+
CCU_GATE_DEFINE(pcie2_dbi_clk, CCU_PARENT_HW(pmua_aclk), APMU_PCIE_CLK_RES_CTRL_2, BIT(0), 0);
774
+
775
+
CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0);
776
+
CCU_GATE_DEFINE(emac0_ptp_clk, CCU_PARENT_HW(pll2_d6), APMU_EMAC0_CLK_RES_CTRL, BIT(15), 0);
777
+
CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0);
778
+
CCU_GATE_DEFINE(emac1_ptp_clk, CCU_PARENT_HW(pll2_d6), APMU_EMAC1_CLK_RES_CTRL, BIT(15), 0);
779
+
780
+
CCU_GATE_DEFINE(emmc_bus_clk, CCU_PARENT_HW(pmua_aclk), APMU_PMUA_EM_CLK_RES_CTRL, BIT(3), 0);
781
+
/* APMU clocks end */
782
+
783
+
static struct clk_hw *k1_ccu_pll_hws[] = {
784
+
[CLK_PLL1] = &pll1.common.hw,
785
+
[CLK_PLL2] = &pll2.common.hw,
786
+
[CLK_PLL3] = &pll3.common.hw,
787
+
[CLK_PLL1_D2] = &pll1_d2.common.hw,
788
+
[CLK_PLL1_D3] = &pll1_d3.common.hw,
789
+
[CLK_PLL1_D4] = &pll1_d4.common.hw,
790
+
[CLK_PLL1_D5] = &pll1_d5.common.hw,
791
+
[CLK_PLL1_D6] = &pll1_d6.common.hw,
792
+
[CLK_PLL1_D7] = &pll1_d7.common.hw,
793
+
[CLK_PLL1_D8] = &pll1_d8.common.hw,
794
+
[CLK_PLL1_D11] = &pll1_d11_223p4.common.hw,
795
+
[CLK_PLL1_D13] = &pll1_d13_189.common.hw,
796
+
[CLK_PLL1_D23] = &pll1_d23_106p8.common.hw,
797
+
[CLK_PLL1_D64] = &pll1_d64_38p4.common.hw,
798
+
[CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw,
799
+
[CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw,
800
+
[CLK_PLL2_D1] = &pll2_d1.common.hw,
801
+
[CLK_PLL2_D2] = &pll2_d2.common.hw,
802
+
[CLK_PLL2_D3] = &pll2_d3.common.hw,
803
+
[CLK_PLL2_D4] = &pll2_d4.common.hw,
804
+
[CLK_PLL2_D5] = &pll2_d5.common.hw,
805
+
[CLK_PLL2_D6] = &pll2_d6.common.hw,
806
+
[CLK_PLL2_D7] = &pll2_d7.common.hw,
807
+
[CLK_PLL2_D8] = &pll2_d8.common.hw,
808
+
[CLK_PLL3_D1] = &pll3_d1.common.hw,
809
+
[CLK_PLL3_D2] = &pll3_d2.common.hw,
810
+
[CLK_PLL3_D3] = &pll3_d3.common.hw,
811
+
[CLK_PLL3_D4] = &pll3_d4.common.hw,
812
+
[CLK_PLL3_D5] = &pll3_d5.common.hw,
813
+
[CLK_PLL3_D6] = &pll3_d6.common.hw,
814
+
[CLK_PLL3_D7] = &pll3_d7.common.hw,
815
+
[CLK_PLL3_D8] = &pll3_d8.common.hw,
816
+
[CLK_PLL3_80] = &pll3_80.common.hw,
817
+
[CLK_PLL3_40] = &pll3_40.common.hw,
818
+
[CLK_PLL3_20] = &pll3_20.common.hw,
819
+
};
820
+
821
+
static const struct spacemit_ccu_data k1_ccu_pll_data = {
822
+
.hws = k1_ccu_pll_hws,
823
+
.num = ARRAY_SIZE(k1_ccu_pll_hws),
824
+
};
825
+
826
+
static struct clk_hw *k1_ccu_mpmu_hws[] = {
827
+
[CLK_PLL1_307P2] = &pll1_d8_307p2.common.hw,
828
+
[CLK_PLL1_76P8] = &pll1_d32_76p8.common.hw,
829
+
[CLK_PLL1_61P44] = &pll1_d40_61p44.common.hw,
830
+
[CLK_PLL1_153P6] = &pll1_d16_153p6.common.hw,
831
+
[CLK_PLL1_102P4] = &pll1_d24_102p4.common.hw,
832
+
[CLK_PLL1_51P2] = &pll1_d48_51p2.common.hw,
833
+
[CLK_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw,
834
+
[CLK_PLL1_57P6] = &pll1_m3d128_57p6.common.hw,
835
+
[CLK_PLL1_25P6] = &pll1_d96_25p6.common.hw,
836
+
[CLK_PLL1_12P8] = &pll1_d192_12p8.common.hw,
837
+
[CLK_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw,
838
+
[CLK_PLL1_6P4] = &pll1_d384_6p4.common.hw,
839
+
[CLK_PLL1_3P2] = &pll1_d768_3p2.common.hw,
840
+
[CLK_PLL1_1P6] = &pll1_d1536_1p6.common.hw,
841
+
[CLK_PLL1_0P8] = &pll1_d3072_0p8.common.hw,
842
+
[CLK_PLL1_409P6] = &pll1_d6_409p6.common.hw,
843
+
[CLK_PLL1_204P8] = &pll1_d12_204p8.common.hw,
844
+
[CLK_PLL1_491] = &pll1_d5_491p52.common.hw,
845
+
[CLK_PLL1_245P76] = &pll1_d10_245p76.common.hw,
846
+
[CLK_PLL1_614] = &pll1_d4_614p4.common.hw,
847
+
[CLK_PLL1_47P26] = &pll1_d52_47p26.common.hw,
848
+
[CLK_PLL1_31P5] = &pll1_d78_31p5.common.hw,
849
+
[CLK_PLL1_819] = &pll1_d3_819p2.common.hw,
850
+
[CLK_PLL1_1228] = &pll1_d2_1228p8.common.hw,
851
+
[CLK_SLOW_UART] = &slow_uart.common.hw,
852
+
[CLK_SLOW_UART1] = &slow_uart1_14p74.common.hw,
853
+
[CLK_SLOW_UART2] = &slow_uart2_48.common.hw,
854
+
[CLK_WDT] = &wdt_clk.common.hw,
855
+
[CLK_RIPC] = &ripc_clk.common.hw,
856
+
[CLK_I2S_SYSCLK] = &i2s_sysclk.common.hw,
857
+
[CLK_I2S_BCLK] = &i2s_bclk.common.hw,
858
+
[CLK_APB] = &apb_clk.common.hw,
859
+
[CLK_WDT_BUS] = &wdt_bus_clk.common.hw,
860
+
};
861
+
862
+
static const struct spacemit_ccu_data k1_ccu_mpmu_data = {
863
+
.hws = k1_ccu_mpmu_hws,
864
+
.num = ARRAY_SIZE(k1_ccu_mpmu_hws),
865
+
};
866
+
867
+
static struct clk_hw *k1_ccu_apbc_hws[] = {
868
+
[CLK_UART0] = &uart0_clk.common.hw,
869
+
[CLK_UART2] = &uart2_clk.common.hw,
870
+
[CLK_UART3] = &uart3_clk.common.hw,
871
+
[CLK_UART4] = &uart4_clk.common.hw,
872
+
[CLK_UART5] = &uart5_clk.common.hw,
873
+
[CLK_UART6] = &uart6_clk.common.hw,
874
+
[CLK_UART7] = &uart7_clk.common.hw,
875
+
[CLK_UART8] = &uart8_clk.common.hw,
876
+
[CLK_UART9] = &uart9_clk.common.hw,
877
+
[CLK_GPIO] = &gpio_clk.common.hw,
878
+
[CLK_PWM0] = &pwm0_clk.common.hw,
879
+
[CLK_PWM1] = &pwm1_clk.common.hw,
880
+
[CLK_PWM2] = &pwm2_clk.common.hw,
881
+
[CLK_PWM3] = &pwm3_clk.common.hw,
882
+
[CLK_PWM4] = &pwm4_clk.common.hw,
883
+
[CLK_PWM5] = &pwm5_clk.common.hw,
884
+
[CLK_PWM6] = &pwm6_clk.common.hw,
885
+
[CLK_PWM7] = &pwm7_clk.common.hw,
886
+
[CLK_PWM8] = &pwm8_clk.common.hw,
887
+
[CLK_PWM9] = &pwm9_clk.common.hw,
888
+
[CLK_PWM10] = &pwm10_clk.common.hw,
889
+
[CLK_PWM11] = &pwm11_clk.common.hw,
890
+
[CLK_PWM12] = &pwm12_clk.common.hw,
891
+
[CLK_PWM13] = &pwm13_clk.common.hw,
892
+
[CLK_PWM14] = &pwm14_clk.common.hw,
893
+
[CLK_PWM15] = &pwm15_clk.common.hw,
894
+
[CLK_PWM16] = &pwm16_clk.common.hw,
895
+
[CLK_PWM17] = &pwm17_clk.common.hw,
896
+
[CLK_PWM18] = &pwm18_clk.common.hw,
897
+
[CLK_PWM19] = &pwm19_clk.common.hw,
898
+
[CLK_SSP3] = &ssp3_clk.common.hw,
899
+
[CLK_RTC] = &rtc_clk.common.hw,
900
+
[CLK_TWSI0] = &twsi0_clk.common.hw,
901
+
[CLK_TWSI1] = &twsi1_clk.common.hw,
902
+
[CLK_TWSI2] = &twsi2_clk.common.hw,
903
+
[CLK_TWSI4] = &twsi4_clk.common.hw,
904
+
[CLK_TWSI5] = &twsi5_clk.common.hw,
905
+
[CLK_TWSI6] = &twsi6_clk.common.hw,
906
+
[CLK_TWSI7] = &twsi7_clk.common.hw,
907
+
[CLK_TWSI8] = &twsi8_clk.common.hw,
908
+
[CLK_TIMERS1] = &timers1_clk.common.hw,
909
+
[CLK_TIMERS2] = &timers2_clk.common.hw,
910
+
[CLK_AIB] = &aib_clk.common.hw,
911
+
[CLK_ONEWIRE] = &onewire_clk.common.hw,
912
+
[CLK_SSPA0] = &sspa0_clk.common.hw,
913
+
[CLK_SSPA1] = &sspa1_clk.common.hw,
914
+
[CLK_DRO] = &dro_clk.common.hw,
915
+
[CLK_IR] = &ir_clk.common.hw,
916
+
[CLK_TSEN] = &tsen_clk.common.hw,
917
+
[CLK_IPC_AP2AUD] = &ipc_ap2aud_clk.common.hw,
918
+
[CLK_CAN0] = &can0_clk.common.hw,
919
+
[CLK_CAN0_BUS] = &can0_bus_clk.common.hw,
920
+
[CLK_UART0_BUS] = &uart0_bus_clk.common.hw,
921
+
[CLK_UART2_BUS] = &uart2_bus_clk.common.hw,
922
+
[CLK_UART3_BUS] = &uart3_bus_clk.common.hw,
923
+
[CLK_UART4_BUS] = &uart4_bus_clk.common.hw,
924
+
[CLK_UART5_BUS] = &uart5_bus_clk.common.hw,
925
+
[CLK_UART6_BUS] = &uart6_bus_clk.common.hw,
926
+
[CLK_UART7_BUS] = &uart7_bus_clk.common.hw,
927
+
[CLK_UART8_BUS] = &uart8_bus_clk.common.hw,
928
+
[CLK_UART9_BUS] = &uart9_bus_clk.common.hw,
929
+
[CLK_GPIO_BUS] = &gpio_bus_clk.common.hw,
930
+
[CLK_PWM0_BUS] = &pwm0_bus_clk.common.hw,
931
+
[CLK_PWM1_BUS] = &pwm1_bus_clk.common.hw,
932
+
[CLK_PWM2_BUS] = &pwm2_bus_clk.common.hw,
933
+
[CLK_PWM3_BUS] = &pwm3_bus_clk.common.hw,
934
+
[CLK_PWM4_BUS] = &pwm4_bus_clk.common.hw,
935
+
[CLK_PWM5_BUS] = &pwm5_bus_clk.common.hw,
936
+
[CLK_PWM6_BUS] = &pwm6_bus_clk.common.hw,
937
+
[CLK_PWM7_BUS] = &pwm7_bus_clk.common.hw,
938
+
[CLK_PWM8_BUS] = &pwm8_bus_clk.common.hw,
939
+
[CLK_PWM9_BUS] = &pwm9_bus_clk.common.hw,
940
+
[CLK_PWM10_BUS] = &pwm10_bus_clk.common.hw,
941
+
[CLK_PWM11_BUS] = &pwm11_bus_clk.common.hw,
942
+
[CLK_PWM12_BUS] = &pwm12_bus_clk.common.hw,
943
+
[CLK_PWM13_BUS] = &pwm13_bus_clk.common.hw,
944
+
[CLK_PWM14_BUS] = &pwm14_bus_clk.common.hw,
945
+
[CLK_PWM15_BUS] = &pwm15_bus_clk.common.hw,
946
+
[CLK_PWM16_BUS] = &pwm16_bus_clk.common.hw,
947
+
[CLK_PWM17_BUS] = &pwm17_bus_clk.common.hw,
948
+
[CLK_PWM18_BUS] = &pwm18_bus_clk.common.hw,
949
+
[CLK_PWM19_BUS] = &pwm19_bus_clk.common.hw,
950
+
[CLK_SSP3_BUS] = &ssp3_bus_clk.common.hw,
951
+
[CLK_RTC_BUS] = &rtc_bus_clk.common.hw,
952
+
[CLK_TWSI0_BUS] = &twsi0_bus_clk.common.hw,
953
+
[CLK_TWSI1_BUS] = &twsi1_bus_clk.common.hw,
954
+
[CLK_TWSI2_BUS] = &twsi2_bus_clk.common.hw,
955
+
[CLK_TWSI4_BUS] = &twsi4_bus_clk.common.hw,
956
+
[CLK_TWSI5_BUS] = &twsi5_bus_clk.common.hw,
957
+
[CLK_TWSI6_BUS] = &twsi6_bus_clk.common.hw,
958
+
[CLK_TWSI7_BUS] = &twsi7_bus_clk.common.hw,
959
+
[CLK_TWSI8_BUS] = &twsi8_bus_clk.common.hw,
960
+
[CLK_TIMERS1_BUS] = &timers1_bus_clk.common.hw,
961
+
[CLK_TIMERS2_BUS] = &timers2_bus_clk.common.hw,
962
+
[CLK_AIB_BUS] = &aib_bus_clk.common.hw,
963
+
[CLK_ONEWIRE_BUS] = &onewire_bus_clk.common.hw,
964
+
[CLK_SSPA0_BUS] = &sspa0_bus_clk.common.hw,
965
+
[CLK_SSPA1_BUS] = &sspa1_bus_clk.common.hw,
966
+
[CLK_TSEN_BUS] = &tsen_bus_clk.common.hw,
967
+
[CLK_IPC_AP2AUD_BUS] = &ipc_ap2aud_bus_clk.common.hw,
968
+
};
969
+
970
+
static const struct spacemit_ccu_data k1_ccu_apbc_data = {
971
+
.hws = k1_ccu_apbc_hws,
972
+
.num = ARRAY_SIZE(k1_ccu_apbc_hws),
973
+
};
974
+
975
+
static struct clk_hw *k1_ccu_apmu_hws[] = {
976
+
[CLK_CCI550] = &cci550_clk.common.hw,
977
+
[CLK_CPU_C0_HI] = &cpu_c0_hi_clk.common.hw,
978
+
[CLK_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw,
979
+
[CLK_CPU_C0_ACE] = &cpu_c0_ace_clk.common.hw,
980
+
[CLK_CPU_C0_TCM] = &cpu_c0_tcm_clk.common.hw,
981
+
[CLK_CPU_C1_HI] = &cpu_c1_hi_clk.common.hw,
982
+
[CLK_CPU_C1_CORE] = &cpu_c1_core_clk.common.hw,
983
+
[CLK_CPU_C1_ACE] = &cpu_c1_ace_clk.common.hw,
984
+
[CLK_CCIC_4X] = &ccic_4x_clk.common.hw,
985
+
[CLK_CCIC1PHY] = &ccic1phy_clk.common.hw,
986
+
[CLK_SDH_AXI] = &sdh_axi_aclk.common.hw,
987
+
[CLK_SDH0] = &sdh0_clk.common.hw,
988
+
[CLK_SDH1] = &sdh1_clk.common.hw,
989
+
[CLK_SDH2] = &sdh2_clk.common.hw,
990
+
[CLK_USB_P1] = &usb_p1_aclk.common.hw,
991
+
[CLK_USB_AXI] = &usb_axi_clk.common.hw,
992
+
[CLK_USB30] = &usb30_clk.common.hw,
993
+
[CLK_QSPI] = &qspi_clk.common.hw,
994
+
[CLK_QSPI_BUS] = &qspi_bus_clk.common.hw,
995
+
[CLK_DMA] = &dma_clk.common.hw,
996
+
[CLK_AES] = &aes_clk.common.hw,
997
+
[CLK_VPU] = &vpu_clk.common.hw,
998
+
[CLK_GPU] = &gpu_clk.common.hw,
999
+
[CLK_EMMC] = &emmc_clk.common.hw,
1000
+
[CLK_EMMC_X] = &emmc_x_clk.common.hw,
1001
+
[CLK_AUDIO] = &audio_clk.common.hw,
1002
+
[CLK_HDMI] = &hdmi_mclk.common.hw,
1003
+
[CLK_PMUA_ACLK] = &pmua_aclk.common.hw,
1004
+
[CLK_PCIE0_MASTER] = &pcie0_master_clk.common.hw,
1005
+
[CLK_PCIE0_SLAVE] = &pcie0_slave_clk.common.hw,
1006
+
[CLK_PCIE0_DBI] = &pcie0_dbi_clk.common.hw,
1007
+
[CLK_PCIE1_MASTER] = &pcie1_master_clk.common.hw,
1008
+
[CLK_PCIE1_SLAVE] = &pcie1_slave_clk.common.hw,
1009
+
[CLK_PCIE1_DBI] = &pcie1_dbi_clk.common.hw,
1010
+
[CLK_PCIE2_MASTER] = &pcie2_master_clk.common.hw,
1011
+
[CLK_PCIE2_SLAVE] = &pcie2_slave_clk.common.hw,
1012
+
[CLK_PCIE2_DBI] = &pcie2_dbi_clk.common.hw,
1013
+
[CLK_EMAC0_BUS] = &emac0_bus_clk.common.hw,
1014
+
[CLK_EMAC0_PTP] = &emac0_ptp_clk.common.hw,
1015
+
[CLK_EMAC1_BUS] = &emac1_bus_clk.common.hw,
1016
+
[CLK_EMAC1_PTP] = &emac1_ptp_clk.common.hw,
1017
+
[CLK_JPG] = &jpg_clk.common.hw,
1018
+
[CLK_CCIC2PHY] = &ccic2phy_clk.common.hw,
1019
+
[CLK_CCIC3PHY] = &ccic3phy_clk.common.hw,
1020
+
[CLK_CSI] = &csi_clk.common.hw,
1021
+
[CLK_CAMM0] = &camm0_clk.common.hw,
1022
+
[CLK_CAMM1] = &camm1_clk.common.hw,
1023
+
[CLK_CAMM2] = &camm2_clk.common.hw,
1024
+
[CLK_ISP_CPP] = &isp_cpp_clk.common.hw,
1025
+
[CLK_ISP_BUS] = &isp_bus_clk.common.hw,
1026
+
[CLK_ISP] = &isp_clk.common.hw,
1027
+
[CLK_DPU_MCLK] = &dpu_mclk.common.hw,
1028
+
[CLK_DPU_ESC] = &dpu_esc_clk.common.hw,
1029
+
[CLK_DPU_BIT] = &dpu_bit_clk.common.hw,
1030
+
[CLK_DPU_PXCLK] = &dpu_pxclk.common.hw,
1031
+
[CLK_DPU_HCLK] = &dpu_hclk.common.hw,
1032
+
[CLK_DPU_SPI] = &dpu_spi_clk.common.hw,
1033
+
[CLK_DPU_SPI_HBUS] = &dpu_spi_hbus_clk.common.hw,
1034
+
[CLK_DPU_SPIBUS] = &dpu_spi_bus_clk.common.hw,
1035
+
[CLK_DPU_SPI_ACLK] = &dpu_spi_aclk.common.hw,
1036
+
[CLK_V2D] = &v2d_clk.common.hw,
1037
+
[CLK_EMMC_BUS] = &emmc_bus_clk.common.hw,
1038
+
};
1039
+
1040
+
static const struct spacemit_ccu_data k1_ccu_apmu_data = {
1041
+
.hws = k1_ccu_apmu_hws,
1042
+
.num = ARRAY_SIZE(k1_ccu_apmu_hws),
1043
+
};
1044
+
1045
+
static int spacemit_ccu_register(struct device *dev,
1046
+
struct regmap *regmap,
1047
+
struct regmap *lock_regmap,
1048
+
const struct spacemit_ccu_data *data)
1049
+
{
1050
+
struct clk_hw_onecell_data *clk_data;
1051
+
int i, ret;
1052
+
1053
+
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num),
1054
+
GFP_KERNEL);
1055
+
if (!clk_data)
1056
+
return -ENOMEM;
1057
+
1058
+
for (i = 0; i < data->num; i++) {
1059
+
struct clk_hw *hw = data->hws[i];
1060
+
struct ccu_common *common;
1061
+
const char *name;
1062
+
1063
+
if (!hw) {
1064
+
clk_data->hws[i] = ERR_PTR(-ENOENT);
1065
+
continue;
1066
+
}
1067
+
1068
+
name = hw->init->name;
1069
+
1070
+
common = hw_to_ccu_common(hw);
1071
+
common->regmap = regmap;
1072
+
common->lock_regmap = lock_regmap;
1073
+
1074
+
ret = devm_clk_hw_register(dev, hw);
1075
+
if (ret) {
1076
+
dev_err(dev, "Cannot register clock %d - %s\n",
1077
+
i, name);
1078
+
return ret;
1079
+
}
1080
+
1081
+
clk_data->hws[i] = hw;
1082
+
}
1083
+
1084
+
clk_data->num = data->num;
1085
+
1086
+
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
1087
+
if (ret)
1088
+
dev_err(dev, "failed to add clock hardware provider (%d)\n", ret);
1089
+
1090
+
return ret;
1091
+
}
1092
+
1093
+
static int k1_ccu_probe(struct platform_device *pdev)
1094
+
{
1095
+
struct regmap *base_regmap, *lock_regmap = NULL;
1096
+
struct device *dev = &pdev->dev;
1097
+
int ret;
1098
+
1099
+
base_regmap = device_node_to_regmap(dev->of_node);
1100
+
if (IS_ERR(base_regmap))
1101
+
return dev_err_probe(dev, PTR_ERR(base_regmap),
1102
+
"failed to get regmap\n");
1103
+
1104
+
/*
1105
+
* The lock status of PLLs locate in MPMU region, while PLLs themselves
1106
+
* are in APBS region. Reference to MPMU syscon is required to check PLL
1107
+
* status.
1108
+
*/
1109
+
if (of_device_is_compatible(dev->of_node, "spacemit,k1-pll")) {
1110
+
struct device_node *mpmu = of_parse_phandle(dev->of_node,
1111
+
"spacemit,mpmu", 0);
1112
+
if (!mpmu)
1113
+
return dev_err_probe(dev, -ENODEV,
1114
+
"Cannot parse MPMU region\n");
1115
+
1116
+
lock_regmap = device_node_to_regmap(mpmu);
1117
+
of_node_put(mpmu);
1118
+
1119
+
if (IS_ERR(lock_regmap))
1120
+
return dev_err_probe(dev, PTR_ERR(lock_regmap),
1121
+
"failed to get lock regmap\n");
1122
+
}
1123
+
1124
+
ret = spacemit_ccu_register(dev, base_regmap, lock_regmap,
1125
+
of_device_get_match_data(dev));
1126
+
if (ret)
1127
+
return dev_err_probe(dev, ret, "failed to register clocks\n");
1128
+
1129
+
return 0;
1130
+
}
1131
+
1132
+
static const struct of_device_id of_k1_ccu_match[] = {
1133
+
{
1134
+
.compatible = "spacemit,k1-pll",
1135
+
.data = &k1_ccu_pll_data,
1136
+
},
1137
+
{
1138
+
.compatible = "spacemit,k1-syscon-mpmu",
1139
+
.data = &k1_ccu_mpmu_data,
1140
+
},
1141
+
{
1142
+
.compatible = "spacemit,k1-syscon-apbc",
1143
+
.data = &k1_ccu_apbc_data,
1144
+
},
1145
+
{
1146
+
.compatible = "spacemit,k1-syscon-apmu",
1147
+
.data = &k1_ccu_apmu_data,
1148
+
},
1149
+
{ }
1150
+
};
1151
+
MODULE_DEVICE_TABLE(of, of_k1_ccu_match);
1152
+
1153
+
static struct platform_driver k1_ccu_driver = {
1154
+
.driver = {
1155
+
.name = "spacemit,k1-ccu",
1156
+
.of_match_table = of_k1_ccu_match,
1157
+
},
1158
+
.probe = k1_ccu_probe,
1159
+
};
1160
+
module_platform_driver(k1_ccu_driver);
1161
+
1162
+
MODULE_DESCRIPTION("SpacemiT K1 CCU driver");
1163
+
MODULE_AUTHOR("Haylen Chu <heylenay@4d2.org>");
1164
+
MODULE_LICENSE("GPL");
+48
drivers/clk/spacemit/ccu_common.h
+48
drivers/clk/spacemit/ccu_common.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2024 SpacemiT Technology Co. Ltd
4
+
* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
5
+
*/
6
+
7
+
#ifndef _CCU_COMMON_H_
8
+
#define _CCU_COMMON_H_
9
+
10
+
#include <linux/regmap.h>
11
+
12
+
struct ccu_common {
13
+
struct regmap *regmap;
14
+
struct regmap *lock_regmap;
15
+
16
+
union {
17
+
/* For DDN and MIX */
18
+
struct {
19
+
u32 reg_ctrl;
20
+
u32 reg_fc;
21
+
u32 mask_fc;
22
+
};
23
+
24
+
/* For PLL */
25
+
struct {
26
+
u32 reg_swcr1;
27
+
u32 reg_swcr3;
28
+
};
29
+
};
30
+
31
+
struct clk_hw hw;
32
+
};
33
+
34
+
static inline struct ccu_common *hw_to_ccu_common(struct clk_hw *hw)
35
+
{
36
+
return container_of(hw, struct ccu_common, hw);
37
+
}
38
+
39
+
#define ccu_read(c, reg) \
40
+
({ \
41
+
u32 tmp; \
42
+
regmap_read((c)->regmap, (c)->reg_##reg, &tmp); \
43
+
tmp; \
44
+
})
45
+
#define ccu_update(c, reg, mask, val) \
46
+
regmap_update_bits((c)->regmap, (c)->reg_##reg, mask, val)
47
+
48
+
#endif /* _CCU_COMMON_H_ */
+83
drivers/clk/spacemit/ccu_ddn.c
+83
drivers/clk/spacemit/ccu_ddn.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2024 SpacemiT Technology Co. Ltd
4
+
* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
5
+
*
6
+
* DDN stands for "Divider Denominator Numerator", it's M/N clock with a
7
+
* constant x2 factor. This clock hardware follows the equation below,
8
+
*
9
+
* numerator Fin
10
+
* 2 * ------------- = -------
11
+
* denominator Fout
12
+
*
13
+
* Thus, Fout could be calculated with,
14
+
*
15
+
* Fin denominator
16
+
* Fout = ----- * -------------
17
+
* 2 numerator
18
+
*/
19
+
20
+
#include <linux/clk-provider.h>
21
+
#include <linux/rational.h>
22
+
23
+
#include "ccu_ddn.h"
24
+
25
+
static unsigned long ccu_ddn_calc_rate(unsigned long prate,
26
+
unsigned long num, unsigned long den)
27
+
{
28
+
return prate * den / 2 / num;
29
+
}
30
+
31
+
static unsigned long ccu_ddn_calc_best_rate(struct ccu_ddn *ddn,
32
+
unsigned long rate, unsigned long prate,
33
+
unsigned long *num, unsigned long *den)
34
+
{
35
+
rational_best_approximation(rate, prate / 2,
36
+
ddn->den_mask >> ddn->den_shift,
37
+
ddn->num_mask >> ddn->num_shift,
38
+
den, num);
39
+
return ccu_ddn_calc_rate(prate, *num, *den);
40
+
}
41
+
42
+
static long ccu_ddn_round_rate(struct clk_hw *hw, unsigned long rate,
43
+
unsigned long *prate)
44
+
{
45
+
struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
46
+
unsigned long num, den;
47
+
48
+
return ccu_ddn_calc_best_rate(ddn, rate, *prate, &num, &den);
49
+
}
50
+
51
+
static unsigned long ccu_ddn_recalc_rate(struct clk_hw *hw, unsigned long prate)
52
+
{
53
+
struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
54
+
unsigned int val, num, den;
55
+
56
+
val = ccu_read(&ddn->common, ctrl);
57
+
58
+
num = (val & ddn->num_mask) >> ddn->num_shift;
59
+
den = (val & ddn->den_mask) >> ddn->den_shift;
60
+
61
+
return ccu_ddn_calc_rate(prate, num, den);
62
+
}
63
+
64
+
static int ccu_ddn_set_rate(struct clk_hw *hw, unsigned long rate,
65
+
unsigned long prate)
66
+
{
67
+
struct ccu_ddn *ddn = hw_to_ccu_ddn(hw);
68
+
unsigned long num, den;
69
+
70
+
ccu_ddn_calc_best_rate(ddn, rate, prate, &num, &den);
71
+
72
+
ccu_update(&ddn->common, ctrl,
73
+
ddn->num_mask | ddn->den_mask,
74
+
(num << ddn->num_shift) | (den << ddn->den_shift));
75
+
76
+
return 0;
77
+
}
78
+
79
+
const struct clk_ops spacemit_ccu_ddn_ops = {
80
+
.recalc_rate = ccu_ddn_recalc_rate,
81
+
.round_rate = ccu_ddn_round_rate,
82
+
.set_rate = ccu_ddn_set_rate,
83
+
};
+48
drivers/clk/spacemit/ccu_ddn.h
+48
drivers/clk/spacemit/ccu_ddn.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2024 SpacemiT Technology Co. Ltd
4
+
* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
5
+
*/
6
+
7
+
#ifndef _CCU_DDN_H_
8
+
#define _CCU_DDN_H_
9
+
10
+
#include <linux/bitops.h>
11
+
#include <linux/clk-provider.h>
12
+
13
+
#include "ccu_common.h"
14
+
15
+
struct ccu_ddn {
16
+
struct ccu_common common;
17
+
unsigned int num_mask;
18
+
unsigned int num_shift;
19
+
unsigned int den_mask;
20
+
unsigned int den_shift;
21
+
};
22
+
23
+
#define CCU_DDN_INIT(_name, _parent, _flags) \
24
+
CLK_HW_INIT_HW(#_name, &_parent.common.hw, &spacemit_ccu_ddn_ops, _flags)
25
+
26
+
#define CCU_DDN_DEFINE(_name, _parent, _reg_ctrl, _num_shift, _num_width, \
27
+
_den_shift, _den_width, _flags) \
28
+
static struct ccu_ddn _name = { \
29
+
.common = { \
30
+
.reg_ctrl = _reg_ctrl, \
31
+
.hw.init = CCU_DDN_INIT(_name, _parent, _flags), \
32
+
}, \
33
+
.num_mask = GENMASK(_num_shift + _num_width - 1, _num_shift), \
34
+
.num_shift = _num_shift, \
35
+
.den_mask = GENMASK(_den_shift + _den_width - 1, _den_shift), \
36
+
.den_shift = _den_shift, \
37
+
}
38
+
39
+
static inline struct ccu_ddn *hw_to_ccu_ddn(struct clk_hw *hw)
40
+
{
41
+
struct ccu_common *common = hw_to_ccu_common(hw);
42
+
43
+
return container_of(common, struct ccu_ddn, common);
44
+
}
45
+
46
+
extern const struct clk_ops spacemit_ccu_ddn_ops;
47
+
48
+
#endif
+268
drivers/clk/spacemit/ccu_mix.c
+268
drivers/clk/spacemit/ccu_mix.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2024 SpacemiT Technology Co. Ltd
4
+
* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
5
+
*
6
+
* MIX clock type is the combination of mux, factor or divider, and gate
7
+
*/
8
+
9
+
#include <linux/clk-provider.h>
10
+
11
+
#include "ccu_mix.h"
12
+
13
+
#define MIX_FC_TIMEOUT_US 10000
14
+
#define MIX_FC_DELAY_US 5
15
+
16
+
static void ccu_gate_disable(struct clk_hw *hw)
17
+
{
18
+
struct ccu_mix *mix = hw_to_ccu_mix(hw);
19
+
20
+
ccu_update(&mix->common, ctrl, mix->gate.mask, 0);
21
+
}
22
+
23
+
static int ccu_gate_enable(struct clk_hw *hw)
24
+
{
25
+
struct ccu_mix *mix = hw_to_ccu_mix(hw);
26
+
struct ccu_gate_config *gate = &mix->gate;
27
+
28
+
ccu_update(&mix->common, ctrl, gate->mask, gate->mask);
29
+
30
+
return 0;
31
+
}
32
+
33
+
static int ccu_gate_is_enabled(struct clk_hw *hw)
34
+
{
35
+
struct ccu_mix *mix = hw_to_ccu_mix(hw);
36
+
struct ccu_gate_config *gate = &mix->gate;
37
+
38
+
return (ccu_read(&mix->common, ctrl) & gate->mask) == gate->mask;
39
+
}
40
+
41
+
static unsigned long ccu_factor_recalc_rate(struct clk_hw *hw,
42
+
unsigned long parent_rate)
43
+
{
44
+
struct ccu_mix *mix = hw_to_ccu_mix(hw);
45
+
46
+
return parent_rate * mix->factor.mul / mix->factor.div;
47
+
}
48
+
49
+
static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
50
+
unsigned long parent_rate)
51
+
{
52
+
struct ccu_mix *mix = hw_to_ccu_mix(hw);
53
+
struct ccu_div_config *div = &mix->div;
54
+
unsigned long val;
55
+
56
+
val = ccu_read(&mix->common, ctrl) >> div->shift;
57
+
val &= (1 << div->width) - 1;
58
+
59
+
return divider_recalc_rate(hw, parent_rate, val, NULL, 0, div->width);
60
+
}
61
+
62
+
/*
63
+
* Some clocks require a "FC" (frequency change) bit to be set after changing
64
+
* their rates or reparenting. This bit will be automatically cleared by
65
+
* hardware in MIX_FC_TIMEOUT_US, which indicates the operation is completed.
66
+
*/
67
+
static int ccu_mix_trigger_fc(struct clk_hw *hw)
68
+
{
69
+
struct ccu_common *common = hw_to_ccu_common(hw);
70
+
unsigned int val;
71
+
72
+
if (common->reg_fc)
73
+
return 0;
74
+
75
+
ccu_update(common, fc, common->mask_fc, common->mask_fc);
76
+
77
+
return regmap_read_poll_timeout_atomic(common->regmap, common->reg_fc,
78
+
val, !(val & common->mask_fc),
79
+
MIX_FC_DELAY_US,
80
+
MIX_FC_TIMEOUT_US);
81
+
}
82
+
83
+
static long ccu_factor_round_rate(struct clk_hw *hw, unsigned long rate,
84
+
unsigned long *prate)
85
+
{
86
+
return ccu_factor_recalc_rate(hw, *prate);
87
+
}
88
+
89
+
static int ccu_factor_set_rate(struct clk_hw *hw, unsigned long rate,
90
+
unsigned long parent_rate)
91
+
{
92
+
return 0;
93
+
}
94
+
95
+
static unsigned long
96
+
ccu_mix_calc_best_rate(struct clk_hw *hw, unsigned long rate,
97
+
struct clk_hw **best_parent,
98
+
unsigned long *best_parent_rate,
99
+
u32 *div_val)
100
+
{
101
+
struct ccu_mix *mix = hw_to_ccu_mix(hw);
102
+
unsigned int parent_num = clk_hw_get_num_parents(hw);
103
+
struct ccu_div_config *div = &mix->div;
104
+
u32 div_max = 1 << div->width;
105
+
unsigned long best_rate = 0;
106
+
107
+
for (int i = 0; i < parent_num; i++) {
108
+
struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
109
+
unsigned long parent_rate;
110
+
111
+
if (!parent)
112
+
continue;
113
+
114
+
parent_rate = clk_hw_get_rate(parent);
115
+
116
+
for (int j = 1; j <= div_max; j++) {
117
+
unsigned long tmp = DIV_ROUND_CLOSEST_ULL(parent_rate, j);
118
+
119
+
if (abs(tmp - rate) < abs(best_rate - rate)) {
120
+
best_rate = tmp;
121
+
122
+
if (div_val)
123
+
*div_val = j - 1;
124
+
125
+
if (best_parent) {
126
+
*best_parent = parent;
127
+
*best_parent_rate = parent_rate;
128
+
}
129
+
}
130
+
}
131
+
}
132
+
133
+
return best_rate;
134
+
}
135
+
136
+
static int ccu_mix_determine_rate(struct clk_hw *hw,
137
+
struct clk_rate_request *req)
138
+
{
139
+
req->rate = ccu_mix_calc_best_rate(hw, req->rate,
140
+
&req->best_parent_hw,
141
+
&req->best_parent_rate,
142
+
NULL);
143
+
return 0;
144
+
}
145
+
146
+
static int ccu_mix_set_rate(struct clk_hw *hw, unsigned long rate,
147
+
unsigned long parent_rate)
148
+
{
149
+
struct ccu_mix *mix = hw_to_ccu_mix(hw);
150
+
struct ccu_common *common = &mix->common;
151
+
struct ccu_div_config *div = &mix->div;
152
+
u32 current_div, target_div, mask;
153
+
154
+
ccu_mix_calc_best_rate(hw, rate, NULL, NULL, &target_div);
155
+
156
+
current_div = ccu_read(common, ctrl) >> div->shift;
157
+
current_div &= (1 << div->width) - 1;
158
+
159
+
if (current_div == target_div)
160
+
return 0;
161
+
162
+
mask = GENMASK(div->width + div->shift - 1, div->shift);
163
+
164
+
ccu_update(common, ctrl, mask, target_div << div->shift);
165
+
166
+
return ccu_mix_trigger_fc(hw);
167
+
}
168
+
169
+
static u8 ccu_mux_get_parent(struct clk_hw *hw)
170
+
{
171
+
struct ccu_mix *mix = hw_to_ccu_mix(hw);
172
+
struct ccu_mux_config *mux = &mix->mux;
173
+
u8 parent;
174
+
175
+
parent = ccu_read(&mix->common, ctrl) >> mux->shift;
176
+
parent &= (1 << mux->width) - 1;
177
+
178
+
return parent;
179
+
}
180
+
181
+
static int ccu_mux_set_parent(struct clk_hw *hw, u8 index)
182
+
{
183
+
struct ccu_mix *mix = hw_to_ccu_mix(hw);
184
+
struct ccu_mux_config *mux = &mix->mux;
185
+
u32 mask;
186
+
187
+
mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
188
+
189
+
ccu_update(&mix->common, ctrl, mask, index << mux->shift);
190
+
191
+
return ccu_mix_trigger_fc(hw);
192
+
}
193
+
194
+
const struct clk_ops spacemit_ccu_gate_ops = {
195
+
.disable = ccu_gate_disable,
196
+
.enable = ccu_gate_enable,
197
+
.is_enabled = ccu_gate_is_enabled,
198
+
};
199
+
200
+
const struct clk_ops spacemit_ccu_factor_ops = {
201
+
.round_rate = ccu_factor_round_rate,
202
+
.recalc_rate = ccu_factor_recalc_rate,
203
+
.set_rate = ccu_factor_set_rate,
204
+
};
205
+
206
+
const struct clk_ops spacemit_ccu_mux_ops = {
207
+
.determine_rate = ccu_mix_determine_rate,
208
+
.get_parent = ccu_mux_get_parent,
209
+
.set_parent = ccu_mux_set_parent,
210
+
};
211
+
212
+
const struct clk_ops spacemit_ccu_div_ops = {
213
+
.determine_rate = ccu_mix_determine_rate,
214
+
.recalc_rate = ccu_div_recalc_rate,
215
+
.set_rate = ccu_mix_set_rate,
216
+
};
217
+
218
+
const struct clk_ops spacemit_ccu_factor_gate_ops = {
219
+
.disable = ccu_gate_disable,
220
+
.enable = ccu_gate_enable,
221
+
.is_enabled = ccu_gate_is_enabled,
222
+
223
+
.round_rate = ccu_factor_round_rate,
224
+
.recalc_rate = ccu_factor_recalc_rate,
225
+
.set_rate = ccu_factor_set_rate,
226
+
};
227
+
228
+
const struct clk_ops spacemit_ccu_mux_gate_ops = {
229
+
.disable = ccu_gate_disable,
230
+
.enable = ccu_gate_enable,
231
+
.is_enabled = ccu_gate_is_enabled,
232
+
233
+
.determine_rate = ccu_mix_determine_rate,
234
+
.get_parent = ccu_mux_get_parent,
235
+
.set_parent = ccu_mux_set_parent,
236
+
};
237
+
238
+
const struct clk_ops spacemit_ccu_div_gate_ops = {
239
+
.disable = ccu_gate_disable,
240
+
.enable = ccu_gate_enable,
241
+
.is_enabled = ccu_gate_is_enabled,
242
+
243
+
.determine_rate = ccu_mix_determine_rate,
244
+
.recalc_rate = ccu_div_recalc_rate,
245
+
.set_rate = ccu_mix_set_rate,
246
+
};
247
+
248
+
const struct clk_ops spacemit_ccu_mux_div_gate_ops = {
249
+
.disable = ccu_gate_disable,
250
+
.enable = ccu_gate_enable,
251
+
.is_enabled = ccu_gate_is_enabled,
252
+
253
+
.get_parent = ccu_mux_get_parent,
254
+
.set_parent = ccu_mux_set_parent,
255
+
256
+
.determine_rate = ccu_mix_determine_rate,
257
+
.recalc_rate = ccu_div_recalc_rate,
258
+
.set_rate = ccu_mix_set_rate,
259
+
};
260
+
261
+
const struct clk_ops spacemit_ccu_mux_div_ops = {
262
+
.get_parent = ccu_mux_get_parent,
263
+
.set_parent = ccu_mux_set_parent,
264
+
265
+
.determine_rate = ccu_mix_determine_rate,
266
+
.recalc_rate = ccu_div_recalc_rate,
267
+
.set_rate = ccu_mix_set_rate,
268
+
};
+218
drivers/clk/spacemit/ccu_mix.h
+218
drivers/clk/spacemit/ccu_mix.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2024 SpacemiT Technology Co. Ltd
4
+
* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
5
+
*/
6
+
7
+
#ifndef _CCU_MIX_H_
8
+
#define _CCU_MIX_H_
9
+
10
+
#include <linux/clk-provider.h>
11
+
12
+
#include "ccu_common.h"
13
+
14
+
/**
15
+
* struct ccu_gate_config - Gate configuration
16
+
*
17
+
* @mask: Mask to enable the gate. Some clocks may have more than one bit
18
+
* set in this field.
19
+
*/
20
+
struct ccu_gate_config {
21
+
u32 mask;
22
+
};
23
+
24
+
struct ccu_factor_config {
25
+
u32 div;
26
+
u32 mul;
27
+
};
28
+
29
+
struct ccu_mux_config {
30
+
u8 shift;
31
+
u8 width;
32
+
};
33
+
34
+
struct ccu_div_config {
35
+
u8 shift;
36
+
u8 width;
37
+
};
38
+
39
+
struct ccu_mix {
40
+
struct ccu_factor_config factor;
41
+
struct ccu_gate_config gate;
42
+
struct ccu_div_config div;
43
+
struct ccu_mux_config mux;
44
+
struct ccu_common common;
45
+
};
46
+
47
+
#define CCU_GATE_INIT(_mask) { .mask = _mask }
48
+
#define CCU_FACTOR_INIT(_div, _mul) { .div = _div, .mul = _mul }
49
+
#define CCU_MUX_INIT(_shift, _width) { .shift = _shift, .width = _width }
50
+
#define CCU_DIV_INIT(_shift, _width) { .shift = _shift, .width = _width }
51
+
52
+
#define CCU_PARENT_HW(_parent) { .hw = &_parent.common.hw }
53
+
#define CCU_PARENT_NAME(_name) { .fw_name = #_name }
54
+
55
+
#define CCU_MIX_INITHW(_name, _parent, _ops, _flags) \
56
+
.hw.init = &(struct clk_init_data) { \
57
+
.flags = _flags, \
58
+
.name = #_name, \
59
+
.parent_data = (const struct clk_parent_data[]) \
60
+
{ _parent }, \
61
+
.num_parents = 1, \
62
+
.ops = &_ops, \
63
+
}
64
+
65
+
#define CCU_MIX_INITHW_PARENTS(_name, _parents, _ops, _flags) \
66
+
.hw.init = CLK_HW_INIT_PARENTS_DATA(#_name, _parents, &_ops, _flags)
67
+
68
+
#define CCU_GATE_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _flags) \
69
+
static struct ccu_mix _name = { \
70
+
.gate = CCU_GATE_INIT(_mask_gate), \
71
+
.common = { \
72
+
.reg_ctrl = _reg_ctrl, \
73
+
CCU_MIX_INITHW(_name, _parent, spacemit_ccu_gate_ops, _flags), \
74
+
} \
75
+
}
76
+
77
+
#define CCU_FACTOR_DEFINE(_name, _parent, _div, _mul) \
78
+
static struct ccu_mix _name = { \
79
+
.factor = CCU_FACTOR_INIT(_div, _mul), \
80
+
.common = { \
81
+
CCU_MIX_INITHW(_name, _parent, spacemit_ccu_factor_ops, 0), \
82
+
} \
83
+
}
84
+
85
+
#define CCU_MUX_DEFINE(_name, _parents, _reg_ctrl, _shift, _width, _flags) \
86
+
static struct ccu_mix _name = { \
87
+
.mux = CCU_MUX_INIT(_shift, _width), \
88
+
.common = { \
89
+
.reg_ctrl = _reg_ctrl, \
90
+
CCU_MIX_INITHW_PARENTS(_name, _parents, spacemit_ccu_mux_ops, \
91
+
_flags), \
92
+
} \
93
+
}
94
+
95
+
#define CCU_DIV_DEFINE(_name, _parent, _reg_ctrl, _shift, _width, _flags) \
96
+
static struct ccu_mix _name = { \
97
+
.div = CCU_DIV_INIT(_shift, _width), \
98
+
.common = { \
99
+
.reg_ctrl = _reg_ctrl, \
100
+
CCU_MIX_INITHW(_name, _parent, spacemit_ccu_div_ops, _flags) \
101
+
} \
102
+
}
103
+
104
+
#define CCU_FACTOR_GATE_DEFINE(_name, _parent, _reg_ctrl, _mask_gate, _div, \
105
+
_mul) \
106
+
static struct ccu_mix _name = { \
107
+
.gate = CCU_GATE_INIT(_mask_gate), \
108
+
.factor = CCU_FACTOR_INIT(_div, _mul), \
109
+
.common = { \
110
+
.reg_ctrl = _reg_ctrl, \
111
+
CCU_MIX_INITHW(_name, _parent, spacemit_ccu_factor_gate_ops, 0) \
112
+
} \
113
+
}
114
+
115
+
#define CCU_MUX_GATE_DEFINE(_name, _parents, _reg_ctrl, _shift, _width, \
116
+
_mask_gate, _flags) \
117
+
static struct ccu_mix _name = { \
118
+
.gate = CCU_GATE_INIT(_mask_gate), \
119
+
.mux = CCU_MUX_INIT(_shift, _width), \
120
+
.common = { \
121
+
.reg_ctrl = _reg_ctrl, \
122
+
CCU_MIX_INITHW_PARENTS(_name, _parents, \
123
+
spacemit_ccu_mux_gate_ops, _flags), \
124
+
} \
125
+
}
126
+
127
+
#define CCU_DIV_GATE_DEFINE(_name, _parent, _reg_ctrl, _shift, _width, \
128
+
_mask_gate, _flags) \
129
+
static struct ccu_mix _name = { \
130
+
.gate = CCU_GATE_INIT(_mask_gate), \
131
+
.div = CCU_DIV_INIT(_shift, _width), \
132
+
.common = { \
133
+
.reg_ctrl = _reg_ctrl, \
134
+
CCU_MIX_INITHW(_name, _parent, spacemit_ccu_div_gate_ops, \
135
+
_flags), \
136
+
} \
137
+
}
138
+
139
+
#define CCU_MUX_DIV_GATE_DEFINE(_name, _parents, _reg_ctrl, _mshift, _mwidth, \
140
+
_muxshift, _muxwidth, _mask_gate, _flags) \
141
+
static struct ccu_mix _name = { \
142
+
.gate = CCU_GATE_INIT(_mask_gate), \
143
+
.div = CCU_DIV_INIT(_mshift, _mwidth), \
144
+
.mux = CCU_MUX_INIT(_muxshift, _muxwidth), \
145
+
.common = { \
146
+
.reg_ctrl = _reg_ctrl, \
147
+
CCU_MIX_INITHW_PARENTS(_name, _parents, \
148
+
spacemit_ccu_mux_div_gate_ops, _flags), \
149
+
}, \
150
+
}
151
+
152
+
#define CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(_name, _parents, _reg_ctrl, _reg_fc, \
153
+
_mshift, _mwidth, _mask_fc, _muxshift, \
154
+
_muxwidth, _mask_gate, _flags) \
155
+
static struct ccu_mix _name = { \
156
+
.gate = CCU_GATE_INIT(_mask_gate), \
157
+
.div = CCU_DIV_INIT(_mshift, _mwidth), \
158
+
.mux = CCU_MUX_INIT(_muxshift, _muxwidth), \
159
+
.common = { \
160
+
.reg_ctrl = _reg_ctrl, \
161
+
.reg_fc = _reg_fc, \
162
+
.mask_fc = _mask_fc, \
163
+
CCU_MIX_INITHW_PARENTS(_name, _parents, \
164
+
spacemit_ccu_mux_div_gate_ops, _flags), \
165
+
}, \
166
+
}
167
+
168
+
#define CCU_MUX_DIV_GATE_FC_DEFINE(_name, _parents, _reg_ctrl, _mshift, _mwidth,\
169
+
_mask_fc, _muxshift, _muxwidth, _mask_gate, \
170
+
_flags) \
171
+
CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(_name, _parents, _reg_ctrl, _reg_ctrl, _mshift,\
172
+
_mwidth, _mask_fc, _muxshift, _muxwidth, \
173
+
_mask_gate, _flags)
174
+
175
+
#define CCU_MUX_DIV_FC_DEFINE(_name, _parents, _reg_ctrl, _mshift, _mwidth, \
176
+
_mask_fc, _muxshift, _muxwidth, _flags) \
177
+
static struct ccu_mix _name = { \
178
+
.div = CCU_DIV_INIT(_mshift, _mwidth), \
179
+
.mux = CCU_MUX_INIT(_muxshift, _muxwidth), \
180
+
.common = { \
181
+
.reg_ctrl = _reg_ctrl, \
182
+
.reg_fc = _reg_ctrl, \
183
+
.mask_fc = _mask_fc, \
184
+
CCU_MIX_INITHW_PARENTS(_name, _parents, \
185
+
spacemit_ccu_mux_div_ops, _flags), \
186
+
}, \
187
+
}
188
+
189
+
#define CCU_MUX_FC_DEFINE(_name, _parents, _reg_ctrl, _mask_fc, _muxshift, \
190
+
_muxwidth, _flags) \
191
+
static struct ccu_mix _name = { \
192
+
.mux = CCU_MUX_INIT(_muxshift, _muxwidth), \
193
+
.common = { \
194
+
.reg_ctrl = _reg_ctrl, \
195
+
.reg_fc = _reg_ctrl, \
196
+
.mask_fc = _mask_fc, \
197
+
CCU_MIX_INITHW_PARENTS(_name, _parents, spacemit_ccu_mux_ops, \
198
+
_flags) \
199
+
}, \
200
+
}
201
+
202
+
static inline struct ccu_mix *hw_to_ccu_mix(struct clk_hw *hw)
203
+
{
204
+
struct ccu_common *common = hw_to_ccu_common(hw);
205
+
206
+
return container_of(common, struct ccu_mix, common);
207
+
}
208
+
209
+
extern const struct clk_ops spacemit_ccu_gate_ops;
210
+
extern const struct clk_ops spacemit_ccu_factor_ops;
211
+
extern const struct clk_ops spacemit_ccu_mux_ops;
212
+
extern const struct clk_ops spacemit_ccu_div_ops;
213
+
extern const struct clk_ops spacemit_ccu_factor_gate_ops;
214
+
extern const struct clk_ops spacemit_ccu_div_gate_ops;
215
+
extern const struct clk_ops spacemit_ccu_mux_gate_ops;
216
+
extern const struct clk_ops spacemit_ccu_mux_div_ops;
217
+
extern const struct clk_ops spacemit_ccu_mux_div_gate_ops;
218
+
#endif /* _CCU_DIV_H_ */
+157
drivers/clk/spacemit/ccu_pll.c
+157
drivers/clk/spacemit/ccu_pll.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2024 SpacemiT Technology Co. Ltd
4
+
* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
5
+
*/
6
+
7
+
#include <linux/clk-provider.h>
8
+
#include <linux/math.h>
9
+
#include <linux/regmap.h>
10
+
11
+
#include "ccu_common.h"
12
+
#include "ccu_pll.h"
13
+
14
+
#define PLL_TIMEOUT_US 3000
15
+
#define PLL_DELAY_US 5
16
+
17
+
#define PLL_SWCR3_EN ((u32)BIT(31))
18
+
#define PLL_SWCR3_MASK GENMASK(30, 0)
19
+
20
+
static const struct ccu_pll_rate_tbl *ccu_pll_lookup_best_rate(struct ccu_pll *pll,
21
+
unsigned long rate)
22
+
{
23
+
struct ccu_pll_config *config = &pll->config;
24
+
const struct ccu_pll_rate_tbl *best_entry;
25
+
unsigned long best_delta = ULONG_MAX;
26
+
int i;
27
+
28
+
for (i = 0; i < config->tbl_num; i++) {
29
+
const struct ccu_pll_rate_tbl *entry = &config->rate_tbl[i];
30
+
unsigned long delta = abs_diff(entry->rate, rate);
31
+
32
+
if (delta < best_delta) {
33
+
best_delta = delta;
34
+
best_entry = entry;
35
+
}
36
+
}
37
+
38
+
return best_entry;
39
+
}
40
+
41
+
static const struct ccu_pll_rate_tbl *ccu_pll_lookup_matched_entry(struct ccu_pll *pll)
42
+
{
43
+
struct ccu_pll_config *config = &pll->config;
44
+
u32 swcr1, swcr3;
45
+
int i;
46
+
47
+
swcr1 = ccu_read(&pll->common, swcr1);
48
+
swcr3 = ccu_read(&pll->common, swcr3);
49
+
swcr3 &= PLL_SWCR3_MASK;
50
+
51
+
for (i = 0; i < config->tbl_num; i++) {
52
+
const struct ccu_pll_rate_tbl *entry = &config->rate_tbl[i];
53
+
54
+
if (swcr1 == entry->swcr1 && swcr3 == entry->swcr3)
55
+
return entry;
56
+
}
57
+
58
+
return NULL;
59
+
}
60
+
61
+
static void ccu_pll_update_param(struct ccu_pll *pll, const struct ccu_pll_rate_tbl *entry)
62
+
{
63
+
struct ccu_common *common = &pll->common;
64
+
65
+
regmap_write(common->regmap, common->reg_swcr1, entry->swcr1);
66
+
ccu_update(common, swcr3, PLL_SWCR3_MASK, entry->swcr3);
67
+
}
68
+
69
+
static int ccu_pll_is_enabled(struct clk_hw *hw)
70
+
{
71
+
struct ccu_common *common = hw_to_ccu_common(hw);
72
+
73
+
return ccu_read(common, swcr3) & PLL_SWCR3_EN;
74
+
}
75
+
76
+
static int ccu_pll_enable(struct clk_hw *hw)
77
+
{
78
+
struct ccu_pll *pll = hw_to_ccu_pll(hw);
79
+
struct ccu_common *common = &pll->common;
80
+
unsigned int tmp;
81
+
82
+
ccu_update(common, swcr3, PLL_SWCR3_EN, PLL_SWCR3_EN);
83
+
84
+
/* check lock status */
85
+
return regmap_read_poll_timeout_atomic(common->lock_regmap,
86
+
pll->config.reg_lock,
87
+
tmp,
88
+
tmp & pll->config.mask_lock,
89
+
PLL_DELAY_US, PLL_TIMEOUT_US);
90
+
}
91
+
92
+
static void ccu_pll_disable(struct clk_hw *hw)
93
+
{
94
+
struct ccu_common *common = hw_to_ccu_common(hw);
95
+
96
+
ccu_update(common, swcr3, PLL_SWCR3_EN, 0);
97
+
}
98
+
99
+
/*
100
+
* PLLs must be gated before changing rate, which is ensured by
101
+
* flag CLK_SET_RATE_GATE.
102
+
*/
103
+
static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate,
104
+
unsigned long parent_rate)
105
+
{
106
+
struct ccu_pll *pll = hw_to_ccu_pll(hw);
107
+
const struct ccu_pll_rate_tbl *entry;
108
+
109
+
entry = ccu_pll_lookup_best_rate(pll, rate);
110
+
ccu_pll_update_param(pll, entry);
111
+
112
+
return 0;
113
+
}
114
+
115
+
static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
116
+
unsigned long parent_rate)
117
+
{
118
+
struct ccu_pll *pll = hw_to_ccu_pll(hw);
119
+
const struct ccu_pll_rate_tbl *entry;
120
+
121
+
entry = ccu_pll_lookup_matched_entry(pll);
122
+
123
+
WARN_ON_ONCE(!entry);
124
+
125
+
return entry ? entry->rate : -EINVAL;
126
+
}
127
+
128
+
static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate,
129
+
unsigned long *prate)
130
+
{
131
+
struct ccu_pll *pll = hw_to_ccu_pll(hw);
132
+
133
+
return ccu_pll_lookup_best_rate(pll, rate)->rate;
134
+
}
135
+
136
+
static int ccu_pll_init(struct clk_hw *hw)
137
+
{
138
+
struct ccu_pll *pll = hw_to_ccu_pll(hw);
139
+
140
+
if (ccu_pll_lookup_matched_entry(pll))
141
+
return 0;
142
+
143
+
ccu_pll_disable(hw);
144
+
ccu_pll_update_param(pll, &pll->config.rate_tbl[0]);
145
+
146
+
return 0;
147
+
}
148
+
149
+
const struct clk_ops spacemit_ccu_pll_ops = {
150
+
.init = ccu_pll_init,
151
+
.enable = ccu_pll_enable,
152
+
.disable = ccu_pll_disable,
153
+
.set_rate = ccu_pll_set_rate,
154
+
.recalc_rate = ccu_pll_recalc_rate,
155
+
.round_rate = ccu_pll_round_rate,
156
+
.is_enabled = ccu_pll_is_enabled,
157
+
};
+86
drivers/clk/spacemit/ccu_pll.h
+86
drivers/clk/spacemit/ccu_pll.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2024 SpacemiT Technology Co. Ltd
4
+
* Copyright (c) 2024-2025 Haylen Chu <heylenay@4d2.org>
5
+
*/
6
+
7
+
#ifndef _CCU_PLL_H_
8
+
#define _CCU_PLL_H_
9
+
10
+
#include <linux/clk-provider.h>
11
+
12
+
#include "ccu_common.h"
13
+
14
+
/**
15
+
* struct ccu_pll_rate_tbl - Structure mapping between PLL rate and register
16
+
* configuration.
17
+
*
18
+
* @rate: PLL rate
19
+
* @swcr1: Register value of PLLX_SW1_CTRL (PLLx_SWCR1).
20
+
* @swcr3: Register value of the PLLx_SW3_CTRL's lowest 31 bits of
21
+
* PLLx_SW3_CTRL (PLLx_SWCR3). This highest bit is for enabling
22
+
* the PLL and not contained in this field.
23
+
*/
24
+
struct ccu_pll_rate_tbl {
25
+
unsigned long rate;
26
+
u32 swcr1;
27
+
u32 swcr3;
28
+
};
29
+
30
+
struct ccu_pll_config {
31
+
const struct ccu_pll_rate_tbl *rate_tbl;
32
+
u32 tbl_num;
33
+
u32 reg_lock;
34
+
u32 mask_lock;
35
+
};
36
+
37
+
#define CCU_PLL_RATE(_rate, _swcr1, _swcr3) \
38
+
{ \
39
+
.rate = _rate, \
40
+
.swcr1 = _swcr1, \
41
+
.swcr3 = _swcr3, \
42
+
}
43
+
44
+
struct ccu_pll {
45
+
struct ccu_common common;
46
+
struct ccu_pll_config config;
47
+
};
48
+
49
+
#define CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock) \
50
+
{ \
51
+
.rate_tbl = _table, \
52
+
.tbl_num = ARRAY_SIZE(_table), \
53
+
.reg_lock = (_reg_lock), \
54
+
.mask_lock = (_mask_lock), \
55
+
}
56
+
57
+
#define CCU_PLL_HWINIT(_name, _flags) \
58
+
(&(struct clk_init_data) { \
59
+
.name = #_name, \
60
+
.ops = &spacemit_ccu_pll_ops, \
61
+
.parent_data = &(struct clk_parent_data) { .index = 0 }, \
62
+
.num_parents = 1, \
63
+
.flags = _flags, \
64
+
})
65
+
66
+
#define CCU_PLL_DEFINE(_name, _table, _reg_swcr1, _reg_swcr3, _reg_lock, \
67
+
_mask_lock, _flags) \
68
+
static struct ccu_pll _name = { \
69
+
.config = CCU_PLL_CONFIG(_table, _reg_lock, _mask_lock), \
70
+
.common = { \
71
+
.reg_swcr1 = _reg_swcr1, \
72
+
.reg_swcr3 = _reg_swcr3, \
73
+
.hw.init = CCU_PLL_HWINIT(_name, _flags) \
74
+
} \
75
+
}
76
+
77
+
static inline struct ccu_pll *hw_to_ccu_pll(struct clk_hw *hw)
78
+
{
79
+
struct ccu_common *common = hw_to_ccu_common(hw);
80
+
81
+
return container_of(common, struct ccu_pll, common);
82
+
}
83
+
84
+
extern const struct clk_ops spacemit_ccu_pll_ops;
85
+
86
+
#endif
+24
-24
drivers/clk/sunxi-ng/Kconfig
+24
-24
drivers/clk/sunxi-ng/Kconfig
···
9
9
10
10
config SUNIV_F1C100S_CCU
11
11
tristate "Support for the Allwinner newer F1C100s CCU"
12
-
default y
12
+
default ARCH_SUNXI
13
13
depends on MACH_SUNIV || COMPILE_TEST
14
14
15
15
config SUN20I_D1_CCU
16
16
tristate "Support for the Allwinner D1/R528/T113 CCU"
17
-
default y
17
+
default ARCH_SUNXI
18
18
depends on MACH_SUN8I || RISCV || COMPILE_TEST
19
19
20
20
config SUN20I_D1_R_CCU
21
21
tristate "Support for the Allwinner D1/R528/T113 PRCM CCU"
22
-
default y
22
+
default ARCH_SUNXI
23
23
depends on MACH_SUN8I || RISCV || COMPILE_TEST
24
24
25
25
config SUN50I_A64_CCU
26
26
tristate "Support for the Allwinner A64 CCU"
27
-
default y
27
+
default ARCH_SUNXI
28
28
depends on ARM64 || COMPILE_TEST
29
29
30
30
config SUN50I_A100_CCU
31
31
tristate "Support for the Allwinner A100 CCU"
32
-
default y
32
+
default ARCH_SUNXI
33
33
depends on ARM64 || COMPILE_TEST
34
34
35
35
config SUN50I_A100_R_CCU
36
36
tristate "Support for the Allwinner A100 PRCM CCU"
37
-
default y
37
+
default ARCH_SUNXI
38
38
depends on ARM64 || COMPILE_TEST
39
39
40
40
config SUN50I_H6_CCU
41
41
tristate "Support for the Allwinner H6 CCU"
42
-
default y
42
+
default ARCH_SUNXI
43
43
depends on ARM64 || COMPILE_TEST
44
44
45
45
config SUN50I_H616_CCU
46
46
tristate "Support for the Allwinner H616 CCU"
47
-
default y
47
+
default ARCH_SUNXI
48
48
depends on ARM64 || COMPILE_TEST
49
49
50
50
config SUN50I_H6_R_CCU
51
51
tristate "Support for the Allwinner H6 and H616 PRCM CCU"
52
-
default y
52
+
default ARCH_SUNXI
53
53
depends on ARM64 || COMPILE_TEST
54
54
55
55
config SUN55I_A523_CCU
56
56
tristate "Support for the Allwinner A523/T527 CCU"
57
-
default y
57
+
default ARCH_SUNXI
58
58
depends on ARM64 || COMPILE_TEST
59
59
60
60
config SUN55I_A523_R_CCU
61
61
tristate "Support for the Allwinner A523/T527 PRCM CCU"
62
-
default y
62
+
default ARCH_SUNXI
63
63
depends on ARM64 || COMPILE_TEST
64
64
65
65
config SUN4I_A10_CCU
66
66
tristate "Support for the Allwinner A10/A20 CCU"
67
-
default y
67
+
default ARCH_SUNXI
68
68
depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
69
69
70
70
config SUN5I_CCU
71
71
bool "Support for the Allwinner sun5i family CCM"
72
-
default y
72
+
default ARCH_SUNXI
73
73
depends on MACH_SUN5I || COMPILE_TEST
74
74
depends on SUNXI_CCU=y
75
75
76
76
config SUN6I_A31_CCU
77
77
tristate "Support for the Allwinner A31/A31s CCU"
78
-
default y
78
+
default ARCH_SUNXI
79
79
depends on MACH_SUN6I || COMPILE_TEST
80
80
81
81
config SUN6I_RTC_CCU
82
82
tristate "Support for the Allwinner H616/R329 RTC CCU"
83
-
default y
83
+
default ARCH_SUNXI
84
84
depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST
85
85
86
86
config SUN8I_A23_CCU
87
87
tristate "Support for the Allwinner A23 CCU"
88
-
default y
88
+
default ARCH_SUNXI
89
89
depends on MACH_SUN8I || COMPILE_TEST
90
90
91
91
config SUN8I_A33_CCU
92
92
tristate "Support for the Allwinner A33 CCU"
93
-
default y
93
+
default ARCH_SUNXI
94
94
depends on MACH_SUN8I || COMPILE_TEST
95
95
96
96
config SUN8I_A83T_CCU
97
97
tristate "Support for the Allwinner A83T CCU"
98
-
default y
98
+
default ARCH_SUNXI
99
99
depends on MACH_SUN8I || COMPILE_TEST
100
100
101
101
config SUN8I_H3_CCU
102
102
tristate "Support for the Allwinner H3 CCU"
103
-
default y
103
+
default ARCH_SUNXI
104
104
depends on MACH_SUN8I || ARM64 || COMPILE_TEST
105
105
106
106
config SUN8I_V3S_CCU
107
107
tristate "Support for the Allwinner V3s CCU"
108
-
default y
108
+
default ARCH_SUNXI
109
109
depends on MACH_SUN8I || COMPILE_TEST
110
110
111
111
config SUN8I_DE2_CCU
112
112
tristate "Support for the Allwinner SoCs DE2 CCU"
113
-
default y
113
+
default ARCH_SUNXI
114
114
depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST
115
115
116
116
config SUN8I_R40_CCU
117
117
tristate "Support for the Allwinner R40 CCU"
118
-
default y
118
+
default ARCH_SUNXI
119
119
depends on MACH_SUN8I || COMPILE_TEST
120
120
121
121
config SUN9I_A80_CCU
122
122
tristate "Support for the Allwinner A80 CCU"
123
-
default y
123
+
default ARCH_SUNXI
124
124
depends on MACH_SUN9I || COMPILE_TEST
125
125
126
126
config SUN8I_R_CCU
127
127
tristate "Support for Allwinner SoCs' PRCM CCUs"
128
-
default y
128
+
default ARCH_SUNXI
129
129
depends on MACH_SUN8I || ARM64 || COMPILE_TEST
130
130
131
131
endif
+1
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
+1
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
···
1094
1094
[RST_BUS_TCON_LCD1] = { 0xb7c, BIT(17) },
1095
1095
[RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
1096
1096
[RST_BUS_TCON_TV1] = { 0xb9c, BIT(17) },
1097
+
[RST_BUS_LVDS] = { 0xbac, BIT(16) },
1097
1098
[RST_BUS_TVE_TOP] = { 0xbbc, BIT(16) },
1098
1099
[RST_BUS_TVE0] = { 0xbbc, BIT(17) },
1099
1100
[RST_BUS_HDCP] = { 0xc4c, BIT(16) },
+25
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+25
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
···
5
5
6
6
#include <linux/clk.h>
7
7
#include <linux/clk-provider.h>
8
+
#include <linux/io.h>
8
9
#include <linux/module.h>
9
10
#include <linux/of.h>
10
11
#include <linux/platform_device.h>
···
240
239
.num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
241
240
};
242
241
242
+
static const struct sunxi_ccu_desc sun50i_h616_de33_clk_desc = {
243
+
.ccu_clks = sun8i_de2_ccu_clks,
244
+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
245
+
246
+
.hw_clks = &sun8i_h3_de2_hw_clks,
247
+
248
+
.resets = sun50i_h5_de2_resets,
249
+
.num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
250
+
};
251
+
243
252
static int sunxi_de2_clk_probe(struct platform_device *pdev)
244
253
{
245
254
struct clk *bus_clk, *mod_clk;
···
302
291
goto err_disable_mod_clk;
303
292
}
304
293
294
+
/*
295
+
* The DE33 requires these additional (unknown) registers set
296
+
* during initialisation.
297
+
*/
298
+
if (of_device_is_compatible(pdev->dev.of_node,
299
+
"allwinner,sun50i-h616-de33-clk")) {
300
+
writel(0, reg + 0x24);
301
+
writel(0x0000a980, reg + 0x28);
302
+
}
303
+
305
304
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc);
306
305
if (ret)
307
306
goto err_assert_reset;
···
355
334
{
356
335
.compatible = "allwinner,sun50i-h6-de3-clk",
357
336
.data = &sun50i_h5_de2_clk_desc,
337
+
},
338
+
{
339
+
.compatible = "allwinner,sun50i-h616-de33-clk",
340
+
.data = &sun50i_h616_de33_clk_desc,
358
341
},
359
342
{ }
360
343
};
+5
-5
drivers/clk/sunxi/Kconfig
+5
-5
drivers/clk/sunxi/Kconfig
···
2
2
menuconfig CLK_SUNXI
3
3
bool "Legacy clock support for Allwinner SoCs"
4
4
depends on (ARM && ARCH_SUNXI) || COMPILE_TEST
5
-
default y
5
+
default (ARM && ARCH_SUNXI)
6
6
7
7
if CLK_SUNXI
8
8
9
9
config CLK_SUNXI_CLOCKS
10
10
bool "Legacy clock drivers"
11
-
default y
11
+
default ARCH_SUNXI
12
12
help
13
13
Legacy clock drivers being used on older (A10, A13, A20,
14
14
A23, A31, A80) SoCs. These drivers are kept around for
···
19
19
20
20
config CLK_SUNXI_PRCM_SUN6I
21
21
bool "Legacy A31 PRCM driver"
22
-
default y
22
+
default ARCH_SUNXI
23
23
help
24
24
Legacy clock driver for the A31 PRCM clocks. Those are
25
25
usually needed for the PMIC communication, mostly.
26
26
27
27
config CLK_SUNXI_PRCM_SUN8I
28
28
bool "Legacy sun8i PRCM driver"
29
-
default y
29
+
default ARCH_SUNXI
30
30
help
31
31
Legacy clock driver for the sun8i family PRCM clocks.
32
32
Those are usually needed for the PMIC communication,
···
34
34
35
35
config CLK_SUNXI_PRCM_SUN9I
36
36
bool "Legacy A80 PRCM driver"
37
-
default y
37
+
default ARCH_SUNXI
38
38
help
39
39
Legacy clock driver for the A80 PRCM clocks. Those are
40
40
usually needed for the PMIC communication, mostly.
+168
-28
drivers/clk/thead/clk-th1520-ap.c
+168
-28
drivers/clk/thead/clk-th1520-ap.c
···
847
847
static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2), 0);
848
848
static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1), 0);
849
849
850
+
static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk",
851
+
video_pll_clk_pd, 0x0, BIT(0), 0);
852
+
static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_pd,
853
+
0x0, BIT(3), 0);
854
+
static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk",
855
+
video_pll_clk_pd, 0x0, BIT(4), 0);
856
+
static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk",
857
+
video_pll_clk_pd, 0x0, BIT(5), 0);
858
+
static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk",
859
+
video_pll_clk_pd, 0x0, BIT(6), 0);
860
+
static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0,
861
+
BIT(7), 0);
862
+
static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0,
863
+
BIT(8), 0);
864
+
static CCU_GATE(CLK_DPU_CCLK, dpu_cclk, "dpu-cclk", video_pll_clk_pd, 0x0,
865
+
BIT(9), 0);
866
+
static CCU_GATE(CLK_HDMI_SFR, hdmi_sfr_clk, "hdmi-sfr-clk", video_pll_clk_pd,
867
+
0x0, BIT(10), 0);
868
+
static CCU_GATE(CLK_HDMI_PCLK, hdmi_pclk, "hdmi-pclk", video_pll_clk_pd, 0x0,
869
+
BIT(11), 0);
870
+
static CCU_GATE(CLK_HDMI_CEC, hdmi_cec_clk, "hdmi-cec-clk", video_pll_clk_pd,
871
+
0x0, BIT(12), 0);
872
+
static CCU_GATE(CLK_MIPI_DSI0_PCLK, mipi_dsi0_pclk, "mipi-dsi0-pclk",
873
+
video_pll_clk_pd, 0x0, BIT(13), 0);
874
+
static CCU_GATE(CLK_MIPI_DSI1_PCLK, mipi_dsi1_pclk, "mipi-dsi1-pclk",
875
+
video_pll_clk_pd, 0x0, BIT(14), 0);
876
+
static CCU_GATE(CLK_MIPI_DSI0_CFG, mipi_dsi0_cfg_clk, "mipi-dsi0-cfg-clk",
877
+
video_pll_clk_pd, 0x0, BIT(15), 0);
878
+
static CCU_GATE(CLK_MIPI_DSI1_CFG, mipi_dsi1_cfg_clk, "mipi-dsi1-cfg-clk",
879
+
video_pll_clk_pd, 0x0, BIT(16), 0);
880
+
static CCU_GATE(CLK_MIPI_DSI0_REFCLK, mipi_dsi0_refclk, "mipi-dsi0-refclk",
881
+
video_pll_clk_pd, 0x0, BIT(17), 0);
882
+
static CCU_GATE(CLK_MIPI_DSI1_REFCLK, mipi_dsi1_refclk, "mipi-dsi1-refclk",
883
+
video_pll_clk_pd, 0x0, BIT(18), 0);
884
+
static CCU_GATE(CLK_HDMI_I2S, hdmi_i2s_clk, "hdmi-i2s-clk", video_pll_clk_pd,
885
+
0x0, BIT(19), 0);
886
+
static CCU_GATE(CLK_X2H_DPU1_ACLK, x2h_dpu1_aclk, "x2h-dpu1-aclk",
887
+
video_pll_clk_pd, 0x0, BIT(20), 0);
888
+
static CCU_GATE(CLK_X2H_DPU_ACLK, x2h_dpu_aclk, "x2h-dpu-aclk",
889
+
video_pll_clk_pd, 0x0, BIT(21), 0);
890
+
static CCU_GATE(CLK_AXI4_VO_PCLK, axi4_vo_pclk, "axi4-vo-pclk",
891
+
video_pll_clk_pd, 0x0, BIT(22), 0);
892
+
static CCU_GATE(CLK_IOPMP_VOSYS_DPU_PCLK, iopmp_vosys_dpu_pclk,
893
+
"iopmp-vosys-dpu-pclk", video_pll_clk_pd, 0x0, BIT(23), 0);
894
+
static CCU_GATE(CLK_IOPMP_VOSYS_DPU1_PCLK, iopmp_vosys_dpu1_pclk,
895
+
"iopmp-vosys-dpu1-pclk", video_pll_clk_pd, 0x0, BIT(24), 0);
896
+
static CCU_GATE(CLK_IOPMP_VOSYS_GPU_PCLK, iopmp_vosys_gpu_pclk,
897
+
"iopmp-vosys-gpu-pclk", video_pll_clk_pd, 0x0, BIT(25), 0);
898
+
static CCU_GATE(CLK_IOPMP_DPU1_ACLK, iopmp_dpu1_aclk, "iopmp-dpu1-aclk",
899
+
video_pll_clk_pd, 0x0, BIT(27), 0);
900
+
static CCU_GATE(CLK_IOPMP_DPU_ACLK, iopmp_dpu_aclk, "iopmp-dpu-aclk",
901
+
video_pll_clk_pd, 0x0, BIT(28), 0);
902
+
static CCU_GATE(CLK_IOPMP_GPU_ACLK, iopmp_gpu_aclk, "iopmp-gpu-aclk",
903
+
video_pll_clk_pd, 0x0, BIT(29), 0);
904
+
static CCU_GATE(CLK_MIPIDSI0_PIXCLK, mipi_dsi0_pixclk, "mipi-dsi0-pixclk",
905
+
video_pll_clk_pd, 0x0, BIT(30), 0);
906
+
static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk",
907
+
video_pll_clk_pd, 0x0, BIT(31), 0);
908
+
static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk_pd,
909
+
0x4, BIT(0), 0);
910
+
850
911
static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m",
851
912
&gmac_pll_clk.common.hw, 10, 1, 0);
852
913
···
1024
963
&sram3_clk.common,
1025
964
};
1026
965
1027
-
#define NR_CLKS (CLK_UART_SCLK + 1)
966
+
static struct ccu_common *th1520_vo_gate_clks[] = {
967
+
&axi4_vo_aclk.common,
968
+
&gpu_core_clk.common,
969
+
&gpu_cfg_aclk.common,
970
+
&dpu0_pixelclk.common,
971
+
&dpu1_pixelclk.common,
972
+
&dpu_hclk.common,
973
+
&dpu_aclk.common,
974
+
&dpu_cclk.common,
975
+
&hdmi_sfr_clk.common,
976
+
&hdmi_pclk.common,
977
+
&hdmi_cec_clk.common,
978
+
&mipi_dsi0_pclk.common,
979
+
&mipi_dsi1_pclk.common,
980
+
&mipi_dsi0_cfg_clk.common,
981
+
&mipi_dsi1_cfg_clk.common,
982
+
&mipi_dsi0_refclk.common,
983
+
&mipi_dsi1_refclk.common,
984
+
&hdmi_i2s_clk.common,
985
+
&x2h_dpu1_aclk.common,
986
+
&x2h_dpu_aclk.common,
987
+
&axi4_vo_pclk.common,
988
+
&iopmp_vosys_dpu_pclk.common,
989
+
&iopmp_vosys_dpu1_pclk.common,
990
+
&iopmp_vosys_gpu_pclk.common,
991
+
&iopmp_dpu1_aclk.common,
992
+
&iopmp_dpu_aclk.common,
993
+
&iopmp_gpu_aclk.common,
994
+
&mipi_dsi0_pixclk.common,
995
+
&mipi_dsi1_pixclk.common,
996
+
&hdmi_pixclk.common
997
+
};
1028
998
1029
999
static const struct regmap_config th1520_clk_regmap_config = {
1030
1000
.reg_bits = 32,
···
1064
972
.fast_io = true,
1065
973
};
1066
974
975
+
struct th1520_plat_data {
976
+
struct ccu_common **th1520_pll_clks;
977
+
struct ccu_common **th1520_div_clks;
978
+
struct ccu_common **th1520_mux_clks;
979
+
struct ccu_common **th1520_gate_clks;
980
+
981
+
int nr_clks;
982
+
int nr_pll_clks;
983
+
int nr_div_clks;
984
+
int nr_mux_clks;
985
+
int nr_gate_clks;
986
+
};
987
+
988
+
static const struct th1520_plat_data th1520_ap_platdata = {
989
+
.th1520_pll_clks = th1520_pll_clks,
990
+
.th1520_div_clks = th1520_div_clks,
991
+
.th1520_mux_clks = th1520_mux_clks,
992
+
.th1520_gate_clks = th1520_gate_clks,
993
+
994
+
.nr_clks = CLK_UART_SCLK + 1,
995
+
996
+
.nr_pll_clks = ARRAY_SIZE(th1520_pll_clks),
997
+
.nr_div_clks = ARRAY_SIZE(th1520_div_clks),
998
+
.nr_mux_clks = ARRAY_SIZE(th1520_mux_clks),
999
+
.nr_gate_clks = ARRAY_SIZE(th1520_gate_clks),
1000
+
};
1001
+
1002
+
static const struct th1520_plat_data th1520_vo_platdata = {
1003
+
.th1520_gate_clks = th1520_vo_gate_clks,
1004
+
1005
+
.nr_clks = CLK_HDMI_PIXCLK + 1,
1006
+
1007
+
.nr_gate_clks = ARRAY_SIZE(th1520_vo_gate_clks),
1008
+
};
1009
+
1067
1010
static int th1520_clk_probe(struct platform_device *pdev)
1068
1011
{
1012
+
const struct th1520_plat_data *plat_data;
1069
1013
struct device *dev = &pdev->dev;
1070
1014
struct clk_hw_onecell_data *priv;
1071
1015
···
1110
982
struct clk_hw *hw;
1111
983
int ret, i;
1112
984
1113
-
priv = devm_kzalloc(dev, struct_size(priv, hws, NR_CLKS), GFP_KERNEL);
985
+
plat_data = device_get_match_data(&pdev->dev);
986
+
if (!plat_data)
987
+
return dev_err_probe(&pdev->dev, -ENODEV,
988
+
"No device match data found\n");
989
+
990
+
priv = devm_kzalloc(dev, struct_size(priv, hws, plat_data->nr_clks), GFP_KERNEL);
1114
991
if (!priv)
1115
992
return -ENOMEM;
1116
993
1117
-
priv->num = NR_CLKS;
994
+
priv->num = plat_data->nr_clks;
1118
995
1119
996
base = devm_platform_ioremap_resource(pdev, 0);
1120
997
if (IS_ERR(base))
···
1129
996
if (IS_ERR(map))
1130
997
return PTR_ERR(map);
1131
998
1132
-
for (i = 0; i < ARRAY_SIZE(th1520_pll_clks); i++) {
1133
-
struct ccu_pll *cp = hw_to_ccu_pll(&th1520_pll_clks[i]->hw);
999
+
for (i = 0; i < plat_data->nr_pll_clks; i++) {
1000
+
struct ccu_pll *cp = hw_to_ccu_pll(&plat_data->th1520_pll_clks[i]->hw);
1134
1001
1135
-
th1520_pll_clks[i]->map = map;
1002
+
plat_data->th1520_pll_clks[i]->map = map;
1136
1003
1137
-
ret = devm_clk_hw_register(dev, &th1520_pll_clks[i]->hw);
1004
+
ret = devm_clk_hw_register(dev, &plat_data->th1520_pll_clks[i]->hw);
1138
1005
if (ret)
1139
1006
return ret;
1140
1007
1141
1008
priv->hws[cp->common.clkid] = &cp->common.hw;
1142
1009
}
1143
1010
1144
-
for (i = 0; i < ARRAY_SIZE(th1520_div_clks); i++) {
1145
-
struct ccu_div *cd = hw_to_ccu_div(&th1520_div_clks[i]->hw);
1011
+
for (i = 0; i < plat_data->nr_div_clks; i++) {
1012
+
struct ccu_div *cd = hw_to_ccu_div(&plat_data->th1520_div_clks[i]->hw);
1146
1013
1147
-
th1520_div_clks[i]->map = map;
1014
+
plat_data->th1520_div_clks[i]->map = map;
1148
1015
1149
-
ret = devm_clk_hw_register(dev, &th1520_div_clks[i]->hw);
1016
+
ret = devm_clk_hw_register(dev, &plat_data->th1520_div_clks[i]->hw);
1150
1017
if (ret)
1151
1018
return ret;
1152
1019
1153
1020
priv->hws[cd->common.clkid] = &cd->common.hw;
1154
1021
}
1155
1022
1156
-
for (i = 0; i < ARRAY_SIZE(th1520_mux_clks); i++) {
1157
-
struct ccu_mux *cm = hw_to_ccu_mux(&th1520_mux_clks[i]->hw);
1023
+
for (i = 0; i < plat_data->nr_mux_clks; i++) {
1024
+
struct ccu_mux *cm = hw_to_ccu_mux(&plat_data->th1520_mux_clks[i]->hw);
1158
1025
const struct clk_init_data *init = cm->common.hw.init;
1159
1026
1160
-
th1520_mux_clks[i]->map = map;
1027
+
plat_data->th1520_mux_clks[i]->map = map;
1161
1028
hw = devm_clk_hw_register_mux_parent_data_table(dev,
1162
1029
init->name,
1163
1030
init->parent_data,
···
1173
1040
priv->hws[cm->common.clkid] = hw;
1174
1041
}
1175
1042
1176
-
for (i = 0; i < ARRAY_SIZE(th1520_gate_clks); i++) {
1177
-
struct ccu_gate *cg = hw_to_ccu_gate(&th1520_gate_clks[i]->hw);
1043
+
for (i = 0; i < plat_data->nr_gate_clks; i++) {
1044
+
struct ccu_gate *cg = hw_to_ccu_gate(&plat_data->th1520_gate_clks[i]->hw);
1178
1045
1179
-
th1520_gate_clks[i]->map = map;
1046
+
plat_data->th1520_gate_clks[i]->map = map;
1180
1047
1181
1048
hw = devm_clk_hw_register_gate_parent_data(dev,
1182
1049
cg->common.hw.init->name,
···
1190
1057
priv->hws[cg->common.clkid] = hw;
1191
1058
}
1192
1059
1193
-
ret = devm_clk_hw_register(dev, &osc12m_clk.hw);
1194
-
if (ret)
1195
-
return ret;
1196
-
priv->hws[CLK_OSC12M] = &osc12m_clk.hw;
1060
+
if (plat_data == &th1520_ap_platdata) {
1061
+
ret = devm_clk_hw_register(dev, &osc12m_clk.hw);
1062
+
if (ret)
1063
+
return ret;
1064
+
priv->hws[CLK_OSC12M] = &osc12m_clk.hw;
1197
1065
1198
-
ret = devm_clk_hw_register(dev, &gmac_pll_clk_100m.hw);
1199
-
if (ret)
1200
-
return ret;
1201
-
priv->hws[CLK_PLL_GMAC_100M] = &gmac_pll_clk_100m.hw;
1066
+
ret = devm_clk_hw_register(dev, &gmac_pll_clk_100m.hw);
1067
+
if (ret)
1068
+
return ret;
1069
+
priv->hws[CLK_PLL_GMAC_100M] = &gmac_pll_clk_100m.hw;
1202
1070
1203
-
ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw);
1204
-
if (ret)
1205
-
return ret;
1071
+
ret = devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw);
1072
+
if (ret)
1073
+
return ret;
1074
+
}
1206
1075
1207
1076
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv);
1208
1077
if (ret)
···
1216
1081
static const struct of_device_id th1520_clk_match[] = {
1217
1082
{
1218
1083
.compatible = "thead,th1520-clk-ap",
1084
+
.data = &th1520_ap_platdata,
1085
+
},
1086
+
{
1087
+
.compatible = "thead,th1520-clk-vo",
1088
+
.data = &th1520_vo_platdata,
1219
1089
},
1220
1090
{ /* sentinel */ },
1221
1091
};
+27
include/dt-bindings/clock/qcom,sm6350-videocc.h
+27
include/dt-bindings/clock/qcom,sm6350-videocc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H
8
+
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM6350_H
9
+
10
+
/* VIDEO_CC clocks */
11
+
#define VIDEO_PLL0 0
12
+
#define VIDEO_PLL0_OUT_EVEN 1
13
+
#define VIDEO_CC_IRIS_AHB_CLK 2
14
+
#define VIDEO_CC_IRIS_CLK_SRC 3
15
+
#define VIDEO_CC_MVS0_AXI_CLK 4
16
+
#define VIDEO_CC_MVS0_CORE_CLK 5
17
+
#define VIDEO_CC_MVSC_CORE_CLK 6
18
+
#define VIDEO_CC_MVSC_CTL_AXI_CLK 7
19
+
#define VIDEO_CC_SLEEP_CLK 8
20
+
#define VIDEO_CC_SLEEP_CLK_SRC 9
21
+
#define VIDEO_CC_VENUS_AHB_CLK 10
22
+
23
+
/* GDSCs */
24
+
#define MVSC_GDSC 0
25
+
#define MVS0_GDSC 1
26
+
27
+
#endif
+3
include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+3
include/dt-bindings/clock/renesas,r9a09g047-cpg.h
···
17
17
#define R9A09G047_CM33_CLK0 6
18
18
#define R9A09G047_CST_0_SWCLKTCK 7
19
19
#define R9A09G047_IOTOP_0_SHCLK 8
20
+
#define R9A09G047_SPI_CLK_SPI 9
21
+
#define R9A09G047_GBETH_0_CLK_PTP_REF_I 10
22
+
#define R9A09G047_GBETH_1_CLK_PTP_REF_I 11
20
23
21
24
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
+24
include/dt-bindings/clock/renesas,r9a09g056-cpg.h
+24
include/dt-bindings/clock/renesas,r9a09g056-cpg.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
*
3
+
* Copyright (C) 2025 Renesas Electronics Corp.
4
+
*/
5
+
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__
6
+
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__
7
+
8
+
#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
+
10
+
/* Core Clock list */
11
+
#define R9A09G056_SYS_0_PCLK 0
12
+
#define R9A09G056_CA55_0_CORE_CLK0 1
13
+
#define R9A09G056_CA55_0_CORE_CLK1 2
14
+
#define R9A09G056_CA55_0_CORE_CLK2 3
15
+
#define R9A09G056_CA55_0_CORE_CLK3 4
16
+
#define R9A09G056_CA55_0_PERIPHCLK 5
17
+
#define R9A09G056_CM33_CLK0 6
18
+
#define R9A09G056_CST_0_SWCLKTCK 7
19
+
#define R9A09G056_IOTOP_0_SHCLK 8
20
+
#define R9A09G056_USB2_0_CLK_CORE0 9
21
+
#define R9A09G056_GBETH_0_CLK_PTP_REF_I 10
22
+
#define R9A09G056_GBETH_1_CLK_PTP_REF_I 11
23
+
24
+
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */
+4
include/dt-bindings/clock/renesas,r9a09g057-cpg.h
+4
include/dt-bindings/clock/renesas,r9a09g057-cpg.h
···
17
17
#define R9A09G057_CM33_CLK0 6
18
18
#define R9A09G057_CST_0_SWCLKTCK 7
19
19
#define R9A09G057_IOTOP_0_SHCLK 8
20
+
#define R9A09G057_USB2_0_CLK_CORE0 9
21
+
#define R9A09G057_USB2_0_CLK_CORE1 10
22
+
#define R9A09G057_GBETH_0_CLK_PTP_REF_I 11
23
+
#define R9A09G057_GBETH_1_CLK_PTP_REF_I 12
20
24
21
25
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */
+1
include/dt-bindings/clock/rk3036-cru.h
+1
include/dt-bindings/clock/rk3036-cru.h
+6
include/dt-bindings/clock/rockchip,rk3528-cru.h
+6
include/dt-bindings/clock/rockchip,rk3528-cru.h
···
414
414
#define MCLK_I2S2_2CH_SAI_SRC_PRE 402
415
415
#define MCLK_I2S3_8CH_SAI_SRC_PRE 403
416
416
#define MCLK_SDPDIF_SRC_PRE 404
417
+
#define SCLK_SDMMC_DRV 405
418
+
#define SCLK_SDMMC_SAMPLE 406
419
+
#define SCLK_SDIO0_DRV 407
420
+
#define SCLK_SDIO0_SAMPLE 408
421
+
#define SCLK_SDIO1_DRV 409
422
+
#define SCLK_SDIO1_SAMPLE 410
417
423
418
424
/* scmi-clocks indices */
419
425
#define SCMI_PCLK_KEYREADER 0
+10
include/dt-bindings/clock/rockchip,rk3576-cru.h
+10
include/dt-bindings/clock/rockchip,rk3576-cru.h
···
594
594
#define SCMI_ARMCLK_B 11
595
595
#define SCMI_CLK_GPU 456
596
596
597
+
/* IOC-controlled output clocks */
598
+
#define CLK_SAI0_MCLKOUT_TO_IO 571
599
+
#define CLK_SAI1_MCLKOUT_TO_IO 572
600
+
#define CLK_SAI2_MCLKOUT_TO_IO 573
601
+
#define CLK_SAI3_MCLKOUT_TO_IO 574
602
+
#define CLK_SAI4_MCLKOUT_TO_IO 575
603
+
#define CLK_SAI4_MCLKOUT_TO_IO 575
604
+
#define CLK_FSPI0_TO_IO 576
605
+
#define CLK_FSPI1_TO_IO 577
606
+
597
607
#endif
+51
include/dt-bindings/clock/samsung,exynosautov920.h
+51
include/dt-bindings/clock/samsung,exynosautov920.h
···
162
162
#define DOUT_CLKCMU_TAA_NOC 146
163
163
#define DOUT_TCXO_DIV2 147
164
164
165
+
/* CMU_CPUCL0 */
166
+
#define CLK_FOUT_CPUCL0_PLL 1
167
+
168
+
#define CLK_MOUT_PLL_CPUCL0 2
169
+
#define CLK_MOUT_CPUCL0_CLUSTER_USER 3
170
+
#define CLK_MOUT_CPUCL0_DBG_USER 4
171
+
#define CLK_MOUT_CPUCL0_SWITCH_USER 5
172
+
#define CLK_MOUT_CPUCL0_CLUSTER 6
173
+
#define CLK_MOUT_CPUCL0_CORE 7
174
+
175
+
#define CLK_DOUT_CLUSTER0_ACLK 8
176
+
#define CLK_DOUT_CLUSTER0_ATCLK 9
177
+
#define CLK_DOUT_CLUSTER0_MPCLK 10
178
+
#define CLK_DOUT_CLUSTER0_PCLK 11
179
+
#define CLK_DOUT_CLUSTER0_PERIPHCLK 12
180
+
#define CLK_DOUT_CPUCL0_DBG_NOC 13
181
+
#define CLK_DOUT_CPUCL0_DBG_PCLKDBG 14
182
+
#define CLK_DOUT_CPUCL0_NOCP 15
183
+
184
+
/* CMU_CPUCL1 */
185
+
#define CLK_FOUT_CPUCL1_PLL 1
186
+
187
+
#define CLK_MOUT_PLL_CPUCL1 2
188
+
#define CLK_MOUT_CPUCL1_CLUSTER_USER 3
189
+
#define CLK_MOUT_CPUCL1_SWITCH_USER 4
190
+
#define CLK_MOUT_CPUCL1_CLUSTER 5
191
+
#define CLK_MOUT_CPUCL1_CORE 6
192
+
193
+
#define CLK_DOUT_CLUSTER1_ACLK 7
194
+
#define CLK_DOUT_CLUSTER1_ATCLK 8
195
+
#define CLK_DOUT_CLUSTER1_MPCLK 9
196
+
#define CLK_DOUT_CLUSTER1_PCLK 10
197
+
#define CLK_DOUT_CLUSTER1_PERIPHCLK 11
198
+
#define CLK_DOUT_CPUCL1_NOCP 12
199
+
200
+
/* CMU_CPUCL2 */
201
+
#define CLK_FOUT_CPUCL2_PLL 1
202
+
203
+
#define CLK_MOUT_PLL_CPUCL2 2
204
+
#define CLK_MOUT_CPUCL2_CLUSTER_USER 3
205
+
#define CLK_MOUT_CPUCL2_SWITCH_USER 4
206
+
#define CLK_MOUT_CPUCL2_CLUSTER 5
207
+
#define CLK_MOUT_CPUCL2_CORE 6
208
+
209
+
#define CLK_DOUT_CLUSTER2_ACLK 7
210
+
#define CLK_DOUT_CLUSTER2_ATCLK 8
211
+
#define CLK_DOUT_CLUSTER2_MPCLK 9
212
+
#define CLK_DOUT_CLUSTER2_PCLK 10
213
+
#define CLK_DOUT_CLUSTER2_PERIPHCLK 11
214
+
#define CLK_DOUT_CPUCL2_NOCP 12
215
+
165
216
/* CMU_PERIC0 */
166
217
#define CLK_MOUT_PERIC0_IP_USER 1
167
218
#define CLK_MOUT_PERIC0_NOC_USER 2
+153
include/dt-bindings/clock/sophgo,sg2044-clk.h
+153
include/dt-bindings/clock/sophgo,sg2044-clk.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@gmail.com>
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_SOPHGO_SG2044_CLK_H__
7
+
#define __DT_BINDINGS_SOPHGO_SG2044_CLK_H__
8
+
9
+
#define CLK_DIV_AP_SYS_FIXED 0
10
+
#define CLK_DIV_AP_SYS_MAIN 1
11
+
#define CLK_DIV_RP_SYS_FIXED 2
12
+
#define CLK_DIV_RP_SYS_MAIN 3
13
+
#define CLK_DIV_TPU_SYS_FIXED 4
14
+
#define CLK_DIV_TPU_SYS_MAIN 5
15
+
#define CLK_DIV_NOC_SYS_FIXED 6
16
+
#define CLK_DIV_NOC_SYS_MAIN 7
17
+
#define CLK_DIV_VC_SRC0_FIXED 8
18
+
#define CLK_DIV_VC_SRC0_MAIN 9
19
+
#define CLK_DIV_VC_SRC1_FIXED 10
20
+
#define CLK_DIV_VC_SRC1_MAIN 11
21
+
#define CLK_DIV_CXP_MAC_FIXED 12
22
+
#define CLK_DIV_CXP_MAC_MAIN 13
23
+
#define CLK_DIV_DDR0_FIXED 14
24
+
#define CLK_DIV_DDR0_MAIN 15
25
+
#define CLK_DIV_DDR1_FIXED 16
26
+
#define CLK_DIV_DDR1_MAIN 17
27
+
#define CLK_DIV_DDR2_FIXED 18
28
+
#define CLK_DIV_DDR2_MAIN 19
29
+
#define CLK_DIV_DDR3_FIXED 20
30
+
#define CLK_DIV_DDR3_MAIN 21
31
+
#define CLK_DIV_DDR4_FIXED 22
32
+
#define CLK_DIV_DDR4_MAIN 23
33
+
#define CLK_DIV_DDR5_FIXED 24
34
+
#define CLK_DIV_DDR5_MAIN 25
35
+
#define CLK_DIV_DDR6_FIXED 26
36
+
#define CLK_DIV_DDR6_MAIN 27
37
+
#define CLK_DIV_DDR7_FIXED 28
38
+
#define CLK_DIV_DDR7_MAIN 29
39
+
#define CLK_DIV_TOP_50M 30
40
+
#define CLK_DIV_TOP_AXI0 31
41
+
#define CLK_DIV_TOP_AXI_HSPERI 32
42
+
#define CLK_DIV_TIMER0 33
43
+
#define CLK_DIV_TIMER1 34
44
+
#define CLK_DIV_TIMER2 35
45
+
#define CLK_DIV_TIMER3 36
46
+
#define CLK_DIV_TIMER4 37
47
+
#define CLK_DIV_TIMER5 38
48
+
#define CLK_DIV_TIMER6 39
49
+
#define CLK_DIV_TIMER7 40
50
+
#define CLK_DIV_CXP_TEST_PHY 41
51
+
#define CLK_DIV_CXP_TEST_ETH_PHY 42
52
+
#define CLK_DIV_C2C0_TEST_PHY 43
53
+
#define CLK_DIV_C2C1_TEST_PHY 44
54
+
#define CLK_DIV_PCIE_1G 45
55
+
#define CLK_DIV_UART_500M 46
56
+
#define CLK_DIV_GPIO_DB 47
57
+
#define CLK_DIV_SD 48
58
+
#define CLK_DIV_SD_100K 49
59
+
#define CLK_DIV_EMMC 50
60
+
#define CLK_DIV_EMMC_100K 51
61
+
#define CLK_DIV_EFUSE 52
62
+
#define CLK_DIV_TX_ETH0 53
63
+
#define CLK_DIV_PTP_REF_I_ETH0 54
64
+
#define CLK_DIV_REF_ETH0 55
65
+
#define CLK_DIV_PKA 56
66
+
#define CLK_MUX_DDR0 57
67
+
#define CLK_MUX_DDR1 58
68
+
#define CLK_MUX_DDR2 59
69
+
#define CLK_MUX_DDR3 60
70
+
#define CLK_MUX_DDR4 61
71
+
#define CLK_MUX_DDR5 62
72
+
#define CLK_MUX_DDR6 63
73
+
#define CLK_MUX_DDR7 64
74
+
#define CLK_MUX_NOC_SYS 65
75
+
#define CLK_MUX_TPU_SYS 66
76
+
#define CLK_MUX_RP_SYS 67
77
+
#define CLK_MUX_AP_SYS 68
78
+
#define CLK_MUX_VC_SRC0 69
79
+
#define CLK_MUX_VC_SRC1 70
80
+
#define CLK_MUX_CXP_MAC 71
81
+
#define CLK_GATE_AP_SYS 72
82
+
#define CLK_GATE_RP_SYS 73
83
+
#define CLK_GATE_TPU_SYS 74
84
+
#define CLK_GATE_NOC_SYS 75
85
+
#define CLK_GATE_VC_SRC0 76
86
+
#define CLK_GATE_VC_SRC1 77
87
+
#define CLK_GATE_DDR0 78
88
+
#define CLK_GATE_DDR1 79
89
+
#define CLK_GATE_DDR2 80
90
+
#define CLK_GATE_DDR3 81
91
+
#define CLK_GATE_DDR4 82
92
+
#define CLK_GATE_DDR5 83
93
+
#define CLK_GATE_DDR6 84
94
+
#define CLK_GATE_DDR7 85
95
+
#define CLK_GATE_TOP_50M 86
96
+
#define CLK_GATE_SC_RX 87
97
+
#define CLK_GATE_SC_RX_X0Y1 88
98
+
#define CLK_GATE_TOP_AXI0 89
99
+
#define CLK_GATE_INTC0 90
100
+
#define CLK_GATE_INTC1 91
101
+
#define CLK_GATE_INTC2 92
102
+
#define CLK_GATE_INTC3 93
103
+
#define CLK_GATE_MAILBOX0 94
104
+
#define CLK_GATE_MAILBOX1 95
105
+
#define CLK_GATE_MAILBOX2 96
106
+
#define CLK_GATE_MAILBOX3 97
107
+
#define CLK_GATE_TOP_AXI_HSPERI 98
108
+
#define CLK_GATE_APB_TIMER 99
109
+
#define CLK_GATE_TIMER0 100
110
+
#define CLK_GATE_TIMER1 101
111
+
#define CLK_GATE_TIMER2 102
112
+
#define CLK_GATE_TIMER3 103
113
+
#define CLK_GATE_TIMER4 104
114
+
#define CLK_GATE_TIMER5 105
115
+
#define CLK_GATE_TIMER6 106
116
+
#define CLK_GATE_TIMER7 107
117
+
#define CLK_GATE_CXP_CFG 108
118
+
#define CLK_GATE_CXP_MAC 109
119
+
#define CLK_GATE_CXP_TEST_PHY 110
120
+
#define CLK_GATE_CXP_TEST_ETH_PHY 111
121
+
#define CLK_GATE_PCIE_1G 112
122
+
#define CLK_GATE_C2C0_TEST_PHY 113
123
+
#define CLK_GATE_C2C1_TEST_PHY 114
124
+
#define CLK_GATE_UART_500M 115
125
+
#define CLK_GATE_APB_UART 116
126
+
#define CLK_GATE_APB_SPI 117
127
+
#define CLK_GATE_AHB_SPIFMC 118
128
+
#define CLK_GATE_APB_I2C 119
129
+
#define CLK_GATE_AXI_DBG_I2C 120
130
+
#define CLK_GATE_GPIO_DB 121
131
+
#define CLK_GATE_APB_GPIO_INTR 122
132
+
#define CLK_GATE_APB_GPIO 123
133
+
#define CLK_GATE_SD 124
134
+
#define CLK_GATE_AXI_SD 125
135
+
#define CLK_GATE_SD_100K 126
136
+
#define CLK_GATE_EMMC 127
137
+
#define CLK_GATE_AXI_EMMC 128
138
+
#define CLK_GATE_EMMC_100K 129
139
+
#define CLK_GATE_EFUSE 130
140
+
#define CLK_GATE_APB_EFUSE 131
141
+
#define CLK_GATE_SYSDMA_AXI 132
142
+
#define CLK_GATE_TX_ETH0 133
143
+
#define CLK_GATE_AXI_ETH0 134
144
+
#define CLK_GATE_PTP_REF_I_ETH0 135
145
+
#define CLK_GATE_REF_ETH0 136
146
+
#define CLK_GATE_APB_RTC 137
147
+
#define CLK_GATE_APB_PWM 138
148
+
#define CLK_GATE_APB_WDT 139
149
+
#define CLK_GATE_AXI_SRAM 140
150
+
#define CLK_GATE_AHB_ROM 141
151
+
#define CLK_GATE_PKA 142
152
+
153
+
#endif /* __DT_BINDINGS_SOPHGO_SG2044_CLK_H__ */
+27
include/dt-bindings/clock/sophgo,sg2044-pll.h
+27
include/dt-bindings/clock/sophgo,sg2044-pll.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
2
+
/*
3
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@gmail.com>
4
+
*/
5
+
6
+
#ifndef __DT_BINDINGS_SOPHGO_SG2044_PLL_H__
7
+
#define __DT_BINDINGS_SOPHGO_SG2044_PLL_H__
8
+
9
+
#define CLK_FPLL0 0
10
+
#define CLK_FPLL1 1
11
+
#define CLK_FPLL2 2
12
+
#define CLK_DPLL0 3
13
+
#define CLK_DPLL1 4
14
+
#define CLK_DPLL2 5
15
+
#define CLK_DPLL3 6
16
+
#define CLK_DPLL4 7
17
+
#define CLK_DPLL5 8
18
+
#define CLK_DPLL6 9
19
+
#define CLK_DPLL7 10
20
+
#define CLK_MPLL0 11
21
+
#define CLK_MPLL1 12
22
+
#define CLK_MPLL2 13
23
+
#define CLK_MPLL3 14
24
+
#define CLK_MPLL4 15
25
+
#define CLK_MPLL5 16
26
+
27
+
#endif /* __DT_BINDINGS_SOPHGO_SG2044_PLL_H__ */
+247
include/dt-bindings/clock/spacemit,k1-syscon.h
+247
include/dt-bindings/clock/spacemit,k1-syscon.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (C) 2024-2025 Haylen Chu <heylenay@outlook.com>
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_SPACEMIT_CCU_H_
7
+
#define _DT_BINDINGS_SPACEMIT_CCU_H_
8
+
9
+
/* APBS (PLL) clocks */
10
+
#define CLK_PLL1 0
11
+
#define CLK_PLL2 1
12
+
#define CLK_PLL3 2
13
+
#define CLK_PLL1_D2 3
14
+
#define CLK_PLL1_D3 4
15
+
#define CLK_PLL1_D4 5
16
+
#define CLK_PLL1_D5 6
17
+
#define CLK_PLL1_D6 7
18
+
#define CLK_PLL1_D7 8
19
+
#define CLK_PLL1_D8 9
20
+
#define CLK_PLL1_D11 10
21
+
#define CLK_PLL1_D13 11
22
+
#define CLK_PLL1_D23 12
23
+
#define CLK_PLL1_D64 13
24
+
#define CLK_PLL1_D10_AUD 14
25
+
#define CLK_PLL1_D100_AUD 15
26
+
#define CLK_PLL2_D1 16
27
+
#define CLK_PLL2_D2 17
28
+
#define CLK_PLL2_D3 18
29
+
#define CLK_PLL2_D4 19
30
+
#define CLK_PLL2_D5 20
31
+
#define CLK_PLL2_D6 21
32
+
#define CLK_PLL2_D7 22
33
+
#define CLK_PLL2_D8 23
34
+
#define CLK_PLL3_D1 24
35
+
#define CLK_PLL3_D2 25
36
+
#define CLK_PLL3_D3 26
37
+
#define CLK_PLL3_D4 27
38
+
#define CLK_PLL3_D5 28
39
+
#define CLK_PLL3_D6 29
40
+
#define CLK_PLL3_D7 30
41
+
#define CLK_PLL3_D8 31
42
+
#define CLK_PLL3_80 32
43
+
#define CLK_PLL3_40 33
44
+
#define CLK_PLL3_20 34
45
+
46
+
/* MPMU clocks */
47
+
#define CLK_PLL1_307P2 0
48
+
#define CLK_PLL1_76P8 1
49
+
#define CLK_PLL1_61P44 2
50
+
#define CLK_PLL1_153P6 3
51
+
#define CLK_PLL1_102P4 4
52
+
#define CLK_PLL1_51P2 5
53
+
#define CLK_PLL1_51P2_AP 6
54
+
#define CLK_PLL1_57P6 7
55
+
#define CLK_PLL1_25P6 8
56
+
#define CLK_PLL1_12P8 9
57
+
#define CLK_PLL1_12P8_WDT 10
58
+
#define CLK_PLL1_6P4 11
59
+
#define CLK_PLL1_3P2 12
60
+
#define CLK_PLL1_1P6 13
61
+
#define CLK_PLL1_0P8 14
62
+
#define CLK_PLL1_409P6 15
63
+
#define CLK_PLL1_204P8 16
64
+
#define CLK_PLL1_491 17
65
+
#define CLK_PLL1_245P76 18
66
+
#define CLK_PLL1_614 19
67
+
#define CLK_PLL1_47P26 20
68
+
#define CLK_PLL1_31P5 21
69
+
#define CLK_PLL1_819 22
70
+
#define CLK_PLL1_1228 23
71
+
#define CLK_SLOW_UART 24
72
+
#define CLK_SLOW_UART1 25
73
+
#define CLK_SLOW_UART2 26
74
+
#define CLK_WDT 27
75
+
#define CLK_RIPC 28
76
+
#define CLK_I2S_SYSCLK 29
77
+
#define CLK_I2S_BCLK 30
78
+
#define CLK_APB 31
79
+
#define CLK_WDT_BUS 32
80
+
81
+
/* APBC clocks */
82
+
#define CLK_UART0 0
83
+
#define CLK_UART2 1
84
+
#define CLK_UART3 2
85
+
#define CLK_UART4 3
86
+
#define CLK_UART5 4
87
+
#define CLK_UART6 5
88
+
#define CLK_UART7 6
89
+
#define CLK_UART8 7
90
+
#define CLK_UART9 8
91
+
#define CLK_GPIO 9
92
+
#define CLK_PWM0 10
93
+
#define CLK_PWM1 11
94
+
#define CLK_PWM2 12
95
+
#define CLK_PWM3 13
96
+
#define CLK_PWM4 14
97
+
#define CLK_PWM5 15
98
+
#define CLK_PWM6 16
99
+
#define CLK_PWM7 17
100
+
#define CLK_PWM8 18
101
+
#define CLK_PWM9 19
102
+
#define CLK_PWM10 20
103
+
#define CLK_PWM11 21
104
+
#define CLK_PWM12 22
105
+
#define CLK_PWM13 23
106
+
#define CLK_PWM14 24
107
+
#define CLK_PWM15 25
108
+
#define CLK_PWM16 26
109
+
#define CLK_PWM17 27
110
+
#define CLK_PWM18 28
111
+
#define CLK_PWM19 29
112
+
#define CLK_SSP3 30
113
+
#define CLK_RTC 31
114
+
#define CLK_TWSI0 32
115
+
#define CLK_TWSI1 33
116
+
#define CLK_TWSI2 34
117
+
#define CLK_TWSI4 35
118
+
#define CLK_TWSI5 36
119
+
#define CLK_TWSI6 37
120
+
#define CLK_TWSI7 38
121
+
#define CLK_TWSI8 39
122
+
#define CLK_TIMERS1 40
123
+
#define CLK_TIMERS2 41
124
+
#define CLK_AIB 42
125
+
#define CLK_ONEWIRE 43
126
+
#define CLK_SSPA0 44
127
+
#define CLK_SSPA1 45
128
+
#define CLK_DRO 46
129
+
#define CLK_IR 47
130
+
#define CLK_TSEN 48
131
+
#define CLK_IPC_AP2AUD 49
132
+
#define CLK_CAN0 50
133
+
#define CLK_CAN0_BUS 51
134
+
#define CLK_UART0_BUS 52
135
+
#define CLK_UART2_BUS 53
136
+
#define CLK_UART3_BUS 54
137
+
#define CLK_UART4_BUS 55
138
+
#define CLK_UART5_BUS 56
139
+
#define CLK_UART6_BUS 57
140
+
#define CLK_UART7_BUS 58
141
+
#define CLK_UART8_BUS 59
142
+
#define CLK_UART9_BUS 60
143
+
#define CLK_GPIO_BUS 61
144
+
#define CLK_PWM0_BUS 62
145
+
#define CLK_PWM1_BUS 63
146
+
#define CLK_PWM2_BUS 64
147
+
#define CLK_PWM3_BUS 65
148
+
#define CLK_PWM4_BUS 66
149
+
#define CLK_PWM5_BUS 67
150
+
#define CLK_PWM6_BUS 68
151
+
#define CLK_PWM7_BUS 69
152
+
#define CLK_PWM8_BUS 70
153
+
#define CLK_PWM9_BUS 71
154
+
#define CLK_PWM10_BUS 72
155
+
#define CLK_PWM11_BUS 73
156
+
#define CLK_PWM12_BUS 74
157
+
#define CLK_PWM13_BUS 75
158
+
#define CLK_PWM14_BUS 76
159
+
#define CLK_PWM15_BUS 77
160
+
#define CLK_PWM16_BUS 78
161
+
#define CLK_PWM17_BUS 79
162
+
#define CLK_PWM18_BUS 80
163
+
#define CLK_PWM19_BUS 81
164
+
#define CLK_SSP3_BUS 82
165
+
#define CLK_RTC_BUS 83
166
+
#define CLK_TWSI0_BUS 84
167
+
#define CLK_TWSI1_BUS 85
168
+
#define CLK_TWSI2_BUS 86
169
+
#define CLK_TWSI4_BUS 87
170
+
#define CLK_TWSI5_BUS 88
171
+
#define CLK_TWSI6_BUS 89
172
+
#define CLK_TWSI7_BUS 90
173
+
#define CLK_TWSI8_BUS 91
174
+
#define CLK_TIMERS1_BUS 92
175
+
#define CLK_TIMERS2_BUS 93
176
+
#define CLK_AIB_BUS 94
177
+
#define CLK_ONEWIRE_BUS 95
178
+
#define CLK_SSPA0_BUS 96
179
+
#define CLK_SSPA1_BUS 97
180
+
#define CLK_TSEN_BUS 98
181
+
#define CLK_IPC_AP2AUD_BUS 99
182
+
183
+
/* APMU clocks */
184
+
#define CLK_CCI550 0
185
+
#define CLK_CPU_C0_HI 1
186
+
#define CLK_CPU_C0_CORE 2
187
+
#define CLK_CPU_C0_ACE 3
188
+
#define CLK_CPU_C0_TCM 4
189
+
#define CLK_CPU_C1_HI 5
190
+
#define CLK_CPU_C1_CORE 6
191
+
#define CLK_CPU_C1_ACE 7
192
+
#define CLK_CCIC_4X 8
193
+
#define CLK_CCIC1PHY 9
194
+
#define CLK_SDH_AXI 10
195
+
#define CLK_SDH0 11
196
+
#define CLK_SDH1 12
197
+
#define CLK_SDH2 13
198
+
#define CLK_USB_P1 14
199
+
#define CLK_USB_AXI 15
200
+
#define CLK_USB30 16
201
+
#define CLK_QSPI 17
202
+
#define CLK_QSPI_BUS 18
203
+
#define CLK_DMA 19
204
+
#define CLK_AES 20
205
+
#define CLK_VPU 21
206
+
#define CLK_GPU 22
207
+
#define CLK_EMMC 23
208
+
#define CLK_EMMC_X 24
209
+
#define CLK_AUDIO 25
210
+
#define CLK_HDMI 26
211
+
#define CLK_PMUA_ACLK 27
212
+
#define CLK_PCIE0_MASTER 28
213
+
#define CLK_PCIE0_SLAVE 29
214
+
#define CLK_PCIE0_DBI 30
215
+
#define CLK_PCIE1_MASTER 31
216
+
#define CLK_PCIE1_SLAVE 32
217
+
#define CLK_PCIE1_DBI 33
218
+
#define CLK_PCIE2_MASTER 34
219
+
#define CLK_PCIE2_SLAVE 35
220
+
#define CLK_PCIE2_DBI 36
221
+
#define CLK_EMAC0_BUS 37
222
+
#define CLK_EMAC0_PTP 38
223
+
#define CLK_EMAC1_BUS 39
224
+
#define CLK_EMAC1_PTP 40
225
+
#define CLK_JPG 41
226
+
#define CLK_CCIC2PHY 42
227
+
#define CLK_CCIC3PHY 43
228
+
#define CLK_CSI 44
229
+
#define CLK_CAMM0 45
230
+
#define CLK_CAMM1 46
231
+
#define CLK_CAMM2 47
232
+
#define CLK_ISP_CPP 48
233
+
#define CLK_ISP_BUS 49
234
+
#define CLK_ISP 50
235
+
#define CLK_DPU_MCLK 51
236
+
#define CLK_DPU_ESC 52
237
+
#define CLK_DPU_BIT 53
238
+
#define CLK_DPU_PXCLK 54
239
+
#define CLK_DPU_HCLK 55
240
+
#define CLK_DPU_SPI 56
241
+
#define CLK_DPU_SPI_HBUS 57
242
+
#define CLK_DPU_SPIBUS 58
243
+
#define CLK_DPU_SPI_ACLK 59
244
+
#define CLK_V2D 60
245
+
#define CLK_EMMC_BUS 61
246
+
247
+
#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */
+34
include/dt-bindings/clock/thead,th1520-clk-ap.h
+34
include/dt-bindings/clock/thead,th1520-clk-ap.h
···
93
93
#define CLK_SRAM3 83
94
94
#define CLK_PLL_GMAC_100M 84
95
95
#define CLK_UART_SCLK 85
96
+
97
+
/* VO clocks */
98
+
#define CLK_AXI4_VO_ACLK 0
99
+
#define CLK_GPU_MEM 1
100
+
#define CLK_GPU_CORE 2
101
+
#define CLK_GPU_CFG_ACLK 3
102
+
#define CLK_DPU_PIXELCLK0 4
103
+
#define CLK_DPU_PIXELCLK1 5
104
+
#define CLK_DPU_HCLK 6
105
+
#define CLK_DPU_ACLK 7
106
+
#define CLK_DPU_CCLK 8
107
+
#define CLK_HDMI_SFR 9
108
+
#define CLK_HDMI_PCLK 10
109
+
#define CLK_HDMI_CEC 11
110
+
#define CLK_MIPI_DSI0_PCLK 12
111
+
#define CLK_MIPI_DSI1_PCLK 13
112
+
#define CLK_MIPI_DSI0_CFG 14
113
+
#define CLK_MIPI_DSI1_CFG 15
114
+
#define CLK_MIPI_DSI0_REFCLK 16
115
+
#define CLK_MIPI_DSI1_REFCLK 17
116
+
#define CLK_HDMI_I2S 18
117
+
#define CLK_X2H_DPU1_ACLK 19
118
+
#define CLK_X2H_DPU_ACLK 20
119
+
#define CLK_AXI4_VO_PCLK 21
120
+
#define CLK_IOPMP_VOSYS_DPU_PCLK 22
121
+
#define CLK_IOPMP_VOSYS_DPU1_PCLK 23
122
+
#define CLK_IOPMP_VOSYS_GPU_PCLK 24
123
+
#define CLK_IOPMP_DPU1_ACLK 25
124
+
#define CLK_IOPMP_DPU_ACLK 26
125
+
#define CLK_IOPMP_GPU_ACLK 27
126
+
#define CLK_MIPIDSI0_PIXCLK 28
127
+
#define CLK_MIPIDSI1_PIXCLK 29
128
+
#define CLK_HDMI_PIXCLK 30
129
+
96
130
#endif
+1
include/dt-bindings/reset/sun50i-h616-ccu.h
+1
include/dt-bindings/reset/sun50i-h616-ccu.h