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riscv: dts: allwinner: d1: fix vlenb property

According to [1], the C906 vector registers are 128 bits wide.
The 'thead,vlenb' property specifies the vector register length
in bytes, so its value must be set to 16.

[1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf

Fixes: ce1daeeba600 ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree")
Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Link: https://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>

authored by

Sergey Matyukevich and committed by
Chen-Yu Tsai 9f393d8e 3a866087

+1 -1
+1 -1
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
··· 28 28 riscv,isa-base = "rv64i"; 29 29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 30 30 "zifencei", "zihpm", "xtheadvector"; 31 - thead,vlenb = <128>; 31 + thead,vlenb = <16>; 32 32 #cooling-cells = <2>; 33 33 34 34 cpu0_intc: interrupt-controller {