···141141 break;142142 }143143144144+ /* Ignoring the last page when ddr size is 128M. Cached145145+ * accesses to last page is causing the processor to prefetch146146+ * using address above 128M stepping out of the ddr address147147+ * space.148148+ */149149+ if (mem == 0x8000000)150150+ mem -= 0x1000;151151+144152 add_memory_region(0, mem, BOOT_MEM_RAM);145153}146154