tjh.dev / kernel
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drm/amd/pm/smu7: Remove non-functional SMU7 voltage dependency on DAL

It looks like this was written for an old version of DC (DAL)
and was never adapted afterwards. This was non-functional
because it relied on the "dal_power_level" field which was
never assigned anywhere in the code base.

Also, it was not implemented for CI ASICs.

Now superseded by the newer voltage dependency on display
clock table added by the previous commit, let's remove.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Timur Kristóf and committed by
Alex Deucher 9f49e3d4 0138610c

-95
-9
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
··· 2794 2794 if (tmp) 2795 2795 return -EINVAL; 2796 2796 2797 - tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 2798 - if (tmp) 2799 - return -EINVAL; 2800 - 2801 2797 tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk); 2802 2798 if (tmp) 2803 2799 return -EINVAL; ··· 2883 2887 2884 2888 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 2885 2889 { 2886 - kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 2887 - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; 2888 2890 kfree(hwmgr->dyn_state.vddc_dependency_on_display_clock); 2889 2891 hwmgr->dyn_state.vddc_dependency_on_display_clock = NULL; 2890 2892 kfree(hwmgr->backend); ··· 3039 3045 smu7_patch_dependency_tables_with_leakage(hwmgr); 3040 3046 smu7_set_private_data_based_on_pptable_v0(hwmgr); 3041 3047 } 3042 - 3043 - /* Initalize Dynamic State Adjustment Rule Settings */ 3044 - result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr); 3045 3048 3046 3049 if (result) 3047 3050 goto fail;
-83
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c
··· 484 484 return 0; 485 485 } 486 486 487 - /** 488 - * phm_initializa_dynamic_state_adjustment_rule_settings - Initialize Dynamic State Adjustment Rule Settings 489 - * 490 - * @hwmgr: the address of the powerplay hardware manager. 491 - */ 492 - int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr) 493 - { 494 - struct phm_clock_voltage_dependency_table *table_clk_vlt; 495 - struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 496 - 497 - /* initialize vddc_dep_on_dal_pwrl table */ 498 - table_clk_vlt = kzalloc_flex(*table_clk_vlt, entries, 4); 499 - 500 - if (NULL == table_clk_vlt) { 501 - pr_err("Can not allocate space for vddc_dep_on_dal_pwrl! \n"); 502 - return -ENOMEM; 503 - } else { 504 - table_clk_vlt->count = 4; 505 - table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW; 506 - if (hwmgr->chip_id >= CHIP_POLARIS10 && 507 - hwmgr->chip_id <= CHIP_VEGAM) 508 - table_clk_vlt->entries[0].v = 700; 509 - else 510 - table_clk_vlt->entries[0].v = 0; 511 - table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW; 512 - if (hwmgr->chip_id >= CHIP_POLARIS10 && 513 - hwmgr->chip_id <= CHIP_VEGAM) 514 - table_clk_vlt->entries[1].v = 740; 515 - else 516 - table_clk_vlt->entries[1].v = 720; 517 - table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL; 518 - if (hwmgr->chip_id >= CHIP_POLARIS10 && 519 - hwmgr->chip_id <= CHIP_VEGAM) 520 - table_clk_vlt->entries[2].v = 800; 521 - else 522 - table_clk_vlt->entries[2].v = 810; 523 - table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE; 524 - table_clk_vlt->entries[3].v = 900; 525 - if (pptable_info != NULL) 526 - pptable_info->vddc_dep_on_dal_pwrl = table_clk_vlt; 527 - hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; 528 - } 529 - 530 - return 0; 531 - } 532 - 533 487 uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask) 534 488 { 535 489 uint32_t level = 0; ··· 492 538 level++; 493 539 494 540 return level; 495 - } 496 - 497 - void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr) 498 - { 499 - struct phm_ppt_v1_information *table_info = 500 - (struct phm_ppt_v1_information *)hwmgr->pptable; 501 - struct phm_clock_voltage_dependency_table *table = 502 - table_info->vddc_dep_on_dal_pwrl; 503 - struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table; 504 - enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level; 505 - uint32_t req_vddc = 0, req_volt, i; 506 - 507 - if (!table || table->count <= 0 508 - || dal_power_level < PP_DAL_POWERLEVEL_ULTRALOW 509 - || dal_power_level > PP_DAL_POWERLEVEL_PERFORMANCE) 510 - return; 511 - 512 - for (i = 0; i < table->count; i++) { 513 - if (dal_power_level == table->entries[i].clk) { 514 - req_vddc = table->entries[i].v; 515 - break; 516 - } 517 - } 518 - 519 - vddc_table = table_info->vdd_dep_on_sclk; 520 - for (i = 0; i < vddc_table->count; i++) { 521 - if (req_vddc <= vddc_table->entries[i].vddc) { 522 - req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE); 523 - smum_send_msg_to_smc_with_parameter(hwmgr, 524 - PPSMC_MSG_VddC_Request, 525 - req_volt, 526 - NULL); 527 - return; 528 - } 529 - } 530 - pr_err("DAL requested level can not" 531 - " found a available voltage in VDDC DPM Table \n"); 532 541 } 533 542 534 543 int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
-2
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.h
··· 87 87 extern int phm_find_boot_level(void *table, uint32_t value, uint32_t *boot_level); 88 88 extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, 89 89 uint16_t virtual_voltage_id, int32_t *sclk); 90 - extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); 91 90 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask); 92 - extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr); 93 91 94 92 extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 95 93 uint32_t sclk, uint16_t id, uint16_t *voltage);
-1
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h
··· 773 773 const struct pp_smumgr_func *smumgr_funcs; 774 774 bool is_kicker; 775 775 776 - enum PP_DAL_POWERLEVEL dal_power_level; 777 776 struct phm_dynamic_state_info dyn_state; 778 777 const struct pp_hwmgr_func *hwmgr_func; 779 778 const struct pp_table_func *pptable_func;