Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
RISC-V: KVM: Handle MMIO exits for VCPU
We will get stage2 page faults whenever Guest/VM access SW emulated
MMIO device or unmapped Guest RAM.
This patch implements MMIO read/write emulation by extracting MMIO
details from the trapped load/store instruction and forwarding the
MMIO read/write to user-space. The actual MMIO emulation will happen
in user-space and KVM kernel module will only take care of register
updates before resuming the trapped VCPU.
The handling for stage2 page faults for unmapped Guest RAM will be
implemeted by a separate patch later.
[jiangyifei: ioeventfd and in-kernel mmio device support]
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alexander Graf <graf@amazon.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
authored by
Anup Patel
and committed by
Anup Patel
9f701326
34bde9d8
+651
-4
+22
arch/riscv/include/asm/kvm_host.h
+22
arch/riscv/include/asm/kvm_host.h
···
49
49
phys_addr_t pgd_phys;
50
50
};
51
51
52
+
struct kvm_mmio_decode {
53
+
unsigned long insn;
54
+
int insn_len;
55
+
int len;
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+
int shift;
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+
int return_handled;
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+
};
59
+
52
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struct kvm_cpu_trap {
53
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unsigned long sepc;
54
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unsigned long scause;
···
155
147
unsigned long irqs_pending;
156
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unsigned long irqs_pending_mask;
157
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+
/* MMIO instruction details */
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struct kvm_mmio_decode mmio_decode;
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+
158
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/* VCPU power-off state */
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bool power_off;
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155
···
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static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
174
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static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
175
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+
int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu,
166
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struct kvm_memory_slot *memslot,
167
+
gpa_t gpa, unsigned long hva, bool is_write);
176
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void kvm_riscv_stage2_flush_cache(struct kvm_vcpu *vcpu);
177
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int kvm_riscv_stage2_alloc_pgd(struct kvm *kvm);
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void kvm_riscv_stage2_free_pgd(struct kvm *kvm);
179
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void kvm_riscv_stage2_update_hgatp(struct kvm_vcpu *vcpu);
180
172
173
+
void __kvm_riscv_unpriv_trap(void);
174
+
175
+
unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vcpu *vcpu,
176
+
bool read_insn,
177
+
unsigned long guest_addr,
178
+
struct kvm_cpu_trap *trap);
179
+
void kvm_riscv_vcpu_trap_redirect(struct kvm_vcpu *vcpu,
180
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struct kvm_cpu_trap *trap);
181
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int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
182
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int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
183
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struct kvm_cpu_trap *trap);
+6
arch/riscv/kernel/asm-offsets.c
+6
arch/riscv/kernel/asm-offsets.c
···
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OFFSET(KVM_ARCH_HOST_STVEC, kvm_vcpu_arch, host_stvec);
190
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OFFSET(KVM_ARCH_HOST_SCOUNTEREN, kvm_vcpu_arch, host_scounteren);
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OFFSET(KVM_ARCH_TRAP_SEPC, kvm_cpu_trap, sepc);
193
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OFFSET(KVM_ARCH_TRAP_SCAUSE, kvm_cpu_trap, scause);
194
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OFFSET(KVM_ARCH_TRAP_STVAL, kvm_cpu_trap, stval);
195
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OFFSET(KVM_ARCH_TRAP_HTVAL, kvm_cpu_trap, htval);
196
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OFFSET(KVM_ARCH_TRAP_HTINST, kvm_cpu_trap, htinst);
197
+
192
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/*
193
199
* THREAD_{F,X}* might be larger than a S-type offset can handle, but
194
200
* these are used in performance-sensitive assembly so we can't resort
+1
arch/riscv/kvm/Kconfig
+1
arch/riscv/kvm/Kconfig
+1
-1
arch/riscv/kvm/Makefile
+1
-1
arch/riscv/kvm/Makefile
+8
arch/riscv/kvm/mmu.c
+8
arch/riscv/kvm/mmu.c
···
58
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return 0;
59
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}
60
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+
int kvm_riscv_stage2_map(struct kvm_vcpu *vcpu,
62
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struct kvm_memory_slot *memslot,
63
+
gpa_t gpa, unsigned long hva, bool is_write)
64
+
{
65
+
/* TODO: */
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+
return 0;
67
+
}
68
+
61
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void kvm_riscv_stage2_flush_cache(struct kvm_vcpu *vcpu)
62
70
{
63
71
/* TODO: */
+589
-3
arch/riscv/kvm/vcpu_exit.c
+589
-3
arch/riscv/kvm/vcpu_exit.c
···
6
6
* Anup Patel <anup.patel@wdc.com>
7
7
*/
8
8
9
+
#include <linux/bitops.h>
9
10
#include <linux/errno.h>
10
11
#include <linux/err.h>
11
12
#include <linux/kvm_host.h>
13
+
#include <asm/csr.h>
14
+
15
+
#define INSN_MATCH_LB 0x3
16
+
#define INSN_MASK_LB 0x707f
17
+
#define INSN_MATCH_LH 0x1003
18
+
#define INSN_MASK_LH 0x707f
19
+
#define INSN_MATCH_LW 0x2003
20
+
#define INSN_MASK_LW 0x707f
21
+
#define INSN_MATCH_LD 0x3003
22
+
#define INSN_MASK_LD 0x707f
23
+
#define INSN_MATCH_LBU 0x4003
24
+
#define INSN_MASK_LBU 0x707f
25
+
#define INSN_MATCH_LHU 0x5003
26
+
#define INSN_MASK_LHU 0x707f
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+
#define INSN_MATCH_LWU 0x6003
28
+
#define INSN_MASK_LWU 0x707f
29
+
#define INSN_MATCH_SB 0x23
30
+
#define INSN_MASK_SB 0x707f
31
+
#define INSN_MATCH_SH 0x1023
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+
#define INSN_MASK_SH 0x707f
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+
#define INSN_MATCH_SW 0x2023
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+
#define INSN_MASK_SW 0x707f
35
+
#define INSN_MATCH_SD 0x3023
36
+
#define INSN_MASK_SD 0x707f
37
+
38
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#define INSN_MATCH_C_LD 0x6000
39
+
#define INSN_MASK_C_LD 0xe003
40
+
#define INSN_MATCH_C_SD 0xe000
41
+
#define INSN_MASK_C_SD 0xe003
42
+
#define INSN_MATCH_C_LW 0x4000
43
+
#define INSN_MASK_C_LW 0xe003
44
+
#define INSN_MATCH_C_SW 0xc000
45
+
#define INSN_MASK_C_SW 0xe003
46
+
#define INSN_MATCH_C_LDSP 0x6002
47
+
#define INSN_MASK_C_LDSP 0xe003
48
+
#define INSN_MATCH_C_SDSP 0xe002
49
+
#define INSN_MASK_C_SDSP 0xe003
50
+
#define INSN_MATCH_C_LWSP 0x4002
51
+
#define INSN_MASK_C_LWSP 0xe003
52
+
#define INSN_MATCH_C_SWSP 0xc002
53
+
#define INSN_MASK_C_SWSP 0xe003
54
+
55
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#define INSN_16BIT_MASK 0x3
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+
57
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#define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)
58
+
59
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#define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4)
60
+
61
+
#ifdef CONFIG_64BIT
62
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#define LOG_REGBYTES 3
63
+
#else
64
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#define LOG_REGBYTES 2
65
+
#endif
66
+
#define REGBYTES (1 << LOG_REGBYTES)
67
+
68
+
#define SH_RD 7
69
+
#define SH_RS1 15
70
+
#define SH_RS2 20
71
+
#define SH_RS2C 2
72
+
73
+
#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
74
+
#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
75
+
(RV_X(x, 10, 3) << 3) | \
76
+
(RV_X(x, 5, 1) << 6))
77
+
#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
78
+
(RV_X(x, 5, 2) << 6))
79
+
#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
80
+
(RV_X(x, 12, 1) << 5) | \
81
+
(RV_X(x, 2, 2) << 6))
82
+
#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
83
+
(RV_X(x, 12, 1) << 5) | \
84
+
(RV_X(x, 2, 3) << 6))
85
+
#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
86
+
(RV_X(x, 7, 2) << 6))
87
+
#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
88
+
(RV_X(x, 7, 3) << 6))
89
+
#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
90
+
#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
91
+
#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
92
+
93
+
#define SHIFT_RIGHT(x, y) \
94
+
((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
95
+
96
+
#define REG_MASK \
97
+
((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
98
+
99
+
#define REG_OFFSET(insn, pos) \
100
+
(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
101
+
102
+
#define REG_PTR(insn, pos, regs) \
103
+
((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))
104
+
105
+
#define GET_RM(insn) (((insn) >> 12) & 7)
106
+
107
+
#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
108
+
#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
109
+
#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
110
+
#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
111
+
#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
112
+
#define GET_SP(regs) (*REG_PTR(2, 0, regs))
113
+
#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
114
+
#define IMM_I(insn) ((s32)(insn) >> 20)
115
+
#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
116
+
(s32)(((insn) >> 7) & 0x1f))
117
+
#define MASK_FUNCT3 0x7000
118
+
119
+
static int emulate_load(struct kvm_vcpu *vcpu, struct kvm_run *run,
120
+
unsigned long fault_addr, unsigned long htinst)
121
+
{
122
+
u8 data_buf[8];
123
+
unsigned long insn;
124
+
int shift = 0, len = 0, insn_len = 0;
125
+
struct kvm_cpu_trap utrap = { 0 };
126
+
struct kvm_cpu_context *ct = &vcpu->arch.guest_context;
127
+
128
+
/* Determine trapped instruction */
129
+
if (htinst & 0x1) {
130
+
/*
131
+
* Bit[0] == 1 implies trapped instruction value is
132
+
* transformed instruction or custom instruction.
133
+
*/
134
+
insn = htinst | INSN_16BIT_MASK;
135
+
insn_len = (htinst & BIT(1)) ? INSN_LEN(insn) : 2;
136
+
} else {
137
+
/*
138
+
* Bit[0] == 0 implies trapped instruction value is
139
+
* zero or special value.
140
+
*/
141
+
insn = kvm_riscv_vcpu_unpriv_read(vcpu, true, ct->sepc,
142
+
&utrap);
143
+
if (utrap.scause) {
144
+
/* Redirect trap if we failed to read instruction */
145
+
utrap.sepc = ct->sepc;
146
+
kvm_riscv_vcpu_trap_redirect(vcpu, &utrap);
147
+
return 1;
148
+
}
149
+
insn_len = INSN_LEN(insn);
150
+
}
151
+
152
+
/* Decode length of MMIO and shift */
153
+
if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
154
+
len = 4;
155
+
shift = 8 * (sizeof(ulong) - len);
156
+
} else if ((insn & INSN_MASK_LB) == INSN_MATCH_LB) {
157
+
len = 1;
158
+
shift = 8 * (sizeof(ulong) - len);
159
+
} else if ((insn & INSN_MASK_LBU) == INSN_MATCH_LBU) {
160
+
len = 1;
161
+
shift = 8 * (sizeof(ulong) - len);
162
+
#ifdef CONFIG_64BIT
163
+
} else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) {
164
+
len = 8;
165
+
shift = 8 * (sizeof(ulong) - len);
166
+
} else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) {
167
+
len = 4;
168
+
#endif
169
+
} else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) {
170
+
len = 2;
171
+
shift = 8 * (sizeof(ulong) - len);
172
+
} else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {
173
+
len = 2;
174
+
#ifdef CONFIG_64BIT
175
+
} else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {
176
+
len = 8;
177
+
shift = 8 * (sizeof(ulong) - len);
178
+
insn = RVC_RS2S(insn) << SH_RD;
179
+
} else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP &&
180
+
((insn >> SH_RD) & 0x1f)) {
181
+
len = 8;
182
+
shift = 8 * (sizeof(ulong) - len);
183
+
#endif
184
+
} else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) {
185
+
len = 4;
186
+
shift = 8 * (sizeof(ulong) - len);
187
+
insn = RVC_RS2S(insn) << SH_RD;
188
+
} else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP &&
189
+
((insn >> SH_RD) & 0x1f)) {
190
+
len = 4;
191
+
shift = 8 * (sizeof(ulong) - len);
192
+
} else {
193
+
return -EOPNOTSUPP;
194
+
}
195
+
196
+
/* Fault address should be aligned to length of MMIO */
197
+
if (fault_addr & (len - 1))
198
+
return -EIO;
199
+
200
+
/* Save instruction decode info */
201
+
vcpu->arch.mmio_decode.insn = insn;
202
+
vcpu->arch.mmio_decode.insn_len = insn_len;
203
+
vcpu->arch.mmio_decode.shift = shift;
204
+
vcpu->arch.mmio_decode.len = len;
205
+
vcpu->arch.mmio_decode.return_handled = 0;
206
+
207
+
/* Update MMIO details in kvm_run struct */
208
+
run->mmio.is_write = false;
209
+
run->mmio.phys_addr = fault_addr;
210
+
run->mmio.len = len;
211
+
212
+
/* Try to handle MMIO access in the kernel */
213
+
if (!kvm_io_bus_read(vcpu, KVM_MMIO_BUS, fault_addr, len, data_buf)) {
214
+
/* Successfully handled MMIO access in the kernel so resume */
215
+
memcpy(run->mmio.data, data_buf, len);
216
+
vcpu->stat.mmio_exit_kernel++;
217
+
kvm_riscv_vcpu_mmio_return(vcpu, run);
218
+
return 1;
219
+
}
220
+
221
+
/* Exit to userspace for MMIO emulation */
222
+
vcpu->stat.mmio_exit_user++;
223
+
run->exit_reason = KVM_EXIT_MMIO;
224
+
225
+
return 0;
226
+
}
227
+
228
+
static int emulate_store(struct kvm_vcpu *vcpu, struct kvm_run *run,
229
+
unsigned long fault_addr, unsigned long htinst)
230
+
{
231
+
u8 data8;
232
+
u16 data16;
233
+
u32 data32;
234
+
u64 data64;
235
+
ulong data;
236
+
unsigned long insn;
237
+
int len = 0, insn_len = 0;
238
+
struct kvm_cpu_trap utrap = { 0 };
239
+
struct kvm_cpu_context *ct = &vcpu->arch.guest_context;
240
+
241
+
/* Determine trapped instruction */
242
+
if (htinst & 0x1) {
243
+
/*
244
+
* Bit[0] == 1 implies trapped instruction value is
245
+
* transformed instruction or custom instruction.
246
+
*/
247
+
insn = htinst | INSN_16BIT_MASK;
248
+
insn_len = (htinst & BIT(1)) ? INSN_LEN(insn) : 2;
249
+
} else {
250
+
/*
251
+
* Bit[0] == 0 implies trapped instruction value is
252
+
* zero or special value.
253
+
*/
254
+
insn = kvm_riscv_vcpu_unpriv_read(vcpu, true, ct->sepc,
255
+
&utrap);
256
+
if (utrap.scause) {
257
+
/* Redirect trap if we failed to read instruction */
258
+
utrap.sepc = ct->sepc;
259
+
kvm_riscv_vcpu_trap_redirect(vcpu, &utrap);
260
+
return 1;
261
+
}
262
+
insn_len = INSN_LEN(insn);
263
+
}
264
+
265
+
data = GET_RS2(insn, &vcpu->arch.guest_context);
266
+
data8 = data16 = data32 = data64 = data;
267
+
268
+
if ((insn & INSN_MASK_SW) == INSN_MATCH_SW) {
269
+
len = 4;
270
+
} else if ((insn & INSN_MASK_SB) == INSN_MATCH_SB) {
271
+
len = 1;
272
+
#ifdef CONFIG_64BIT
273
+
} else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) {
274
+
len = 8;
275
+
#endif
276
+
} else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {
277
+
len = 2;
278
+
#ifdef CONFIG_64BIT
279
+
} else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
280
+
len = 8;
281
+
data64 = GET_RS2S(insn, &vcpu->arch.guest_context);
282
+
} else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP &&
283
+
((insn >> SH_RD) & 0x1f)) {
284
+
len = 8;
285
+
data64 = GET_RS2C(insn, &vcpu->arch.guest_context);
286
+
#endif
287
+
} else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {
288
+
len = 4;
289
+
data32 = GET_RS2S(insn, &vcpu->arch.guest_context);
290
+
} else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP &&
291
+
((insn >> SH_RD) & 0x1f)) {
292
+
len = 4;
293
+
data32 = GET_RS2C(insn, &vcpu->arch.guest_context);
294
+
} else {
295
+
return -EOPNOTSUPP;
296
+
}
297
+
298
+
/* Fault address should be aligned to length of MMIO */
299
+
if (fault_addr & (len - 1))
300
+
return -EIO;
301
+
302
+
/* Save instruction decode info */
303
+
vcpu->arch.mmio_decode.insn = insn;
304
+
vcpu->arch.mmio_decode.insn_len = insn_len;
305
+
vcpu->arch.mmio_decode.shift = 0;
306
+
vcpu->arch.mmio_decode.len = len;
307
+
vcpu->arch.mmio_decode.return_handled = 0;
308
+
309
+
/* Copy data to kvm_run instance */
310
+
switch (len) {
311
+
case 1:
312
+
*((u8 *)run->mmio.data) = data8;
313
+
break;
314
+
case 2:
315
+
*((u16 *)run->mmio.data) = data16;
316
+
break;
317
+
case 4:
318
+
*((u32 *)run->mmio.data) = data32;
319
+
break;
320
+
case 8:
321
+
*((u64 *)run->mmio.data) = data64;
322
+
break;
323
+
default:
324
+
return -EOPNOTSUPP;
325
+
};
326
+
327
+
/* Update MMIO details in kvm_run struct */
328
+
run->mmio.is_write = true;
329
+
run->mmio.phys_addr = fault_addr;
330
+
run->mmio.len = len;
331
+
332
+
/* Try to handle MMIO access in the kernel */
333
+
if (!kvm_io_bus_write(vcpu, KVM_MMIO_BUS,
334
+
fault_addr, len, run->mmio.data)) {
335
+
/* Successfully handled MMIO access in the kernel so resume */
336
+
vcpu->stat.mmio_exit_kernel++;
337
+
kvm_riscv_vcpu_mmio_return(vcpu, run);
338
+
return 1;
339
+
}
340
+
341
+
/* Exit to userspace for MMIO emulation */
342
+
vcpu->stat.mmio_exit_user++;
343
+
run->exit_reason = KVM_EXIT_MMIO;
344
+
345
+
return 0;
346
+
}
347
+
348
+
static int stage2_page_fault(struct kvm_vcpu *vcpu, struct kvm_run *run,
349
+
struct kvm_cpu_trap *trap)
350
+
{
351
+
struct kvm_memory_slot *memslot;
352
+
unsigned long hva, fault_addr;
353
+
bool writeable;
354
+
gfn_t gfn;
355
+
int ret;
356
+
357
+
fault_addr = (trap->htval << 2) | (trap->stval & 0x3);
358
+
gfn = fault_addr >> PAGE_SHIFT;
359
+
memslot = gfn_to_memslot(vcpu->kvm, gfn);
360
+
hva = gfn_to_hva_memslot_prot(memslot, gfn, &writeable);
361
+
362
+
if (kvm_is_error_hva(hva) ||
363
+
(trap->scause == EXC_STORE_GUEST_PAGE_FAULT && !writeable)) {
364
+
switch (trap->scause) {
365
+
case EXC_LOAD_GUEST_PAGE_FAULT:
366
+
return emulate_load(vcpu, run, fault_addr,
367
+
trap->htinst);
368
+
case EXC_STORE_GUEST_PAGE_FAULT:
369
+
return emulate_store(vcpu, run, fault_addr,
370
+
trap->htinst);
371
+
default:
372
+
return -EOPNOTSUPP;
373
+
};
374
+
}
375
+
376
+
ret = kvm_riscv_stage2_map(vcpu, memslot, fault_addr, hva,
377
+
(trap->scause == EXC_STORE_GUEST_PAGE_FAULT) ? true : false);
378
+
if (ret < 0)
379
+
return ret;
380
+
381
+
return 1;
382
+
}
383
+
384
+
/**
385
+
* kvm_riscv_vcpu_unpriv_read -- Read machine word from Guest memory
386
+
*
387
+
* @vcpu: The VCPU pointer
388
+
* @read_insn: Flag representing whether we are reading instruction
389
+
* @guest_addr: Guest address to read
390
+
* @trap: Output pointer to trap details
391
+
*/
392
+
unsigned long kvm_riscv_vcpu_unpriv_read(struct kvm_vcpu *vcpu,
393
+
bool read_insn,
394
+
unsigned long guest_addr,
395
+
struct kvm_cpu_trap *trap)
396
+
{
397
+
register unsigned long taddr asm("a0") = (unsigned long)trap;
398
+
register unsigned long ttmp asm("a1");
399
+
register unsigned long val asm("t0");
400
+
register unsigned long tmp asm("t1");
401
+
register unsigned long addr asm("t2") = guest_addr;
402
+
unsigned long flags;
403
+
unsigned long old_stvec, old_hstatus;
404
+
405
+
local_irq_save(flags);
406
+
407
+
old_hstatus = csr_swap(CSR_HSTATUS, vcpu->arch.guest_context.hstatus);
408
+
old_stvec = csr_swap(CSR_STVEC, (ulong)&__kvm_riscv_unpriv_trap);
409
+
410
+
if (read_insn) {
411
+
/*
412
+
* HLVX.HU instruction
413
+
* 0110010 00011 rs1 100 rd 1110011
414
+
*/
415
+
asm volatile ("\n"
416
+
".option push\n"
417
+
".option norvc\n"
418
+
"add %[ttmp], %[taddr], 0\n"
419
+
/*
420
+
* HLVX.HU %[val], (%[addr])
421
+
* HLVX.HU t0, (t2)
422
+
* 0110010 00011 00111 100 00101 1110011
423
+
*/
424
+
".word 0x6433c2f3\n"
425
+
"andi %[tmp], %[val], 3\n"
426
+
"addi %[tmp], %[tmp], -3\n"
427
+
"bne %[tmp], zero, 2f\n"
428
+
"addi %[addr], %[addr], 2\n"
429
+
/*
430
+
* HLVX.HU %[tmp], (%[addr])
431
+
* HLVX.HU t1, (t2)
432
+
* 0110010 00011 00111 100 00110 1110011
433
+
*/
434
+
".word 0x6433c373\n"
435
+
"sll %[tmp], %[tmp], 16\n"
436
+
"add %[val], %[val], %[tmp]\n"
437
+
"2:\n"
438
+
".option pop"
439
+
: [val] "=&r" (val), [tmp] "=&r" (tmp),
440
+
[taddr] "+&r" (taddr), [ttmp] "+&r" (ttmp),
441
+
[addr] "+&r" (addr) : : "memory");
442
+
443
+
if (trap->scause == EXC_LOAD_PAGE_FAULT)
444
+
trap->scause = EXC_INST_PAGE_FAULT;
445
+
} else {
446
+
/*
447
+
* HLV.D instruction
448
+
* 0110110 00000 rs1 100 rd 1110011
449
+
*
450
+
* HLV.W instruction
451
+
* 0110100 00000 rs1 100 rd 1110011
452
+
*/
453
+
asm volatile ("\n"
454
+
".option push\n"
455
+
".option norvc\n"
456
+
"add %[ttmp], %[taddr], 0\n"
457
+
#ifdef CONFIG_64BIT
458
+
/*
459
+
* HLV.D %[val], (%[addr])
460
+
* HLV.D t0, (t2)
461
+
* 0110110 00000 00111 100 00101 1110011
462
+
*/
463
+
".word 0x6c03c2f3\n"
464
+
#else
465
+
/*
466
+
* HLV.W %[val], (%[addr])
467
+
* HLV.W t0, (t2)
468
+
* 0110100 00000 00111 100 00101 1110011
469
+
*/
470
+
".word 0x6803c2f3\n"
471
+
#endif
472
+
".option pop"
473
+
: [val] "=&r" (val),
474
+
[taddr] "+&r" (taddr), [ttmp] "+&r" (ttmp)
475
+
: [addr] "r" (addr) : "memory");
476
+
}
477
+
478
+
csr_write(CSR_STVEC, old_stvec);
479
+
csr_write(CSR_HSTATUS, old_hstatus);
480
+
481
+
local_irq_restore(flags);
482
+
483
+
return val;
484
+
}
485
+
486
+
/**
487
+
* kvm_riscv_vcpu_trap_redirect -- Redirect trap to Guest
488
+
*
489
+
* @vcpu: The VCPU pointer
490
+
* @trap: Trap details
491
+
*/
492
+
void kvm_riscv_vcpu_trap_redirect(struct kvm_vcpu *vcpu,
493
+
struct kvm_cpu_trap *trap)
494
+
{
495
+
unsigned long vsstatus = csr_read(CSR_VSSTATUS);
496
+
497
+
/* Change Guest SSTATUS.SPP bit */
498
+
vsstatus &= ~SR_SPP;
499
+
if (vcpu->arch.guest_context.sstatus & SR_SPP)
500
+
vsstatus |= SR_SPP;
501
+
502
+
/* Change Guest SSTATUS.SPIE bit */
503
+
vsstatus &= ~SR_SPIE;
504
+
if (vsstatus & SR_SIE)
505
+
vsstatus |= SR_SPIE;
506
+
507
+
/* Clear Guest SSTATUS.SIE bit */
508
+
vsstatus &= ~SR_SIE;
509
+
510
+
/* Update Guest SSTATUS */
511
+
csr_write(CSR_VSSTATUS, vsstatus);
512
+
513
+
/* Update Guest SCAUSE, STVAL, and SEPC */
514
+
csr_write(CSR_VSCAUSE, trap->scause);
515
+
csr_write(CSR_VSTVAL, trap->stval);
516
+
csr_write(CSR_VSEPC, trap->sepc);
517
+
518
+
/* Set Guest PC to Guest exception vector */
519
+
vcpu->arch.guest_context.sepc = csr_read(CSR_VSTVEC);
520
+
}
12
521
13
522
/**
14
523
* kvm_riscv_vcpu_mmio_return -- Handle MMIO loads after user space emulation
···
528
19
*/
529
20
int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
530
21
{
531
-
/* TODO: */
22
+
u8 data8;
23
+
u16 data16;
24
+
u32 data32;
25
+
u64 data64;
26
+
ulong insn;
27
+
int len, shift;
28
+
29
+
if (vcpu->arch.mmio_decode.return_handled)
30
+
return 0;
31
+
32
+
vcpu->arch.mmio_decode.return_handled = 1;
33
+
insn = vcpu->arch.mmio_decode.insn;
34
+
35
+
if (run->mmio.is_write)
36
+
goto done;
37
+
38
+
len = vcpu->arch.mmio_decode.len;
39
+
shift = vcpu->arch.mmio_decode.shift;
40
+
41
+
switch (len) {
42
+
case 1:
43
+
data8 = *((u8 *)run->mmio.data);
44
+
SET_RD(insn, &vcpu->arch.guest_context,
45
+
(ulong)data8 << shift >> shift);
46
+
break;
47
+
case 2:
48
+
data16 = *((u16 *)run->mmio.data);
49
+
SET_RD(insn, &vcpu->arch.guest_context,
50
+
(ulong)data16 << shift >> shift);
51
+
break;
52
+
case 4:
53
+
data32 = *((u32 *)run->mmio.data);
54
+
SET_RD(insn, &vcpu->arch.guest_context,
55
+
(ulong)data32 << shift >> shift);
56
+
break;
57
+
case 8:
58
+
data64 = *((u64 *)run->mmio.data);
59
+
SET_RD(insn, &vcpu->arch.guest_context,
60
+
(ulong)data64 << shift >> shift);
61
+
break;
62
+
default:
63
+
return -EOPNOTSUPP;
64
+
};
65
+
66
+
done:
67
+
/* Move to next instruction */
68
+
vcpu->arch.guest_context.sepc += vcpu->arch.mmio_decode.insn_len;
69
+
532
70
return 0;
533
71
}
534
72
···
586
30
int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
587
31
struct kvm_cpu_trap *trap)
588
32
{
589
-
/* TODO: */
590
-
return 0;
33
+
int ret;
34
+
35
+
/* If we got host interrupt then do nothing */
36
+
if (trap->scause & CAUSE_IRQ_FLAG)
37
+
return 1;
38
+
39
+
/* Handle guest traps */
40
+
ret = -EFAULT;
41
+
run->exit_reason = KVM_EXIT_UNKNOWN;
42
+
switch (trap->scause) {
43
+
case EXC_INST_GUEST_PAGE_FAULT:
44
+
case EXC_LOAD_GUEST_PAGE_FAULT:
45
+
case EXC_STORE_GUEST_PAGE_FAULT:
46
+
if (vcpu->arch.guest_context.hstatus & HSTATUS_SPV)
47
+
ret = stage2_page_fault(vcpu, run, trap);
48
+
break;
49
+
default:
50
+
break;
51
+
};
52
+
53
+
/* Print details in-case of error */
54
+
if (ret < 0) {
55
+
kvm_err("VCPU exit error %d\n", ret);
56
+
kvm_err("SEPC=0x%lx SSTATUS=0x%lx HSTATUS=0x%lx\n",
57
+
vcpu->arch.guest_context.sepc,
58
+
vcpu->arch.guest_context.sstatus,
59
+
vcpu->arch.guest_context.hstatus);
60
+
kvm_err("SCAUSE=0x%lx STVAL=0x%lx HTVAL=0x%lx HTINST=0x%lx\n",
61
+
trap->scause, trap->stval, trap->htval, trap->htinst);
62
+
}
63
+
64
+
return ret;
591
65
}
+23
arch/riscv/kvm/vcpu_switch.S
+23
arch/riscv/kvm/vcpu_switch.S
···
201
201
/* Return to C code */
202
202
ret
203
203
ENDPROC(__kvm_riscv_switch_to)
204
+
205
+
ENTRY(__kvm_riscv_unpriv_trap)
206
+
/*
207
+
* We assume that faulting unpriv load/store instruction is
208
+
* 4-byte long and blindly increment SEPC by 4.
209
+
*
210
+
* The trap details will be saved at address pointed by 'A0'
211
+
* register and we use 'A1' register as temporary.
212
+
*/
213
+
csrr a1, CSR_SEPC
214
+
REG_S a1, (KVM_ARCH_TRAP_SEPC)(a0)
215
+
addi a1, a1, 4
216
+
csrw CSR_SEPC, a1
217
+
csrr a1, CSR_SCAUSE
218
+
REG_S a1, (KVM_ARCH_TRAP_SCAUSE)(a0)
219
+
csrr a1, CSR_STVAL
220
+
REG_S a1, (KVM_ARCH_TRAP_STVAL)(a0)
221
+
csrr a1, CSR_HTVAL
222
+
REG_S a1, (KVM_ARCH_TRAP_HTVAL)(a0)
223
+
csrr a1, CSR_HTINST
224
+
REG_S a1, (KVM_ARCH_TRAP_HTINST)(a0)
225
+
sret
226
+
ENDPROC(__kvm_riscv_unpriv_trap)