Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk driver fixes from Stephen Boyd:
- Make the regulator state match the GDSC power domain state at boot on
Qualcomm SoCs so that the regulator isn't turned off inadvertently.
- Fix earlycon on i.MX6Q SoCs
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: qcom: gdsc: Ensure regulator init state matches GDSC state
clk: imx6q: fix uart earlycon unwork
+38
-20
+1
-1
drivers/clk/imx/clk-imx6q.c
+1
-1
drivers/clk/imx/clk-imx6q.c
+37
-19
drivers/clk/qcom/gdsc.c
+37
-19
drivers/clk/qcom/gdsc.c
···
357
357
if (on < 0)
358
358
return on;
359
359
360
-
/*
361
-
* Votable GDSCs can be ON due to Vote from other masters.
362
-
* If a Votable GDSC is ON, make sure we have a Vote.
363
-
*/
364
-
if ((sc->flags & VOTABLE) && on)
360
+
if (on) {
361
+
/* The regulator must be on, sync the kernel state */
362
+
if (sc->rsupply) {
363
+
ret = regulator_enable(sc->rsupply);
364
+
if (ret < 0)
365
+
return ret;
366
+
}
367
+
368
+
/*
369
+
* Votable GDSCs can be ON due to Vote from other masters.
370
+
* If a Votable GDSC is ON, make sure we have a Vote.
371
+
*/
372
+
if (sc->flags & VOTABLE) {
373
+
ret = regmap_update_bits(sc->regmap, sc->gdscr,
374
+
SW_COLLAPSE_MASK, val);
375
+
if (ret)
376
+
return ret;
377
+
}
378
+
379
+
/* Turn on HW trigger mode if supported */
380
+
if (sc->flags & HW_CTRL) {
381
+
ret = gdsc_hwctrl(sc, true);
382
+
if (ret < 0)
383
+
return ret;
384
+
}
385
+
386
+
/*
387
+
* Make sure the retain bit is set if the GDSC is already on,
388
+
* otherwise we end up turning off the GDSC and destroying all
389
+
* the register contents that we thought we were saving.
390
+
*/
391
+
if (sc->flags & RETAIN_FF_ENABLE)
392
+
gdsc_retain_ff_on(sc);
393
+
} else if (sc->flags & ALWAYS_ON) {
394
+
/* If ALWAYS_ON GDSCs are not ON, turn them ON */
365
395
gdsc_enable(&sc->pd);
366
-
367
-
/*
368
-
* Make sure the retain bit is set if the GDSC is already on, otherwise
369
-
* we end up turning off the GDSC and destroying all the register
370
-
* contents that we thought we were saving.
371
-
*/
372
-
if ((sc->flags & RETAIN_FF_ENABLE) && on)
373
-
gdsc_retain_ff_on(sc);
374
-
375
-
/* If ALWAYS_ON GDSCs are not ON, turn them ON */
376
-
if (sc->flags & ALWAYS_ON) {
377
-
if (!on)
378
-
gdsc_enable(&sc->pd);
379
396
on = true;
380
-
sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
381
397
}
382
398
383
399
if (on || (sc->pwrsts & PWRSTS_RET))
···
401
385
else
402
386
gdsc_clear_mem_on(sc);
403
387
388
+
if (sc->flags & ALWAYS_ON)
389
+
sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
404
390
if (!sc->pd.power_off)
405
391
sc->pd.power_off = gdsc_disable;
406
392
if (!sc->pd.power_on)